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AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

具有高 CMTI 的 AMC1306x 小型、高精度、增强型

隔离式 Δ-Σ 调制器

1 特性

3 说明

1

•

针对基于分流电阻器的电流测量进行优化的引脚可

兼容系列：

AMC1306 是一款高精度 Δ-Σ 调制器，通过抗电磁干扰

性能极强的电容式双隔离层将输出与输入电路隔离开。

该隔离层经过认证，可以按照 DIN VDE V 0884-11 和

UL1577 标准提供高达 7000V_PEAK的增强型隔离。与

隔离式电源结合使用时，该隔离式调制器可将以不同共

模电压等级运行的系统的各器件隔开，并防止较低电压

器件损坏。

–

输入电压范围为 ±50mV 或 ±250mV

曼彻斯特编码或未编码的位流选项

•

出色的直流性能：

–

失调电压误差：±50µV 或 ±100µV（最大值）

温漂：1µV/°C（最大值）

增益误差：±0.2%（最大值）

AMC1306 的输入针对直接连接分流电阻器或其他低电

压等级信号源进行了优化。器件具有独特的 ±50mV 低

输入电压范围，可通过分流器显著降低功率耗散，同时

具有出色的交流和直流性能。AMC1306 的输出位流采

用曼彻斯特编码 (AMC1306Ex) 或未编码

增益漂移：±40ppm/°C（最大值）

•

瞬态抗扰性：100kV/µs（典型值）

系统级诊断功能

安全相关认证：

–

7000V_PEAK增强型隔离，符合 DIN VDE V

0884-11: 2017-01 标准

(AMC1306Mx)，具体情况因导数而异。通过使用集成

式数字滤波器（如 TMS320F2807x 或

符合 UL1577 标准且长达 1 分钟的 5000V_RMS

隔离

TMS320F2837x 微控制器系列中的滤波器）来抽取位

流，该器件可在 78kSPS 数据速率下实现 85dB 动态

范围的 16 位分辨率。

符合 CAN/CSA No. 5A 组件验收服务通知和

IEC 62368-1 终端设备标准

•

完整的额定工作温度范围：–40°C 至 +125°C

曼彻斯特编码的 AMC1306Ex 版本的位流输出支持单

线数据和时钟传输，无需考虑接收设备的设置和保持时

间要求。

2 应用

•

基于分流电阻器的电流感应和隔离式电压测量，包

括：

器件信息⁽¹⁾

器件型号

封装

SOIC (8)

封装尺寸（标称值）

–

工业电机驱动

AMC1306x

5.85mm × 7.50mm

光电逆变器

不间断电源

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

Floating

Power Supply

HV+

AMC1306Mx

3.3 V or 5.0 V

AVDD

DVDD

3.0 V, 3.3 V, or 5.0 V

AGND

AINN

AINP

DGND

DOUT

CLKIN

TMS320F28x7x

Optional

R_SHUNT

To Load

SD-Dx

Optional

SD-Cx

PWMx

HV-

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS734

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

www.ti.com.cn

8.1 Overview ................................................................. 21

8.2 Functional Block Diagram ....................................... 21

8.3 Feature Description................................................. 22

8.4 Device Functional Modes........................................ 26

Application and Implementation ........................ 27

9.1 Application Information............................................ 27

9.2 Typical Applications ................................................ 28

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Power Ratings........................................................... 5

7.6 Insulation Specifications............................................ 6

7.7 Safety-Related Certifications..................................... 7

7.8 Safety Limiting Values .............................................. 7

7.9 Electrical Characteristics: AMC1306x05................... 8

7.10 Electrical Characteristics: AMC1306x25............... 10

7.11 Switching Characteristics...................................... 12

7.12 Insulation Characteristics Curves ......................... 13

7.13 Typical Characteristics.......................................... 14

Detailed Description ............................................ 21

9

10 Power Supply Recommendations ..................... 33

11 Layout................................................................... 34

11.1 Layout Guidelines ................................................. 34

11.2 Layout Example .................................................... 34

12 器件和文档支持 ..................................................... 35

12.1 器件支持................................................................ 35

12.2 文档支持................................................................ 35

12.3 相关链接................................................................ 35

12.4 接收文档更新通知 ................................................. 35

12.5 社区资源................................................................ 35

12.6 商标....................................................................... 35

12.7 静电放电警告......................................................... 35

12.8 Glossary................................................................ 36

13 机械、封装和可订购信息....................................... 36

8

4 修订历史记录

Changes from Revision B (June 2018) to Revision C

Page

•

已更改更改了安全相关认证项目符号（位于特性部分）：将 VDE 认证版本从 DIN V VDE V 0884-10 (VDE V 0884-

11) 更改为 DIN VDE V 0884-11，并将 IEC 60950-1 和 IEC 60065 更改为 IEC 62368-1..................................................... 1

•

已更改将 DIN V VDE V 更改为 DIN VDE V（位于说明部分）............................................................................................. 1

Changed CLR and CPG values from ≥ 9 mm to ≥ 8.5 mm in Insulation Specifications table ............................................... 6

Changed Insulation Specifications table header row from DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 to DIN

VDE V 0884-11: 2017-01 ....................................................................................................................................................... 6

•

Changed VDE certification details in Safety-Related Certifications table............................................................................... 7

Changed Safety Limiting Values table format as per current standard.................................................................................. 7

Changed free air to ambient in condition statement of Switching Characteristics table ...................................................... 12

Changed 6.05 dB to 6.02 dB in Equation 3.......................................................................................................................... 27

Changed input common-mode voltage from 2 V to 1.9 V for consistency with Input Bias Current vs Common-Mode

Input Voltage figure in What To Do and What Not To Do section........................................................................................ 32

•

Changed VINx to AINx in Layout Guidelines section ........................................................................................................... 34

Changed Recommended Layout of the AMC1306x figure to include connection to the shunt resistor and input filter

components .......................................................................................................................................................................... 34

Changes from Revision A (July 2017) to Revision B

Page

•

Changed Reinforced Isolation Capacitor Lifetime Projection figure .................................................................................... 13

Changes from Original (March 2017) to Revision A

Page

•

AMC1306E05 和 AMC1306M05 已投入生产.......................................................................................................................... 1

已添加向第一个直流性能子项目符号中添加了 ±50µV，以反映 AMC1306x05 器件的情况.................................................. 1

已更改将第一个安全相关认证子项目符号中的标准偏差从 0884-10 更改为 0884-11 ........................................................... 1

2

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

www.ti.com.cn

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

•

已更改将 V_PEAK从 8000 更改为 7000，将标准偏差从 0884-10 变更为 0884-11（均位于说明部分的第一段） .................. 1

Deleted Status column from Device Comparison Table......................................................................................................... 4

Changed standard deviation from 0884-10 to 0884-11 in DIN V VDE V 0884-11 section of Insulation Specifications table 6

Changed standard deviation from 0884-10 to 0884-11 in Safety-Related Certifications table .............................................. 7

Changed prevent to minimize in condition statement of Safety Limiting Values table........................................................... 7

Added Electrical Characteristics: AMC1306x05 table ........................................................................................................... 8

Changed test conditions of Analog Inputs test conditions from (AINP – AINN) / 2 to AGND to (AINP + AINN) / 2 to

AGND to include all possible conditions............................................................................................................................... 10

•

Changed I_IBtest condition from Inputs shorted to AGND to AINP = AINN = AGND, I_IB= I_IBP+ I_IBN.................................... 10

Added AINP = AINN = AGND to E_Oparameter test conditions .......................................................................................... 10

Changed minus sign to plus or minus sign in typical specification of E_Gparameter ........................................................... 10

Changed 10% to 90% to 90% to 10% in test conditions of t_fparameter ............................................................................ 12

Added AMC1306x05 devices to Typical Characteristics section ........................................................................................ 14

3

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

www.ti.com.cn

5 Device Comparison Table

DIFFERENTIAL INPUT

RESISTANCE

PART NUMBER

INPUT VOLTAGE RANGE

DIGITAL OUTPUT INTERFACE

AMC1306E05

AMC1306E25

AMC1306M05

AMC1306M25

±50 mV

±250 mV

±50 mV

4.9 kΩ

22 kΩ

4.9 kΩ

22 kΩ

Manchester coded CMOS

Uncoded CMOS

±250 mV

Uncoded CMOS

6 Pin Configuration and Functions

DWV Package

8-Pin SOIC

Top View

AVDD

AINP

1

2

3

4

8

7

6

5

DVDD

CLKIN

DOUT

DGND

AINN

AGND

Not to scale

Pin Functions

I/O

NO.

NAME

DESCRIPTION

Analog (high-side) power supply, 3.0 V to 5.5 V.

1

AVDD

—

See the Power Supply Recommendations section for decoupling recommendations.

2

3

4

5

6

7

AINP

AINN

I

Noninverting analog input

Inverting analog input

AGND

DGND

DOUT

CLKIN

—

O

I

Analog (high-side) ground reference

Digital (controller-side) ground reference

Modulator data output. This pin is a Manchester coded output for AMC1306Ex derivates.

Modulator clock input: 5 MHz to 21 MHz (5-V operation) with internal pulldown resistor (typical value: 1.5 MΩ)

Digital (controller-side) power supply, 2.7 V to 5.5 V.

See the Power Supply Recommendations section for decoupling recommendations.

8

DVDD

—

4

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

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ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.3

MAX

6.5

UNIT

V

Supply voltage

AVDD to AGND or DVDD to DGND

Analog input voltage at AINP, AINN

Digital input or output voltage at CLKIN or DOUT

Input current to any pin except supply pins

Junction temperature, T_J

AGND – 6

DGND – 0.5

–10

AVDD + 0.5

DVDD + 0.5

10

V

mA

°C

150

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

3.0

NOM

5.0

MAX

5.5

UNIT

V

AVDD

DVDD

T_A

Analog (high-side) supply voltage (AVDD to AGND)

Digital (controller-side) supply voltage (DVDD to DGND)

Operating ambient temperature

2.7

3.3

5.5

V

–40

125

°C

7.4 Thermal Information

AMC1306x

DWV (SOIC)

8 PINS

112.2

(1)

THERMAL METRIC

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

47.6

R_θJB

ψ_JT

Junction-to-board thermal resistance

60.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

23.1

ψ_JB

60.0

R_θJC(bot)Junction-to-case (bottom) thermal resistance

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

91.85

86.90

UNIT

AMC1306Ex, AVDD = DVDD = 5.5 V

AMC1306Mx, AVDD = DVDD = 5.5 V

Maximum power dissipation

(both sides)

P_D

mW

Maximum power dissipation

(high-side supply)

P_D1

P_D2

AVDD = 5.5 V

53.90

mW

AMC1306Ex, DVDD = 5.5 V

AMC1306Mx, DVDD = 5.5 V

37.95

33.00

Maximum power dissipation

(low-side supply)

5

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

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7.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance through air

≥ 8.5

mm

Shortest pin-to-pin distance across the package surface

Minimum internal gap (internal clearance) of the double insulation

(2 × 0.0105 mm)

DTI

CTI

Distance through insulation

≥ 0.021

mm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥ 600

I

Rated mains voltage ≤ 300 V_RMS

I-IV

I-III

Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

DIN VDE V 0884-11: 2017-01⁽²⁾

Maximum repetitive peak isolation

voltage

V_IORM

V_IOWM

At ac voltage (bipolar)

2121

V_PK

At ac voltage (sine wave)

1500

2121

7000

8400

V_RMS

V_DC

Maximum-rated isolation working

voltage

At dc voltage

V_TEST= V_IOTM, t = 60 s (qualification test)

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production test)

V_IOTMMaximum transient isolation voltage

V_IOSMMaximum surge isolation voltage⁽³⁾

V_PK

Test method per IEC 60065, 1.2/50-μs waveform,

V_TEST= 1.6 × V_IOSM= 12800 V_PK(qualification)

8000

Method a, after input/output safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s,

≤ 5

V_pd(m)= 1.2 × V_IORM= 2545 V_PK, t_m= 10 s

Method a, after environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s,

V_pd(m)= 1.6 × V_IORM= 3394 V_PK, t_m= 10 s

q_pd

Apparent charge⁽⁴⁾

pC

≤ 5

Method b1, at routine test (100% production) and preconditioning

(type test), V_ini= V_IOTM, t_ini= 1 s,

V_pd(m)= 1.875 × V_IORM= 3977 V_PK, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

V_IO= 0.5 V_PPat 1 MHz

~1

> 10¹²

> 10¹¹

> 10⁹

pF

V_IO= 500 V at T_A= 25°C

Insulation resistance, input to output⁽⁵⁾V_IO= 500 V at 100°C ≤ T_A≤ 125°C

Ω

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

2

40/125/21

UL1577

V_TEST= V_ISO= 5000 V_RMSor 7000 V_DC, t = 60 s (qualification),

V_TEST= 1.2 × V_ISO= 6000 V_RMS, t = 1 s (100% production test)

V_ISO

Withstand isolation voltage

5000

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed

circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as

inserting grooves and ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier are tied together, creating a two-pin device.

6

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

www.ti.com.cn

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

7.7 Safety-Related Certifications

VDE

UL

Certified according to DIN VDE V 0884-11: 2017-01, DIN EN

62368-1: 2016-05, EN 62368-1: 2014, and IEC 62368-1: 2014

Recognized under 1577 component recognition and

CSA component acceptance NO 5 programs

Reinforced insulation

Single protection

File number: DIN 40040142

File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R

_θJA= 112.2°C/W, AVDD = DVDD = 5.5 V,

202.5

T_J= 150°C, T_A= 25°C

_θJA= 112.2°C/W, AVDD = DVDD = 3.6 V,

T_J= 150°C, T_A= 25°C

_θJA= 112.2°C/W, T_J= 150°C, T_A= 25°C

I_S

Safety input, output, or supply current

mA

R

309.4

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

R

1114⁽¹⁾

150

mW

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of I_Sand P_S. These

limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum junction temperature.

P_S= I_S× AVDD_max+ I_S× AVDD_max, where AVDD_maxis the maximum high-side supply voltage and DVDD_maxis the maximum controller-

side supply voltage.

7

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

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7.9 Electrical Characteristics: AMC1306x05

minimum and maximum specifications apply from T_A= –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –50 mV to 50 mV, AINN = AGND, and sinc³filter with OSR = 256 (unless otherwise noted); typical specifications are

at T_A= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

V_ClippingDifferential input voltage before clipping output

V_IN= AINP – AINN

±64

mV

V

FSR

Specified linear differential full-scale

Absolute common-mode input voltage⁽¹⁾

Operating common-mode input voltage

Common-mode overvoltage detection level⁽²⁾

Single-ended input capacitance

Differential input capacitance

Input bias current

V_IN= AINP – AINN

–50

–2

50

AVDD

(AINP + AINN) / 2 to AGND

AINN = AGND

V_CM

V_CMov

C_IN

–0.032

AVDD - 2

AVDD – 2.1

V

4

2

pF

μA

kΩ

nA

kV/μs

C_IND

I_IB

AINP = AINN = AGND, I_IB= I_IBP+ I_IBN

AINN = AGND

–97

50

–72

4.75

4.9

–57

R_IN

Single-ended input resistance

Differential input resistance

R_IND

I_IO

Input offset current

±10

100

CMTI

Common-mode transient immunity

AINP = AINN, f_IN= 0 Hz,

–99

V_{CM min}≤ V_IN≤ V_{CM max}

CMRR Common-mode rejection ratio

dB

AINP = AINN, f_INfrom 0.1 Hz to 50 kHz,

–98

800

V_{CM min}≤ V_IN≤ V_{CM max}

BW

DC ACCURACY

Input bandwidth⁽³⁾

kHz

DNL

Differential nonlinearity

Resolution: 16 bits

–0.99

–4

0.99

4

LSB

Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V

Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V

Initial, at 25°C, AINP = AINN = AGND

±1

±1.5

INL

Integral nonlinearity⁽⁴⁾

–5

5

E_O

Offset error

Offset error thermal drift⁽⁵⁾

–50

–1

±2.5

50

1

µV

TCE_O

E_G

±0.25

±0.005%

±20

μV/°C

Gain error

Gain error thermal drift⁽⁶⁾

Initial, at 25°C

–0.2%

–40

0.2%

40

TCE_G

ppm/°C

dB

AINP = AINN = AGND,

3.0 V ≤ AVDD ≤ 5.5 V, at dc

–108

PSRR

Power-supply rejection ratio

AINP = AINN = AGND,

3.0 V ≤ AVDD ≤ 5.5 V,

10 kHz, 100-mV ripple

–107

AC ACCURACY

SNR

Signal-to-noise ratio

f_IN= 1 kHz

78

82.5

82.3

dB

SINAD Signal-to-noise + distortion

77.5

4.5 V ≤ AVDD ≤ 5.5 V,

5 MHz ≤ f_CLKIN≤ 21 MHz, f_IN= 1 kHz

–98

–84

–83

THD

Total harmonic distortion

dB

3.0 V ≤ AVDD ≤ 3.6 V,

5 MHz ≤ f_CLKIN≤ 20 MHz, f_IN= 1 kHz

–93

100

SFDR

Spurious-free dynamic range

f_IN= 1 kHz

83

(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage V_CMfor normal

operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.

(2) The common-mode overvoltage detection level has a typical hysteresis of 90 mV.

(3) This is the –3-dB, second-order roll-off frequency of the integrated differential input amplifier to consider for the antialiasing filter design.

(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).

(5) Offset error drift is calculated using the box method, as described by the following equation:

value_MAX- value_MIN

TempRange

TCE_O

=

(6) Gain error drift is calculated using the box method, as described by the following equation:

≈ value _MAX- value _MIN

’

6

∆

÷

TCE_G( ppm) =

ì10

value ìTempRange

«

◊

8

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Electrical Characteristics: AMC1306x05 (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –50 mV to 50 mV, AINN = AGND, and sinc³filter with OSR = 256 (unless otherwise noted); typical specifications are

at T_A= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V

PARAMETER

DIGITAL INPUTS/OUTPUTS

CMOS Logic With Schmitt-Trigger

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_IN

Input current

DGND ≤ V_IN≤ DVDD

0

7

µA

pF

V

C_IN

V_IH

Input capacitance

4

High-level input voltage

Low-level input voltage

Output load capacitance

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

V_IL

V

C_LOAD

30

pF

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

I_OL= 4 mA

DVDD – 0.1

DVDD – 0.4

V_OH

High-level output voltage

Low-level output voltage

V

0.1

0.4

V_OL

POWER SUPPLY

AVDD

High-side supply voltage

3.0

2.7

5.0

6.3

7.2

3.3

5.5

8.5

9.8

5.5

V

mA

V

3.0 V ≤ AVDD ≤ 3.6 V

4.5 V ≤ AVDD ≤ 5.5 V

I_AVDD

High-side supply current

DVDD Controller-side supply voltage

AMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

4.1

3.3

5.0

3.9

5.5

4.8

6.9

6.0

AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

I_DVDD

Controller-side supply current

mA

AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

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7.10 Electrical Characteristics: AMC1306x25

minimum and maximum specifications apply from T_A= –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –250 mV to 250 mV, AINN = AGND, and sinc³filter with OSR = 256 (unless otherwise noted); typical specifications

are at T_A= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

V_ClippingDifferential input voltage before clipping output AINP – AINN

±320

mV

V

FSR

Specified linear differential full-scale

Absolute common-mode input voltage⁽¹⁾

Operating common-mode input voltage

Common-mode overvoltage detection level⁽²⁾

Single-ended input capacitance

Differential input capacitance

Input bias current

AINP – AINN

–250

–2

250

AVDD

(AINP + AINN) / 2 to AGND

AINN = AGND

V_CM

V_CMov

C_IN

–0.16

AVDD – 2.1

V

AVDD – 2

V

2

1

pF

µA

kΩ

nA

kV/µs

C_IND

I_IB

AINP = AINN = AGND, I_IB= I_IBP+ I_IBN

AINN = AGND

–82

50

–60

19

–48

R_IN

Single-ended input resistance

Differential input resistance

R_IND

I_IO

22

Input offset current

±5

CMTI

Common-mode transient immunity

100

AINP = AINN, f_IN= 0 Hz,

–95

V_{CM min}≤ V_IN≤ V_{CM max}

CMRR Common-mode rejection ratio

dB

AINP = AINN, f_INfrom 0.1 Hz to 50 kHz,

–95

900

V_{CM min}≤ V_IN≤ V_{CM max}

BW

DC ACCURACY

Input bandwidth⁽³⁾

kHz

DNL

INL

Differential nonlinearity

Integral nonlinearity⁽⁴⁾

Resolution: 16 bits

–0.99

–4

0.99

4

LSB

µV

Resolution: 16 bits

±1

±4.5

E_O

Offset error

Initial, at 25°C, AINP = AINN = AGND

–100

–1

100

1

TCE_O

E_G

Offset error thermal drift⁽⁵⁾

Gain error

Gain error thermal drift⁽⁶⁾

±0.15

µV/°C

Initial, at 25°C

–0.2%

–40

±0.005%

±20

0.2%

40

TCE_G

ppm/°C

dB

AINP = AINN = AGND,

3.0 V ≤ AVDD ≤ 5.5 V, at dc

–103

PSRR Power-supply rejection ratio

AINP = AINN = AGND,

3.0 V ≤ AVDD ≤ 5.5 V,

10 kHz, 100-mV ripple

–92

AC ACCURACY

SNR

Signal-to-noise ratio

f_IN= 1 kHz

82

86

dB

SINAD Signal-to-noise + distortion

81.9

85.7

4.5 V ≤ AVDD ≤ 5.5 V,

5 MHz ≤ f_CLKIN≤ 21 MHz, f_IN= 1 kHz

–98

–86

–85

THD

Total harmonic distortion

dB

3.0 V ≤ AVDD ≤ 3.6 V,

5 MHz ≤ f_CLKIN≤ 20 MHz, f_IN= 1 kHz

–93

100

SFDR

Spurious-free dynamic range

f_IN= 1 kHz

83

(1) Steady-state voltage supported by the device in case of a system failure; see the specified common-mode input voltage V_CMfor normal

operation. Adhere to the analog input voltage range as specified in the Absolute Maximum Ratings table.

(2) The common-mode overvoltage detection level has a typical hysteresis of 90 mV.

(3) This parameter is the –3-dB, second-order, roll-off frequency of the integrated differential input amplifier to consider for antialiasing filter

designs.

(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

value_MAX- value_MIN

TempRange

TCE_O

=

(5) Offset error drift is calculated using the box method, as described by the following equation:

.

≈ value _MAX- value _MIN

’

6

∆

÷

TCE_G( ppm) =

ì10

value ìTempRange

«

◊

(6) Gain error drift is calculated using the box method, as described by the following equation:

.

10

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ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

Electrical Characteristics: AMC1306x25 (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –250 mV to 250 mV, AINN = AGND, and sinc³filter with OSR = 256 (unless otherwise noted); typical specifications

are at T_A= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V

PARAMETER

DIGITAL INPUTS/OUTPUTS

CMOS Logic with Schmitt-trigger

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_IN

Input current

DGND ≤ V_IN≤ DVDD

0

7

μA

pF

V

C_IN

V_IH

Input capacitance

4

High-level input voltage

Low-level input voltage

Output load capacitance

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

V_IL

V

C_LOAD

f_CLKIN= 20 MHz

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

30

pF

DVDD – 0.1

DVDD – 0.4

V_OH

High-level output voltage

Low-level output voltage

V

0.1

0.4

V_OL

I_OL= 4 mA

POWER SUPPLY

AVDD High-side supply voltage

3.0

2.7

5.0

6.3

7.2

3.3

5.5

8.5

9.8

5.5

V

mA

V

3.0 V ≤ AVDD ≤ 3.6 V

4.5 V ≤ AVDD ≤ 5.5 V

I_AVDD

High-side supply current

DVDD Controller-side supply voltage

AMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

4.1

3.3

5.0

3.9

5.5

4.8

6.9

6.0

AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

I_DVDD

Controller-side supply current

mA

AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

11

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7.11 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

4.5 V ≤ AVDD ≤ 5.5 V

MIN

5

TYP

MAX

UNIT

21

20

f_CLKIN

CLKIN clock frequency

MHz

3.0 V ≤ AVDD ≤ 5.5 V

4.5 V ≤ AVDD ≤ 5.5 V

3.0 V ≤ AVDD ≤ 5.5 V

5

47.6

50

20

200

120

t_CLKIN

CLKIN clock period

ns

t_HIGH

t_LOW

CLKIN clock high time

CLKIN clock low time

25

ns

DOUT hold time after rising edge AMC1306Mx⁽¹⁾

,

t_H

t_D

3.5

ns

of CLKIN

C_LOAD= 15 pF

Rising edge of CLKIN to DOUT

valid delay

AMC1306Mx⁽¹⁾, C_LOAD= 15 pF

15

3.5

3.9

3.5

3.9

32

10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,

0.8

1.8

0.8

1.8

C_LOAD= 15 pF

t_r

DOUT rise time

DOUT fall time

ns

10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

t_f

90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

DVDD at 2.7 V (min) to DOUT valid with

AVDD ≥ 3.0 V

CLKIN

cycles

t_ISTARTInterface startup time

t_ASTARTAnalog startup time

32

AVDD step to 3.0 V with DVDD ≥ 2.7 V,

0.1% settling

0.5

ms

(1) The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns;

see the Manchester Coding Feature section for additional details.

t_CLKIN

t_HIGH

CLKIN

t_LOW

t_H

t_D

t_r/ t_f

DOUT

Figure 1. Digital Interface Timing

AVDD

DVDD

t_ASTART

CLKIN

DOUT

...

Bitream not valid

(analog settling)

Test Pattern

Valid bitstream

t_ISTART

Figure 2. Device Startup Timing

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7.12 Insulation Characteristics Curves

500

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

AVDD = DVDD = 3.6 V

AVDD = DVDD = 5.5 V

400

300

200

100

0

50

100

T_A(°C)

150

200

0

50

100

T_A(°C)

150

200

D001

D002

Figure 3. Thermal Derating Curve for Safety-Limiting

Current per VDE

Figure 4. Thermal Derating Curve for Safety-Limiting

Power per VDE

1.E+11

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

TDDB Line (<1 PPM Fail Rate)

1.E+10

87.5%

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

20%

1.E+2

1.E+1

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

T_Aup to 150°C, stress-voltage frequency = 60 Hz,

isolation working voltage = 1500 V_RMS, operating lifetime = 135 years

Figure 5. Reinforced Isolation Capacitor Lifetime Projection

13

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7.13 Typical Characteristics

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25),

AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless otherwise noted)

4

3.5

3

3.3

3.25

3.2

3.15

3.1

2.5

2

3.05

3

1.5

1

2.95

2.9

0.5

3

3.5

4

4.5

AVDD (V)

5

5.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

D003

D004

Figure 6. Maximum Operating Common-Mode Input Voltage

vs High-Side Supply Voltage

Figure 7. Common-Mode Overvoltage Detection Level vs

Temperature

60

40

20

0

AMC1306x25

AMC1306x05

-20

-40

-60

-80

-20

-40

-100

-60

AMC1306x25

AMC1306x05

-80

-0.5

-120

0.1

0

0.5

1

1.5

V_CM(V)

2

2.5 3 3.5

1

10

f_IN(kHz)

100

1000

D005

D006

Figure 8. Input Bias Current vs

Common-Mode Input Voltage

Figure 9. Common-Mode Rejection Ratio vs

Input Signal Frequency

4

100

75

AMC1306x

AMC1306x05, AVDD = 3.3 V

AMC1306x25

AMC1306x05

3.5

3

50

2.5

2

25

0

1.5

1

-25

-50

-75

-100

0.5

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

3

3.5

4

4.5

AVDD (V)

5

5.5

D008

D009

Figure 10. Integral Nonlinearity vs Temperature

Figure 11. Offset Error vs High-Side Supply Voltage

14

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25),

AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless otherwise noted)

100

AMC1306x25

AMC1306x05

80

60

40

20

0

-20

-40

-60

-80

-100

-20

-40

-60

-80

-100

Device 1

Device 2

Device 3

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

9

13

f_CLKIN(MHz)

17

21

D010

D011

Figure 12. Offset Error vs Temperature

Figure 13. Offset Error vs Clock Frequency

0.25

0.2

0.3

0.2

0.1

0

0.15

0.1

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.25

-0.1

-0.2

-0.3

3

3.5

4

4.5

AVDD (V)

5

5.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

D012

D013

Figure 14. Gain Error vs High-Side Supply Voltage

Figure 15. Gain Error vs Temperature

0

-20

0.3

0.2

0.1

0

AMC1306x25

AMC1306x05

-40

-60

-80

-0.1

-0.2

-0.3

-100

-120

5

9

13

f_CLKIN(MHz)

17

21

0.1 0.2 0.5

1

2

3 45 7 10 2030 50 100 200 5001000

Ripple Frequency (kHz)

D014

D015

Figure 16. Gain Error vs Clock Frequency

Figure 17. Power-Supply Rejection Ratio vs

Ripple Frequency

15

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25),

AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless otherwise noted)

90

89

88

87

86

85

84

83

82

81

80

90

89

88

87

86

85

84

83

82

81

80

AMC1306x25, SNR

AMC1306x25, SINAD

AMC1306x05, SNR

AMC1306x05, SINAD

AMC1306x25, SNR

AMC1306x25, SINAD

AMC1306x05, SNR

AMC1306x05, SINAD

3

3.5

4

4.5

AVDD (V)

5

5.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

D016

D017

Figure 18. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs High-Side Supply Voltage

Figure 19. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Temperature

90

88

AMC1306x25, SNR

AMC1306x25, SINAD

AMC1306x05, SNR

AMC1306x05, SINAD

89

88

87

86

85

84

83

82

81

80

86

84

82

80

78

76

74

72

70

AMC1306x25, SNR

AMC1306x25, SINAD

AMC1306x05, SNR

AMC1306x05, SINAD

5

9

13

f_CLKIN(MHz)

17

21

0.1

1

10

100

f_IN(kHz)

D018

D019

Figure 20. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Clock Frequency

Figure 21. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Input Signal Frequency

100

95

AMC1306x25, SNR

AMC1306x25, SINAD

AMC1306x05, SNR

AMC1306x05, SINAD

95

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

45

0

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

0

10

20

30

40

50

V_IN(mVpp)

60

70

80

90 100

D020

D042

Figure 22. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Input Signal Amplitude

Figure 23. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Input Signal Amplitude

16

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25),

AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless otherwise noted)

-86

-88

-90

-92

-94

-96

-98

-100

-102

-104

-106

-108

-110

-100

-102

-104

-106

-108

-110

4.5

4.75

5

AVDD (V)

5.25

5.5

3

3.5

4

4.5

AVDD (V)

5

5.5

D021

D039

f_CLKIN= 21 MHz

f_CLKIN= 20 MHz

Figure 24. Total Harmonic Distortion vs

High-Side Supply Voltage (5 V, nom)

Figure 25. Total Harmonic Distortion vs

High-Side Supply Voltage (3.3 V, nom)

-86

-88

-86

-88

-90

-92

-94

-96

-98

-100

-102

-104

-106

-108

-110

-100

-102

-104

-106

-108

-110

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

9

13

f_CLKIN(MHz)

17

21

D022

D023

Figure 26. Total Harmonic Distortion vs Temperature

Figure 27. Total Harmonic Distortion vs Clock Frequency

-85

-70

-75

-80

-90

-95

-85

-90

-100

-105

-110

-115

-120

-95

-100

-105

-110

-115

-120

0.1

1

f_IN(kHz)

10

0

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

D024

D025

AMC1306x25

Figure 28. Total Harmonic Distortion vs

Input Signal Frequency

Figure 29. Total Harmonic Distortion vs

Input Signal Amplitude

17

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25),

AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless otherwise noted)

-65

118

114

110

106

102

98

-70

-75

-80

-85

-90

-95

94

-100

-105

-110

-115

90

86

82

0

10

20

30

40

50

V_IN(mVpp)

60

70

80

90 100

3

5

0

3.5

4

4.5

AVDD (V)

5

5.5

D043

D026

AMC1306x05

Figure 30. Total Harmonic Distortion vs

Input Signal Amplitude

Figure 31. Spurious-Free Dynamic Range vs

High-Side Supply Voltage

118

114

110

106

102

98

118

114

110

106

102

98

94

90

86

82

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

9

13

f_CLKIN(MHz)

17

21

D027

D028

Figure 32. Spurious-Free Dynamic Range vs Temperature

Figure 33. Spurious-Free Dynamic Range vs

Clock Frequency

118

114

110

106

102

98

125

120

115

110

105

100

95

94

90

85

86

80

82

75

0.1

1

f_IN(kHz)

10

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

D029

D030

AMC1306x25

Figure 34. Spurious-Free Dynamic Range vs

Input Signal Frequency

Figure 35. Spurious-Free Dynamic Range vs

Input Signal Amplitude

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25),

AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless otherwise noted)

120

115

110

105

100

95

0

-20

-40

-60

-80

90

-100

-120

-140

-160

85

80

75

70

0

10

20

30

40

50

V_IN(mVpp)

60

70

80

90 100

0

5

10

15

Frequency (kHz)

20

25

30

35

40

D046

D044

AMC1306x05

AMC1306x05, 4096-point FFT, V_IN= 100 mV_PP

Figure 36. Spurious-Free Dynamic Range vs

Input Signal Amplitude

Figure 37. Frequency Spectrum with 1-kHz Input Signal

0

-20

0

-20

-40

-60

-80

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

5

10

15

Frequency (kHz)

20

25

30

35

40

0

5

10

15

Frequency (kHz)

20

25

30

35

40

D045

D031

AMC1306x05, 4096-point FFT, V_IN= 100 mV_PP

AMC1306x25, 4096-point FFT, V_IN= 500 mV_PP

Figure 38. Frequency Spectrum with 10-kHz Input Signal

Figure 39. Frequency Spectrum with 1-kHz Input Signal

0

10

9.5

9

-20

-40

-60

-80

8.5

8

7.5

7

6.5

6

-100

-120

-140

-160

5.5

5

4.5

4

0

5

10

15

20

Frequency (kHz)

25

30

35

40

3

3.5

4

4.5

AVDD (V)

5

5.5

D032

D033

AMC1306x25, 4096-point FFT, V_IN= 500 mV_PP

Figure 40. Frequency Spectrum with 10-kHz Input Signal

Figure 41. High-Side Supply Current vs

High-Side Supply Voltage

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Typical Characteristics (continued)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25),

AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless otherwise noted)

10

9.5

9

10

9.5

9

8.5

8

8.5

8

7.5

7

7.5

7

6.5

6

6.5

6

5.5

5

5.5

5

4.5

4

4.5

4

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

9

13

Clock Frequency (MHz)

17

21

D034

D035

Figure 42. High-Side Supply Current vs Temperature

Figure 43. High-Side Supply Current vs Clock Frequency

8

7.5

7

8

AMC1306Mx

AMC1306Ex

AMC1306Mx, DVDD = 3.3 V

AMC1306Mx, DVDD = 5 V

AMC1306Ex, DVDD = 3.3 V

AMC1306Ex, DVDD = 5 V

7.5

7

6.5

6

6.5

6

5.5

5

5.5

5

4.5

4

4.5

4

3.5

3

3.5

3

2.5

2

2.7

3.1

3.5

3.9

DVDD (V)

4.3

4.7

5.1

5.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

D036

D037

Figure 44. Controller-Side Supply Current vs

Controller-Side Supply Voltage

Figure 45. Controller-Side Supply Current vs Temperature

8

7.5

7

AMC1306Mx, DVDD = 3.3 V

AMC1306Mx, DVDD = 5 V

AMC1306Ex, DVDD = 3.3 V

AMC1306Ex, DVDD = 5 V

6.5

6

5.5

5

4.5

4

3.5

3

2.5

2

5

9

13

f_CLKIN(MHz)

17

21

D038

Figure 46. Controller-Side Supply Current vs

Clock Frequency

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8 Detailed Description

8.1 Overview

The differential analog input (comprised of input signals AINP and AINN) of the AMC1306 is a fully-differential

amplifier feeding the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes

the input signal into a 1-bit output stream. The isolated data output DOUT of the converter provides a stream of

digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin with a

frequency in the range of 5 MHz to 21 MHz. The time average of this serial bitstream output is proportional to the

analog input voltage.

The Functional Block Diagram section shows a detailed block diagram of the AMC1306. The analog input range

is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The silicon-

dioxide (SiO₂) based capacitive isolation barrier supports a high level of magnetic field immunity as described in

the ISO72x Digital Isolator Magnetic-Field Immunity application report, available for download at www.ti.com. The

external clock input simplifies the synchronization of multiple current-sensing channels on the system level. The

extended frequency range of up to 21 MHz supports higher performance levels compared to the other solutions

available on the market.

8.2 Functional Block Diagram

AVDD

DVDD

Reinforced

Isolation

Barrier

AMC1306x

AINP

AINN

ûꢀ Modulator

DOUT

Band-Gap

Reference

CLKIN

V_CM, AVDD

Diagnostic

AGND

DGND

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8.3 Feature Description

8.3.1 Analog Input

The AMC1306 incorporates front-end circuitry that contains a differential amplifier and a sampling stage, followed

by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for

devices with a specified input voltage range of ±250 mV (this value is for the AMC1306x25), or to a factor of 20

in devices with a ±50-mV input voltage range (for the AMC1306x05), resulting in a differential input impedance of

4.9 kΩ (for the AMC1306x05) or 22 kΩ (for the AMC1306x25). For reduced offset and offset drift, the differential

amplifier is chopper-stabilized with the switching frequency set at f_CLKIN/ 32. The switching frequency generates

a spur as shown in Figure 47.

0

-20

-40

-60

-80

-100

-120

-140

-160

0.1

1

10 100

Frequency (kHz)

1000

10000

D007

sinc³filter, OSR = 2, f_CLKIN= 20 MHz, f_IN= 1 kHz

Figure 47. Quantization Noise Shaping

Consider the input impedance of the AMC1306 in designs with high-impedance signal sources that can cause

degradation of gain and offset specifications. The importance of this effect, however, depends on the desired

system performance. Additionally, the input bias current caused by the internal common-mode voltage at the

output of the differential amplifier is dependent on the actual amplitude of the input signal; see the Isolated

Voltage Sensing section for more details on reducing these effects.

There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the

range AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input

electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are

ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR),

that is ±250 mV (for the AMC1306x25) or ±50 mV (for the AMC1306x05), and within the specified input common-

mode range.

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Feature Description (continued)

8.3.2 Modulator

The modulator implemented in the AMC1306 is a second-order, switched-capacitor, feed-forward ΔΣ modulator,

such as the one conceptualized in Figure 48. The analog input voltage V_INand the output V₅of the 1-bit digital-

to-analog converter (DAC) are differentiated, providing an analog voltage V₁at the input of the first integrator

stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage

V₃that is differentiated with the input signal V_INand the output of the first integrator V₂. Depending on the polarity

of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the

next clock pulse by changing the associated analog output voltage V₅, causing the integrators to progress in the

opposite direction and forcing the value of the integrator output to track the average value of the input.

f_CLKIN

V₁

V₂

V₃

V₄

V_IN

Integrator 1

Integrator 2

ꢀ

CMP

0 V

V₅

DAC

Figure 48. Block Diagram of a Second-Order Modulator

The modulator shifts the quantization noise to high frequencies, as shown in Figure 48. Therefore, use a low-

pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert

from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's

microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter

structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1306 family. Also,

SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated sinc-

filters for a simple system-level solution for multichannel, isolated current sensing. An additional option is to use a

suitable application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a field-

programmable gate array (FPGA) can be used to implement the filter.

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Feature Description (continued)

8.3.3 Isolation Channel Signal Transmission

The AMC1306 device uses an on-off keying (OOK) modulation scheme to transmit the modulator output

bitstream across the capacitive SiO₂-based isolation barrier. The transmitter modulates the bitstream at TX IN in

Figure 49 with an internally-generated, 480-MHz carrier across the isolation barrier to represent a digital one and

sends a no signal to represent the digital zero. The receiver demodulates the signal after advanced signal

conditioning and produces the output. The symmetrical design of each isolation channel improves the CMTI

performance and reduces the radiated emissions caused by the high-frequency carrier. The block diagram of an

isolation channel integrated in the AMC1306 is shown in Figure 49.

Transmitter

Receiver

OOK

Modulation

SiO₂-Based

Capacitive

Reinforced

Isolation

TX IN

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

RX OUT

Barrier

Oscillator

Figure 49. Block Diagram of an Isolation Channel

Figure 50 shows the concept of the on-off keying scheme.

TX IN

Carrier Signal Across

the Isolation Barrier

RX OUT

Figure 50. OOK-Based Modulation Scheme

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Feature Description (continued)

8.3.4 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 250 mV (for the AMC1306x25) or 50 mV (for the AMC1306x05) produces a stream of ones

and zeros that are high 89.06% of the time. With 16 bits of resolution, that percentage ideally corresponds to the

code 58368. A differential input of –250 mV (–50 mV for the AMC1306x05) produces a stream of ones and zeros

that are high 10.94% of the time and ideally results in code 7168 with 16-bit resolution. These input voltages are

also the specified linear ranges of the different AMC1306 versions with performance as specified in this

document. If the input voltage value exceeds these ranges, the output of the modulator shows nonlinear behavior

when the quantization noise increases. The output of the modulator clips with a stream of only zeros with an

input less than or equal to –320 mV (–64 mV for the AMC1306x05) or with a stream of only ones with an input

greater than or equal to 320 mV (64 mV for the AMC1306x05). In this case, however, the AMC1306 generates a

single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see

the Fail-Safe Output section for more details). The input voltage versus the output modulator signal is shown in

Figure 51.

Modulator Output

+FS (Analog Input)

-FS (Analog Input)

Analog Input

Figure 51. Analog Input versus the AMC1306 Modulator Output

The density of ones in the output bitstream for any input voltage value (with the exception of a full-scale input

signal, as described in the Output Behavior in Case of a Full-Scale Input section) can be calculated using

Equation 1:

V_IN+ V_Clipping

2ì V_Clipping

(1)

The AMC1306 system clock is provided externally at the CLKIN pin. For more details, see the Switching

Characteristics table and the Manchester Coding Feature section.

8.3.5 Manchester Coding Feature

The AMC1306Ex offers the IEEE 802.3-compliant Manchester coding feature that generates at least one

transition per bit to support clock signal recovery from the bitstream. A Manchester coded bitstream is free of dc

components. The Manchester coding combines the clock and data information using exclusive or (XOR) logical

operation and results in a bitstream as shown in Figure 52. The duty cycle of the Manchester encoded bitstream

depends on the duty cycle of the input clock CLKIN.

Clock

Uncoded

Bitstream

0

1

0

1

0

1

0

1

0

1

Machester

Coded

Bitstream

Figure 52. Manchester Coded Output of the AMC1306Ex

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8.4 Device Functional Modes

8.4.1 Fail-Safe Output

In the case of a missing high-side supply voltage AVDD, the output of a ΔΣ modulator is not defined and can

cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.

Therefore, the AMC1306 implements a fail-safe output function that ensures that the output DOUT of the device

offers a steady-state bitstream of logic 0's in case of a missing AVDD, as shown in Figure 53.

Additionally, if the common-mode voltage of the input reaches or exceeds the specified common-mode

overvoltage detection level V_CMovas defined in the Electrical Characteristics table, the AMC1306 offers a steady-

state bitstream of logic 1's at the output DOUT, as also shown in Figure 53.

t_ASTART

t_ISTART

CLKIN

...

AVDD

AVDD GOOD

Missing AVDD

AVDD GOOD

V_CM

V_CM< V_CMov

V_CM≥ V_CMov

V_CM< V_CMov

DOUT

Valid Bit Stream

1

0

Test Pattern

1

Bit Stream Not Valid Valid Bit Stream

Figure 53. Fail-Safe Output of the AMC1306

8.4.2 Output Behavior in Case of a Full-Scale Input

If a full-scale input signal is applied to the AMC1306 (that is, V_IN≥ V_Clipping), the device generates a single one or

zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 54.

In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the system level.

CLKIN

...

DOUT

V_IN≤ œ320 mV (AMC1306x05: œ64 mV)

...

V_IN≥ 320 mV (AMC1306x05: 64 mV)

127 CLKIN Cycles

Figure 54. Overrange Output of the AMC1306

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Digital Filter Usage

The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a

conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort

and hardware, is a sinc³-type filter, as shown in Equation 2:

3

-OSR

≈

’

1- z

H z =

( )

∆

÷

1- z^-1

«

◊

(2)

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-

order modulator. All the characterization in this document is also done with a sinc³filter with an oversampling

ratio (OSR) of 256 and an output word width of 16 bits.

The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.

Figure 55 shows the ENOB of the AMC1306 with different oversampling ratios. In this document, this number is

calculated from the SINAD by using Equation 3:

SINAD = 1.76 dB + 6.02 dB × ENOB

(3)

16

14

12

10

8

6

4

sinc³

sinc²

sinc¹

2

0

1

10

100

1000

OSR

D040

Figure 55. Measured Effective Number of Bits versus Oversampling Ratio

An example code for implementing a sinc³filter in an FPGA is discussed in the Combining the ADS1202 with an

FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for

download at www.ti.com.

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9.2 Typical Applications

9.2.1 Frequency Inverter Application

Isolated ΔΣ modulators are being widely used in frequency inverter designs because of their high ac and dc

performance. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters (string and

central inverters), uninterruptible power supplies (UPS), electrical and hybrid electrical vehicles, and other

industrial applications.

Figure 56 shows a simplified schematics of the AMC1306Mx in a typical frequency inverter application as used in

industrial motor drives with shunt resistors (R_SHUNT) used for current sensing. Depending on the system design,

either all three or only two motor phase currents are sensed.

The Manchester coded bitstream output of the AMC1306Ex minimizes the wiring efforts of the connection

between the power board and the control board; see Figure 57. This bitstream output also allows the clock to be

generated locally on the power board without the having to adjust the propagation delay time of each DOUT

connection to fulfill the setup and hold time requirements of the microcontroller.

In both examples, an additional fourth AMC1306 is used to support isolated voltage sensing of the dc link. This

high voltage is reduced using a high-impedance resistive divider and is sensed by the device across a smaller

resistor. The value of this resistor can degrade the performance of the measurement, as described in the Isolated

Voltage Sensing section.

Motor

DC link

R_SHUNT

L1

L3

L2

R_SHUNT

AMC1306Mx

3.3 V

AVDD

DVDD

AINP CLKIN

3.3 V

DOUT

DGND

AINN

AGND

TMS320F28x7x

AMC1306Mx

AVDD

3.3 V

DVDD

AINP CLKIN

3.3 V

SD-D1

SD-C1

DOUT

DGND

SD-D2

SD-C2

AINN

AGND

AMC1306Mx

AVDD

SD-D3

SD-C3

3.3 V

DVDD

AINP CLKIN

3.3 V

SD-D4

SD-C4

DOUT

DGND

AINN

AGND

AMC1306Mx

AVDD

CDCLVC1104

PWMx

3.3 V

DVDD

AINP CLKIN

3.3 V

DOUT

DGND

AINN

AGND

Power Board

Control Board

Figure 56. The AMC1306Mx in a Frequency Inverter Application

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Typical Applications (continued)

Motor

DC link

R_SHUNT

L1

L3

R_SHUNT

L2

AMC1306Ex

3.3 V

AVDD

AINP

DVDD

CLKIN

3.3 V

AINN DOUT

DGND

AGND

TMS320F28x7x

AMC1306Ex

AVDD

3.3 V

DVDD

AINP CLKIN

3.3 V

DOUT

DGND

AINN

SD-D1

SD-D2

SD-D3

SD-D4

AGND

AMC1306Ex

AVDD

3.3 V

DVDD

AINP CLKIN

3.3 V

DOUT

DGND

AINN

AGND

AMC1306Ex

AVDD

3.3 V

DVDD

AINP CLKIN

3.3 V

DOUT

DGND

AINN

AGND

Clock Source

Power Board

Control Board

Figure 57. The AMC1306Ex in a Frequency Inverter Application

9.2.1.1 Design Requirements

Table 1 lists the parameters for the typical application in the Frequency Inverter Application section.

Table 1. Design Requirements

PARAMETER

High-side supply voltage

VALUE

3.3 V or 5 V

Low-side supply voltage

3.3 V or 5 V

Voltage drop across the shunt for a linear response

±250 mV (maximum)

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9.2.1.2 Detailed Design Procedure

The high-side power supply (AVDD) for the AMC1306 device is derived from the power supply of the upper gate

driver. Further details are provided in the Power Supply Recommendations section.

The floating ground reference (AGND) is derived from one of the ends of the shunt resistor that is connected to

the negative input of the AMC1306 (AINN). If a four-pin shunt is used, the inputs of the device are connected to

the inner leads and AGND is connected to one of the outer shunt leads.

Use Ohm's Law to calculate the voltage drop across the shunt resistor (V_SHUNT) for the desired measured

current: V_SHUNT= I × R_SHUNT

.

Consider the following two restrictions to choose the proper value of the shunt resistor R_SHUNT

:

•

The voltage drop caused by the nominal current range must not exceed the recommended differential input

voltage range: V_SHUNT≤ ±250 mV

The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes

a clipping output: |V_SHUNT| ≤ |V_Clipping

|

The typically recommended RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the

signal path is not required for the AMC1306. By design, the input bandwidth of the analog front-end of the device

is limited as specified in the Electrical Characteristics table.

For modulator output bitstream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers

(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These families support up to eight

channels of dedicated hardwired filter structures that significantly simplify system level design by offering two

filtering paths per channel: one providing high accuracy results for the control loop and one fast response path

for overcurrent detection.

9.2.1.3 Application Curve

In motor control applications, a very fast response time for overcurrent detection is required. The time for fully

settling the filter in case of a step-signal at the input of the modulator depends on the filter order; that is, a sinc³

filter requires three data updates for full settling (with f_DATA= f_CLK/ OSR). Therefore, for overcurrent protection,

filter types other than sinc³can be a better choice; an alternative is the sinc²filter. Figure 58 compares the

settling times of different filter orders.

The delay time of the sinc filter with a continuous signal is half of the settling time.

16

14

12

10

8

6

4

sinc¹

sinc²

sinc³

2

0

2

4

6

8

10

12

Settling Time (µs)

14

16

18 20

D041

Figure 58. Measured Effective Number of Bits versus Settling Time

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9.2.2 Isolated Voltage Sensing

The AMC1306 is optimized for usage in current-sensing applications using low-impedance shunts. However, the

device can also be used in isolated voltage-sensing applications if the affect of the (usually higher) impedance of

the resistor used in this case is considered.

High Voltage

Potential

3.3 V

or 5 V

R1

AVDD

R2

R4

R5

AINP

I_IB

R3

R_IND

ûꢀ Modulator

AINN

R4'

R5'

R3'

AGND

V_CM= 1.9 V

AGND

Figure 59. Using the AMC1306 for Isolated Voltage Sensing

9.2.2.1 Design Requirements

Figure 59 shows a simplified circuit typically used in high-voltage-sensing applications. The high impedance

resistors (R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of

the sensing resistor R3 is chosen to meet the input voltage range of the AMC1306. This resistor and the

differential input impedance of the device (the AMC1306x25 is 22 kΩ, the AMC1306x05 is 4.9 kΩ) also create a

voltage divider that results in an additional gain error. With the assumption of R1, R2, and R_INhaving a

considerably higher value than R3, the resulting total gain error can be estimated using Equation 4, with E_G

being the gain error of the AMC1306.

R3

E_Gtot= E_G

+

R_IN

(4)

This gain error can be easily minimized during the initial system-level gain calibration procedure.

9.2.2.2 Detailed Design Procedure

As indicated in Figure 59, the output of the integrated differential amplifier is internally biased to a common-mode

voltage of 1.9 V. This voltage results in a bias current I_IBthrough the resistive network R4 and R5 (or R4' and

R5') used for setting the gain of the amplifier. The value range of this current is specified in the Electrical

Characteristics table. This bias current generates additional offset error that depends on the value of the resistor

R3. The initial system offset calibration does not minimize this effect because the value of the bias current

depends on the actual common-mode amplitude of the input signal (as illustrated in Figure 60). Therefore, in

systems with high accuracy requirements, a series resistor is recommended to be used at the negative input

(AINN) of the AMC1306 with a value equal to the shunt resistor R3 (that is, R3' = R3 in Figure 59) to eliminate

the effect of the bias current.

31

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

www.ti.com.cn

This additional series resistor (R3') influences the gain error of the circuit. The effect can be calculated using

Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 2.5 kΩ (for the AMC1306x05) or 12.5 kΩ (for the

AMC1306x25).

R4

≈

’

E_G(%) = 1-

ì100%

∆

÷

◊

R4'+ R3'

«

(5)

9.2.2.3 Application Curve

Figure 60 shows the dependency of the input bias current on the common-mode voltage at the input of the

AMC1306.

60

40

20

0

-20

-40

-60

AMC1306x25

AMC1306x05

-80

-0.5

0

0.5

1

1.5

V_CM(V)

2

2.5 3 3.5

D005

Figure 60. Input Bias Current vs Common-Mode Input Voltage

9.2.3 What To Do and What Not To Do

Do not leave the inputs of the AMC1306 unconnected (floating) when the device is powered up. If both modulator

inputs are left floating, the input bias current drives these inputs to the output common-mode of the analog front-

end of approximately 1.9 V. If that voltage is above the specified input common-mode range, the front gain

diminishes and the modulator outputs a bitstream resembling a zero input differential voltage.

32

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

www.ti.com.cn

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

10 Power Supply Recommendations

In a typical frequency-inverter application, the high-side power supply (AVDD) for the device is directly derived

from the floating power supply of the upper gate driver. For lowest system-level cost, a Zener diode can be used

to limit the voltage to 5 V or 3.3 V (±10%). Alternatively a low-cost low-drop regulator (LDO), for example the

LM317-N, can be used to adjust the supply voltage level and minimize noise on the power-supply node. A low-

ESR decoupling capacitor of 0.1 µF is recommended for filtering this power-supply path. Place this capacitor (C2

in Figure 61) as close as possible to the AVDD pin of the AMC1306 for best performance. If better filtering is

required, an additional 10-µF capacitor can be used.

The floating ground reference (AGND) is derived from the end of the shunt resistor that is connected to the

negative input (AINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads

and AGND is connected to one of the outer leads of the shunt.

For decoupling of the digital power supply on the controller side, a 0.1-µF capacitor is recommended to be

placed as close to the DVDD pin of the AMC1306 as possible, followed by an additional capacitor in the range of

1 µF to 10 µF.

Floating

Power Supply

20 V

HV+

R1

800 ꢀ

AMC1306Mx

Gate Driver

3.0 V,

3.3 V,

or 5.0 V

5.1 V

AVDD

DVDD

C1

10 ꢁF

C4

0.1 ꢁF

C2

0.1 ꢁF

C5

2.2 ꢁF

Z1

1N751A

AGND

AINN

AINP

DGND

DOUT

CLKIN

R_SHUNT

To Load

SD-Dx

SD-Cx

PWMx

Gate Driver

TMS320F2837x

HV-

Figure 61. Decoupling the AMC1306

33

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

A layout recommendation showing the critical placement of the decoupling capacitors (as close as possible to the

AMC1306) and placement of the other components required by the device is shown in Figure 62. For best

performance, place the shunt resistor close to the AINP and AINN inputs of the AMC1306 and keep the layout of

both connections symmetrical.

11.2 Layout Example

Clearance area,

to be kept free of any

conductive materials.

0.1 µF

2.2 µF

0.1 µF

SMD

0603

SMD

0603

SMD

0603

SMD

0603

To Floating

Power

Supply

1

AVDD

AINP

DVDD

CLKIN

DOUT

DGND

16

SMD

R_FLT

From Clock

Source

0603

C_FLT

AMC1306x

SMD

0603

To Digital

Filter

(MCU)

SMD

R_FLT

AINN

AGND

0603

LEGEND

Copper Pour and Traces

High-Side Area

Controller-Side Area

Via to Ground Plane

Via to Supply Plane

Figure 62. Recommended Layout of the AMC1306x

34

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

www.ti.com.cn

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

12.1.1.1 隔离相关术语

请参阅《隔离相关术语》

12.2 文档支持

12.2.1 相关文档

请参阅如下相关文档：

•

《适用于二阶 Δ-Σ 调制器的 AMC1210 四路数字滤波器》

《MSP430F677x 多相位仪表计量 SoC》

《TMS320F2807x Piccolo™ 微控制器》

《TMS320F2837xD 双核 Delfino™ 微控制器》

《ISO72x 数字隔离器磁场抗扰度》

《将 ADS1202 与 FPGA 数字滤波器结合，以便在电机控制应用中进行电流测量》

《CDCLVC11xx 3.3V 和 2.5V LVCMOS 高性能时钟缓冲器系列》

12.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。

表 2. 相关链接

器件

产品文件夹

单击此处

立即订购

单击此处

技术文档

单击此处

工具与软件

单击此处

支持和社区

单击此处

AMC1306E05

AMC1306E25

AMC1306M05

AMC1306M25

12.4 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.5 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.6 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

35

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

ZHCSG26C –MARCH 2017–REVISED JANAURY 2020

www.ti.com.cn

12.8 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

36

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AMC1306E05DWVR

AMC1306E25DWVR

AMC1306M05DWVR

AMC1306M25DWVR

SOIC

DWV

8

1000

330.0

16.4

12.05 6.15

3.3

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

AMC1306E05DWVR

AMC1306E25DWVR

AMC1306M05DWVR

AMC1306M25DWVR

SOIC

DWV

8

1000

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

AMC1306E05DWV

AMC1306E25DWV

AMC1306M05DWV

AMC1306M25DWV

DWV

SOIC

8

64

505.46

13.94

4826

6.6

Pack Materials-Page 3

PACKAGE OUTLINE

DWV0008A

SOIC - 2.8 mm max height

S

C

A

L

E

2

.

0

SOIC

C

SEATING PLANE

11.5 0.25

TYP

PIN 1 ID

AREA

0.1 C

6X 1.27

8

1

2X

5.95

5.75

NOTE 3

3.81

4

5

0.51

0.31

8X

7.6

7.4

0.25

C A

B

A

B

2.8 MAX

NOTE 4

0.33

0.13

TYP

SEE DETAIL A

(2.286)

0.25

GAGE PLANE

0.46

0.36

0 -8

1.0

0.5

DETAIL A

TYPICAL

(2)

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DWV0008A

SOIC - 2.8 mm max height

SOIC

8X (1.8)

SEE DETAILS

SYMM

8X (0.6)

6X (1.27)

(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWV0008A

SOIC - 2.8 mm max height

SOIC

SYMM

8X (1.8)

8X (0.6)

SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AMC1306E05DWVR
厂家：	TEXAS INSTRUMENTS
描述：	具有曼彻斯特编码的 ±50mV 输入、精密电流检测增强型隔离式调制器 \| DWV \| 8 \| -40 to 125 光电二极管
文件：	总45页 (文件大小：2010K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AMC1306E05DWVR [TI]

相关型号：

AMC1306E25

AMC1306E25DWV

AMC1306E25DWVR

AMC1306M05

AMC1306M05-Q1

AMC1306M05DWV

AMC1306M05DWVR

AMC1306M05QDWVRQ1

AMC1306M25

AMC1306M25-Q1

AMC1306M25DWV

AMC1306M25DWVR