AMC1306M25-Q1 [TI]
汽车类 ±250mV 输入、精密电流检测增强型隔离式调制器;
| 型号： | AMC1306M25-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 ±250mV 输入、精密电流检测增强型隔离式调制器 |
| 文件： | 总35页 (文件大小：1881K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMC1306M25-Q1
ZHCSPG7 –FEBRUARY 2022
AMC1306M25-Q1 汽车类高精度±250mV 输入
增强型隔离式Δ-Σ 调制器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 提供功能安全
AMC1306M25-Q1 是一款精密 Δ-Σ 调制器，此调制
器的输出与输入电路由抗电磁干扰性能极强的隔离层隔
开。该隔离栅经认证可提供高达 7070VPEAK 的增强型
隔离，符合 DIN VDE V 0884-11 和 UL1577 标准，并
且可支持最高 1.5kVRMS 的工作电压。该隔离层可将系
统中以不同共模电压电平运行的各器件隔开，防止高电
压冲击导致低压侧器件电气损坏或对操作员造成伤害。
– 有助于进行功能安全系统设计的文档
• 线性输入电压范围：±250mV
• 低直流误差：
– 失调电压误差：±100μV（最大值）
– 温漂1μV/°C（最大值）
– 增益误差：±0.2%（最大值）
– 增益漂移：±40ppm/°C（最大值）
• 高CMTI：100kV/µs（最小值）
• 低EMI：符合CISPR-11 和CISPR-25 标准
• 安全相关认证：
AMC1306M25-Q1 的输入端经过了优化，可直接连接
到分流电阻器或其他低电压电平信号源。具有出色的直
流精度和低温漂，可支持精确的电流控制，适用于车载
充电器 (OBC)、直流/直流转换器、牵引逆变器或其他
高压应用。通过使用集成式数字滤波器（ 如
TMS320F2807x 或 TMS320F2837x 微控制器系列中
的滤波器）来抽取位流，该器件可在 78kSPS 数据速
率下实现85dB 动态范围的16 位分辨率。
– 符合DIN VDE V 0884-11 标准的7070VPEAK 增
强型隔离：2017-01
– 符合UL1577 标准且长达1 分钟的5000VRMS
隔离
AMC1306M25-Q1 采用宽体 8 引脚 SOIC 封装，符合
面向汽车应用的 AEC-Q100 标准，并支持 –40°C 至
+125°C 的温度范围。
2 应用
器件信息(1)
• 基于分流电阻器的电流感应和隔离式电压测量，包
括：
– 牵引逆变器
封装尺寸（标称值）
器件型号
封装
AMC1306M25-Q1
SOIC (8)
5.85mm × 7.50mm
– 车载充电器
– 直流/直流转换器
– 混合动力汽车/电动汽车直流充电器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
High-side supply
(3.3 V or 5 V)
Low-side supply
(3.3 V or 5 V)
AMC1306M25-Q1
AVDD
INP
DVDD
CLKIN
I
+250 mV
–250 mV
0 V
ISO
-ADC
MCU
INN
DOUT
DGND
AGND
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASAH9
AMC1306M25-Q1
ZHCSPG7 –FEBRUARY 2022
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Table of Contents
7.2 Functional Block Diagram.........................................19
7.3 Feature Description...................................................20
7.4 Device Functional Modes..........................................23
8 Application and Implementation..................................24
8.1 Application Information............................................. 24
8.2 Typical Application.................................................... 24
8.3 What to Do and What Not to Do............................... 27
9 Power Supply Recommendations................................28
10 Layout...........................................................................28
10.1 Layout Guidelines................................................... 28
10.2 Layout Example...................................................... 28
11 Device and Documentation Support..........................29
11.1 Documentation Support.......................................... 29
11.2 接收文档更新通知................................................... 29
11.3 支持资源..................................................................29
11.4 Trademarks............................................................. 29
11.5 Electrostatic Discharge Caution..............................29
11.6 术语表..................................................................... 29
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 6
6.7 Safety-Related Certifications...................................... 7
Safety Limiting Values.......................................................7
6.8 Electrical Characteristics.............................................8
Switching Characteristics................................................11
6.9 Timing Diagrams....................................................... 11
6.10 Insulation Characteristics Curves........................... 12
6.11 Typical Characteristics............................................ 13
7 Detailed Description......................................................19
7.1 Overview...................................................................19
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
February 2022
*
Initial Release
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5 Pin Configuration and Functions
AVDD
INP
1
2
3
4
8
7
6
5
DVDD
CLKIN
DOUT
DGND
INN
AGND
Not to scale
图5-1. DWV Package, 8-Pin SOIC (Top View)
表5-1. Pin Functions
PIN
NAME
TYPE
NO.
1
DESCRIPTION
AVDD
INP
High-side power
Analog input
Analog (high-side) power supply(1)
Noninverting analog input
Inverting analog input
2
3
INN
Analog input
4
AGND
DGND
DOUT
CLKIN
DVDD
High-side ground
Low-side ground
Digital output
Analog (high-side) ground reference
Digital (low-side) ground reference
Modulator data output
5
6
7
Digital input
Modulator clock input with internal pulldown resistor (typical value: 1.5 MΩ)
8
Low-side power
Digital (low-side) power supply(1)
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
PARAMETER
MIN
–0.3
MAX
6.5
UNIT
AVDD to AGND
Power-supply voltage
V
DVDD to DGND
INP, INN
CLKIN
6.5
–0.3
Analog input voltage
Digital input voltage
Digital output voltage
AVDD + 0.5V
DVDD + 0.5
DVDD + 0.5
V
V
V
AGND –6
DGND –0.5
DGND –0.5
DOUT
Continuous, any pin except power-
supply pins
Input current
Temperature
10
mA
°C
–10
Junction, TJ
Storage, Tstg
150
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions . If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
,
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011,
CDM ESD classification level C6
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVDD
DVDD
Hgh-side power supply
Low-side power supply
AVDD to AGND
DVDD to DGND
3
5.0
3.3
5.5
5.5
V
V
2.7
ANALOG INPUT
VClipping Differential input voltage before clipping output
±320
mV
mV
VIN = VINP –VINN
VIN = VINP –VINN
VFSR
VCM
DIGITAL I/O
Specified linear differential full-scale voltage
250
–250
AVDD –
2.1
Operating common-mode input voltage
(VINP + VINN) / 2 to AGND
V
–0.16
VIO
Digital input / output voltage
0
5
VDD
21
V
20
20
25
25
4.5 V ≤AVDD ≤5.5 V
3.0 V ≤AVDD ≤5.5 V
fCLKIN
Input clock frequency
MHz
5
20
tHIGH
tLOW
Input clock high time
Input clock low time
20
20
120
120
ns
ns
TEMPERATURE RANGE
TA Specified ambient temperature
125
°C
–40
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6.4 Thermal Information
AMC1306M25-Q1
THERMAL METRIC(1)
DWV (SOIC)
8 PINS
112.2
47.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
60.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
23.1
60.0
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
AVDD = DVDD = 5.5 V
VALUE
87
UNIT
PD
Maximum power dissipation (both sides)
mW
AVDD = 3.6 V
AVDD = 5.5 V
DVDD = 3.6 V
DVDD = 5.5 V
31
PD1
Maximum power dissipation (high-side supply)
Maximum power dissipation (low-side supply)
mW
mW
54
17
PD2
33
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UNIT
6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance(1)
External creepage(1)
Shortest pin-to-pin distance through air
mm
mm
≥8.5
≥8.5
CPG
Shortest pin-to-pin distance across the package surface
Distance through
insulation
DTI
CTI
Minimum internal gap (internal clearance) of the double insulation
DIN EN 60112 (VDE 0303-11); IEC 60112
mm
V
≥0.021
≥600
Comparative tracking
index
Material group
According to IEC 60664-1
I
I-IV
I-III
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
Overvoltage category
per IEC 60664-1
DIN VDE V 0884-11: 2017-01(2)
Maximum repetitive peak
VIORM
At AC voltage
2120
VPK
isolation voltage
At AC voltage (sine wave)
1500
2120
7070
8480
VRMS
VDC
Maximum-rated isolation
VIOWM
working voltage
At DC voltage
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Maximum transient
VIOTM
VPK
VPK
isolation voltage
Maximum surge
VIOSM
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
≤5
≤5
isolation voltage(3)
Method a, after input/output safety test subgroups 2 & 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and preconditioning
(type test),
≤5
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s
Barrier capacitance,
input to output(5)
CIO
RIO
VIO = 0.5 VPP at 1 MHz
~1.5
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(5)
VIO = 500 V at 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL1577
VTEST = VISO = 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
VISO
Withstand isolation voltage
5000
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11):
2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition program
Reinforced insulation
Single protection
Certificate number: pending
File number: pending
Safety Limiting Values
PARAMETER
TEST CONDITIONS
θJA = 112.2°C/W, AVDD = DVDD = 5.5 V,
TJ = 150°C, TA = 25°C
θJA = 112.2°C/W, AVDD = DVDD = 3.6 V,
TJ = 150°C, TA = 25°C
θJA = 112.2°C/W, TJ = 150°C, TA = 25°C
MIN
TYP
MAX UNIT
R
203
309
mA
mA
IS
Safety input, output, or supply current
R
PS Safety input, output, or total power(1)
TS Maximum safety temperature
R
1114
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × AVDDmax + IS × DVDDmax, where AVDDmax is the maximum high-side voltage and DVDDmax is the maximum controller-side
supply voltage.
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6.8 Electrical Characteristics
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, INP = –
250 mV to 250 mV, INN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA
= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUTS
Common-mode overvoltage
detection level
VCMov
(INP + INN) / 2 to AGND
V
AVDD –2
CIN
Single-ended input capacitance
Differential input capacitance
Input bias current
INN = AGND
2
1
pF
pF
CIND
IIB
INP = INN = AGND, IIB = IBP + IBN
INN = AGND
–82
–60
19
–48
μA
kΩ
RIN
Single-ended input resistance
Differential input resistance
Input offset current
RIND
IIO
22
kΩ
±5
nA
CMTI
Common-mode transient immunity
100
150
kV/μs
INP = INN, fIN = 0 Hz,
–95
V
CM min ≤VIN ≤VCM max
INP = INN, fIN from 0.1 Hz to 50 kHz,
CM min ≤VIN ≤VCM max
CMRR
BW
Common-mode rejection ratio
Input bandwidth
dB
–95
V
900
kHz
DC ACCURACY
DNL
INL
Differential nonlinearity
Resolution: 16 bits
0.99
4
LSB
LSB
µV
–0.99
–4
Integral nonlinearity(2)
Offset error(1)
Resolution: 16 bits
±1
EO
TA = 25°C, INP = INN = GND1
±4.5
100
1
–100
–1
TCEO
EG
Offset error temperature drift(3)
Gain error
µV/°C
TA = 25°C
±0.005%
±20
0.2%
–0.2%
–40
TCEG
Gain error temperature drift(4)
40 ppm/°C
dB
INP = INN = AGND,
AVDD from 3.0 V to 5.5 V, at DC
–103
–92
PSRR
Power-supply rejection ratio
INP = INN = AGND,
AVDD from 3.0 V to 5.5 V,
10 kHz / 100 mV ripple
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
fIN = 1 kHz
82
86
dB
dB
SINAD
Signal-to-noise + distortion
Total harmonic distortion(5)
Spurious-free dynamic range
81.9
85.7
4.5 V ≤AVDD ≤5.5 V, fIN = 1 kHz,
5 MHz ≤fCLKIN ≤21 MHz
–98
–86
THD
dB
dB
3.0 V ≤AVDD ≤3.6 V, fIN = 1 kHz,
5 MHz ≤fCLKIN ≤20 MHz
–93
–85
SFDR
fIN = 1 kHz
83
0
100
CMOS LOGIC WITH SCHMITT-TRIGGER
IIN
Input current
7
DGND ≤VIN ≤DVDD
μA
CIN
Input capacitance
4
pF
0.7 ×
DVDD
DVDD +
0.3
VIH
High-level input voltage
V
0.3 ×
DVDD
VIL
Low-level input voltage
Output load capacitance
High-level output voltage
V
pF
V
–0.3
CLOAD
VOH
30
DVDD –
IOH = –4 mA
0.4
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6.8 Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, INP = –
250 mV to 250 mV, INN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA
= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOL
Low-level output voltage
IOL = 4 mA
0.4
V
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6.8 Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, INP = –
250 mV to 250 mV, INN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA
= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
6.3
7.2
8.5
mA
9.8
3.0 V ≤AVDD ≤3.6 V
IAVDD
High-side supply current
Low-side supply current
4.5 V ≤AVDD ≤5.5 V
2.7 V ≤DVDD ≤3.6 V,
CLOAD = 15 pF
3.3
3.9
4.8
mA
6.0
IDVDD
4.5 V ≤DVDD ≤5.5 V,
CLOAD = 15 pF
AVDD rising
AVDD falling
DVDD rising
DVDD falling
2.45
2.4
2.7
2.6
2.9
V
High-side undervoltage detection
threshold
AVDDUV
DVDDUV
2.8
2.2
2.45
2.0
2.65
V
2.2
Low-side undervoltage detection
threshold
1.75
(1) This parameter is input referred.
(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(3) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCEO = (EO,MAX –EO,MIN) / TempRange where EO,MAX and EO,MIN refer to the maximum and minimum EO values measured within the
temperature range (–40 to 125℃).
(4) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %)
measured within the temperature range (–40 to 125℃).
(5) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.
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Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DOUT hold time after rising edge
of CLKIN
tH
CLOAD = 15 pF
CLOAD = 15 pF
3.5
ns
Rising edge of CLKIN to DOUT
valid delay
tD
15
6
ns
ns
10% to 90%, 2.7 V ≤DVDD ≤3.6 V, CLOAD = 15
pF
2.5
3.2
2.2
2.9
0.5
tr
DOUT rise time
10% to 90%, 4.5 V ≤DVDD ≤5.5 V, CLOAD = 15
pF
6
10% to 90%, 2.7 V ≤DVDD ≤3.6 V, CLOAD = 15
pF
6
tf
DOUT fall time
ns
10% to 90%, 4.5 V ≤DVDD ≤5.5 V,CLOAD = 15
pF
6
AVDD step from 0 to 3.0 V with DVDD ≥2.7 V to
bitstream valid, 0.1% settling
tSTART
Device start-up time
ms
6.9 Timing Diagrams
tCLKIN
tHIGH
CLKIN
50%
tLOW
tH
tD
tr / tf
90%
10%
DOUT
图6-1. Digital Interface Timing
DVDD
AVDD
CLKIN
DOUT
tSTART
Bitstream not valid (analog settling)
Valid bitstream
图6-2. Device Start-Up Timing
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6.10 Insulation Characteristics Curves
400
1200
1000
800
600
400
200
0
AVDD = DVDD = 3.6 V
AVDD = DVDD = 5.5 V
300
200
100
0
0
50
100
150
0
25
50
75
TA (°C)
100
125
150
TA (°C)
D070
D069
图6-4. Thermal Derating Curve for Safety-Limiting Power per
图6-3. Thermal Derating Curve for Safety-Limiting Current per
VDE
VDE
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 years
图6-5. Reinforced Isolation Capacitor Lifetime Projection
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6.11 Typical Characteristics
at AVDD = 5 V, DVDD = 3.3 V, INP = –250 mV to 250 mV, INN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256
(unless otherwise noted)
4
3.5
3
3.3
3.25
3.2
3.15
3.1
2.5
2
3.05
3
1.5
1
2.95
2.9
0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
3
3.5
4
4.5
AVDD (V)
5
5.5
Temperature (C)
D002
D001
图6-7. Common-Mode Overvoltage Detection Level vs
图6-6. Maximum Operating Common-Mode Input Voltage vs
Temperature
High-Side Supply Voltage
60
40
0
-20
20
-40
0
-60
-20
-40
-60
-80
-80
-100
-120
0.1
1
10
fIN (kHz)
100
1000
-0.5
0
0.5
1
1.5
VCM (V)
2
2.5
3
3.5
D038
D003
图6-9. Common-Mode Rejection Ratio vs Input Signal
图6-8. Input Bias Current vs Common-Mode Input Voltage
Frequency
4
3.5
3
100
75
50
25
2.5
2
0
-25
-50
-75
-100
1.5
1
0.5
0
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D027
D030
图6-11. Offset Error vs High-Side Supply Voltage
图6-10. Integral Nonlinearity vs Temperature
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6.11 Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, INP = –250 mV to 250 mV, INN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256
(unless otherwise noted)
100
80
100
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
Device 1
Device 2
Device 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
5
9
13
17
21
fCLKIN (MHz)
D026
D025
图6-12. Offset Error vs Temperature
图6-13. Offset Error vs Clock Frequency
0.25
0.2
0.3
0.2
0.1
0
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.1
-0.2
-0.3
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
D020
Temperature (C)
D021
图6-14. Gain Error vs High-Side Supply Voltage
图6-15. Gain Error vs Temperature
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
5
9
13
17
21
fCLKIN (MHz)
D022
图6-17. Power-Supply Rejection Ratio vs Ripple Frequency
图6-16. Gain Error vs Clock Frequency
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6.11 Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, INP = –250 mV to 250 mV, INN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256
(unless otherwise noted)
90
89
88
87
86
85
84
83
82
81
80
90
89
88
87
86
85
84
83
82
81
80
SNR
SINAD
SNR
SINAD
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
D034
D035
图6-18. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
图6-19. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
vs High-Side Supply Voltage
vs Temperature
90
88
86
84
82
80
78
76
74
SNR
SINAD
89
88
87
86
85
84
83
82
81
80
SNR
SINAD
72
70
5
9
13
17
21
0.1
1
10
100
fCLKIN (MHz)
fIN (kHz)
D036
D033
图6-20. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
图6-21. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
vs Clock Frequency
vs Input Signal Frequency
100
-86
-88
SNR
SINAD
95
-90
90
85
80
75
70
65
60
55
50
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
4.5
4.75
5
5.25
5.5
0
50 100 150 200 250 300 350 400 450 500
VIN (mVpp)
AVDD (V)
D056a
D032
fCLKIN = 21 MHz
图6-23. Total Harmonic Distortion vs High-Side Supply Voltage
图6-22. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
(5 V, nom)
vs Input Signal Amplitude
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6.11 Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, INP = –250 mV to 250 mV, INN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256
(unless otherwise noted)
-86
-88
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
3
3.5
4
4.5
AVDD (V)
5
5.5
D056b
fCLKIN = 20 MHz
图6-24. Total Harmonic Distortion vs High-Side Supply Voltage
图6-25. Total Harmonic Distortion vs Temperature
(3.3 V, nom)
-86
-88
-85
-90
-95
-90
-92
-94
-96
-100
-105
-110
-115
-120
-98
-100
-102
-104
-106
-108
-110
5
9
13
17
21
0.1
1
10
fCLKIN (MHz)
fIN (kHz)
D062
D052
图6-26. Total Harmonic Distortion vs Clock Frequency
图6-27. Total Harmonic Distortion vs Input Signal Frequency
-70
-75
118
114
110
106
102
98
-80
-85
-90
-95
-100
-105
-110
-115
-120
94
90
86
82
0
50 100 150 200 250 300 350 400 450 500
VIN (mVpp)
3
3.5
4
4.5
AVDD (V)
5
5.5
D049
D058
图6-28. Total Harmonic Distortion vs Input Signal Amplitude
图6-29. Spurious-Free Dynamic Range vs High-Side Supply
Voltage
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6.11 Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, INP = –250 mV to 250 mV, INN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256
(unless otherwise noted)
118
114
110
106
102
98
118
114
110
106
102
98
94
94
90
90
86
86
82
82
5
9
13
17
21
-40 -25 -10
5
20 35 50 65 80 95 110 125
fCLKIN (MHz)
Temperature (C)
D064
D061
图6-31. Spurious-Free Dynamic Range vs Clock Frequency
图6-30. Spurious-Free Dynamic Range vs Temperature
118
114
110
106
102
98
125
120
115
110
105
100
95
94
90
90
85
86
80
82
75
0.1
1
10
0
50 100 150 200 250 300 350 400 450 500
VIN (mVpp)
fIN (kHz)
D054
D051
图6-32. Spurious-Free Dynamic Range vs Input Signal
图6-33. Spurious-Free Dynamic Range vs Input Signal
Frequency
Amplitude
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Frequency (kHz)
Frequency (kHz)
D014
D015
4096-point FFT, VIN = 500 mVPP
4096-point FFT, VIN = 500 mVPP
图6-34. Frequency Spectrum With 1-kHz Input Signal
图6-35. Frequency Spectrum With 10-kHz Input Signal
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6.11 Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, INP = –250 mV to 250 mV, INN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256
(unless otherwise noted)
10
9
10
9
IAVDD vs AVDD
IDVDD vs DVDD
IAVDD
IDVDD
8
8
7
7
6
6
5
5
4
4
3
3
2
2
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
VDD (V)
Temperature (C)
D043
D044
图6-36. Supply Current vs Supply Voltage
图6-37. Supply Current vs Temperature
10
IAVDD
IDVDD
9
8
7
6
5
4
3
2
5
9
13
fCLKIN (MHz)
17
21
D045
图6-38. Supply Current vs Clock Frequency
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7 Detailed Description
7.1 Overview
The input stage of the AMC1306M25-Q1 consists of a fully differential amplifier that feeds the switched-capacitor
input of a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the analog input signal into a
digital bitstream that is transferred across the isolation barrier that separates the high-side from the low-side. The
isolated data output DOUT of the converter provides a stream of digital ones and zeros that is synchronous to
the externally provided clock source at the CLKIN pin. The time average of this serial bitstream output is
proportional to the analog input voltage. The external clock input simplifies the synchronization of multiple
current-sensing channels on the system level.
The silicon-dioxide (SiO2) based capacitive isolation barrier supports a high level of magnetic field immunity as
described in the ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used
in the AMC1306M25-Q1 to transmit data across the isolation barrier, and the isolation barrier characteristics
itself, result in high reliability and common-mode transient immunity.
7.2 Functional Block Diagram
AVDD
DVDD
CLKIN
DOUT
DGND
AMC1306M25-Q1
Diagnostics
Modulator
INP
Digital
Interface
INN
AGND
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7.3 Feature Description
7.3.1 Analog Input
The differential amplifier input stage of the AMC1306M25-Q1 feeds a second-order, switched-capacitor, feed-
forward ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a
differential input impedance of RIND. The modulator converts the analog input signal into a bitstream that is
transferred across the isolation barrier, as described in the Isolation Channel Signal Transmission section.
For reduced offset and offset drift, the differential amplifier is chopper-stabilized with the switching frequency set
at fCLKIN / 32. As shown in 图7-1, the switching frequency generates a spur at 625 kHz.
0
-20
-40
-60
-80
-100
-120
-140
-160
0.1
1
10
100
1000
10000
Frequency (kHz)
D016
sinc3 filter, OSR = 2, fCLKIN = 20 MHz, fIN = 1 kHz
图7-1. Quantization Noise Shaping
There are two restrictions on the analog input signals INP and INN. First, if the input voltages VINP or VINN
exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the
absolute maximum value because the electrostatic discharge (ESD) protection turns on. In addition, the linearity
and parametric performance of the device are ensured only when the analog input voltage remains within the
linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the
Recommended Operating Conditions table.
7.3.2 Modulator
图 7-2 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the
AMC1306M25-Q1. The analog input voltage VIN and the output V5 of the 1-bit digital-to-analog converter (DAC)
are differentiated, providing an analog voltage V1 at the input of the first integrator stage. The output of the first
integrator feeds the input of the second integrator stage, resulting in output voltage V3 that is differentiated with
the input signal VIN and the output of the first integrator V2. Depending on the polarity of the resulting voltage V4,
the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by
changing the associated analog output voltage V5, causing the integrators to progress in the opposite direction,
and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
V2
V3
V4
VIN
Integrator 1
Integrator 2
+
–
Σ
Σ
DOUT
0 V
V5
DAC
图7-2. Block Diagram of a Second-Order Modulator
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The modulator shifts the quantization noise to high frequencies, as illustrated in 图 7-1. Therefore, use a low-
pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert
the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's C2000
™ and Sitara™ microcontroller families offer a suitable programmable, hardwired filter structure termed a sigma-
delta filter module (SDFM) optimized for usage with the AMC1306M25-Q1. Alternatively, a field-programmable
gate array (FPGA) or complex programmable logic device (CPLD) can be used to implement the filter.
7.3.3 Isolation Channel Signal Transmission
The AMC1306M25-Q1 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-3, to transmit the
modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the
Functional Block Diagram transmits an internally generated, high-frequency carrier across the isolation barrier to
represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC1306M25-Q1 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and produces
the output. The AMC1306M25-Q1 transmission channel is optimized to achieve the highest level of common-
mode transient immunity (CMTI) and lowest level of radiated emissions caused by the high-frequency carrier and
RX/TX buffer switching.
Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图7-3. OOK-Based Modulation Scheme
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7.3.4 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 250 mV produces a stream of ones and zeros that are high 89.06% of the time. With 16 bits
of resolution, that percentage ideally corresponds to code 58368. A differential input of –250 mV produces a
stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with 16-bit resolution.
These input voltages are also the specified linear range of the AMC1306M25-Q1. If the input voltage value
exceeds this range, the output of the modulator shows nonlinear behavior as the quantization noise increases.
The output of the modulator clips with a constant stream of zeros with an input less than or equal to –320 mV or
with a constant stream of ones with an input greater than or equal to 320 mV. In this case, however, the
AMC1306M25-Q1 generates a single 1 (if the input is at negative full-scale) or 0 (if the input is at positive full-
scale) every 128 clock cycles to indicate proper device function (see the Output Behavior in Case of a Full-Scale
Input section for more details). 图7-4 shows the input voltage versus the output modulator signal.
+ FS (Analog Input)
Modulator Output
– FS (Analog Input)
Analog Input
图7-4. AMC1306M25-Q1 Modulator Output vs Analog Input
The density of ones in the output bitstream can be calculated using 方程式 1 for any input voltage (VIN= VINP –
VINN) value with the exception of a full-scale input signal, as described in 方程式1:
V
+ V
IN
Clipping
Clipping
ρ =
(1)
2 × V
7.3.4.1 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC1306M25-Q1 (that is, |VIN| ≥ |VClipping|), the device generates a
single one or zero every 128 bits at DOUT, as shown in 图 7-5, depending on the actual polarity of the signal
being sensed. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the
system level.
CLKIN
DOUT
DOUT
VIN –320 mV
VIN ≥ 320 mV
127 CLKIN cycles
127 CLKIN cycles
图7-5. Output of the AMC1306M25-Q1 in Case of an Input Overrange
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7.3.4.2 Output Behavior in Case of Input Common-Mode Overrange
If INN or INP is disconnected from the shunt resistor, the input bias current of the AMC1306M25-Q1 drives the
disconnected terminal towards the positive supply rail, and the common-mode input voltage increases. A similar
effect happens when there is no DC current path between INN, INP, and HGND. If the input common-mode
voltage exceeds the common-mode overvoltage detection threshold VCMov, the device provides a constant
bitstream of logic 1's at the output, as shown in 图 7-6; that is, DOUT is permanently high. A zero is not
generated every 128 clock pulses, which differentiates this condition from a valid positive full-scale input. This
feature is useful to identify interconnect problems on the board.
CLKIN
DOUT
VCM
Data valid
1
Data valid
VCM < VCMov
VCM VCMov
VCM < VCMov
图7-6. Output of the AMC1306M25-Q1 in Case of a Common-Mode Overvoltage
There is no common-mode overvoltage detection in the negative direction; thus, if the common-mode input
voltage is below the minimum VCM value specified in the Recommended Operating Conditions table, the
bitstream at the DOUT output is not determined.
7.3.4.3 Output Behavior in Case of a Missing High-Side Supply
If the high-side supply is missing, the device provides a constant bitstream of logic 0's at the output, as shown in
图7-7; that is, DOUT is permanently low. A one is not generated every 128 clock pulses, which differentiates this
condition from a valid negative full-scale input. This feature is useful to identify high-side power-supply problems
on the board.
CLKIN
DOUT
AVDD
Data valid
0
Data valid
图7-7. Output of the AMC1306M25-Q1 in Case of a Missing High-Side Supply
7.4 Device Functional Modes
The AMC1306M25-Q1 is operational when the power supplies AVDD and DVDD are applied as specified in the
Recommended Operating Conditions table.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The low analog input voltage range, excellent accuracy, and low temperature drift make the AMC1306M25-Q1 a
high-performance solution for automotive applications where shunt-based current sensing in the presence of
high common-mode voltage levels is required.
8.2 Typical Application
The AMC1306M25-Q1 is ideally suited for shunt-based, current-sensing applications where accurate current
monitoring is required in the presence of high common-mode voltages.
图 8-1 shows the AMC1306M25-Q1 in a typical application. The load current flowing through an external shunt
resistor RSHUNT produces a voltage drop that is sensed by the AMC1306M25-Q1. The AMC1306M25-Q1
digitizes the analog input signal on the high-side, transfers the data across the isolation barrier to the low-side,
and outputs the digital bitstream on the DOUT pin. The 5-V high-side power supply (AVDD) is generated from
the floating gate driver supply using a resistor (R4) and a Zener diode (D1).
The differential input, digital output, and the high common-mode transient immunity (CMTI) of the AMC1306M25-
Q1 ensure reliable and accurate operation even in high-noise environments.
Floating Gate
Driver Supply
+ DC Link
Low-side supply
(3.3 V or 5 V)
R4
1 uF 100 nF
100 nF 1 uF
5 V
AMC1306M25-Q1
AVDD
DVDD
CLKIN
DOUT
DGND
D1
10
10
10 nF
INP
RSHUNT
MCU
INN
Load
AGND
– DC Link
图8-1. Using the AMC1306M25-Q1 for Current Sensing in a Typical Application
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8.2.1 Design Requirements
表8-1 lists the parameters for this typical application.
表8-1. Design Requirements
PARAMETER
High-side supply voltage
VALUE
3.3 V or 5 V
3.3 V or 5 V
Low-side supply voltage
Voltage drop across RSHUNT for a linear response
±250 mV (maximum)
8.2.2 Detailed Design Procedure
In 图 8-1, the high-side power supply (AVDD) for the AMC1306M25-Q1 is derived from the floating power supply
of the upper gate driver, using a resistor (R4) and a Zener diode (D1).
The floating ground reference (AGND) is derived from the end of the shunt resistor that is connected to the
negative input of the AMC1306M25-Q1 (INN). If a four-pin shunt is used, the inputs of the AMC1306M25-Q1 are
connected to the inner leads and AGND is connected to the outer lead on the INN-side of the shunt. To minimize
offset and improve accuracy, route the ground connection as a separate trace that connects directly to the shunt
resistor rather than shorting AGND to INN directly at the input to the device. See the Layout section for more
details.
8.2.2.1 Shunt Resistor Sizing
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT.
Consider the following two restrictions when selecting the value of the shunt resistor, RSHUNT:
• The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range for a linear response: |VSHUNT| ≤|VFSR
|
• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: |VSHUNT| ≤|VClipping
|
8.2.2.2 Input Filter Design
Place an RC filter in front of the isolated amplifier to improve signal-to-noise performance of the signal path.
Design the input filter such that:
• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (fCLKIN
)
of the ΔΣmodulator
• The input bias current does not generate significant voltage drop across the DC impedance of the input filter
• The impedances measured from the analog inputs are equal
For most applications, the structure shown in 图8-2 achieves excellent performance.
AMC1306M25-Q1
AVDD
DVDD
CLKIN
DOUT
DGND
10
10
10 nF
INP
INN
AGND
图8-2. Differential Input Filter
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8.2.2.3 Bitstream Filtering
The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). As described by 方程式 2, a very simple
filter built with minimal effort and hardware, is a sinc3-type filter:
3
−OSR
1 − z
H z =
(2)
−1
1 − z
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-
order modulator. All characterization in this document is also done with a sinc3 filter with an oversampling ratio
(OSR) of 256 and an output word width of 16 bits, unless specified otherwise. The measured effective number of
bits (ENOB) as a function of the OSR is illustrated in 图8-3 of the Typical Application section.
A Delta Sigma Modulator Filter Calculator is available for download at www.ti.com that aids in the filter design
and selecting the right OSR and filter order to achieve the desired output resolution and filter response time.
An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with an
FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for
download at www.ti.com.
For modulator output bitstream filtering, a device from TI's C2000™ or Sitara™ microcontroller families is
recommended. These families support up to eight channels of dedicated hardwired filter structures that
significantly simplify system level design by offering two filtering paths per channel: one providing high-accuracy
results for the control loop and one fast-response path for overcurrent detection.
A delta sigma modulator filter calculator is available for download at www.ti.com that aids in the filter design and
selecting the right OSR and filter order to achieve the desired output resolution and filter response time.
8.2.3 Application Curve
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
图 8-3 shows the ENOB of the AMC1306M25-Q1 with different oversampling ratios. By using 方程式 3, this
number can also be calculated from the SINAD:
SINAD = 1.76 dB + 6.02 dB × ENOB
(3)
16
14
12
10
8
6
4
sinc3
sinc2
sinc1
2
0
1
10
100
1000
OSR
D01430
图8-3. Measured Effective Number of Bits vs Oversampling Ratio
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8.3 What to Do and What Not to Do
Do not leave the inputs of the AMC1306M25-Q1 unconnected (floating) when the device is powered up. If the
device inputs are left floating, the input bias current may drive the inputs to a positive value that exceeds the
operating common-mode input voltage and DOUT is permanently high as described in the Output Behavior in
Case of Input Common-Mode Overrange section.
Connect the high-side ground (AGND) to INN, either by a hard short or through a resistive path. A DC current
path between INN and AGND is required to define the input common-mode voltage. Take care not to exceed the
input common-mode range as specified in the Recommended Operating Conditions table. For best accuracy,
route the ground connection as a separate trace that connects directly to the shunt resistor rather than shorting
AGND to INN directly at the input to the device. See the Layout section for more details.
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9 Power Supply Recommendations
The AMC1306M25-Q1 does not require any specific power-up sequencing. The high-side power supply (AVDD)
is decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-µF capacitor (C2). The low-side
power supply (DVDD) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-µF
capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible.
The ground reference for the high-side (AGND) is derived from the end of the shunt resistor that is connected to
the negative input (INN) of the device. For best DC accuracy, use a separate trace to make this connection
instead of shorting AGND to INN directly at the device input. If a four-terminal shunt is used, the device inputs
are connected to the inner leads and AGND is connected to the outer lead on the INN-side of the shunt. 图 9-1
shows a decoupling diagram of the AMC1306M25-Q1.
INP
AVDD
DVDD
C2 1 µF
C1 100 nF
R2 10
C4 1 µF
AMC1306M25-Q1
I
C3 100 nF
AVDD
DVDD
CLKIN
DOUT
DGND
INP
from MCU
to MCU
C5
10 nF
R1 10
INN
AGND
图9-1. Decoupling of the AMC1306M25-Q1
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
10 Layout
10.1 Layout Guidelines
图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1306M25-Q1 supply pins) and placement of the other components required by the device.
For best performance, place the shunt resistor close to the INP and INN inputs of the AMC1306M25-Q1 and
keep the layout of both connections symmetrical.
10.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
C2
C1
C4
C3
INP
R2
R1
from MCU
to MCU
CLKIN
DOUT
AMC1306M25-Q1
INN
DGND
AGND
Top Metal
Inner or Bottom Layer Metal
Via
图10-1. Recommended Layout of the AMC1306M25-Q1
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Isolation Glossary application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, Delta Sigma Modulator Filter Calculator design tool
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
C2000™, Sitara™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1306M25QDWVRQ1
ACTIVE
SOIC
DWV
8
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
1306M25Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AMC1306M25-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2022
Catalog : AMC1306M25
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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