AWR2243ABGABLQ1_技术文档

AWR2243

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AWR2243 Single-Chip 76- to 81-GHz FMCW Transceiver

•

AEC-Q100 qualified

AWR2243 advanced features

1 Features

•

FMCW transceiver

– Embedded self-monitoring with limited Host

processor involvement

– Complex baseband architecture

– Option of cascading multiple devices to

increase channel count

– Integrated PLL, transmitter, receiver, baseband,

and A2D

– 76- to 81-GHz coverage with 5 GHz available

bandwidth

– Four receive channels

– Three transmit channels

– Ultra-accurate chirp engine based on

Fractional-N PLL

– TX power: 13 dBm

– RX noise figure: 12 dB

– Phase noise at 1 MHz:

– Embedded interference detection capability

Power management

– Built-in LDO Network for enhanced PSRR

– I/Os support dual voltage 3.3 V/1.8 V

Clock source

•

– Supports externally driven clock (square/sine)

at 40 MHz

•

–96 dBc/Hz (76 to 77 GHz)

–94 dBc/Hz (77 to 81 GHz)

– Supports 40 MHz crystal connection with load

capacitors

•

Built-in calibration and self-test

– Built-in firmware (ROM)

– Self-calibrating system across frequency and

temperature

Host interface

– Control interface with external processor over

SPI or I2C interface

– Data interface with external processor over

MIPI D-PHY and CSI2 v1.1

– Interrupts for Fault Reporting

Functional Safety-Compliant targeted

– Developed for functional safety applications

– Documentation is available to aid ISO 26262

functional safety system design

– Hardware integrity up to ASIL B targeted

– Safety-related certification

•

Easy hardware design

– 0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm flip

chip BGA package for easy assembly and low-

cost PCB design

– Small solution size

Supports automotive temperature operating range

2 Applications

•

Automated Highway Driving

Automatic Emergency Braking

Adaptive Cruise Control

•

Imaging Radar using Cascading Configuration

•

ISO 26262 certification by TUV Sud planned

Crystal

Power Management

RX1

RX2

Antenna

Structure

SPI/I2C

RX3

External

MCU

RX4

Automotive

Interface PHY

AWR2243

CSI2 (4 Lane Data + 1 Clock lane)

TX1

TX2

Reset

Error

TX3

MCU Clock

Figure 2-1. Radar Sensor for Automotive Applications

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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3 Description

The AWR2243 device is an integrated single-chip FMCW transceiver capable of operation in the 76- to 81-GHz

band. The device enables unprecedented levels of integration in an extremely small form factor. AWR2243 is an

ideal solution for low power, self-monitored, ultra-accurate radar systems in the automotive space.

The AWR2243 device is a self-contained FMCW transceiver single-chip solution that simplifies the

implementation of Automotive Radar sensors in the band of 76 to 81 GHz. It is built on TI’s low-power 45-nm

RFCMOS process, which enables a monolithic implementation of a 3TX, 4RX system with built-in PLL and A2D

converters. Simple programming model changes can enable a wide variety of sensor implementation (Short,

Mid, Long) with the possibility of dynamic reconfiguration for implementing a multimode sensor. Additionally, the

device is provided as a complete platform solution including reference hardware design, software drivers,

sample configurations, API guide, and user documentation.

Device Information

PART NUMBER⁽¹⁾

AWR2243ABGABLQ1 (Tray)

AWR2243ABGABLRQ1 (Reel)

AWR2243APBGABLQ1 (Tray)

AWR2243APBGABLRQ1 (Reel)

PACKAGE

FCBGA (161)

BODY SIZE

10.4 mm × 10.4 mm

(1) For more information, see Section 13, Mechanical Packaging and Orderable Information.

2

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4 Functional Block Diagram

LNA

IF

ADC

Digital Front-end

(Decimation filter

chain)

ADC output

interface

ADC Buffer

CSI2

PA

û-

Phase

Shifter

Control ⁽¹⁾

Synth

(20 GHz)

Ramp Generator

x4

Host control

interface

Synth Cycle

Counter

SPI/I2C

Multi-chip cascading⁽²⁾

RF Control / BIST

Temp⁽³⁾

GPADC

Osc.

VMON

RF/Analog Subsystem

Digital

A. Phase Shift Control:

•

0° / 180° BPM

0° / 180° BPM and 5.625° resolution control option for AWR2243, AWR2243P, and AWR1843

B. Multi-chip cascading feature is available in AWR2243P

C. Internal temperature sensor accuracy is ± 7 °C.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................2

4 Functional Block Diagram.............................................. 3

5 Revision History.............................................................. 4

6 Device Comparison.........................................................6

6.1 Related Products........................................................ 7

7 Terminal Configuration and Functions..........................8

7.1 Pin Diagram................................................................ 8

7.2 Signal Descriptions................................................... 12

8 Specifications................................................................ 16

8.1 Absolute Maximum Ratings ..................................... 16

8.2 ESD Ratings............................................................. 16

8.3 Power-On Hours (POH) ...........................................17

8.4 Recommended Operating Conditions ......................17

8.5 Power Supply Specifications ....................................18

8.6 Power Consumption Summary ................................ 19

8.7 RF Specification........................................................20

8.8 Thermal Resistance Characteristics for FCBGA

9.2 Functional Block Diagram.........................................36

9.3 Subsystems.............................................................. 37

9.4 Other Subsystems.................................................... 39

10 Monitoring and Diagnostic Mechanisms...................41

11 Applications, Implementation, and Layout............... 43

11.1 Application Information............................................43

11.2 Short-, Medium-, and Long-Range Radar...............43

11.3 Imaging Radar using Cascade Configuration......... 44

11.4 Reference Schematic..............................................45

11.5 Layout..................................................................... 46

12 Device and Documentation Support..........................51

12.1 Device Nomenclature..............................................51

12.2 Tools and Software................................................. 52

12.3 Documentation Support.......................................... 53

12.4 Support Resources................................................. 53

12.5 Trademarks.............................................................53

12.6 Electrostatic Discharge Caution..............................53

12.7 Export Control Notice..............................................53

12.8 Glossary..................................................................53

13 Mechanical, Packaging, and Orderable

Package [ABL0161] ....................................................21

8.9 Timing and Switching Characteristics....................... 22

9 Detailed Description......................................................36

9.1 Overview...................................................................36

Information.................................................................... 54

13.1 Packaging Information............................................ 54

5 Revision History

Changes from February 11, 2020 to August 31, 2020 (from Revision * (February 2020) to

Revision A (August 2020))

Page

•

Global: Updated the numbering format for tables, figures, and cross-references throughout the document..... 1

Global: Added/Updated cascading feature in supported on the AWR2243P only..............................................1

Global: Added/Updated Functional Safety-Compliant targeted information....................................................... 1

Global: Updated AWR2243 Product Status from "Advance Information (AI)" to "Production Data (PD)"...........1

(Device Information): Updated/Changed table to reflect production part numbers.............................................2

(Functional Block Diagram): Updated/Changed footnotes to reflect AWR2243, AWR2243P, and AWR1843....3

Table 6-1 (Device Features Comparison): Added AWR2243P device-specific features to table and updated

associated footnotes...........................................................................................................................................6

Table 6-1: Updated/Changed Max sampling rate FUNCTION to separate complex 1x and 2x cases............... 6

Table 7-1 (Signal Descriptions): Updated/Changed the DEFAULT PULL STATUS and DESCRIPTION for

NRESET (P12)................................................................................................................................................. 12

Table 7-1: Added recommended connectivity for GPIO[0] (N4) during Debug.................................................12

Section 8.1 (Absolute Maximum Ratings): Updated/Changed the MAX value for Operating junction

•

temperature range from "125" to "140", as Automotive.................................................................................... 16

Section 8.3 (Power-On Hours (POH)): Updated/Changed table to reflect automotive junction temp POH

percentages......................................................................................................................................................17

Section 8.4 (Recommended Operating Conditions): Added T_J, Operating junction temperature range.......... 17

Section 8.6 (Power Consumption Summary): Added missing table reference to the paragraph......................19

Table 8-3 (Maximum Current Ratings at Power Terminals): Added the current consumption VDDIN MAX value

of "850 mA" for AWR2243P..............................................................................................................................19

Section 8.7 (RF Specification): Updated/Changed the MAX values for IF bandwidth and A2D sampling rate

for both "(real/complex 2x)" and "(complex 1x)" to reflect the AWR2243P and AWR2243 devices................. 20

•

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•

Section 8.7: Added 20GHz SYNC OUT output level max value of 10 dBm and 20GHz SYNC IN input level

max value of 7 dBm with associated footnote. ................................................................................................ 20

Section 8.7: Corrected the phase noise measurement conditions to reflect VCO1 value only.........................20

Section 8.7: Updated/Changed the 1-dB compression point TYP value from "-8" to "-9" dBm, and updated the

corresponding footnote frequency from "50" to "10" kHz..................................................................................20

Figure 8-1 (Noise Figure, In-band P1dB vs Receiver Gain): Updated figure....................................................20

Section 8.8 (Thermal Resistance Characteristics): Deleted the 125°C junction temperature reference from

footnote ⁽³⁾.........................................................................................................................................................21

Figure 8-2 (Device Wake-Up Sequence): Removed associated MCU_CLK_OUT footnote from image..........22

Section 8.9.3.1 (Clock Specifications): Added the External Clock Mode Specifications table .........................24

Section 8.9.4 (Multibuffered / Standard Serial Peripheral Interface (MibSPI)): Updated section..................... 26

Figure 8-6 (SPI Communication): Updated figure.............................................................................................28

Section 10 (Monitoring and Diagnostic Mechanisms): Added new section...................................................... 41

Figure 11-1 (Short-, Medium-, and Long-Range Radar): Updated figure......................................................... 43

Section 11.3 (Imaging Radar using Cascade Configuration): Updated figure.................................................. 44

Figure 11-3 (Reference Schematic): Updated/Changed the VBGAP decoupling capacitor value from "0.22 uF"

to "47 nF"..........................................................................................................................................................45

Figure 12-1 (Device Nomenclature): Updated/Changed figure........................................................................ 51

•

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6 Device Comparison

Table 6-1. Device Features Comparison

FUNCTION

AWR2243P

AWR2243

AWR1243

AWR1443

AWR1642

AWR1843

Number of receivers

4

Number of transmitters

On-chip memory

3⁽¹⁾

—

3⁽¹⁾

—

3

—

3

576KB

—

2

1.5MB

B-Targeted

5

3⁽¹⁾

2MB

ASIL

B-Targeted

15

B-Targeted

Max I/F (Intermediate Frequency) (MHz)

5

20

45

15

10

25

Max real/complex 2x sampling rate (Msps)

Max complex 1x sampling rate (Msps)

37.5

12.5

6.25

12.5

6.25

37.5

18.75

22.5

12.5

Processor

MCU (R4F)

—

Yes

—

Yes

DSP (C674x)

Peripherals

Serial Peripheral Interface (SPI) ports

1

—

1

—

1

—

1

2

Quad Serial Peripheral Interface (QSPI)

Yes

1

Yes

1

Yes

1

Inter-Integrated Circuit (I²C) interface

1

—

Controller Area Network (DCAN) interface

—

Yes

—

Yes

—

Yes

—

CAN FD

—

Trace

—

PWM

—

Hardware In Loop (HIL/DMM)

GPADC

—

Yes

—

LVDS/Debug

CSI2

Yes

—

Yes

—

Yes

—

Hardware accelerator

1-V bypass mode

Cascade (20-GHz sync)

JTAG

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

Number of Tx that can be simultaneously

used⁽¹⁾

3⁽¹⁾

2

3⁽¹⁾

Per chirp configurable Tx phase shifter

PRODUCT PREVIEW (PP),

Yes

—

Yes

Product

ADVANCE INFORMATION

(AI),

PD

status⁽²⁾

or PRODUCTION DATA (PD)

(1) 3 Tx Simultaneous operation is supported only in AWR1843, AWR2243, and AWR2243P with 1V LDO bypass and PA LDO disable

mode. In this mode 1V supply needs to be fed on the VOUT PA pin.

(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

6

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6.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less

power using the smallest footprint mmWave sensor portfolio for automotive applications.

Automotive

TI’s automotive mmWave sensor portfolio offers high-performance radar front end to ultra-

mmWave Sensors high resolution, small and low-power single-chip radar solutions. TI’s scalable sensor

portfolio enables design and development of ADAS system solution for every performance,

application and sensor configuration ranging from comfort functions to safety functions in

all vehicles.

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7 Terminal Configuration and Functions

7.1 Pin Diagram

Figure 7-1 shows the pin locations for the 161-pin FCBGA package. Figure 7-2, Figure 7-3, Figure 7-4, and

Figure 7-5 show the same pins, but split into four quadrants.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

VOUT

_14APLL

VOUT

_14SYNTH

OSC

_CLKOUT

A

B

C

D

E

F

VSSA

VOUT_PA

VSSA

FM_CW

_SYNCIN1

VIN

_18CLK

VIN

_18VCO

FM_CW

_CLKOUT

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VSSA

VBGAP

VSSA

VIN

_13RF2

ANAMUX

VSENSE

VSSA

FM_CW

_SYNCOUT

VIN

_13RF2

VIOIN

_18DIFF

FM_CW

_SYNCIN2

VSSA

RX4

VSSA

VSS

VSSA

VDDIN

Reserved

TDI

CLKP

CLKM

VSSA

VIN_18BB

VSS

VIN

_13RF1

CSI2

_TXM[0]

CSI2

_TXP[0]

G

H

J

VSSA

RX3

VSS

VIN

_13RF1

CSI2

_TXM[1]

CSI2

_TXP[1]

VSS

VIN

_13RF1

VSSA

RX2

VSS

TDO

CSI2_CLKM

CSI2_CLKP

CSI2

_TXM[2]

CSI2

_TXP[2]

K

L

VIN_18BB

VSS

VIOIN_18

CSI2

_TXM[3]

CSI2

_TXP[3]

VSSA

RX1

VSS

TMS

HS_M

_Debug1

HS_P

_Debug1

M

N

P

R

TCK

WARM

_RESET

HS_M

_Debug2

HS_P

_Debug2

VSSA

GPIO[0]

RS232_RX

RS232_TX

GPIO[1]

NERROR_OUTMCU_CLK_OUT

Sync_in

QSPI[3]

VDDIN

Sync_out

QSPI[0]

GPIO[2]

Analog Test 1 Analog Test 2 Analog Test 3

I2C_SCL

MISO_1 SPI_HOST_INTR_1NERROR_IN

QSPI_CS

MOSI_1

QSPI[1]

NRESET PMIC_CLK_OUT

VNWA

VDDIN

Analog Test 4

I2C_SDA

VSSA

Reserved

VDDIN

SPI_CS_1

SPI_CLK_1

QSPI_CLK

QSPI[2]

VIOIN

VIN_SRAM

VSS

Not to scale

Figure 7-1. Pin Diagram

8

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1

2

3

4

5

6

7

8

A

B

C

D

E

F

VSSA

VOUT_PA

VSSA

FM_CW

_SYNCIN1

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VIN

_13RF2

VSSA

FM_CW

_SYNCOUT

VIN

_13RF2

VSSA

VSS

RX4

VIN_18BB

VIN

_13RF1

G

VSSA

VSS

Not to scale

1

2

4

3

Figure 7-2. Top Left Quadrant

9

10

11

12

13

14

15

VOUT

_14APLL

VOUT

_14SYNTH

OSC

_CLKOUT

A

VSSA

VIN

_18CLK

VIN

_18VCO

FM_CW

_CLKOUT

B

C

D

E

F

VSSA

VBGAP

VSSA

ANAMUX

VSENSE

VSSA

VIOIN

_18DIFF

FM_CW

_SYNCIN2

VSS

VSSA

VDDIN

CLKP

CLKM

VSSA

VSS

CSI2

_TXM[0]

CSI2

_TXP[0]

G

VSS

Reserved

Not to scale

1

3

2

4

Figure 7-3. Top Right Quadrant

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1

2

3

4

5

6

7

8

VIN

_13RF1

H

RX3

VSSA

VSS

VIN

_13RF1

J

VSSA

RX2

VSSA

VSS

K

L

VIN_18BB

VSSA

RX1

VSS

M

N

P

R

VSSA

GPIO[0]

RS232_RX

RS232_TX

GPIO[1]

NERROR_OUT

Analog Test 1 Analog Test 2 Analog Test 3

I2C_SCL

MISO_1 SPI_HOST_INTR_1NERROR_IN

QSPI_CS

Analog Test 4

I2C_SDA

VSSA

Reserved

VDDIN

SPI_CS_1

MOSI_1

Not to scale

1

3

2

4

Figure 7-4. Bottom Left Quadrant

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9

10

11

12

13

14

15

CSI2

_TXM[1]

CSI2

_TXP[1]

H

J

VSS

TDI

VSS

TDO

VIOIN_18

TMS

CSI2_CLKM

CSI2_CLKP

CSI2

_TXM[2]

CSI2

_TXP[2]

K

L

VSS

CSI2

_TXM[3]

CSI2

_TXP[3]

HS_M

_Debug1

HS_P

_Debug1

M

N

P

R

TCK

WARM

_RESET

HS_M

_Debug2

HS_P

_Debug2

MCU_CLK_OUT

Sync_in

QSPI[3]

VDDIN

Sync_out

QSPI[0]

GPIO[2]

QSPI[1]

NRESET PMIC_CLK_OUT

VNWA

VDDIN

SPI_CLK_1

QSPI_CLK

QSPI[2]

VIOIN

VIN_SRAM

VSS

Not to scale

1

3

2

4

Figure 7-5. Bottom Right Quadrant

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7.2 Signal Descriptions

Table 7-1 lists the pins by function and describes that function.

Note

All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe;

hence, care needs to be taken that they are not driven externally without the VIO supply being present

to the device.

Table 7-1. Signal Descriptions

NUMBER

TYPE

DEFAULT PULL

STATUS⁽¹⁾

FUNCTION

SIGNAL NAME

TX1

DESCRIPTION

Single-ended transmitter1 o/p

B4

B6

O

I

—

Transmitters

TX2

Single-ended transmitter2 o/p

Single-ended transmitter3 o/p

Single-ended receiver1 i/p

Single-ended receiver2 i/p

Single-ended receiver3 i/p

Single-ended receiver4 i/p

TX3

B8

RX1

M2

RX2

K2

I

Receivers

RX3

H2

I

RX4

F2

I

CSI2_TXP[0]

CSI2_TXM[0]

CSI2_CLKP

CSI2_CLKM

CSI2_TXP[1]

CSI2_TXM[1]

CSI2_TXP[2]

CSI2_TXM[2]

CSI2_TXP[3]

CSI2_TXM[3]

HS_DEBUG1_P

HS_DEBUG1_M

HS_DEBUG2_P

HS_DEBUG2_M

FM_CW_CLKOUT

FM_CW_SYNCOUT

FM_CW_SYNCIN1

FM_CW_SYNCIN2

G15

G14

J15

J14

H15

H14

K15

K14

L15

L14

M15

M14

N15

N14

B15

D1

O

Differential data Out – Lane 0 (for CSI and LVDS

debug interface)

Differential clock Out (for CSI and LVDS debug

interface)

Differential data Out – Lane 1 (for CSI and LVDS

debug interface)

Differential data Out – Lane 2 (for CSI and LVDS

debug interface)

CSI2 TX

Differential data Out – Lane 3 (for CSI and LVDS

debug interface)

Differential debug port 1 (for LVDS debug interface)

Differential debug port 2 (for LVDS debug interface)

20-GHz single-ended output. Modulated waveform

Chip-to-chip

cascading

O

I

—

synchronization

B1

20-GHz single-ended input. Only one of these pins

should be used. Multiple instances for layout flexibility.

signals⁽²⁾

D15

Reference clock output from clocking subsystem after

cleanup PLL. Can be used by slave chip in multichip

cascading

Reference clock OSC_CLKOUT

A14

P11

N10

O

I

—

Low-frequency frame synchronization signal output.

Can be used by slave chip in multichip cascading

SYNC_OUT

System

Pull Down

Low-frequency frame synchronization signal input.

This signal could also be used as a hardware trigger

for frame start

synchronization

SYNC_IN

SPI_CS_1

R7

R9

R8

P5

P6

I

Pull Up

Pull Down

Pull Up

SPI chip select

SPI clock

SPI control

interface from

external MCU

(default slave

mode)

SPI_CLK_1

MOSI_1

I

SPI data input

SPI data output

SPI interrupt to host

MISO_1

O

Pull Up

SPI_HOST_INTR_1

Pull Down

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Table 7-1. Signal Descriptions (continued)

NUMBER

TYPE

DEFAULT PULL

STATUS⁽¹⁾

FUNCTION

SIGNAL NAME

DESCRIPTION

Reserved. For debug purposes, it is recommended to

have test points on these pins.

Reserved

RESERVED

R4, R5

P12

—

Power on reset for chip. Active low.

The NRESET needs to be pulled low for a minimum

of 20 μsec to ensure proper device reset.

NRESET

I

Reset

Open-drain fail-safe warm reset signal. Can be used

as a status signal that the device is going through

reset.

WARM_RESET⁽³⁾

N12

O

Open Drain

SOP2

SOP1

P13

P11

I

—

The SOP pins are driven externally (weak drive) and

the AWR device senses the state of these pins during

bootup to decide the bootup mode. After boot the

same pins have other functionality.

Sense on Power

[SOP2 SOP1 SOP0] = [0 0 1] -> Functional SPI mode

[SOP2 SOP1 SOP0] = [1 0 1] -> Flashing mode

[SOP2 SOP1 SOP0] = [0 1 1] -> debug mode

[SOP2 SOP1 SOP0] = [1 1 1] -> Functional I2C mode

SOP0

J13

I

—

Open-drain fail-safe output signal. Connected to

PMIC/Processor/MCU to indicate that some severe

criticality fault has happened. Recovery would be

through reset.

NERROR_OUT

NERROR_IN

N8

P7

O

I

Open Drain

Safety

JTAG

Fail-safe input to the device. Error output from any

other device can be concentrated in the error

signaling monitor module inside the device and

appropriate action can be taken by firmware

TMS

TCK

TDI

L13

M13

H13

J13

I

Pull Up

Pull Down

Pull Up

—

JTAG port for TI internal development.

For debug purposes, it is recommended to have test

points on these pins.

I

TDO

CLKP

O

I

E14

—

In XTAL mode: Differential port for reference crystal

In External clock mode: Single ended input reference

clock port (Output CLKM is grounded in this case)

Reference

oscillator

CLKM

F14

B10

O

—

Band-gap

voltage

VBGAP

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Table 7-1. Signal Descriptions (continued)

NUMBER

TYPE

DEFAULT PULL

STATUS⁽¹⁾

FUNCTION

SIGNAL NAME

VDDIN

DESCRIPTION

F13,N11,P15

,R6

POW

—

1.2-V digital power supply

VIN_SRAM

VNWA

R14

P14

POW

—

1.2-V power rail for internal SRAM

1.2-V power rail for SRAM array back bias

I/O supply (3.3-V or 1.8-V): All CMOS I/Os would

operate on this supply.

VIOIN

R13

POW

—

VIOIN_18

K13

B11

POW

—

1.8-V supply for CMOS IO

1.8-V supply for clock module

1.8-V supply for CSI2 port

No connect

VIN_18CLK

VIOIN_18DIFF

Reserved

D13

G13

VIN_13RF1

VIN_13RF2

VIN_18BB

G5,J5,H5

C2,D2

K5,F5

B12

1.3-V Analog and RF supply,VIN_13RF1 and

VIN_13RF2 could be shorted on the board

1.8-V Analog baseband power supply

1.8-V RF VCO supply

VIN_18VCO

E5,E6,E8,E1

0,E11,F9,F11

,G6,G7,G8,G

10,H7,H9,H1

Power supply

VSS

1,J6,J7,J8,J1 GND

0,K7,K8,K9,

K10,K11,L5,

L6,L8,L10,R

15

—

Digital ground

A1,A3,A5,A7

,A9,A15,B3,

B5,B7,B9,B1

3,B14,C1,C3

,C4,C5,C6,C

7,C8,C9,C15

,E1,E2,E3,E GND

13,E15,F3,G

1,G2,G3,H3,

J1,J2,J3,K3,

L1,L2,L3,

VSSA

—

Analog ground

M3,N1,N2,N

3,R1

VOUT_14APLL

A10

A13

O

—

VOUT_14SYNTH

When internal PA LDO is used this pin provides the

output voltage of the LDO. When the internal PA LDO

is bypassed and disabled 1V supply should be fed on

this pin. This is mandatory in 3TX simultaneous use

case.

Internal LDO

output/inputs

VOUT_PA

A2,B2

IO

—

PMIC_CLK_OUT

MCU_CLK_OUT

P13

N9

O

—

Dithered clock input to PMIC

External clock

out

Programmable clock given out to external MCU or the

processor

14

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Table 7-1. Signal Descriptions (continued)

NUMBER

TYPE

DEFAULT PULL

STATUS⁽¹⁾

FUNCTION

SIGNAL NAME

GPIO[0]

DESCRIPTION

N4

N7

IO

Pull Down

General-purpose IOs. These pins are also used to set

the I2C address incase of functional I2C mode.

GPIO[1]

GPIO[2:0] -> 0x000 -> I2C address 0x28

GPIO[2:0] -> 0x001 -> I2C address 0x29

GPIO[2:0] -> 0x111 -> I2C address 0x2F

General-

purpose I/Os

GPIO[2]

N13

IO

Pull Down

It is recommended that the GPIO[0] signal is

connected to the host processor digital pin for debug.

For proper operations, the host processor needs to be

able to drive a pulse on this pin.

I2C_SDA

I2C_SCL

R3

P4

IO

I

Open Drain

I2C data

I2C clock

I2C interface

from external

MCU (slave

mode)

The host interface of I2C is selected by booting the

device in SOP mode 7 [111]. The I2C address is

selected using the GPIO[2:0] pins.

Chip-select output from the device. Device is a

master connected to serial flash slave.

QSPI_CS

P8

O

Pull Up

Clock output from the device. Device is a master

connected to serial flash slave.

QSPI_CLK

R10

Pull Down

QSPI for Serial

Flash

QSPI[0]

QSPI[1]

QSPI[2]

QSPI[3]

RS232_TX

R11

P9

IO

O

Pull Down

Pull Up

Data IN/OUT

R12

P10

N6

Pull Up

Flash

Pull Down

UART pins for programming external flash

For debug purposes, it is recommended to have test

points on these pins.

programming

and RS232

UART

RS232_RX

N5

I

Pull Up

Analog Test1

Analog Test2

Analog Test3

Analog Test4

ANAMUX

P1

P2

IO

—

Internal test signal

Test and Debug

output for

preproduction

phase. Can be

pinned out on

production

P3

R2

C13

C14

hardware for

field debug

VSENSE

(1) Status of PULL structures associated with the IO after device POWER UP.

(2) Cascading feature is available only in the AWR2243P device .

(3) For the AWR2243, WARM_RESET can be used as an output only pin for status indication.

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

PARAMETERS

MIN

–0.5

MAX

1.4

UNIT

VDDIN

1.2 V digital power supply

V

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

1.4

I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this

supply.

VIOIN

–0.5

3.8

V

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for CSI2 port

–0.5

2

V

VIN_18CLK

VIOIN_18DIFF

VIN_13RF1

VIN_13RF2

VIN_13RF1

1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could

be shorted on the board.

–0.5

1.45

V

1-V Internal LDO bypass mode. Device supports mode where

external Power Management block can supply 1 V on

VIN_13RF1 and VIN_13RF2 rails. In this configuration, the

internal LDO of the device would be kept bypassed.

–0.5

1.4

V

VIN_13RF2

VIN_18BB

VIN_18VCO supply

RX1-4

1.8-V Analog baseband power supply

1.8-V RF VCO supply

–0.5

2

V

2

V

Externally applied power on RF inputs

Externally applied power on RF outputs⁽³⁾

Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)

10

dBm

TX1-4

–0.3V

VIOIN + 0.3

Input and output

voltage range

V

Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V

(Transient Overshoot/Undershoot) or external oscillator input

VIOIN + 20% up to

20% of signal period

CLKP, CLKM

Clamp current

Input ports for reference crystal

–0.5

2

V

Input or Output Voltages 0.3 V above or below their respective

power rails. Limit clamp current that flows through the internal

diode protection cells of the I/O.

–20

20

mA

T_J

Operating junction temperature range

–40

–55

140

150

°C

T_STG

Storage temperature range after soldered onto PC board

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma= 1 can be applied on

the TX output.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

All pins

V_(ESD)Electrostatic discharge

V

Corner pins

(A1, A15, R1, R15)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

16

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8.3 Power-On Hours (POH)

JUNCTION

TEMPERATURE (T_j)

OPERATING

CONDITION

NOMINAL CVDD VOLTAGE (V)

POWER-ON HOURS [POH] (HOURS)^{(1) (2)}

–40°C

75°C

600 (6%)

2000 (20%)

6500 (65%)

800 (8%)

95°C

100% duty cycle

1.2

130°C

140°C

100 (1%)

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would

not be applicable, if the Tx gain table is overwritten using an API.

8.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.14

3.135

1.71

NOM

1.2

3.3

1.8

MAX

1.32

3.465

1.89

1.9

UNIT

VDDIN

1.2 V digital power supply

V

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

I/O supply (3.3 V or 1.8 V):

All CMOS I/Os would operate on this supply.

VIOIN

V

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for CSI2 port

V

VIN_18CLK

VIOIN_18DIFF

VIN_13RF1

VIN_13RF2

1.9

1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2

could be shorted on the board

1.23

1.3

1.36

V

VIN_13RF1

(1-V Internal LDO

bypass mode)

0.95

1

1.05

V

VIN_13RF2

(1-V Internal LDO

bypass mode)

VIN18BB

1.8-V Analog baseband power supply

1.8V RF VCO supply

1.71

1.17

2.25

1.8

1.9

V

VIN_18VCO

Voltage Input High (1.8 V mode)

Voltage Input High (3.3 V mode)

Voltage Input Low (1.8 V mode)

Voltage Input Low (3.3 V mode)

High-level output threshold (I_OH= 6 mA)

Low-level output threshold (I_OL= 6 mA)

V_IL(1.8V Mode)

V_IH

V_IL

V

0.3*VIOIN

0.62

V_OH

V_OL

VIOIN – 450

0.96

mV

450

0.45

V_IH(1.8V Mode)

NRESET

SOP[2:0]

V

V_IL(3.3V Mode)

0.65

140

V_IH(3.3V Mode)

1.57

-40

T_J

Operating junction temperature range

℃

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8.5 Power Supply Specifications

Table 8-1 describes the four rails from an external power supply block of the AWR2243 device.

Table 8-1. Power Supply Rails Characteristics

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOS IN THE DEVICE

Input: VIN_18VCO, VIN18CLK, VIN_18BB,

VIOIN_18DIFF, VIOIN_18IO

LDO Output: VOUT_14SYNTH, VOUT_14APLL

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, CSI2

1.8 V

1.3 V (or 1 V in internal

LDO bypass mode)⁽¹⁾

Power Amplifier, Low Noise Amplifier, Mixers and LO

Distribution

Input: VIN_13RF2, VIN_13RF1

LDO Output: VOUT_PA

3.3 V (or 1.8 V for 1.8 V

I/O mode)

Digital I/Os

Input VIOIN

1.2 V

Core Digital and SRAMs

Input: VDDIN, VIN_SRAM

(1) Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply

needs to be fed on the VOUT PA pin.

The 1.3V (1.0V) and 1.8V power supply ripple specifications mentioned in Table 8-2 are defined to meet a target

spur level of –105dBc (RF Pin = –15dBm) at the RX. The spur and ripple levels have a dB to dB relationship, for

example, a 1dB increase in supply ripple leads to a ~1dB increase in spur level. Values quoted are rms levels for

a sinusoidal input applied at the specified frequency.

Table 8-2. Ripple Specifications

RF RAIL

VCO/IF RAIL

FREQUENCY (kHz)

1.0 V (INTERNAL LDO BYPASS)

1.3 V (µV_RMS

)

1.8 V (µV_RMS)

(µV_RMS

)

137.5

275

7

5

648

76

22

4

83

21

11

6

550

3

1100

2200

4400

6600

2

11

13

22

82

93

117

13

19

29

18

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8.6 Power Consumption Summary

Table 8-3 and Table 8-4 summarize the power consumption at the power terminals.

Table 8-3. Maximum Current Ratings at Power Terminals

PARAMETER⁽²⁾

SUPPLY NAME

DESCRIPTION

MIN

TYP

MAX UNIT

500

AWR2243P

AWR2243

Total current drawn by all

nodes driven by 1.2V rail

VDDIN, VIN_SRAM, VNWA

850

Total current drawn by all

nodes driven by 1.3V (or

1V in LDO Bypass mode)

rail when 3 transmitters

are used ⁽¹⁾

VIN_13RF1, VIN_13RF2

2500

mA

Current consumption

VIOIN_18, VIN_18CLK, VIOIN_18DIFF,

VIN_18BB, VIN_18VCO

Total current drawn by all

nodes driven by 1.8V rail

850

50

Total current drawn by all

nodes driven by 3.3V rail

VIOIN

(1) Three transmitters can simultaneously be deployed in the AWR2243 device with 1V / LDO bypass and PA LDO disable mode. In this

mode 1V supply needs to be fed on the VOUT PA pin. For a 2Tx use case, the peak 1V supply current goes up to 2000 mA.

(2) The specified current values are at typical supply voltage level.

Table 8-4. Average Power Consumption at Power Terminals

PARAMETER

Average power

consumption in single chip

mode.

CONDITION

DESCRIPTION

MIN

TYP

1.42

1.62

1.82

MAX UNIT

1TX, 4RX

The frame is set to 50% duty cycle.

4lane CSI interface is enabled at

600Mbps for ADC data transfer

1.0-V internal LDO

bypass mode

2TX, 4RX

3TX, 4RX

W

Average power

consumption in master

mode.

The frame is set to 50% duty cycle.

4lane CSI interface is enabled at

600Mbps for ADC data transfer

1.0-V internal LDO

bypass mode

3TX, 4RX

1.97

1.85

W

Average power

consumption in slave

mode.

The frame is set to 50% duty cycle.

4lane CSI interface is enabled at

600Mbps for ADC data transfer

1.0-V internal LDO

bypass mode

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8.7 RF Specification

over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)

PARAMETER

Noise figure AWR2243P

Noise figure AWR2243

1-dB compression point (Out Of Band)⁽¹⁾

Maximum gain

MIN

TYP

12

13

–9

52

20

2

MAX UNIT

dB

dBm

dB

Gain range

Gain step size

dB

Image Rejection Ratio (IMRR)

30

dB

AWR2243P

20 MHz

15 MHz

45 Msps

37.5 Msps

22.5 Msps

18.75 Msps

Bits

IF bandwidth⁽²⁾

AWR2243

AWR2243P

AWR2243

AWR2243P

AWR2243

A2D sampling rate

(Real/ Complex 2x)

Receiver

A2D sampling rate

(Complex 1x)

A2D resolution

12

<–10

±0.5

±3

Return loss (S11)

dB

Gain mismatch variation (over temperature)

Phase mismatch variation (over temperature)

dB

°

RX gain = 30dB

In-band IIP2

16

24

dBm

IF = 1.5, 2 MHz at -12 dBFS

RX gain = 24dB

Out-of-band IIP2

IF = 10 KHz at -10 dBm,

1.9 MHz at -30 dBm

Idle Channel Spurs

Output power

–90

13

dBFS

dBm

Transmitter

Phase shifter accuracy

Amplitude noise

Frequency range

Ramp rate

±5

°

–145

dBc/Hz

76

81 GHz

266⁽³⁾MHz/µs

Clock subsystem

76 to 78 GHz (VCO1)⁽⁴⁾

76 to 81 GHz (VCO2)

–96

–94

Phase noise at 1-MHz offset

dBc/Hz

Frequency range

Output power at the pin

Return loss

19

3

20.25 GHz

10 dBm

dB

7

20 GHz SYNC OUT signal

(FM_CW_CLKOUT and

FM_CW_SYNCOUT)⁽⁵⁾

–9

Impedance

50

Ω

Frequency range

Input power at the pin

Return loss

19

-6

20.25 GHz

7⁽⁶⁾dBm

20 GHz SYNC IN signal

(FM_CW_SYNCIN)⁽⁵⁾

–10

50

dB

Ω

Impedance

(1) 1-dB Compression Point (Out Of Band) is measured by feeding a continuous wave tone below the lowest HPF cut-off frequency

(10 kHz).

(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set

of available HPF corners is summarized as follows:

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Available HPF Corner Frequencies (kHz)

HPF1

HPF2

175,235,350,700

350, 700, 1400, 2800

The filtering performed by the digital baseband chain is targeted to provide:

•

Less than ±0.5 dB pass-band ripple/droop, and

Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

(3) The max ramp rate depends on the PLL bandwidth configuration set using the"AWR_APLL_SYNTH_BW_CONTROL_SB" API. For

more details, see the mmWave radar Interface Control Users Guide.

(4) The phase noise numbers use the following configuration: SYNTH ICP TRIM = 3 , SYNTH RZ TRIM = 8 , and APLL ICP TRIM = 0x26.

(5) Cascading Feature is available in AWR2243P variant.

(6) At 140°C T_J, the max input level recommended is 3 dBm

Figure 8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain

programmed.

18

17

16

15

14

13

12

11

10

-18

-21

-24

-27

-30

-33

-36

-39

-42

NF (dB)

P1dB (dBm)

28 30 32 34 36 38 40 42 44 46 48 50

Rx Gain (dB)

D001

Figure 8-1. Noise Figure, In-band P1dB vs Receiver Gain

8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]

THERMAL METRICS⁽¹⁾

°C/W^{(2) (3)}

5

RΘ_JC

RΘ_JB

RΘ_JA

RΘ_JMA

Psi_JT

Psi_JB

Junction-to-case

Junction-to-board

5.9

Junction-to-free air

Junction-to-moving air

Junction-to-package top

Junction-to-board

21.6

15.3⁽⁴⁾

0.69

5.8

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(4) Air flow = 1 m/s

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8.9 Timing and Switching Characteristics

8.9.1 Power Supply Sequencing and Reset Timing

The AWR2243 device expects all external voltage rails and SOP lines to be stable before reset is deasserted.

Figure 8-2 describes the device wake-up sequence.

SOP

Setup

Time

SOP

Hold time to

nRESET

DC power

Stable before

nRESET

MSS

BOOT

START

nRESET

ASSERT

tPGDEL

DC

Power

notOK

DC

Power

OK

QSPI

READ

release

VDDIN,

VIN_SRAM

VNWA

VIOIN_18

VIN18_CLK

VIOIN_18DIFF

VIN18_BB

VIN_13RF1

VIN_13RF2

VIOIN

SOP[2.1.0]

nRESET

Warm reset

delay for crystal

or ext osc

WARMRESET

OUTPUT

VBGAP

OUTPUT

CLKP, CLKM

Using Crystal

MCUCLK

OUTPUT

QSPI_CS

OUTPUT

7ms (XTAL Mode)

500 µs (REFCLK Mode)

Figure 8-2. Device Wake-up Sequence

8.9.2 Synchronized Frame Triggering

The AWR2243 device supports a hardware based mechanism to trigger radar frames. An external host can

pulse the SYNC_IN signal to start radar frames. The typical time difference between the rising edge of the

external pulse and the frame transmission on air (Tlag) is about 160 ns. There is also an additional

programmable delay that the user can set to control the frame start time.

The periodicity of the external SYNC_IN pulse should be always greater than the programmed frame periodic in

the frame configurations in all instances.

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T_{active_frame}

SYNC_IN

(Hardware

Trigger)

Radar

Frames

T_pulse

T_lag

Frame-2

Frame-1

Figure 8-3. Sync In Hardware Trigger

Table 8-5. Frame Trigger Timing

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

T_{active_frame}

T_pulse

Active frame duration

User defined

25

ns

< T_{active_frame}

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8.9.3 Input Clocks and Oscillators

8.9.3.1 Clock Specifications

An external crystal is connected to the device pins. Figure 8-4 shows the crystal implementation.

C_f1

CLKP

C_p

40 MHz

CLKM

C_f2

Figure 8-4. Crystal Implementation

Note

The load capacitors, C_f1and C_f2in Figure 8-4, should be chosen such that Equation 1 is satisfied. C_L

in the equation is the load specified by the crystal manufacturer. All discrete components used to

implement the oscillator circuit should be placed as close as possible to the associated oscillator

CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.

C _f2

C_L= C _f1

´

+C_P

C

_f1+C _f2

(1)

Table 8-6 lists the electrical characteristics of the clock crystal.

Table 8-6. Crystal Electrical Characteristics (Oscillator Mode)

NAME

DESCRIPTION

MIN

TYP

40

8

MAX

UNIT

MHz

pF

f_P

Parallel resonance crystal frequency

C_L

Crystal load capacitance

Crystal ESR

5

12

50

ESR

Ω

Temperature range Expected temperature range of operation

–40

150

°C

Frequency

Crystal frequency tolerance^{(1) (2)}

tolerance

-200

200

ppm

µW

Drive level

50

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM

is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-7

lists the electrical characteristics of the external clock signal.

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Table 8-7. External Clock Mode Specifications

SPECIFICATION

PARAMETER

UNIT

MIN

TYP

MAX

Frequency

40

MHz

mV (pp)

ns

AC-Amplitude

700

1200

10

DC-t_rise/fall

Input Clock:

External AC-coupled sine wave or DC-

coupled square wave

Phase Noise at 1 kHz

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Duty Cycle

–132

–143

–152

–153

65

dBc/Hz

%

Phase Noise referred to 40 MHz

35

Freq Tolerance

–50

50

ppm

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Period jitter @40Mhz

Spur levels (sum of all spurs)

-127

-137

-147

1.75

-52

dBc/Hz

ps rms

dBc

Input clock requirements for slave

mode (assuming the 20Ghz clock is

provided from the master device)

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8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)

8.9.4.1 Peripheral Description

The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream to be shifted

into and out of the device at a programmed bit-transfer rate. The MibSPI/SPI is normally used for communication

between the microcontroller and external peripherals or another microcontroller.

Section 8.9.4.1.2 and Section 8.9.4.1.3 assume the operating conditions stated in Section 8.9.4.1.1, Section

8.9.4.1.2, Section 8.9.4.1.3, and Figure 8-5 describe the timing and switching characteristics of the MibSPI.

8.9.4.1.1 SPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOADOutput load capacitance

2

15

pF

8.9.4.1.2 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)

NO.

1

PARAMETER

Cycle time, SPICLK

MIN

25

TYP

MAX

UNIT

ns

t_c(SPC)S

2

t_w(SPCH)S

Pulse duration, SPICLK high

10

ns

3

t_w(SPCL)S

Pulse duration, SPICLK low

10

ns

4

t_{d(SPCL-SOMI)S}

t_{h(SPCL-SOMI)S}

Delay time, SPISOMI valid after SPICLK low

Hold time, SPISOMI data valid after SPICLK low

10

ns

5

2

ns

8.9.4.1.3 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)

NO.

6

MIN

3

TYP

MAX UNIT

t_{su(SIMO-SPCH)S}

t_{h(SPCH-SIMO)S}

Setup time, SPISIMO before SPICLK high

ns

7

Hold time, SPISIMO data valid after SPICLK high

1

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Figure 8-5. SPI Slave Mode External Timing

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8.9.4.2 Typical Interface Protocol Diagram (Slave Mode)

1. Host should ensure that there is a delay of at least two SPI clocks between CS going low and start of SPI

clock.

2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.

Figure 8-6 shows the SPI communication timing of the typical interface protocol.

Figure 8-6. SPI Communication

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8.9.5 Inter-Integrated Circuit Interface (I2C)

The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface between

devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I²C-bus™.

This module will support any slave or master I2C compatible device.

The I2C has the following features:

•

Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398

393 40011)

– Bit/Byte format transfer

– 7-bit and 10-bit device addressing modes

– General call

– START byte

– Multi-master transmitter/ slave receiver mode

– Multi-master receiver/ slave transmitter mode

– Combined master transmit/receive and receive/transmit mode

– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)

Free data format

Two DMA events (transmit and receive)

DMA event enable/disable capability

Module enable/disable capability

The SDA and SCL are optionally configurable as general purpose I/O

Slew rate control of the outputs

Open drain control of the outputs

Programmable pullup/pulldown capability on the inputs

Supports Ignore NACK mode

•

Note

This I2C module does not support:

•

High-speed (HS) mode

C-bus compatibility mode

The combined format in 10-bit address mode (the I2C sends the slave address second byte every

time it sends the slave address first byte)

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8.9.5.1 I2C Timing Requirements

(1)

STANDARD MODE

FAST MODE

MIN

10

MAX

MIN

2.5

MAX

t_c(SCL)

Cycle time, SCL

μs

t_{su(SCLH-SDAL)}

Setup time, SCL high before SDA low

(for a repeated START condition)

4.7

0.6

t_h(SCLL-SDAL)

Hold time, SCL low after SDA low

4

0.6

μs

(for a START and a repeated START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

μs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

t_h(SCLL-SDA)

t_w(SDAH)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0

3.45⁽¹⁾

0.9

Pulse duration, SDA high between STOP and START

conditions

4.7

1.3

t_{su(SCLH-SDAH)}

t_w(SP)

Setup time, SCL high before SDA high

(for STOP condition)

4

0.6

0

μs

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

ns

(2) (3)

C_b

400

pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the

SCL signal.

(3) C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

Figure 8-7. I2C Timing Diagram

Note

•

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period

(tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode

I2C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA

line tr max + t_su(SDA-SCLH)

.

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8.9.6 LVDS Interface Configuration

The AWR2243 supports seven differential LVDS IOs/Lanes to support debug where raw ADC data could be

extracted. The lane configuration supported is four Data lanes (LVDS_TXP/M), one Bit Clock lane

(LVDS_CLKP/M) one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data

rates:

•

900 Mbps (450 MHz DDR Clock)

600 Mbps (300 MHz DDR Clock)

450 Mbps (225 MHz DDR Clock)

400 Mbps (200 MHz DDR Clock)

300 Mbps (150 MHz DDR Clock)

225 Mbps (112.5 MHz DDR Clock)

150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.

LVDS_TXP/M

LVDS_FRCLKP/M

Data bitwidth

LVDS_CLKP/M

Figure 8-8. LVDS Interface Lane Configuration And Relative Timings

8.9.6.1 LVDS Interface Timings

Trise

LVDS_CLK

Clock Jitter = 6sigma

LVDS_TXP/M

LVDS_FRCLKP/M

1100 ps

Figure 8-9. Timing Parameters

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Table 8-8. LVDS Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

Duty Cycle Requirements

max 1 pF lumped capacitive load on

LVDS lanes

48%

52%

Output Differential Voltage

peak-to-peak single-ended with 100 Ω

resistive load between differential pairs

250

450

mV

Output Offset Voltage

Trise and Tfall

1125

1275

mV

ps

20%-80%, 900 Mbps

900 Mbps

330

80

Jitter (pk-pk)

ps

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8.9.7 General-Purpose Input/Output

Section 8.9.7.1 lists the switching characteristics of output timing relative to load capacitance.

8.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (C_L)

PARAMETER^{(1) (2)}

TEST CONDITIONS

C_L= 20 pF

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

2.8

6.4

9.4

2.8

6.4

9.4

3.3

6.7

9.6

3.1

6.6

9.6

3.0

6.9

t_r

t_f

t_r

t_f

Max rise time

C_L= 50 pF

ns

C_L= 75 pF

10.2

2.8

Slew control = 0

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

Max fall time

Max rise time

Max fall time

6.6

ns

9.8

3.3

7.2

10.5

3.1

Slew control = 1

6.6

9.6

(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).

(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

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8.9.8 Camera Serial Interface (CSI)

The CSI is a MIPI D-PHY compliant interface for connecting this device to a camera receiver module. This

interface is made of four differential lanes; each lane is configurable for carrying data or clock. The polarity of

each wire of a lane is also configurable. Section 8.9.8.1, Figure 8-10, Figure 8-11, and Figure 8-12 describe the

clock and data timing of the CSI.The clock is always ON once the CSI IP is enabled. Hence it remains in HS

mode.

8.9.8.1 CSI Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

HPTX

HSTX_DBR

f_CLK

Data bit rate

(1/2/4 data lane PHY)

150

75

600 Mbps

DDR clock frequency

300

50

MHz

mV

UI

Δ_VCMTX(LF)

t_Rand t_F

LPTX DRIVER

t_EOT

Common-level variation

–50

20% to 80% rise time and fall time

0.3

Time from start of THS-TRAIL period to start of LP-11 state

105 +

12*UI

ns

DATA-CLOCK Timing Specification

UINOM

Nominal Unit Interval

1.67

1.131

–0.15

13.33

ns

UIINST,MIN

TSKEW[TX]

Minimum instantaneous Unit Interval

Data to clock skew measured at transmitter

0.15 UIINST,

MIN

CSI2 TIMING SPECIFICATION

T_CLK-PRE

Time that the HS clock shall be driven by the transmitter before

any associated data lane beginning the transition from LP to HS

mode.

8

38

ns

T_CLK-PREPARE

Time that the transmitter drives the clock lane LP-00 line state

immediately before the HS-0 line state starting the HS

transmission.

95

ns

T_CLK-PREPARE+ T_CLK-ZEROT_CLK-PREPARE+ time that the transmitter drives the HS-0 state

before starting the clock.

300

ns

T_EOT

Transmitted time interval from the start of T_HS-TRAILor T_CLKTRAIL

,

105 ns

+ 12*UI

to the start of the LP-11 state following a HS burst.

T_HS-PREPARE

Time that the transmitter drives the data lane LP-00 line state

immediately before the HS-0 line state starting the HS

transmission

40 + 4*UI

85 +

6*UI

T_HS-PREPARE+ T_HS-ZERO

T_HS-PREPARE+ time that the transmitter drives the HS-0 state prior

to transmitting the Sync sequence.

145 ns +

10*UI

ns

T_HS-EXIT

Time that the transmitter drives LP-11 following a HS burst.

100

ns

T_HS-TRAIL

Time that the transmitter drives the flipped differential state after

last payload data bit of a HS transmission burst

max(8*UI, 60

ns + 4*UI)

T_LPX

TXXXransmitted length of any low-power state period

50

ns

CSI2_CLK(P/M)

0.5UI + T_skew

CSI2_TX(P/M)

1 UI

Figure 8-10. Clock and Data Timing in HS Transmission

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Clock

Lane

Data Lane

Dp/Dn

T_LPX

T_HS-ZERO

T_HS-SYNC

Disconnect

Terminator

VOH

T_HS-PREPARE

VIH(min)

VIL(max)

VOL

T_REOT

Capture

1^stData Bit

T_D-TERM-EN

T_HS-SKIP

T_EOT

T_HS-TRAIL

LP-11

LP-01

LP-00

T_HS-SETTLE

T_HS-EXIT

LOW-POWER TO

HIGH-SPEED

TRANSITION

START OF

HS-ZERO TRANSMISSION

SEQUENCE

HIGH-SPEED TO

HS-TRAIL LOW-POWER

TRANSITION

HIGH-SPEED DATA

TRANSMISSION

Figure 8-11. High-Speed Data Transmission Burst

Disconnect

Terminator

Clock Lane

Dp/Dn

T

CLK-SETTLE

VIH(min)

VIL(max)

T

LPX

T

CLK-PRE

CLK-ZERO

T

CLK-PREPARE

Data Lane

Dp/Dn

T

HS-PREPARE

Disconnect

Terminator

T

LPX

VIH(min)

VIL(max)

T

HS-SKIP

T

HS-SETTLE

A. The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.

Figure 8-12. Switching the Clock Lane Between Clock Transmission and Low-Power Mode

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9 Detailed Description

9.1 Overview

The AWR2243 device is a single-chip highly integrated 77-GHz transceiver and front end that includes three

transmit and four receive chains. The device can be used in long-range automotive radar applications such as

automatic emergency braking and automatic adaptive cruise control. The AWR2243 has extremely small form

factor and provides ultra-high resolution with very low power consumption. This device, when used with the

TDA3X or TDA2X, offers higher levels of performance and flexibility through a programmable digital signal

processor (DSP); thus addressing the standard short-, mid-, and long-range automotive radar applications.

9.2 Functional Block Diagram

LNA

IF

ADC

Digital Front-end

(Decimation filter

chain)

ADC output

interface

ADC Buffer

CSI2

PA

û-

Phase

Shifter

Control ⁽¹⁾

Synth

(20 GHz)

Ramp Generator

PA

x4

Host control

interface

Synth Cycle

Counter

SPI/I2C

Multi-chip cascading⁽²⁾

RF Control / BIST

Temp⁽³⁾

GPADC

Osc.

VMON

RF/Analog Subsystem

Digital

A. Phase Shift Control

•

0° / 180° BPM

0° / 180° BPM and 5.625° resolution control option for AWR2243, AWR2243P, and AWR1843

B. Internal temperature sensor accuracy is ± 7 °C.

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9.3 Subsystems

9.3.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,

IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit

channels can be operated simultaneously for transmit beamforming purpose as required; whereas the four

receive channels can all be operated simultaneously.

The AWR2243 device supports simultaneous operation of 3 transmitters.

9.3.1.1 Clock Subsystem

The AWR2243 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has a

built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF

synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz spectrum.

The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective

sensor operation.

The output of the RF synthesizer is available at the device pin boundary for multichip cascaded configuration.

The clean-up PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the

quality of the generated clock.

Figure 9-1 describes the clock subsystem.

RX LO

x4

MULT

TX LO

SYNC_OUT

SYNC_IN

Timing

Engine

RFSYNTH

Lock Detect

SoC Clock

Clean-Up

PLL

XO /

Slicer

CLK Detect

40 MHz

* These pins are 20GHz LO input pins. Connect LO to one pin while grounding the

other pin.

Figure 9-1. Clock Subsystem

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9.3.1.2 Transmit Subsystem

The AWR2243 transmit subsystem consists of three parallel transmit chains, each with independent phase and

amplitude control. All three transmitters can be used simultaneously or in time-multiplexed fashion. The device

supports binary phase modulation for MIMO radar and interference mitigation. For AWR2243, additional phase

shifters are associated with Tx channels, and these can programmed on a per chirp basis.

Each transmit chain can deliver a maximum of 13 dBm at the antenna port on the PCB. The transmit chains also

support programmable backoff for system optimization.

Figure 9-2 describes the transmit subsystem.

Loopback Path

Fine Phase Shifter Control

PCB

6 bits

13dBm

@ 50 Ω

û-

LO

0/180°

(from Timing Engine)

Self Test

Figure 9-2. Transmit Subsystem (Per Channel)

9.3.1.3 Receive Subsystem

The AWR2243 receive subsystem consists of four parallel channels. A single receive channel consists of an

LNA, mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational at the

same time an individual power-down option is also available for system optimization.

Unlike conventional real-only receivers, the AWR2243 device supports a complex baseband architecture, which

uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver

channel. The AWR2243 is targeted for fast chirp systems. The band-pass IF chain has configurable lower cutoff

frequencies above 175 kHz and can support bandwidths up to 20 MHz.

Figure 9-3 describes the receive subsystem.

Self Test

DAC

Loopback

Path

DSM

PCB

I

RSSI

50 W

GSG

LO

Q

DSM

DAC

Figure 9-3. Receive Subsystem (Per Channel)

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9.3.2 Host Interface

The AWR2243 device communicates with the host radar processor over the following main interfaces:

•

Reference Clock – Reference clock available for host processor after device wakeup

Control – 4-port standard SPI (slave or I2C) for host control along with HOST INTR pin for async events.. All

radio control commands (and response) flow through this interface.

•

Data – High-speed serial port following the MIPI CSI2 format. Four data and one clock lane (all differential).

Data from different receive channels can be multiplexed on a single data lane to optimize board routing. This

is a unidirectional interface used for data transfer only.

•

Reset – Active-low reset for device wakeup from host

Out-of-band interrupt

Error – Used for notifying the host in case the radio controller detects a fault

9.4 Other Subsystems

9.4.1 A2D Data Format Over CSI2 Interface

The AWR2243 device uses MIPI D-PHY / CSI2-based format to transfer the raw A2D samples to the external

MCU. This is shown in Figure 9-4.

•

Supports four data lanes

CSI-2 data rate scalable from 150 Mbps to 600 Mbps per lane

Virtual channel based

CRC generation

Normal Mode

Frame Period

Acquisition Period

Frame

Ramp/Chirp

1

2

3

N

Data Ready

F

L

H

L

H

L

H

L

H

L

F

S

E

S

E

S

E

S

E

Short

Packet

Short

Packet

Long

Packet

Short

Packet

ST SP ET

LPS

ST SP ET

.5μs-.8μs

ST PH

DATA

PF ET LPS

ST SP ET

LPS

Chirp 1 data

Data rate/Lane should be such that "Chirp + Interchirp" period

should be able to accommodate the data transfer

Frame Start – CSi2 VSYNC Start Short Packet

Line Start – CSI2 HSYNC Start Short Packet

Line End – CSI2 HSYNC End Short Packet

Frame End – CSi2 VSYNC End Short Packet

Figure 9-4. CSI-2 Transmission Format

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The data payload is constructed with the following three types of information:

•

Chirp profile information

The actual chirp number

A2D data corresponding to chirps of all four channels

– Interleaved fashion

•

Chirp quality data (configurable)

The payload is then split across the four physical data lanes and transmitted to the receiving D-PHY. The data

packet packing format is shown in Figure 9-5

First

11

5

1

0

11

0

CH Chirp

Profile

Channel

Number

NU

Chirp Num

5

1

11

CH Chirp

Profile

Channel

Number

Chirp Num

5

1

11

CH Chirp

Profile

Channel

Number

Chirp Num

5

1

11

CH Chirp

Profile

Channel

Number

Chirp Num

11

Channel 0 Sample 0 i

Channel 1 Sample 0 i

Channel 2 Sample 0 i

Channel 3 Sample 0 i

Channel 0 Sample 1 i

Channel 1 Sample 1 i

Channel 2 Sample 1 i

Channel 3 Sample 1 i

CQ Data [11:0]

Channel 0 Sample 0 q

11

Channel 1 Sample 0 q

11

Channel 2 Sample 0 q

11

Channel 3 Sample 0 q

11

Channel 0 Sample 1 q

11

Channel 1 Sample 1 q

11

Channel 2 Sample 1 q

11

Channel 3 Sample 1 q

Continues till the

last sample. Max 1023

11

CQ Data [23:12]

11

CQ Data [35:24]

CQ Data [47:36]

11

CQ Data [59:48]

NU

CQ Data [63:60]

Last

Figure 9-5. Data Packet Packing Format for 12-Bit Complex Configuration

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10 Monitoring and Diagnostic Mechanisms

Below is the list given for the main monitoring and diagnostic mechanisms available in the AWR2243

Table 10-1. Monitoring and Diagnostic Mechanisms for AWR2243

S No

Feature

Description

AWR2243 architecture supports hardware logic BIST (LBIST) engine self-test Controller

(STC). This logic is used to provide a very high diagnostic coverage (>90%) on the Master

R4F CPU core and Vectored Interrupt Module (VIM) at a transistor level.

LBIST for the CPU and VIM are triggered by the bootloader.

Boot time LBIST For Master

R4F Core and associated

VIM

1

Master R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and

TCMB1. AWR2243 architecture supports a hardware programmable memory BIST (PBIST)

engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the

implemented Master R4F TCMs at a transistor level.

PBIST for TCM memories is triggered by Bootloader at the boot time . CPU stays there in

while loop and does not proceed further if a fault is identified.

Boot time PBIST for Master

R4F TCM Memories

2

3

TCMs diagnostic is supported by Single error correction double error detection (SECDED)

ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the 64-

bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This scheme

provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU is

configured to have predetermined response (Ignore or Abort generation) to single and

double bit error conditions.

End to End ECC for Master

R4F TCM Memories

Logical TCM word and its associated ECC code is split and stored in two physical SRAM

banks. This scheme provides an inherent diagnostic mechanism for address decode failures

in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an

ECC fault.Further, bit multiplexing scheme implemented such that the bits accessed to

generate a logical (CPU) word are not physically adjacent. This scheme helps to reduce the

probability of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest

as multiple single bit faults. As the SECDED TCM ECC can correct a single bit fault in a

logical word, this scheme improves the usefulness of the TCM ECC diagnostic.

Master R4F TCM bit

multiplexing

4

AWR2243 architecture supports Three Digital Clock Comparators (DCCs) and an internal

RCOSC. Dual functionality is provided by these modules – Clock detection and Clock

Monitoring.

DCCint is used to check the availability/range of Reference clock at boot otherwise the

device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source. This

provides debug capability). DCCint is only used by boot loader during boot time. It is

disabled once the APLL is enabled and locked.

5

Clock Monitor

DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided

version with the Reference input clock of the device. Initially (before configuring APLL),

DCC1 is used by bootloader to identify the precise frequency of reference input clock

against the internal RCOSC clock source. Failure detection for DCC1 would cause the

device to go into limp mode.

Clock Compare module (CCC) module is used to compare the APLL divided down

frequency with reference clock (XTAL). Failure detection is indicated by the nERROR OUT

signal.

Internal watchdog is enabled by the bootloader in a windowed watchdog (DWWD) mode..

Watchdog expiry issues an internal warm reset and nERROR OUT signal to the host.

6

7

RTI/WD for Master R4F

MPU for Master R4F

Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial

separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions. It

is expected that the operating system controls the MPU and changes the MPU settings

based on the needs of each task. A violation of a configured memory protection policy

results in a CPU abort.

AWR2243 architecture supports a hardware programmable memory BIST (PBIST) engine

for Peripheral SRAMs as well.

PBIST for Peripheral interface PBIST for peripheral SRAM memories is triggered by the bootloader. The PBIST tests are

8

SRAMs - SPI, I2C

destructive to memory contents, and as such are typically run only at boot time. .

Any fault detected by the PBIST results in an error indicated in PBIST and boot status

response message.

Peripheral interface SRAMs diagnostic is supported by Single error correction double error

detection (SECDED) ECC diagnostic. When a single or double bit error is detected the error

is indicated by nERROR (double bit error) or via SPI message (single bit error).

ECC for Peripheral interface

SRAMs – SPI, I2C

9

Cyclic Redundancy Check – Cyclic Redundancy Check (CRC) module is available for the Master SS. The firmware uses

Master SS this feature for data transfer checks in mailbox and SPI communication.

10

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Table 10-1. Monitoring and Diagnostic Mechanisms for AWR2243 (continued)

S No

Feature

Description

AWR2243 architecture supports MPUs on Master SS DMAs. The firmware uses this for

stack protection.

11

MPU for DMAs

AWR2243 architecture supports hardware logic BIST (LBIST) even for BIST R4F core and

associated VIM module. This logic provides very high diagnostic coverage (>90%) on the

BIST R4F CPU core and VIM.

This is triggered by Master R4F boot loader at boot time and it does not proceed further if

the fault is detected.

Boot time LBIST For BIST

R4F Core and associated

VIM

12

AWR2243 architecture supports a hardware programmable memory BIST (PBIST) engine

for BIST R4F TCMs which provide a very high diagnostic coverage (March-13n) on the BIST

R4F TCMs.

Boot time PBIST for BIST

R4F TCM Memories

13

14

15

PBIST is triggered at the power up of the BIST R4F.

BIST R4F TCMs diagnostic is supported by Single error correction double error detection

(SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while

double bit error is communicated to Master R4F as an interrupt which sends a async event

to the host.

End to End ECC for BIST

R4F TCM Memories

Logical TCM word and its associated ECC code is split and stored in two physical SRAM

banks. This scheme provides an inherent diagnostic mechanism for address decode failures

in the physical SRAM banks and helps to reduce the probability of physical multi-bit faults

resulting in logical multi-bit faults.

BIST R4F TCM bit

multiplexing

AWR2243 architecture supports various temperature sensors all across the device (next to

power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame

period.⁽¹⁾

16

17

18

Temperature Sensors

Tx Power Monitors

AWR2243 architecture supports power detectors at the Tx output.⁽²⁾

When a diagnostic detects a fault, the error must be indicated. The AWR2243 architecture

provides aggregation of fault indication from internal monitoring/diagnostic mechanisms

using nERROR signaling or async event over SPI interface.

Error Signaling

Error Output

Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and

comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if

any, are detected and reported.

Synthesizer (Chirp) frequency

monitor

19

20

AWR2243 architecture supports a ball break detection mechanism based on Impedance

measurement at the TX output(s) to detect and report any large deviations that can indicate

a ball break.

Ball break detection for TX

ports (TX Ball break monitor) Monitoring is done by TIs code running on BIST R4F and failure is reported to the host.

It is completely up to customer SW to decide on the appropriate action based on the

message from BIST R4F.

Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain,

inter-RX balance, etc.

21

22

23

RX loopback test

Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect

IF loopback test

failure.

Provision to detect ADC saturation due to excessive incoming signal level and/or

RX saturation detect

interference.

(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the

temperature sensed via API by customer application.

a. Report the temperature sensed after every N frames

b. Report the condition once the temperature crosses programmed threshold.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.

(2) Monitoring is done by the TI's code running on BIST R4F.

There are two modes in which it could be configured to report the detected output power via API by customer application.

a. Report the power detected after every N frames

b. Report the condition once the output power degrades by more than configured threshold from the configured.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.

42

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11 Applications, Implementation, and Layout

Note

Information in the following Applications section is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

11.1 Application Information

A typical application addresses the standard short-, mid-, long-range, and high-performance imaging radar

applications with this radar front end and external programmable MCU. Figure 11-1 shows a short-, medium-, or

long-range radar application.

11.2 Short-, Medium-, and Long-Range Radar

Crystal

Power Management

RX1

RX2

Antenna

Structure

SPI/I2C

RX3

External

MCU

RX4

Automotive

Interface PHY

AWR2243

CSI2 (4 Lane Data + 1 Clock lane)

TX1

TX2

Reset

Error

TX3

MCU Clock

Figure 11-1. Short-, Medium-, and Long-Range Radar

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11.3 Imaging Radar using Cascade Configuration

CSI-2 (4 lanes)

RX1

RX2

RX3

Control (SPI, GPIOs)

Reset

FMCW_SYNCOUT

RX4

AWR2243P

Master

TX1

FMCW_SYNCIN

SYNC_OUT

TX2

TX3

SYNC_IN

CLKP

CLKM

OSC_CLK_OUT

External

Host

40MHz

CLKP

CLKM

RX1

RX2

RX3

RX4

SYNC_IN

FMCW_SYNCIN

Reset

AWR2243P

Slave

TX1

Control (SPI, GPIOs, RESET)

CSI-2 (4 lanes)

TX2

TX3

Figure 11-2. Imaging Radar using Cascade Configuration

44

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11.5 Layout

The top layer routing, top layer closeup, and bottom layer routing are shown in Figure 11-4, Figure 11-5, and

Figure 11-6, respectively.

46

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11.5.1 Layout Guidelines

Figure 11-4. Top Layer Routing

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Figure 11-5. Top Layer Routing Closeup

48

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Figure 11-6. Bottom Layer Routing

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11.5.2 Stackup Details

1

2

0.689

Rogers 4835 4.000

1.260

2.067

4.000

1.260

100.000

Rogers 4835 4mil coreH/1 Low Pro

3.480

73.000

Iteq IT180A Prepreg 1080

Dielectric

4.195

2.830

3.700

3

4

1.260

28.000

1.260

28.000

1.260

69.000

48.000

Iteq IT180A 28 mil core 1/1

FR4

4.280

Iteq IT180A Prepreg 1080

Dielectric

4.195

2.691

3.700

5

6

1.260

4.000

0.689

1.260

4.000

2.067

72.000

Iteq IT180A 4 mil core 1/H

FR4

3.790

100.000

50

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SWRS223A – FEBRUARY 2020 – REVISED AUGUST 2020

12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions follow.

12.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, AWR2243). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

X

P

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, ABL0161), the temperature range (for example, blank is the default commercial temperature

range). Figure 12-1 provides a legend for reading the complete device name for any AWR2243 device.

For orderable part numbers of AWR2243 devices in the ABL0161 package types, see the Package Option

Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the AWR2243 Device Errata.

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2

43

B

AWR

G

ABL

Q1

Qualification

Q1 = AEC-Q100

Blank = no special Qual

Prefix

XA = Pre-production

AWR = Production

Tray or Tape & Reel

Generation

2 = 76 œ 81 GHz

R = Big Reel

Blank = Tray

Variant

2 = FE

4 = FE + FFT + MCU

6 = FE + MCU + DSP + 1.5 MB

Package

ABL = BGA

Security

Num RX/TX Channels

G = General

S = Secure

D = Development Secure

RX = 1,2,3,4

TX = 1,2,3

Silicon PG Revision

Blank = Rev 1.0

A = Rev 1.1

Features

Blank = Baseline

P = High Performance

Safety

A = ASIL A Targeted

B = ASIL B Targeted

Figure 12-1. Device Nomenclature

12.2 Tools and Software

Development Tools

AWR2243 Cascade Application Note Describes TI's cascaded mmWave radar system.

Models

AWR2243 BSDL Model Boundary scan database of testable input and output pins for IEEE 1149.1 of the

specific device.

52

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12.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

The current documentation that describes the DSP, related peripherals, and other technical collateral follows.

Errata

AWR2243 Device Errata Silicon Revisions 1.0 and 1.1

Describes known advisories, limitations, and cautions on silicon and provides workarounds.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

12.8 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

13.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

CAUTION

The following package information is subject to change without notice.

54

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PACKAGE MATERIALS INFORMATION

www.ti.com

4-Sep-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AWR2243ABGABLRQ1 FC/CSP

AWR2243APBGABLRQ1 FC/CSP

ABL

161

1000

330.0

24.4

10.7

1.65

16.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Sep-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

AWR2243ABGABLRQ1

AWR2243APBGABLRQ1

FC/CSP

ABL

161

1000

336.6

41.3

Pack Materials-Page 2

PACKAGE OUTLINE

ABL0161A

FCBGA - 1.17 mm max height

SCALE 1.400

PLASTIC BALL GRID ARRAY

10.5

10.3

B

A

BALL A1 CORNER

10.5

10.3

1.17 MAX

C

SEATING PLANE

0.1 C

BALL TYP

0.37

0.27

TYP

9.1 TYP

PKG

(0.65) TYP

R

P

N

M

L

K

J

PKG

H

G

F

9.1

TYP

E

D

C

0.45

161X

0.35

0.15

0.08

C A B

C

B

A

0.65 TYP

BALL A1 CORNER

1

3

4

5

6

7

8

9 10 11

12 13 14 15

2

0.65 TYP

4222493/B 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ABL0161A

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

(0.65) TYP

161X ( 0.32)

8

9

1

2

3

4

5

6

7

10 11

12 13 14 15

A

B

C

(0.65) TYP

D

E

F

G

H

J

PKG

K

L

M

N

P

R

PKG

LAND PATTERN EXAMPLE

SCALE:10X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.32)

METAL

(

0.32)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4222493/B 10/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

ABL0161A

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

(0.65) TYP

161X ( 0.32)

8

9

1

2

3

4

5

6

7

10 11

12 13 14 15

A

B

C

(0.65) TYP

D

E

F

G

H

J

PKG

K

L

M

N

P

R

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4222493/B 10/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AWR2243ABGABLQ1
厂家：	TEXAS INSTRUMENTS
描述：	AWR2243 Single-Chip 76- to 81-GHz FMCW Transceiver
文件：	总62页 (文件大小：3490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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