AWR2944ABGALTRQ1_技术文档

AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

AWR2943/44 单芯片76GHz 和81GHz FMCW 雷达传感器

• 片上RAM

1 特性

– 3.5MB 至4MB（AWR2943 为3.5MB，

AWR2944 为4MB）

• FMCW 收发器

– 集成PLL、发送器、接收器、基带和ADC

– 76GHz 至81GHz 的覆盖范围，具有5GHz 的可

用带宽

– 4 个接收通道和3 至4 个发送通道（AWR2943

为3 个通道，AWR2944 为4 个通道），带有

PCB 天线接口

– 每发送移相器

– 基于分数N PLL 的超精确线性调频脉冲引擎

– TX 功率

– 存储器空间在DSP、MCU 和共享L3 之间分配

• 器件安全（在部分器件型号上）

– 可编程的嵌入式硬件安全模块(HSM)

– 支持经过身份验证和加密的安全引导

– 客户可编程根密钥、对称密钥（256 位）、具有

密钥撤销功能的非对称密钥（最高RSA-4K 或

ECC-512）

– 加密硬件加速器：带ECC 的PKA、AES（最高

256 位）、SHA（最高512 位）、TRNG/

DRGB

• 13.5dBm

– RX 噪声系数

• 12dBm

• 以功能安全合规型为目标

– 专为功能安全应用开发

– 将提供相关文档来协助进行符合ISO 26262 标

准的功能安全系统设计

– 1MHz 时的相位噪声

• -96dBc/Hz（76 至77 GHz）

• -95dBc/Hz（76 至81GHz）

• 内置校准和自检

– 以硬件完整性高达ASIL B 级为目标

• 符合AEC-Q100 标准

• 高级特性

– 内置固件(ROM)

– 针对工艺和温度进行自校准的系统

• 处理元件

– 嵌入式自监控，无需使用外部处理器

– 嵌入式干扰检测功能

• 电源管理

– Arm^®Cortex-R5F^®内核（支持锁步操作）

@300MHz

– TI 数字信号处理器C66x @360MHz

– 用于FFT、对数幅度、存储器压缩等运算的TI

雷达硬件加速器(HWA2.1)

– 用于数据移动的多个EDMA 实例

• 主机接口

– 内置LDO 网络，可增强PSRR

– LVCMOS IO 支持3.3V 和1.8V 双电压

• 时钟源

– 具有内部振荡器的40MHz 晶体

– 支持频率为40MHz 的外部振荡器

– 支持外部驱动、频率为40MHz 的时钟（方波/正

弦波）

– 2x CAN-FD

• 优化的电源管理解决方案

– 10/100Mbps RGMII/RMII/MII 以太网

• 支持串行闪存接口（从QSPI 闪存加载用户应用）

• 为用户应用提供的其他接口

– 多达9 个ADC 通道

– 推荐的LP87745-Q1 电源管理IC (PMIC)

• 专为满足器件电源要求而设计的配套PMIC

• 灵活的映射和出厂编程配置，支持多种不同

的用例

– 2 个SPI

– 4 个UART

– I²C

– GPIO

– 3 个EPWM

– 用于原始ADC 数据和调试仪表的四通道Aurora

LVDS 接口

• 成本更低的硬件设计

– 0.65mm 间距、12mm × 12mm 倒装芯片BGA

封装，可实现轻松组装和低成本PCB 设计

– 小解决方案尺寸

• 支持汽车运行温度范围

– 工作结温范围：-40°C 至140°C

– CSI2 Rx 接口可回放捕获的数据

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWRS273

AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

www.ti.com.cn

2 应用

• 车道变换辅助

• 盲点检测

• 自动紧急刹车

• 自适应巡航控制

• 侧向来车警示

40-MHz

Crystal

Serial

Flash

Power Management

QSPI

Integrated MCU

ARM Cortex-R5F

Ethernet

PHY

Automotive

Network

Ethernet

Antenna

RX1

Structure

RX2

RX3

MCAN

PHY

Automotive

Network

CAN FD (2)

RX4

Radar

Front End

TX1

TX2

TX3

TX4

Integrated DSP

TI C66x

mmWave Sensor

图2-1. 适用于汽车应用的自主雷达传感器

3 说明

AWR294x 是一款单芯片毫米波传感器，由能够在76GHz 至81GHz 频段内工作的FMCW 收发器、雷达数据处理

元件和车载网络外围设备构成。AWR294x 采用TI 的低功耗45nm RFCMOS 工艺制造，并且在小型封装中以超低

BOM 数量实现了出色的集成度。AWR294x 是适用于汽车领域中低功耗、自监控、超精确雷达系统的理想解决方

案。

TI 的低功耗 45nm RFCMOS 工艺可实现具有集成PLL、VCO、混频器和基带 ADC 的单片实施 3-4 TX、4 RX 系

统。DSP 子系统 (DSS) 中集成了 TI 的高性能 C66x DSP，可用于处理雷达信号。该器件包含一个无线电处理器

子系统 (RSS)，该子系统负责雷达前端配置、控制和校准。在主要子系统 (MSS) 中，该器件实现了一个用户可编

程的 Arm Cortex-R5F 处理器，允许自定义控制和汽车接口应用。硬件加速器块 (HWA 2.0) 通过卸载通用雷达处

理（例如 FFT、恒定误报率 (CFAR)、扩展和压缩）来对 DSS 和 MSS 进行补充。这会节省 DSS 和 MSS 上的

MIPS，为自定义应用和更高级别的算法腾出了资源。

器件中还提供了硬件安全模块 (HSM)（仅适用于安全器件型号）。HSM 由可编程 Arm Cortex-M4 内核和必要的

基础设施组成，用于在器件内提供安全的操作区域。

简单编程模型更改可支持各种传感器实施（近距离、中距离和远距离），并且能够进行动态重新配置，从而实现

多模式传感器。

此外，AWR294x 作为完整的平台解决方案进行提供，其中包括 TI 硬件和软件参考设计、软件驱动程序、示例配

置、API 指南以及用户文档。

English Data Sheet: SWRS273

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器件信息

封装⁽¹⁾

封装尺寸（标称值）

12mm x 12mm

器件型号

AWR2943ABGALTQ1

AWR2943ABGALTRQ1

AWR2943ABSALTRQ1

AWR2944ABGALTQ1

AWR2944ABGALTRQ1

AWR2944ABSALTQ1

AWR2944ABSALTRQ1

FCBGA (266)

(1) 如需更多信息，请参阅节12，机械、封装和可订购信息。

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English Data Sheet: SWRS273

AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

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3.1 功能方框图

图3-1 展示了器件的功能方框图。

9

GPADC

QSPI

Main Subsystem

Serial Flash Interface

(Customer Programmed)

LNA

IF

ADC

Optional External

MCU Interface

SPI

Arm Cortex-R5F

(Lock Step)

at 300 MHz

PMIC Control

Digital

Front-end

SPI / I2C

CAN-FD

Primary Communication

Interfaces (Automotive)

(Decimation

Filter Chain)

Prog

Cache

16KB

Data

Cache

16KB

L1 Data

RAM

128KB

L2 RAM

960KB

Debug

UARTs

For Debug

Test/

Debug

JTAG for Debug/

Development

DMA

Hardware Security

Module ^(A)

100-Mbps Alternate Data

Communication Interface

PA

Ethernet

ADC

Buffer

Mailbox

PA

DSP Subsystem

Synth

(20 GHz)

Ramp

Generator

(Customer Programmed)

x4

C66x DSP Core

at 360 MHz

Radio (BIST)

Processor

Aurora

LVDS

High-Speed ADC Output

Interface (for Recording)

High-Speed Interface to

enable playback of the

captured data

(For RF Calibration

and Self-Test – TI

Programmed)

CSI2 RX

L1P

L1D

L2

(384KB)

(32KB) (32KB)

Prog RAM

and ROM

Data

RAM

DMA

CRC

Osc.

Radar Data Memory

AWR2943 - 2.0MB /

AWR2944 - 2.5MB

GPADC

VMON

Temp

Radio Processor

Subsystem

(TI Programmed)

Radar Hardware Accelerator

(FFT, Log mag, and others)

RF/Analog Subsystem

A. 此特性仅在部分器件型号中可用，如节3“器件信息”表中的“器件类型标识符”所示。

图3-1. 功能方框图

English Data Sheet: SWRS273

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Table of Contents

7.12 Peripheral Information.............................................54

7.13 Emulation and Debug............................................. 76

8 Detailed Description......................................................79

8.1 Overview...................................................................79

8.2 Functional Block Diagram.........................................79

8.3 Subsystems.............................................................. 80

8.4 Other Subsystems.................................................... 84

9 Monitoring and Diagnostics......................................... 86

9.1 Monitoring and Diagnostic Mechanisms................... 86

10 Applications, Implementation, and Layout............... 90

10.1 Application Information........................................... 90

10.2 Short and Medium Range Radar............................ 90

10.3 Reference Schematic..............................................90

11 器件和文档支持..............................................................91

11.1 Device Support........................................................91

11.2 Device Nomenclature..............................................91

11.3 Tools and Software..................................................92

11.4 Documentation support...........................................92

11.5 支持资源..................................................................92

11.6 Trademarks............................................................. 92

11.7 静电放电警告...........................................................92

11.8 术语表..................................................................... 92

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

3.1 功能方框图..................................................................4

4 Revision History.............................................................. 5

5 Device Comparison.........................................................8

5.1 Related Products........................................................ 9

6 Pin Configurations and Functions...............................10

6.1 Pin Diagram.............................................................. 10

6.2 Pin Attributes.............................................................15

6.3 Signal Descriptions - Digital......................................27

6.4 Signal Descriptions - Analog.....................................34

7 Specifications................................................................ 45

7.1 Absolute Maximum Ratings...................................... 45

7.2 ESD Ratings............................................................. 45

7.3 Power-On Hours (POH) ...........................................46

7.4 Recommended Operating Conditions.......................46

7.5 VPP Specifications for One-Time Programmable

(OTP) eFuses..............................................................47

7.6 Power Supply Specifications.....................................48

7.7 Power Consumption Summary................................. 49

7.8 RF Specifications......................................................50

7.9 Thermal Resistance Characteristics ........................ 51

7.10 Power Supply Sequencing and Reset Timing.........52

7.11 Input Clocks and Oscillators....................................53

Information.................................................................... 93

4 Revision History

Changes from November 10, 2021 to March 31, 2023 (from Revision * (November 2021) to

Revision A (March 2023))

Page

•

（标题）：将数据表标题从“AWR2944”更新为“AWR2943/44”.................................................................1

（特性）：将RX 噪声系数从13dB 更新为12dB，将TX 输出功率从12dBm 更新为13.5dBm.......................1

（特性）：添加了Cortex R5F 和DSP C66x 最大工作频率.............................................................................. 1

（特性）：将HWA 的版本从 2.0 更新为 2.1..................................................................................................... 1

（特性）：添加了有关电源管理解决方案的建议................................................................................................1

（说明）：更新了 ES2.0 器件可订购器件型号(OPN)....................................................................................... 2

（功能方框图）：更新了图表以删除脚注...........................................................................................................4

• (Signal Descriptions - Digital) : Corrected descriptions for MSS_RGMII_RDx pins......................................... 27

• (Signal Descriptions - Digital) : Added a table-note for usage of MSS_MIBSPIB signals................................ 27

• (Signal Descriptions - Digital) : Removed pins F16 and E17 from TRACE_CLK and TRACE_CTL................ 27

• (Signal Descriptions - Analog) : Added a table-note for TX4............................................................................34

• (Recommended Operating Conditions) : Updated MAX values for 1.2V digital and SRAM supply; and

1.8V supply.......................................................................................................................................................46

• (VPP Specifications) - Warranty Impact : Rephrased section...........................................................................47

• (Power Supply Specification) : Added Supply Ripple specs.............................................................................48

• (Power Supply Specification) : Added recommendations on power management solutions............................48

• (Power Consumption Summary) : Updated the Max peak current numbers for 1.2V and 1.8V respectively

from 2100mA and 600mA to 2000mA and 550mA in Table - Maximum Current Ratings at Power Terminals for

ES2.0 silicon.....................................................................................................................................................49

• (Power Consumption Summary) : Updated the Description conditions and power numbers in Table - Average

Power Consumption at Power Terminals for ES2.0 silicon...............................................................................49

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English Data Sheet: SWRS273

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• (RF Specifications) : Improved Typical Noise Figure from 13dB to 12dB in ES2.0 silicon............................... 50

• (RF Specifications) : Improved Typical Transmitter Output power from 12dBm to 13.5dBm in ES2.0 silicon..50

• (RF Specifications) : Improved Typical 1-dB compression point (Out Of Band) from -11dBm to -10dBm in

ES2.0 silicon.....................................................................................................................................................50

• (RF Specifications) : Updated table-notes for 1-dB compression point (Out Of Band) measurement technique

and a new note added for VCO2 range............................................................................................................50

• (RF Specifications) : Updated Noise Figure, In-band P1dB vs Receiver Gain figure in the section.................50

• (Clock Specifications): Updated/Changed "Crystal Electrical Characteristics (Oscillator Mode)" to reflect

correct device operating temperature range.....................................................................................................53

• (QSPI Timing Conditions) : Updated the Output load capacitance from 2pF to 5pF........................................54

• (QSPI Timing Requirements) : Updated the Setup time (Q12 and Q14) from 13.2ns to 5 ns..........................54

• (QSPI Switching Characteristics): Updated/Changed Cycle time, sclk from 15ns to 12.5ns; ..........................55

• (QSPI Switching Characteristics): Updated/Changed Pulse duration, sclk i.e. [Q2, Q3] from 0.5*P –1.5 to

0.5*P –0.625 (Min). ....................................................................................................................................... 55

• (QSPI Switching Characteristics): Updated/Changed Delay time, sclk falling edge to d[0] transition i.e. [Q6,

Q9] from 5.5ns to 2ns (Max) and -2.5ns to -4.5ns (Min). .................................................................................55

• (SPI Timing Conditions): Updated/Changed C_LOAD, Output load capacitance from 15pF to 20pF (Max). ...... 57

• (SPI Controller Mode Switching Parameters, Clock Phase =0 ): Updated/Changed Cycle time, SPICLK from

40ns to 20ns; ................................................................................................................................................... 57

• (SPI Controller Mode Switching Parameters, Clock Phase =0): Updated/Changed Pulse duration, SPICLK i.e.

[Q2, Q3] from 0.5t_c(SPC)M+- 4 to 0.5t_c(SPC)M+- 2(Min/Max). ............................................................................57

• (SPI Controller Mode Switching Parameters, Clock Phase =0): Updated/Changed Delay time, SPISIMO valid

before SPICLK low, i.e. [Q4] from 0.5t_c(SPC)M–14 to 0.5t_c(SPC)M–7 (Min). .................................................57

• (SPI Controller Mode Switching Parameters, Clock Phase =0): Updated/Changed Valid time, SPISIMO data

valid after SPICLK low, i.e. [Q5] from 0.5t_c(SPC)M–18 to 0.5t_c(SPC)M–8 (Min). ........................................... 57

• (SPI Controller Mode Switching Parameters, Clock Phase =0): Updated/Changed Hold time, SPISOMI data

valid after SPICLK i.e. [Q9] from 3ns to 2ns (Min). ..........................................................................................57

• (SPI Controller Mode Switching Parameters, Clock Phase =1 ): Updated/Changed Cycle time, SPICLK from

40ns to 20ns; ................................................................................................................................................... 60

• (SPI Controller Mode Switching Parameters, Clock Phase =1): Updated/Changed Pulse duration, SPICLK i.e.

[Q2, Q3] from 0.5t_c(SPC)M+- 4 to 0.5t_c(SPC)M+- 2(Min/Max). ............................................................................60

• (SPI Controller Mode Switching Parameters, Clock Phase =1): Updated/Changed Delay time, SPISIMO valid

before SPICLK low, i.e. [Q4] from 0.5t_c(SPC)M–14 to 0.5t_c(SPC)M–7 (Min). .................................................60

• (SPI Controller Mode Switching Parameters, Clock Phase =1): Updated/Changed Valid time, SPISIMO data

valid after SPICLK low, i.e. [Q5] from 0.5t_c(SPC)M–18 to 0.5t_c(SPC)M–8 (Min). ........................................... 60

• (SPI Controller Mode Switching Parameters, Clock Phase =1): Updated/Changed Hold time, SPISOMI data

valid after SPICLK i.e. [Q9] from 3ns to 2ns (Min). ..........................................................................................60

• (SPI Peripheral Mode Switching Parameters ): Updated/Changed Cycle time, SPICLK from 50ns to 20ns; ..62

• (SPI Peripheral Mode Switching Parameters ): Updated/Changed Pulse duration, SPICLK i.e. [Q2, Q3] from

20ns to 8ns (Min). ............................................................................................................................................62

• (SPI Peripheral Mode Switching Parameters ): Updated/Changed Setup time, SPISIMO before SPICLK i.e.

[Q6] from 6ns to 2.1ns (Min). ...........................................................................................................................62

• (RGMII Receive Data and Control Timing Requirements): Updated/Changed Hold time, i.e. [No. 6] from 4.5ns

to 1ns (Min). .....................................................................................................................................................65

• (RMII Transmit Data and Control Switching Characteristics): Updated/Changed Delay time, REF_CLK high to

selected transmit signals valid, i.e. [RMII 11] from 3ns to 2ns (Min). ...............................................................66

• (MII Transmit Switching Characteristics): Updated/Changed Delay time, miin_txclk to transmit selected

signals valid, i.e. [No. 1] from 3ns to 0ns (Min). ...............................................................................................67

• (LVDS Interface Configuration) : Corrected a typo for the number of data lanes in LVDS from '4' to '2'.......... 70

• (Switching Characteristics for IEEE 1149.1 JTAG): Updated/Changed Delay time, TCK low to TDO valid, i.e.

[No. 2] from 27.1ns to 21ns (Max). .................................................................................................................. 76

• (ADC Channels (Service) for User Application): Added a figure in the section................................................ 84

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• (Monitoring and Diagnostic Mechanisms): Updated the section and added a note for reference to safety

related collateral. ............................................................................................................................................. 86

• (Monitoring and Diagnostic Mechanisms): Removed CRC-8 support since polynomials are not supported in

the Design.........................................................................................................................................................86

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5 Device Comparison

表5-1. Device Features Comparison

FUNCTION

AWR2943

AWR2944

AWR2243

AWR1843

Number of receivers

Number of transmitters

On-chip memory

4

3

4

3⁽¹⁾

2MB

10

3.5MB

15

4MB

15

—

20

45

Max I/F (Intermediate Frequency) (MHz)

Max real/complex 2x sampling rate (Msps)

Max complex 1x sampling rate (Msps)

Safety and Security ⁽³⁾

Device Security⁽⁴⁾

37.5 ⁽²⁾

25

(2)

22.5

12.5

—

Yes

—

AEC-Q100 Qualified

Processor

Yes

MCU (RxF)

Yes⁽⁵⁾

Yes⁽⁶⁾

Yes⁽⁷⁾

Yes

Yes⁽⁵⁾

Yes⁽⁶⁾

Yes⁽⁷⁾

Yes

—

DSP (C6xx)

Hardware accelerator

Hardware Security Module (HSM) ⁽⁸⁾

Security Accelerators ⁽⁸⁾

Peripherals

—

Yes

Serial Peripheral Interface (SPI) ports

Quad Serial Peripheral Interface (QSPI)

LVDS/Debug

2

1

2

Yes

1

Yes

1

Yes

—

Yes

Aurora LVDS

—

1

—

Ethernet Interface

Inter-Integrated Circuit (I²C) interface

Controller Area Network (DCAN) interface

CAN FD

1

Yes

1

—

2

—

2

—

Trace

Yes

Yes⁽⁹⁾

Yes

Yes⁽⁹⁾

Yes

—

ePWM

—

DMM Interface

—

GPADC

Yes

CSI2 TX

—

CSI2 RX ⁽¹⁰⁾

Yes

—

Cascade (20-GHz sync)

JTAG

Yes

—

Yes

—

Per chirp configurable Tx phase shifter

Yes

PRODUCT PREVIEW (PP),

ADVANCE INFORMATION (AI),

or PRODUCTION DATA (PD)

Product

PD

status⁽¹¹⁾

(1) 3 Tx Simultaneous operation in AWR1843 and AWR2243 is supported only with 1V LDO bypass and PA LDO disable mode. In this

mode 1V supply needs to be fed on the VOUT PA pin. Please refer to the respective datasheets for more information.

(2) AWR294x supports a real only receiver.

(3) Developed for Functional Safety applications, the AWR294x device is targeted to support hardware integrity up to ASIL-B. For other

devices, refer to the respective Datasheets.

(4) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as

indicated by the Device Type identifier in the 节3, Device Information table.

(5) In AWR294x, Main-Subsystem Processing core is changed from Arm CR4F in AWR1843 to Arm CR5F.

(6) The DSP processing core in AWR294x is upgraded from C67x in AWR1843 to C66x.

(7) The hardware accelerator in AWR294x is upgraded to HWA2.1 with additional features as compared to AWR1843.

(8) Only applicable for AWR294x Secure Part Variant

English Data Sheet: SWRS273

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(9) AWR294x has a dedicated GPADC for external voltage monitoring.

(10) AWR294x support CSI2 Rx based playback functionality .

(11) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and

other specifications are subject to change without notice.

5.1 Related Products

For information about other devices in this family of products or related products, see the following links.

mmWave Sensors

TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less

power using the smallest footprint mmWave sensor portfolio for automotive applications.

Automotive

mmWave Sensors

TI’s automotive mmWave sensor portfolio offers high-performance radar front end to

ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable

sensor portfolio enables design and development of ADAS system solution for every

performance, application and sensor configuration ranging from comfort functions to safety

functions in all vehicles.

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Product Folder Links: AWR2943 AWR2944

English Data Sheet: SWRS273

AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

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6 Pin Configurations and Functions

6.1 Pin Diagram

图 6-1 shows the pin locations for the 12 x12 mm FCBGA package. 图 6-2, 图 6-3, 图 6-4 and 图 6-5 show the

same pins, but split into four quadrants.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

MSS_UARTB DSS_UARTA

MSS_MCANB

_RX

A

B

C

D

E

F

VSSA

OSC_CLKOUT

VSS

VIOIN

MSS_GPIO_1

VSS

_TX

DSS_UARTA

_RX

MSS_UARTA MSS_MCANB

CLKM

VSSA

CLKP

VSSA

RX4

TX1

VSSA

TX2

VSSA

TX3

VSSA

TX4

VSSA

NERROR_OUT

XREF_CLK1

VSS

WARM_RESET XREF_CLK0

MSS_GPIO_0

VIOIN

_RX

_TX

MSS_UARTA

MSS_EPWMB0MSS_EPWMA1

_TX

VSSA

ADC1

ADC3

ADC5

VPP

VSSA

TCK

TMS

MSS_MCANA MSS_MCANA

VDDA_10RF2 VDDA_10RF2

VDDA_18CLK

TDI

TDO

VIOIN_18

_RX

_TX

MSS_RS232

_TX

VDDA_18VCO

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

MSS_EPWMA0

VSS

MSS_RS232

_RX

VSSA

VDD

VSSA

VSS

VDD

VSS

VDD

VSS

VDD

VSS

LVDS_TXP0 LVDS_TXM0

LVDS_TXP2 LVDS_TXM2

VOUT

_14SYNTH

G

H

J

VSSA

RX3

VSS

MSS_GPIO_2

_CLKP

_CLKM

VOUT

_14APLL

LVDS_TXP3 LVDS_TXM3

_FRCLKP _FRCLKM

VSS

NRESET

MSS_GPIO

_11

VSSA

RX2

VSS

LVDS_TXP1 LVDS_TXM1

VIOIN

_18LVDS

VIOIN

_18CSI

K

L

VBGAP

VSS

CSI2

_RX0CLKP

CSI2

_RX0CLKM

VSSA

RX1

VSS

MSS_GPIO_4

MSS_GPIO_9

MCU_CLKOUT

VIDDA

_10RF1

BSS_UARTA

_TX

M

N

P

R

T

VSS

CSI2_RX0P1 CSI2_RX0M1

CSI2_RX0P0 CSI2_RX0M0

VSSA

VDDA_18BB

VDDA_18PM

ADC7

VSSA

ADC2

ADC4

ADC8

ADC6

VSS

MSS_GPIO

VSS

VDD

VSS

MSS_GPIO_3

_30

MSS_MDIO

_CLK

MSS_RGMII

_TCTL

MSS_I2CA

_SDA

MSS_QSPI

_CLK

MSS_MIBSPIB

_CS2

MSS_GPIO

VIOIN

MSS_QSPI_3

_28

MSS_MDIO

_DATA

MSS_RGMII

_RCTL

MSS_RGMII

_RCLK

MSS_MIBSPIB

_CLK

MSS_MIBSPIA MSS_MIBSPIA

_CS0 _CLK

PMIC

MSS_QSPI_2

MSS_QSPI_0

MSS_QSPI_1

MSS_GPIO_8

_CLKOUT

MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII

_TD3

MSS_GPIO

_17

MSS_I2CA

_SCL

MSS_RGMII

_RD3

MSS_QSPI MSS_MIBSPIB MSS_MIBSPIB MSS_MIBSPIA MSS_MIBSPIA MSS_GPIO

U

V

ADC9

VIOIN_18

_TD1

_TD2

_TD0

_CS

_MISO

_CS0

_MOSI

_MISO

_31

MSS

_MIBSPIA

_HOSTIRQ

MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII

_TCLK _RD1 _RD2 _RD0

MSS_MIBSPIB

_MOSI

MSS_MIBSPIB

_CS1

VSSA

VDD_SRAM

VIOIN

VSS

VIOIN_18

VNWA

VSS

VIOIN

VSS

Not to scale

图6-1. Pin Diagram

English Data Sheet: SWRS273

10

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1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

VSSA

CLKM

VSSA

CLKP

VSSA

RX4

TX1

VSSA

TX2

VSSA

TX3

VSSA

TX4

VSSA

VDDA_10RF2 VDDA_10RF2

VDDA_18CLK

VDDA_18VCO

VSSA

VSS

VOUT

_14SYNTH

G

H

VSSA

RX3

VOUT

_14APLL

VSS

Not to scale

1

2

4

3

图6-2. Top Left Quadrant

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Product Folder Links: AWR2943 AWR2944

English Data Sheet: SWRS273

AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

www.ti.com.cn

10

11

12

13

14

15

16

17

18

MSS_UARTB DSS_UARTA

MSS_MCANB

_RX

A

B

C

D

E

F

VSSA

OSC_CLKOUT

VSS

VIOIN

MSS_GPIO_1

VSS

_TX

DSS_UARTA

_RX

MSS_UARTA MSS_MCANB

VSSA

NERROR_OUT

XREF_CLK1

VSS

WARM_RESET XREF_CLK0

MSS_GPIO_0

VIOIN

_RX

_TX

MSS_UARTA

_TX

TCK

TMS

MSS_EPWMB0MSS_EPWMA1

MSS_MCANA MSS_MCANA

TDI

TDO

VIOIN_18

_RX

_TX

MSS_RS232

_TX

VDD

VSS

VDD

VSS

VDD

VSS

VDD

MSS_EPWMA0

VSS

MSS_RS232

_RX

VSS

LVDS_TXP0 LVDS_TXM0

LVDS_TXP2 LVDS_TXM2

G

H

VSS

MSS_GPIO_2

_CLKP

_CLKM

LVDS_TXP3 LVDS_TXM3

_FRCLKP

VSS

NRESET

_FRCLKM

Not to scale

1

3

2

4

图6-3. Top Right Quadrant

English Data Sheet: SWRS273

12

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1

2

3

4

5

6

7

8

9

J

VSSA

VSS

K

L

RX2

VSSA

RX1

VSSA

ADC1

ADC3

ADC5

VPP

VBGAP

VSSA

VDD

VSS

VDD

VSS

VDD

VSSA

VIDDA

_10RF1

M

N

P

R

T

U

V

VSSA

VDDA_18BB

VDDA_18PM

ADC7

VSSA

ADC2

ADC4

ADC8

ADC6

VSS

VDD

MSS_MDIO

_CLK

MSS_RGMII

_TCTL

MSS_I2CA

_SDA

MSS_MDIO

_DATA

MSS_RGMII

_RCTL

MSS_RGMII

_RCLK

MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII

MSS_GPIO

_17

MSS_I2CA

_SCL

ADC9

_TD3

_TD1

_TD2

_TD0

MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII

_TCLK _RD1 _RD2 _RD0

VSSA

VDD_SRAM

VIOIN

VSS

Not to scale

1

2

4

3

图6-4. Bottom Left Quadrant

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Product Folder Links: AWR2943 AWR2944

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AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

www.ti.com.cn

10

11

12

13

14

15

16

17

18

MSS_GPIO

_11

J

VSS

VDD

LVDS_TXP1 LVDS_TXM1

VIOIN

_18LVDS

VIOIN

_18CSI

K

L

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

CSI2

_RX0CLKP

CSI2

_RX0CLKM

MSS_GPIO_4

MSS_GPIO_9

MCU_CLKOUT

BSS_UARTA

_TX

M

N

P

R

T

U

V

VSS

CSI2_RX0P1 CSI2_RX0M1

CSI2_RX0P0 CSI2_RX0M0

VSS

MSS_GPIO

VSS

MSS_GPIO_3

_30

MSS_QSPI

_CLK

MSS_MIBSPIB

_CS2

MSS_GPIO

VIOIN

MSS_QSPI_3

_28

MSS_MIBSPIB

_CLK

MSS_MIBSPIA MSS_MIBSPIA

_CS0 _CLK

PMIC

MSS_QSPI_2

MSS_QSPI_0

MSS_QSPI_1

MSS_GPIO_8

_CLKOUT

MSS_RGMII

_RD3

MSS_QSPI MSS_MIBSPIB MSS_MIBSPIB MSS_MIBSPIA MSS_MIBSPIA MSS_GPIO

VIOIN_18

_CS

_MISO

_CS0

_MOSI

_MISO

_31

MSS

_MIBSPIA

_HOSTIRQ

MSS_MIBSPIB

_MOSI

MSS_MIBSPIB

_CS1

VIOIN_18

VNWA

VSS

VIOIN

VSS

Not to scale

1

2

4

3

图6-5. Bottom Right Quadrant

English Data Sheet: SWRS273

14

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6.3 Signal Descriptions - Digital

备注

All digital IO pins of the device (except NERROR_OUT and WARM_RESET) are non-failsafe; hence,

care needs to be taken that they are not driven externally without the VIO supply being present to the

device.

备注

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the

application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should

be used to isolate the GPIO output from the radar device and a pull resister used to define the

required state in the application. The NRESET signal to the radar device could be used to control the

output enable (OE) of the tri-state buffer.

表6-1. Signal Descriptions - Digital

FUNCTION

SIGNAL NAME

PIN TYPE DESCRIPTION

PIN NUMBER

MSS_MIBSPIA_CLK

MSS_MIBSPIA_MOSI

IO

SPI Channel A - Clock

T16

U15

SPI Channel A - Controller Out Peripheral

In

MSS_MIBSPIA_MISO

IO

SPI Channel A - Controller In Peripheral

Out

U16

MSS_MIBSPIA_CS0

IO

O

SPI Channel A Chip Select

T15

MSS_MIBSPIA_HOSTIRQ

Out of Band Interrupt to an external host

communicating over SPI

V16,V17

SPI Interface

MSS_MIBSPIB_CLK⁽¹⁾

MSS_MIBSPIB_MOSI⁽¹⁾

IO

SPI Channel B - Clock

T13,R10

V12,V11

SPI Channel B - Controller Out Peripheral

In

MSS_MIBSPIB_MISO⁽¹⁾

IO

SPI Channel B - Controller In Peripheral

Out

U13,U11

MSS_MIBSPIB_CS0

MSS_MIBSPIB_CS1

MSS_MIBSPIB_CS2

MSS_MCANA_RX

MSS_MCANA_TX

MSS_MCANB_RX

MSS_MCANB_TX

MSS_UARTA_RX

IO

I

SPI Channel B Chip Select (Instance ID 0)

SPI Channel B Chip Select (Instance ID 1)

SPI Channel B Chip Select (Instance ID 2)

CAN-FD A (MCAN) Receive Signal

CAN-FD A (MCAN) Transmit Signal

CAN-FD B (MCAN) Receive Signal

CAN-FD B (MCAN) Transmit Signal

U14,U12

V16,A16,R14

A16,V11,R14,V17

T13,R12,C14,F16,D16

U14,T11,C12,E17,D17

V12,A17

O

I

CAN-FD

O

IO

U13,B17

Main Subsystem - UART A Receive

(For Flash programming)

T13,D13,F16,P17,B16,A15

MSS_UARTA_TX

MSS_UARTB_TX

MSS_UARTB_RX

IO

Main Subsystem - UART A Transmit (For

Flash programming)

U14,D15,E17,U17,C16,B14,

A14

UART (MSS)

Main Subsystem - UART B Receive

T13,U14,C12,D15,G15,E17,

L15,U4,B16,A14

Main Subsystem - UART B Transmit

R17,F16,T7,C16

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Product Folder Links: AWR2943 AWR2944

English Data Sheet: SWRS273

AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

www.ti.com.cn

表6-1. Signal Descriptions - Digital (continued)

FUNCTION

SIGNAL NAME

PIN TYPE DESCRIPTION

PIN NUMBER

MSS_QSPI_0

IO

QSPI Data Line #0 (Used with Serial Data

Flash)

U11

V11

T11

R12

MSS_QSPI_1

MSS_QSPI_2

MSS_QSPI_3

I

QSPI Data Line #1 (Used with Serial Data

Flash)

QSPI Data Line #2 (Used with Serial Data

Flash)

QSPI for Serial

Flash

QSPI Data Line #3 (Used with Serial Data

Flash)

MSS_QSPI_CLK

MSS_QSPI_CS

IO

O

QSPI clock (Used with Serial Data Flash)

R10

U12

QSPI chip select (Used with Serial Data

Flash)

MSS_I2CA_SDA

MSS_I2CA_SCL

MSS_RS232_RX

IO

I2C Clock

I2C Data

V12,E17,U17,R8

U13,F16,P17,U9

F16

I2C interface

RS232 UART

Debug UART (Operates as Bus controller) -

Receive Signal

MSS_RS232_TX

IO

Debug UART (Operates as Bus controller) -

Transmit Signal

E17

MSS_EPWMA0

O

I

PWM Module 1 - Output A0

PWM Module 1 - Output A1

PWM Module 1 - Sync Input

PWM Module 1 - Sync Output

PWM Module 2 - Output B0

V12,R15,E17,E15,B17,R6

B15,T17,E17,C18,A17,U8

A16,D17

MSS_EPWMA1

MSS_EPWMA_SYNCI

MSS_EPWMA_SYNCO

MSS_EPWMB0

O

D16

B15,U13,T17,R14,F16,E17,

B17,C17,T7

MSS_EPWMB1

O

I

PWM Module 2 - Output B1

PWM Module 2 - Sync Input

PWM Module 2 - Sync Output

PWM Module 3 - Output C0

PWM Module 3 - Output C1

PWM Module 3 - Sync Input

PWM Module 3 - Sync Output

PWM module Trip Signal 0

PWM module Trip Signal 1

PWM module Trip Signal 2

R14,F16,A17,R8

T18,A14

MSS_EPWMB_SYNCI

MSS_EPWMB_SYNCO

MSS_EPWMC0

PWM Module

O

I

P16

T13,F16,E15,C17,U4

C18,U9

MSS_EPWMC1

MSS_EPWMC_SYNCI

MSS_EPWMC_SYNCO

MSS_EPWM_TZ0

MSS_EPWM_TZ1

MSS_EPWM_TZ2

P17

O

I

N15

G15,J15

I

A16,M16

B15,L15

I

English Data Sheet: SWRS273

28

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FUNCTION

表6-1. Signal Descriptions - Digital (continued)

SIGNAL NAME

PIN TYPE DESCRIPTION

PIN NUMBER

MSS_MII_COL

I

U8

MSS Ethernet MII Collision Detect

MSS_MII_CRS

R8

MSS Ethernet MII Carrier Sense

MSS Ethernet MII Receive Error

MSS Ethernet MII Transmit Enable

MSS_MII_RXER

MSS_MII_TXEN

MSS_MII_RXDV

I

O

I

U9

R6

T7

MSS Ethernet MII Receive Data Valid

MSS_MII_TXD3

MSS_MII_TXD2

MSS_MII_TXD1

MSS_MII_TXD0

MSS_MII_TXCLK

MSS_MII_RXCLK

MSS_MII_RXD3

MSS_MII_RXD2

MSS_MII_RXD1

MSS_MII_RXD0

MSS_RMII_REFCLK

MSS_RMII_CRS_DV

O

I

MSS Ethernet MII Transmit Data 3

MSS Ethernet MII Transmit Data 2

MSS Ethernet MII Transmit Data 1

MSS Ethernet MII Transmit Data 0

MSS Ethernet MII Transmit Clock

MSS Ethernet MII Receive Clock

MSS Ethernet MII Receive Data 3

MSS Ethernet MII Receive Data 2

MSS Ethernet MII Receive Data 1

MSS Ethernet MII Receive Data 0

MSS Ethernet RMII Clock Input

U4

U6

U5

U7

V3

I

T9

I

U10

V5

I

V4

I

V6

IO

I

U8,T9

R8,T7

MSS Ethernet RMII Carrier Sense/Receive

Data Valid

MSS_RMII_RXER

MSS_RMII_TXEN

MSS_RMII_TXD1

MSS_RMII_TXD0

MSS_RMII_RXD1

MSS_RMII_RXD0

MSS_RGMII_TCTL

MSS_RGMII_RCTL

MSS_RGMII_TD3

MSS_RGMII_TD2

MSS_RGMII_TD1

MSS_RGMII_TD0

MSS_RGMII_TCLK

MSS_RGMII_RCLK

MSS_RGMII_RD3

MSS_RGMII_RD2

MSS_RGMII_RD1

MSS_RGMII_RD0

MSS_MDIO_DATA

I

O

I

MSS Ethernet RMII Receive Error

MSS Ethernet RMII Transmit Enable

MSS Ethernet RMII Transmit Data 1

MSS Ethernet RMII Transmit Data 0

MSS Ethernet MII Receive Data 1

MSS Ethernet MII Receive Data 0

MSS Ethernet RGMII Transmit Control

MSS Ethernet RGMII Receive Control

MSS Ethernet RGMII Transmit Data 3

MSS Ethernet RGMII Transmit Data 2

MSS Ethernet RGMII Transmit Data 1

MSS Ethernet RGMII Transmit Data 0

MSS Ethernet RGMII Transmit Clock

MSS Ethernet RGMII Receive Clock

MSS Ethernet RGMII Receive Data 3

MSS Ethernet RGMII Receive Data 2

MSS Ethernet RGMII Receive Data 1

MSS Ethernet RGMII Receive Data 0

U9

R6

U5

U7

V4

V6

R6

T7

RGMII/RMII/MII

Ethernet

I

O

I

O

I

U4

U6

U5

U7

V3

T9

I

U10

V5

V4

V6

T5

I

IO

MSS Ethernet Manage Data Input/Output

data

MSS_MDIO_CLK

O

MSS Ethernet Manage Data Input/Output

Clock

R4

MSS_CPTS0_TS_SYNC

O

I

Ethernet Timestamp SYNC output

B16

C16

MSS_CPTS0_HW2TSPUS

H

Ethernet hardware Timestamp Inputs Pins

MSS_CPTS0_HW1TSPUS

H

I

A15

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表6-1. Signal Descriptions - Digital (continued)

FUNCTION

SIGNAL NAME

TRACE_DATA_0

TRACE_DATA_1

TRACE_DATA_2

TRACE_DATA_3

TRACE_DATA_4

TRACE_DATA_5

TRACE_DATA_6

TRACE_DATA_7

TRACE_DATA_8

TRACE_DATA_9

TRACE_DATA_10

TRACE_DATA_11

TRACE_DATA_12

TRACE_DATA_13

TRACE_DATA_14

TRACE_CLK

PIN TYPE DESCRIPTION

PIN NUMBER

O

Debug Trace Output - Data Line

U17

P17

T18

N15

P16

L15

M16

J15

Debug Trace Output - Data Line

Debug Trace Output - Clock

Trace Signal

D17

D16

E15

C18

B17

A17

C17

R15

T17

TRACE_CTL

Debug Trace Output - Control

English Data Sheet: SWRS273

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FUNCTION

表6-1. Signal Descriptions - Digital (continued)

SIGNAL NAME

PIN TYPE DESCRIPTION

PIN NUMBER

DMM0

I

Debug Interface (Hardware In Loop) - Data

Line

U17

DMM1

Debug Interface (Hardware In Loop) - Data

Line

P17

T18

N15

P16

L15

M16

J15

DMM2

Debug Interface (Hardware In Loop) - Data

Line

DMM3

Debug Interface (Hardware In Loop) - Data

Line

DMM4

Debug Interface (Hardware In Loop) - Data

Line

DMM5

Debug Interface (Hardware In Loop) - Data

Line

DMM6

Debug Interface (Hardware In Loop) - Data

Line

DMM7

Debug Interface (Hardware In Loop) - Data

Line

DMM8

Debug Interface (Hardware In Loop) - Data

Line

D17

D16

E15

C18

B17

A17

C17

R15

DMM9

Debug Interface (Hardware In Loop) - Data

Line

DMM Interface

DMM10

DMM11

DMM12

DMM13

DMM14

DMM_CLK

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) -

Clock

DMM_SYNC

I

Debug Interface (Hardware In Loop) - Sync

T17

DMM_MUX_IN

Debug Interface (Hardware In Loop) Mux

Select between DMM1 and DMM2 (Two

Instances)

A16,R17,R14

NDMM_EN

O

Debug Interface (Hardware In Loop)

Enable - Active Low Signal

D15,E17

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表6-1. Signal Descriptions - Digital (continued)

FUNCTION

SIGNAL NAME

MSS_GPIO_0

MSS_GPIO_1

MSS_GPIO_2

MSS_GPIO_3

MSS_GPIO_4

MSS_GPIO_5

MSS_GPIO_6

MSS_GPIO_7

MSS_GPIO_8

MSS_GPIO_9

MSS_GPIO_10

MSS_GPIO_11

MSS_GPIO_12

MSS_GPIO_13

MSS_GPIO_14

MSS_GPIO_15

MSS_GPIO_16

MSS_GPIO_17

MSS_GPIO_18

MSS_GPIO_19

MSS_GPIO_20

MSS_GPIO_21

MSS_GPIO_22

MSS_GPIO_23

MSS_GPIO_24

MSS_GPIO_25

MSS_GPIO_26

MSS_GPIO_27

MSS_GPIO_28

MSS_GPIO_29

MSS_GPIO_30

MSS_GPIO_31

DSS_UARTA_TX

DSS_UARTA_RX

ADC_VALID

PIN TYPE DESCRIPTION

PIN NUMBER

IO

O

General-purpose I/O

B15,P17,U15,A14

A16,T18,U16,B13

G15,N15,T16,V17,D11

P16,T15

General-purpose I/O

Debug UART Transmit [DSP]

Debug UART Receive [DSP]

When high, indicating valid ADC samples

U14,L15,V17

T13,M16

U12,J15

R10,D17

U11,T18,D16,V17,B16,B13

V11,N15,E15,C16,D11

T11,M16,C18,A15

R12,J15,B17,B14

V16,A17,B16

B15,C17,C16

E17,A15

F16,B14

General-purpose

I/Os

A16

C12,C17,U8

C14,A17,R8

B17,U9

C18,R6

V12,E15,T7

U13,D16,U4

D13,D17,U6

D15,J15,U5

R15,M16,U7

G15,L15,V3

T17,P16,T9

R17,N15,U10

R14,T18,V5,D11

P17,V4,T5,B13

U17,V6,R4,A14

U13,R10,J15,B16,A15,A14

D13,R17,C16,B14

V16,T11,R12,R17

G15,T17

UART (DSS)

CHIRP_START

O

Pulse signal indicating the start of each

chirp

Chirp/Frame signals

CHIRP_END

O

Pulse signal indicating the end of each

chirp

G15,T17

FRAME_START

LVDS_VALID

Pulse signal indicating the start of each

frame

R15,G15,T17

When high, indicating valid LVDS data

A16,R15,G15,T17,R14,E17,

A14

LVDS_VALID

MCU_CLKOUT

PMIC_CLKOUT

Programmable clock given out to external

MCU or the processor

R15,B13

External clock out

Output Clock from the device for PMIC

B15,G15,T17,D11

English Data Sheet: SWRS273

32

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FUNCTION

表6-1. Signal Descriptions - Digital (continued)

SIGNAL NAME

SYNC_IN

PIN TYPE DESCRIPTION

PIN NUMBER

R17

I

Low frequency Synchronization signal input

System

Synchronization

SYNC_OUT

O

Low Frequency Synchronization Signal

output

A16,G15,R17,R14

OBS_CLKOUT

RCOSC_CLK

XREF_CLK0

XREF_CLK1

TCK

O

I

Observation Clock Output

Internal RCOSC Clock Output

External reference input clock 0

External reference input clock 1

JTAG Test Clock

R15,T17

R14

Clock Output

B13

Reference Clock

I

D11

I

C12

TMS

IO

I

JTAG Test Mode Signal

C14

JTAG

TDI

JTAG Test Data Input

D13

TDO

O

JTAG Test Data Output

D15

BSS_UARTA_TX

Debug UART Transmit [Radar Block]

A16,T13,U14,C14,D15,F16,

E17,M16

UART (BSS)

Reset

BSS_UARTA_RX

WARM_RESET

I

Debug UART Receive [Radar Block]

C12,R15

B12

IO

Open drain fail safe warm reset signal. Can

be driven from PMIC for diagnostic or can

be used as status signal that the device is

going through reset.

NERROR_OUT

O

Open drain fail safe output signal.

Connected to PMIC/Processor/MCU to

indicate that some severe criticality fault

has happened. Recovery would be through

reset.

C11

Safety

SOP[0]

SOP[1]

SOP[2]

SOP[3]

SOP[4]

I

The SOP pins are driven externally (weak

drive) and the mmWave device senses the

state of these pins during bootup to decide

the bootup mode. After boot the same pins

have other functionality.

D15

R14

T17

A14

C16

•

[SOP2 SOP1 SOP0] = [0 0 1] ->

Functional QSPI load mode

[SOP2 SOP1 SOP0] = [1 0 1] -> UART

load mode

Sense On power

[SOP2 SOP1 SOP0] = [0 1 1] -> debug

and development mode

The following configuration of SOP pins

help decide the reference crystal frequency

•

[SOP4 SOP3] = [0 0] -> 40 MHz

CSI2_RX0M0

CSI2_RX0P0

CSI2_RX0CLKM

CSI2_RX0CLKP

CSI2_RX0M1

CSI2_RX0P1

I

CSI2.0 Receiver #1, Negative Polarity,

Lane 0

N18

N17

L18

L17

M18

M17

CSI2.0 Receiver #1, Positive Polarity, Lane

0

CSI2.0 Receiver #1, Clock Input, Negative

Polarity

CSI2 RX

CSI2.0 Receiver #1, Clock Input, Positive

Polarity

CSI2.0 Receiver #1, Negative Polarity Lane

1

CSI2.0 Receiver #1, Positive Polarity Lane

1

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表6-1. Signal Descriptions - Digital (continued)

FUNCTION

SIGNAL NAME

LVDS_TXM0

PIN TYPE DESCRIPTION

PIN NUMBER

O

F18

F17

G18

G17

H18

H17

J18

LVDS/Aurora Transmitter, Data Output,

Lane 0

LVDS_TXP0

LVDS_TXM2_CLKM

LVDS_TXP2_CLKP

LVDS_TXM3_FRCLKM

LVDS_TXP3_FRCLKP

LVDS_TXM1

LVDS Clock, Aurora Data output - Lane 2

Aurora LVDS

LVDS Frame Clock, Aurora Data Output -

Lane 3

LVDS/Aurora Transmitter, Data Output,

Lane 1

LVDS_TXP1

J17

(1) In order to meet SPI timings, it is recommended to use MSS_MIBSPIB_CLK = T13 with MSS_MIBSPIB_MOSI = V12 and

MSS_MIBSPIB_MISO = U13. The same applies for the other MSS_MIBSPIB_CLK = R10 as well i.e. with MSS_MIBSPIB_MOSI = V11

and MSS_MIBSPIB_MISO = U11

6.4 Signal Descriptions - Analog

TYPE

INTERFACE

SIGNAL NAME

DESCRIPTION

BALL NO.

TX1

TX2

TX3

TX4⁽¹⁾

RX1

RX2

RX3

RX4

O

I

Single ended transmitter 1 O/P

Single ended transmitter 2 O/P

Single ended transmitter 3 O/P

Single ended transmitter 4 O/P

Single ended receiver 1 I/P

Single ended receiver 2 I/P

Single ended receiver 3 I/P

Single ended receiver 4 I/P

Power on reset for chip. Active low

B3

B5

B7

B9

M2

K2

H2

F2

Transmitters

I

Receivers

Reset

I

NRESET

I

H16

In XTAL mode: Input for the reference crystal

In External clock mode: Single ended input

reference clock port

CLKP

I

D1

B1

Reference

Oscillator

In XTAL mode: Feedback drive for the reference

crystal

CLKM

In External clock mode: Connect this port to ground

Reference clock output from clocking subsystem

after cleanup PLL

Reference clock

Bandgap voltage

OSC_CLKOUT

VBGAP

O

A11

K4

Device's Band Gap Reference Output

E12,E13,E14,F14,H

14,J14,K14,L14,N6,

N14,P6,P7,P9,P10,

P11,P13,P14

VDD

Power 1.2V digital power supply

VDD_SRAM

VNWA

Power 1.2V power rail for internal SRAM

V7

Power 1.2V power rail for SRAM array back bias

V13

I/O Supply (3.3V or 1.8V): All CMOS I/Os would

operate on this supply

A13,B18,R18,V8,V1

5

VIOIN

Power

Power supply

VIOIN_18

Power 1.8V supply for CMOS IO

Power 1.8V supply for clock module

Power 1.8V supply for PM module

Power 1.8V supply for LVDS port

Power 1.8V supply for CSI port

Power Voltage supply for fuse chain

D18,U18,V10

VDDA_18CLK

VDDA_18PM

VIOIN_18LVDS

VIOIN_18CSI

VPP

D9

R1

K17

K18

U3

English Data Sheet: SWRS273

34

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INTERFACE

TYPE

SIGNAL NAME

VIDDA_10RF1

DESCRIPTION

BALL NO.

1V Analog and RF supply,VDDA_10RF1 and

VDDA_10RF2 could be shorted on the board

Power

M4

VDDA_10RF2

VDDA_18BB

VDDA_18VCO

Power 1V Analog and RF supply

Power 1.8V Analog base band power supply

Power 1.8V RF VCO supply

D6, D7

P1

E4

A12,A18,E11,E18,F

8,F9,F10,F11,F12,F

13,G7,G8,G9,G10,

G11,G12,G13,G14,

H7,H8,H9,H10,H11,

H12,H13,J7,J8,J9,J

10,J11,J12,J13,K7,

K8,K9,K10,K11,K12

,K13,K16,L7,L8,L9,

L10,L11,L12,L13,M

7,M8,M9,M10,M11,

M12,M13,M14,N7,N

8,N9,N10,N11,N12,

N13,P8,P12,P18,V2

,V9,V14,V18

VSS⁽³⁾

Ground Digital ground

Power supply

A1,A2,A4,A6,A8,A1

0,B2,B4,B6,B8,B10,

B11,C1,C2,C3,C4,C

5,C6,C7,C8,C9,C10

,D2,D3,E1,E2,E3,F

3,F6,F7,G1,G2,G3,

G6,H3,H6,J1,J2,J3,

J6,K3,K6,L1,L2,L3,

L6,M3,M6,N1,N2,N

3,V1

VSSA⁽⁴⁾

Ground Analog ground

VOUT_14APLL

VOUT_14SYNTH

ADC1

O

Internal LDO output

ADC Channel 1

ADC Channel 2

ADC Channel 3

ADC Channel 4

ADC Channel 5

ADC Channel 6

ADC Channel 7

ADC Channel 8

ADC Channel 9

H4

G4

P3

P2

R3

R2

T3

U2

T1

T2

U1

Internal LDO output/

inputs

O

IO

ADC2

ADC3

General purpose

ADC inputs for

external voltage

monitoring⁽²⁾

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

(1) TX4 is only applicable in the AWR294x variant with 4 transmitters i.e. AWR2944.

(2) For details, see 节8.4.3

(3) Corner BGAs are VSS and redundant, meaning if they fail the device will still function.

(4) The VSSA BGAs around the launches are not redundant and are required for functionality.

6.3 Signal Descriptions - Digital

备注

All digital IO pins of the device (except NERROR_OUT and WARM_RESET) are non-failsafe; hence,

care needs to be taken that they are not driven externally without the VIO supply being present to the

device.

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备注

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the

application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should

be used to isolate the GPIO output from the radar device and a pull resister used to define the

required state in the application. The NRESET signal to the radar device could be used to control the

output enable (OE) of the tri-state buffer.

表6-1. Signal Descriptions - Digital

FUNCTION

SIGNAL NAME

PIN TYPE DESCRIPTION

PIN NUMBER

MSS_MIBSPIA_CLK

MSS_MIBSPIA_MOSI

IO

SPI Channel A - Clock

T16

U15

SPI Channel A - Controller Out Peripheral

In

MSS_MIBSPIA_MISO

IO

SPI Channel A - Controller In Peripheral

Out

U16

MSS_MIBSPIA_CS0

IO

O

SPI Channel A Chip Select

T15

MSS_MIBSPIA_HOSTIRQ

Out of Band Interrupt to an external host

communicating over SPI

V16,V17

SPI Interface

MSS_MIBSPIB_CLK⁽¹⁾

MSS_MIBSPIB_MOSI⁽¹⁾

IO

SPI Channel B - Clock

T13,R10

V12,V11

SPI Channel B - Controller Out Peripheral

In

MSS_MIBSPIB_MISO⁽¹⁾

IO

SPI Channel B - Controller In Peripheral

Out

U13,U11

MSS_MIBSPIB_CS0

MSS_MIBSPIB_CS1

MSS_MIBSPIB_CS2

MSS_MCANA_RX

MSS_MCANA_TX

MSS_MCANB_RX

MSS_MCANB_TX

MSS_UARTA_RX

IO

I

SPI Channel B Chip Select (Instance ID 0)

SPI Channel B Chip Select (Instance ID 1)

SPI Channel B Chip Select (Instance ID 2)

CAN-FD A (MCAN) Receive Signal

CAN-FD A (MCAN) Transmit Signal

CAN-FD B (MCAN) Receive Signal

CAN-FD B (MCAN) Transmit Signal

U14,U12

V16,A16,R14

A16,V11,R14,V17

T13,R12,C14,F16,D16

U14,T11,C12,E17,D17

V12,A17

O

I

CAN-FD

O

IO

U13,B17

Main Subsystem - UART A Receive

(For Flash programming)

T13,D13,F16,P17,B16,A15

MSS_UARTA_TX

MSS_UARTB_TX

IO

Main Subsystem - UART A Transmit (For

Flash programming)

U14,D15,E17,U17,C16,B14,

A14

UART (MSS)

Main Subsystem - UART B Receive

T13,U14,C12,D15,G15,E17,

L15,U4,B16,A14

MSS_UARTB_RX

MSS_QSPI_0

IO

Main Subsystem - UART B Transmit

R17,F16,T7,C16

U11

QSPI Data Line #0 (Used with Serial Data

Flash)

MSS_QSPI_1

MSS_QSPI_2

MSS_QSPI_3

I

QSPI Data Line #1 (Used with Serial Data

Flash)

V11

T11

R12

QSPI Data Line #2 (Used with Serial Data

Flash)

QSPI for Serial

Flash

QSPI Data Line #3 (Used with Serial Data

Flash)

MSS_QSPI_CLK

MSS_QSPI_CS

IO

O

QSPI clock (Used with Serial Data Flash)

R10

U12

QSPI chip select (Used with Serial Data

Flash)

MSS_I2CA_SDA

MSS_I2CA_SCL

IO

I2C Clock

I2C Data

V12,E17,U17,R8

U13,F16,P17,U9

I2C interface

English Data Sheet: SWRS273

36

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表6-1. Signal Descriptions - Digital (continued)

FUNCTION

SIGNAL NAME

PIN TYPE DESCRIPTION

PIN NUMBER

MSS_RS232_RX

IO

Debug UART (Operates as Bus controller) -

Receive Signal

F16

RS232 UART

MSS_RS232_TX

Debug UART (Operates as Bus controller) -

Transmit Signal

E17

MSS_EPWMA0

O

I

PWM Module 1 - Output A0

PWM Module 1 - Output A1

PWM Module 1 - Sync Input

PWM Module 1 - Sync Output

PWM Module 2 - Output B0

V12,R15,E17,E15,B17,R6

B15,T17,E17,C18,A17,U8

A16,D17

MSS_EPWMA1

MSS_EPWMA_SYNCI

MSS_EPWMA_SYNCO

MSS_EPWMB0

O

D16

B15,U13,T17,R14,F16,E17,

B17,C17,T7

MSS_EPWMB1

O

I

PWM Module 2 - Output B1

PWM Module 2 - Sync Input

PWM Module 2 - Sync Output

PWM Module 3 - Output C0

PWM Module 3 - Output C1

PWM Module 3 - Sync Input

PWM Module 3 - Sync Output

PWM module Trip Signal 0

PWM module Trip Signal 1

PWM module Trip Signal 2

R14,F16,A17,R8

T18,A14

MSS_EPWMB_SYNCI

MSS_EPWMB_SYNCO

MSS_EPWMC0

PWM Module

O

I

P16

T13,F16,E15,C17,U4

C18,U9

MSS_EPWMC1

MSS_EPWMC_SYNCI

MSS_EPWMC_SYNCO

MSS_EPWM_TZ0

MSS_EPWM_TZ1

MSS_EPWM_TZ2

P17

O

I

N15

G15,J15

I

A16,M16

B15,L15

I

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表6-1. Signal Descriptions - Digital (continued)

FUNCTION

SIGNAL NAME

PIN TYPE DESCRIPTION

PIN NUMBER

MSS_MII_COL

I

U8

R8

MSS Ethernet MII Collision Detect

MSS_MII_CRS

MSS Ethernet MII Carrier Sense

MSS Ethernet MII Receive Error

MSS Ethernet MII Transmit Enable

MSS_MII_RXER

MSS_MII_TXEN

MSS_MII_RXDV

I

O

I

U9

R6

T7

MSS Ethernet MII Receive Data Valid

MSS_MII_TXD3

MSS_MII_TXD2

MSS_MII_TXD1

MSS_MII_TXD0

MSS_MII_TXCLK

MSS_MII_RXCLK

MSS_MII_RXD3

MSS_MII_RXD2

MSS_MII_RXD1

MSS_MII_RXD0

MSS_RMII_REFCLK

MSS_RMII_CRS_DV

O

I

MSS Ethernet MII Transmit Data 3

MSS Ethernet MII Transmit Data 2

MSS Ethernet MII Transmit Data 1

MSS Ethernet MII Transmit Data 0

MSS Ethernet MII Transmit Clock

MSS Ethernet MII Receive Clock

MSS Ethernet MII Receive Data 3

MSS Ethernet MII Receive Data 2

MSS Ethernet MII Receive Data 1

MSS Ethernet MII Receive Data 0

MSS Ethernet RMII Clock Input

U4

U6

U5

U7

V3

I

T9

I

U10

V5

I

V4

I

V6

IO

I

U8,T9

R8,T7

MSS Ethernet RMII Carrier Sense/Receive

Data Valid

MSS_RMII_RXER

MSS_RMII_TXEN

MSS_RMII_TXD1

MSS_RMII_TXD0

MSS_RMII_RXD1

MSS_RMII_RXD0

MSS_RGMII_TCTL

MSS_RGMII_RCTL

MSS_RGMII_TD3

MSS_RGMII_TD2

MSS_RGMII_TD1

MSS_RGMII_TD0

MSS_RGMII_TCLK

MSS_RGMII_RCLK

MSS_RGMII_RD3

MSS_RGMII_RD2

MSS_RGMII_RD1

MSS_RGMII_RD0

MSS_MDIO_DATA

I

O

I

MSS Ethernet RMII Receive Error

MSS Ethernet RMII Transmit Enable

MSS Ethernet RMII Transmit Data 1

MSS Ethernet RMII Transmit Data 0

MSS Ethernet MII Receive Data 1

MSS Ethernet MII Receive Data 0

MSS Ethernet RGMII Transmit Control

MSS Ethernet RGMII Receive Control

MSS Ethernet RGMII Transmit Data 3

MSS Ethernet RGMII Transmit Data 2

MSS Ethernet RGMII Transmit Data 1

MSS Ethernet RGMII Transmit Data 0

MSS Ethernet RGMII Transmit Clock

MSS Ethernet RGMII Receive Clock

MSS Ethernet RGMII Receive Data 3

MSS Ethernet RGMII Receive Data 2

MSS Ethernet RGMII Receive Data 1

MSS Ethernet RGMII Receive Data 0

U9

R6

U5

U7

V4

V6

R6

T7

RGMII/RMII/MII

Ethernet

I

O

I

O

I

U4

U6

U5

U7

V3

T9

I

U10

V5

V4

V6

T5

I

IO

MSS Ethernet Manage Data Input/Output

data

MSS_MDIO_CLK

O

MSS Ethernet Manage Data Input/Output

Clock

R4

MSS_CPTS0_TS_SYNC

O

I

Ethernet Timestamp SYNC output

B16

C16

MSS_CPTS0_HW2TSPUS

H

Ethernet hardware Timestamp Inputs Pins

MSS_CPTS0_HW1TSPUS

H

I

A15

English Data Sheet: SWRS273

38

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FUNCTION

表6-1. Signal Descriptions - Digital (continued)

SIGNAL NAME

TRACE_DATA_0

TRACE_DATA_1

TRACE_DATA_2

TRACE_DATA_3

TRACE_DATA_4

TRACE_DATA_5

TRACE_DATA_6

TRACE_DATA_7

TRACE_DATA_8

TRACE_DATA_9

TRACE_DATA_10

TRACE_DATA_11

TRACE_DATA_12

TRACE_DATA_13

TRACE_DATA_14

TRACE_CLK

PIN TYPE DESCRIPTION

PIN NUMBER

U17

O

Debug Trace Output - Data Line

Debug Trace Output - Clock

P17

T18

N15

P16

L15

M16

J15

Trace Signal

D17

D16

E15

C18

B17

A17

C17

R15

TRACE_CTL

Debug Trace Output - Control

T17

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表6-1. Signal Descriptions - Digital (continued)

FUNCTION

SIGNAL NAME

PIN TYPE DESCRIPTION

PIN NUMBER

DMM0

I

Debug Interface (Hardware In Loop) - Data

Line

U17

P17

T18

N15

P16

L15

M16

J15

DMM1

Debug Interface (Hardware In Loop) - Data

Line

DMM2

Debug Interface (Hardware In Loop) - Data

Line

DMM3

Debug Interface (Hardware In Loop) - Data

Line

DMM4

Debug Interface (Hardware In Loop) - Data

Line

DMM5

Debug Interface (Hardware In Loop) - Data

Line

DMM6

Debug Interface (Hardware In Loop) - Data

Line

DMM7

Debug Interface (Hardware In Loop) - Data

Line

DMM8

Debug Interface (Hardware In Loop) - Data

Line

D17

D16

E15

C18

B17

A17

C17

R15

DMM9

Debug Interface (Hardware In Loop) - Data

Line

DMM Interface

DMM10

DMM11

DMM12

DMM13

DMM14

DMM_CLK

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) - Data

Line

Debug Interface (Hardware In Loop) -

Clock

DMM_SYNC

I

Debug Interface (Hardware In Loop) - Sync

T17

DMM_MUX_IN

Debug Interface (Hardware In Loop) Mux

Select between DMM1 and DMM2 (Two

Instances)

A16,R17,R14

NDMM_EN

O

Debug Interface (Hardware In Loop)

Enable - Active Low Signal

D15,E17

English Data Sheet: SWRS273

40

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FUNCTION

表6-1. Signal Descriptions - Digital (continued)

SIGNAL NAME

MSS_GPIO_0

MSS_GPIO_1

MSS_GPIO_2

MSS_GPIO_3

MSS_GPIO_4

MSS_GPIO_5

MSS_GPIO_6

MSS_GPIO_7

MSS_GPIO_8

MSS_GPIO_9

MSS_GPIO_10

MSS_GPIO_11

MSS_GPIO_12

MSS_GPIO_13

MSS_GPIO_14

MSS_GPIO_15

MSS_GPIO_16

MSS_GPIO_17

MSS_GPIO_18

MSS_GPIO_19

MSS_GPIO_20

MSS_GPIO_21

MSS_GPIO_22

MSS_GPIO_23

MSS_GPIO_24

MSS_GPIO_25

MSS_GPIO_26

MSS_GPIO_27

MSS_GPIO_28

MSS_GPIO_29

MSS_GPIO_30

MSS_GPIO_31

DSS_UARTA_TX

DSS_UARTA_RX

ADC_VALID

PIN TYPE DESCRIPTION

PIN NUMBER

B15,P17,U15,A14

A16,T18,U16,B13

G15,N15,T16,V17,D11

P16,T15

IO

O

General-purpose I/O

Debug UART Transmit [DSP]

Debug UART Receive [DSP]

When high, indicating valid ADC samples

U14,L15,V17

T13,M16

U12,J15

R10,D17

U11,T18,D16,V17,B16,B13

V11,N15,E15,C16,D11

T11,M16,C18,A15

R12,J15,B17,B14

V16,A17,B16

B15,C17,C16

E17,A15

F16,B14

General-purpose

I/Os

A16

C12,C17,U8

C14,A17,R8

B17,U9

C18,R6

V12,E15,T7

U13,D16,U4

D13,D17,U6

D15,J15,U5

R15,M16,U7

G15,L15,V3

T17,P16,T9

R17,N15,U10

R14,T18,V5,D11

P17,V4,T5,B13

U17,V6,R4,A14

U13,R10,J15,B16,A15,A14

D13,R17,C16,B14

V16,T11,R12,R17

G15,T17

UART (DSS)

CHIRP_START

O

Pulse signal indicating the start of each

chirp

Chirp/Frame signals

CHIRP_END

O

Pulse signal indicating the end of each

chirp

G15,T17

FRAME_START

LVDS_VALID

Pulse signal indicating the start of each

frame

R15,G15,T17

When high, indicating valid LVDS data

A16,R15,G15,T17,R14,E17,

A14

LVDS_VALID

MCU_CLKOUT

PMIC_CLKOUT

Programmable clock given out to external

MCU or the processor

R15,B13

External clock out

Output Clock from the device for PMIC

B15,G15,T17,D11

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表6-1. Signal Descriptions - Digital (continued)

FUNCTION

System

SIGNAL NAME

SYNC_IN

PIN TYPE DESCRIPTION

PIN NUMBER

I

Low frequency Synchronization signal input

R17

SYNC_OUT

O

Low Frequency Synchronization Signal

output

A16,G15,R17,R14

Synchronization

OBS_CLKOUT

RCOSC_CLK

XREF_CLK0

XREF_CLK1

TCK

O

I

Observation Clock Output

Internal RCOSC Clock Output

External reference input clock 0

External reference input clock 1

JTAG Test Clock

R15,T17

R14

Clock Output

B13

Reference Clock

I

D11

I

C12

TMS

IO

I

JTAG Test Mode Signal

C14

JTAG

TDI

JTAG Test Data Input

D13

TDO

O

JTAG Test Data Output

D15

BSS_UARTA_TX

Debug UART Transmit [Radar Block]

A16,T13,U14,C14,D15,F16,

E17,M16

UART (BSS)

Reset

BSS_UARTA_RX

WARM_RESET

I

Debug UART Receive [Radar Block]

C12,R15

B12

IO

Open drain fail safe warm reset signal. Can

be driven from PMIC for diagnostic or can

be used as status signal that the device is

going through reset.

NERROR_OUT

O

Open drain fail safe output signal.

Connected to PMIC/Processor/MCU to

indicate that some severe criticality fault

has happened. Recovery would be through

reset.

C11

Safety

SOP[0]

SOP[1]

SOP[2]

SOP[3]

SOP[4]

I

The SOP pins are driven externally (weak

drive) and the mmWave device senses the

state of these pins during bootup to decide

the bootup mode. After boot the same pins

have other functionality.

D15

R14

T17

A14

C16

•

[SOP2 SOP1 SOP0] = [0 0 1] ->

Functional QSPI load mode

[SOP2 SOP1 SOP0] = [1 0 1] -> UART

load mode

Sense On power

[SOP2 SOP1 SOP0] = [0 1 1] -> debug

and development mode

The following configuration of SOP pins

help decide the reference crystal frequency

•

[SOP4 SOP3] = [0 0] -> 40 MHz

CSI2_RX0M0

CSI2_RX0P0

CSI2_RX0CLKM

CSI2_RX0CLKP

CSI2_RX0M1

CSI2_RX0P1

I

CSI2.0 Receiver #1, Negative Polarity,

Lane 0

N18

N17

L18

L17

M18

M17

CSI2.0 Receiver #1, Positive Polarity, Lane

0

CSI2.0 Receiver #1, Clock Input, Negative

Polarity

CSI2 RX

CSI2.0 Receiver #1, Clock Input, Positive

Polarity

CSI2.0 Receiver #1, Negative Polarity Lane

1

CSI2.0 Receiver #1, Positive Polarity Lane

1

English Data Sheet: SWRS273

42

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FUNCTION

表6-1. Signal Descriptions - Digital (continued)

SIGNAL NAME

LVDS_TXM0

PIN TYPE DESCRIPTION

PIN NUMBER

F18

O

LVDS/Aurora Transmitter, Data Output,

Lane 0

LVDS_TXP0

F17

LVDS_TXM2_CLKM

LVDS_TXP2_CLKP

LVDS_TXM3_FRCLKM

LVDS_TXP3_FRCLKP

LVDS_TXM1

G18

LVDS Clock, Aurora Data output - Lane 2

G17

Aurora LVDS

H18

LVDS Frame Clock, Aurora Data Output -

Lane 3

H17

J18

LVDS/Aurora Transmitter, Data Output,

Lane 1

LVDS_TXP1

J17

(1) In order to meet SPI timings, it is recommended to use MSS_MIBSPIB_CLK = T13 with MSS_MIBSPIB_MOSI = V12 and

MSS_MIBSPIB_MISO = U13. The same applies for the other MSS_MIBSPIB_CLK = R10 as well i.e. with MSS_MIBSPIB_MOSI = V11

and MSS_MIBSPIB_MISO = U11

6.4 Signal Descriptions - Analog

TYPE

INTERFACE

SIGNAL NAME

DESCRIPTION

BALL NO.

TX1

TX2

TX3

TX4⁽¹⁾

RX1

RX2

RX3

RX4

O

I

Single ended transmitter 1 O/P

Single ended transmitter 2 O/P

Single ended transmitter 3 O/P

Single ended transmitter 4 O/P

Single ended receiver 1 I/P

Single ended receiver 2 I/P

Single ended receiver 3 I/P

Single ended receiver 4 I/P

Power on reset for chip. Active low

B3

B5

B7

B9

M2

K2

H2

F2

Transmitters

I

Receivers

Reset

I

NRESET

I

H16

In XTAL mode: Input for the reference crystal

In External clock mode: Single ended input

reference clock port

CLKP

I

D1

B1

Reference

Oscillator

In XTAL mode: Feedback drive for the reference

crystal

CLKM

In External clock mode: Connect this port to ground

Reference clock output from clocking subsystem

after cleanup PLL

Reference clock

Bandgap voltage

OSC_CLKOUT

VBGAP

O

A11

K4

Device's Band Gap Reference Output

E12,E13,E14,F14,H

14,J14,K14,L14,N6,

N14,P6,P7,P9,P10,

P11,P13,P14

VDD

Power 1.2V digital power supply

VDD_SRAM

VNWA

Power 1.2V power rail for internal SRAM

V7

Power 1.2V power rail for SRAM array back bias

V13

I/O Supply (3.3V or 1.8V): All CMOS I/Os would

operate on this supply

A13,B18,R18,V8,V1

5

VIOIN

Power

Power supply

VIOIN_18

Power 1.8V supply for CMOS IO

Power 1.8V supply for clock module

Power 1.8V supply for PM module

Power 1.8V supply for LVDS port

Power 1.8V supply for CSI port

Power Voltage supply for fuse chain

D18,U18,V10

VDDA_18CLK

VDDA_18PM

VIOIN_18LVDS

VIOIN_18CSI

VPP

D9

R1

K17

K18

U3

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BALL NO.

M4

TYPE

INTERFACE

SIGNAL NAME

VIDDA_10RF1

DESCRIPTION

1V Analog and RF supply,VDDA_10RF1 and

VDDA_10RF2 could be shorted on the board

Power

VDDA_10RF2

VDDA_18BB

VDDA_18VCO

Power 1V Analog and RF supply

Power 1.8V Analog base band power supply

Power 1.8V RF VCO supply

D6, D7

P1

E4

A12,A18,E11,E18,F

8,F9,F10,F11,F12,F

13,G7,G8,G9,G10,

G11,G12,G13,G14,

H7,H8,H9,H10,H11,

H12,H13,J7,J8,J9,J

10,J11,J12,J13,K7,

K8,K9,K10,K11,K12

,K13,K16,L7,L8,L9,

L10,L11,L12,L13,M

7,M8,M9,M10,M11,

M12,M13,M14,N7,N

8,N9,N10,N11,N12,

N13,P8,P12,P18,V2

,V9,V14,V18

VSS⁽³⁾

Ground Digital ground

Power supply

A1,A2,A4,A6,A8,A1

0,B2,B4,B6,B8,B10,

B11,C1,C2,C3,C4,C

5,C6,C7,C8,C9,C10

,D2,D3,E1,E2,E3,F

3,F6,F7,G1,G2,G3,

G6,H3,H6,J1,J2,J3,

J6,K3,K6,L1,L2,L3,

L6,M3,M6,N1,N2,N

3,V1

VSSA⁽⁴⁾

Ground Analog ground

VOUT_14APLL

VOUT_14SYNTH

ADC1

O

Internal LDO output

ADC Channel 1

ADC Channel 2

ADC Channel 3

ADC Channel 4

ADC Channel 5

ADC Channel 6

ADC Channel 7

ADC Channel 8

ADC Channel 9

H4

G4

P3

P2

R3

R2

T3

U2

T1

T2

U1

Internal LDO output/

inputs

O

IO

ADC2

ADC3

General purpose

ADC inputs for

external voltage

monitoring⁽²⁾

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

(1) TX4 is only applicable in the AWR294x variant with 4 transmitters i.e. AWR2944.

(2) For details, see 节8.4.3

(3) Corner BGAs are VSS and redundant, meaning if they fail the device will still function.

(4) The VSSA BGAs around the launches are not redundant and are required for functionality.

English Data Sheet: SWRS273

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

PARAMETERS

MIN

–0.5

MAX

1.4

UNIT

VDD

1.2 V digital power supply

V

VDD_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

1.4

I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this

supply.

VIOIN

3.8

V

–0.5

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for the PM Module

1.8 V supply for CSI2 port

1.8 V supply for LVDS port

2

V

–0.5

-0.5

VDDA_18CLK

VDDA_18PM

VIOIN_18CSI

VIOIN_18LVDS

–0.5

VDDA_10RF1

VDDA_10RF2

VDDA_18BB

1 V Analog and RF supply, VDDA_10RF1 and VDDA_10RF2

could be shorted on the board.

1.4

V

–0.5

1.8-V Analog baseband power supply

2

V

–0.5

VDDA_18VCO supply 1.8-V RF VCO supply

2

V

RX1-4

TX1-4

Externally applied power on RF inputs

10

dBm

Externally applied power on RF outputs⁽³⁾

Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)

VIOIN + 0.3

VIOIN + 20% up to

–0.3V

Input and output

voltage range

V

Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V

(Transient Overshoot/Undershoot) or external oscillator input

20% of signal period

CLKP, CLKM

Clamp current

Input ports for reference crystal

2

V

–0.5

Input or Output Voltages 0.3 V above or below their respective

power rails. Limit clamp current that flows through the internal

diode protection cells of the I/O.

20

mA

–20

T_J

Operating junction temperature range

140

150

°C

–40

–55

T_STG

Storage temperature range after soldered onto PC board

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma= 1 can be applied on

the TX output.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

All pins

V_(ESD)Electrostatic discharge

All pins

V

Corner pins

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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7.3 Power-On Hours (POH)

JUNCTION

OPERATING

TEMPERATURE (T_j)

NOMINAL CVDD VOLTAGE (V)

POWER-ON HOURS [POH] (HOURS)

CONDITION

(1) (2)

1440 (6%)

4800 (20%)

15600 (65%)

1920 (8%)

240 (1%)

–40°C

75°C

50% duty cycle

1.2

95°C

130°C

140°C

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would

not be applicable, if the Tx gain table is overwritten using an API.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.14

3.135

1.71

NOM

1.2

3.3

1.8

MAX

1.26

3.465

1.89

UNIT

VDD

1.2 V digital power supply

V

VDD_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

I/O supply (3.3 V or 1.8 V):

All CMOS I/Os would operate on this supply.

VIOIN

V

VIOIN_18

1.8 V supply for CMOS IO

V

VDDA_18CLK

VDDA_18PM

1.8 V supply for clock module

1.8 V supply for the PM module

1.71

1.8

1.89

VIOIN_18CSI

1.8 V supply for CSI2 port

1.8 V supply for LVDS port

V

VIOIN_18LVDS

VDDA_10RF1

VDDA_10RF2

VDDA_18BB

VDDA_18VCO

1 V Analog and RF supply. VDDA_10RF1 and VDDA_10RF2

could be shorted on the board

0.95

1

1.05

V

1.8-V Analog baseband power supply

1.8V RF VCO supply

1.71

1.8

1.89

V

Voltage Input High (1.8 V mode)

Voltage Input High (3.3 V mode)

Voltage Input Low (1.8 V mode)

Voltage Input Low (3.3 V mode)

High-level output threshold (I_OH= 6 mA)

Low-level output threshold (I_OL= 6 mA)

V_IL(1.8V Mode)

1.17

0.3 + VIOIN

0.3*VIOIN

0.62

V_IH

V_IL

V

2.25

-0.3

V_OH

V_OL

mV

VIOIN –450

450

0.45

V_IH(1.8V Mode)

0.96

NRESET

SOP[4:0]

V

V_IL(3.3V Mode)

0.65

140

V_IH(3.3V Mode)

1.57

-40

T_J

Operating junction temperature range

℃

English Data Sheet: SWRS273

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7.5 VPP Specifications for One-Time Programmable (OTP) eFuses

This section specifies the operating conditions required for programming the OTP eFuses and is applicable only

for high-security (AWR294x HS) devices. During the process of writing the customer specific keys or other fields

like software version etc. in the efuse , the user needs to provide the VPP supply.

7.5.1 Recommended Operating Conditions for OTP eFuse Programming

PARAMETER

DESCRIPTION

MIN

NOM

MAX

UNIT

Supply voltage range for the eFuse ROM domain during

normal operation

NC

VPP

Supply voltage range for the eFuse ROM domain during OTP

programming⁽¹⁾

1.65

1.7

1.75

50

V

I(VPP)

mA

(1) During normal operation, no voltage should be applied to VPP. This can be typically achieved by disabling the external regulator

attached to the VPP terminal.

7.5.2 Hardware Requirements

The following hardware requirements must be met when programming keys in the OTP eFuses:

• The VPP power supply must be disabled when not programming OTP registers.

7.5.3 Impact to Your Hardware Warranty

You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You

acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a failure

may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI device

specifications prior to the attempted eFuse. CONSEQUENTLY, in these cases of faulty EFUSE programmability,

TI WILL HAVE NO LIABILITY.

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7.6 Power Supply Specifications

表 7-1 describes the four required power rails which must be provided to the AWR294x from an external power

supply. In the case when 1.8V LVCMOS IO is utilized, VIOIN is powered from a 1.8V rail and the 3.3V rail can be

ommited, so only three rails must be provided. Also, depending on the power topology utilized, additional power

supply filtering can be required for the RF 1.0V and baseband, clock and VCO 1.8V supplies to meet the

required ripple specifications. This additional filtering results in separate supply power nets being generated from

these four basic rails.

表7-1. Power Supply Rails Characteristics

SUPPLY VOLTAGE

DEVICE BLOCKS POWERED FROM THE SUPPLY

DEVICE POWER NETS

Input: VDDA_18VCO, VDDA_18CLK, VDDA_18PM,

VDDA_18BB, VIOIN_18CSI, VIOIN_18LVDS,

VIOIN_18

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, CSI2, LVDS, LVCMOS IO

1.8 V

LDO Output: VOUT_14SYNTH, VOUT_14APLL

Power Amplifier, Low Noise Amplifier, Mixers and LO

Distribution

1.0 V

Input: VDDA_10RF2, VDDA_10RF1

VIOIN

3.3 V (or 1.8 V for 1.8 V

I/O mode)

LVCMOS IO

1.2 V

1.7 V

Core Digital and SRAM

VDD, VDD_SRAM, VNWA

VPP

Programming OTP eFuse (For secure devices)

The 1.0 V and 1.8 V power supply ripple specifications are mentioned in 表7-2 The spur and ripple levels have a

dB to dB relationship, for example, a 1 dB increase in supply ripple leads to an approximately 1 dB increase in

spur level. Values quoted are rms levels for a sinusoidal input applied at the specified frequency.

表7-2. Ripple Specifications

RF RAIL

VCO/IF RAIL

FREQUENCY (kHz)

Spur Level (dBc)

1 V (µV_RMS

)

1.8 V (uV_RMS)

10

-85

-95

22

8

6

4

3

2

10990

1420

730

450

300

80

100

200

-98

500

-102

-105

1000

2000

5000

10000

15000

20000

60

40

Power Supply Guidelines

The LP87745-Q1 Power Management IC (PMIC) is recommended for an integrated AWR294x power solution.

This cost and space optimized solution is designed to power the AWR294x radar sensor and its principal

peripherals.

List of benefits when using LP87745-Q1 PMIC to power AWR294x:

1. Full device performance entitlement as validated on TI Evaluation boards

2. Noise/Ripple performance that meets AWR noise/ripple performance specification

a. LP87745-Q1 has high switching frequency at 17.6MHz switching outside IF band & avoiding the LDOs

helps with thermal performance at the system level and bypasses the need for 2^ndstage LC filters to

suppress the ripple and filter out the spurs.

b. Thermal dissipation does not affect RF performance

English Data Sheet: SWRS273

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7.7 Power Consumption Summary

表7-3 and 表7-4 summarize the power consumption at the power terminals.

表7-3. Maximum Current Ratings at Power Terminals

PARAMETER⁽¹⁾

SUPPLY NAME

DESCRIPTION

MIN

TYP

MAX⁽¹⁾

UNIT

Total current drawn by all

nodes driven by 1.2V rail

VDD, VDD_SRAM, VNWA

2000

Total current drawn by all

nodes driven by 1V rail

when all 4 transmitters

are used

VDDA_10RF1, VDDA_10RF2

2300

Current consumption

mA

VIOIN_18, VDDA_18CLK,

VDDA_18PM, VIOIN_18CSI,

VIOIN_18LVDS, VDDA_18BB,

VDDA_18VCO

Total current drawn by all

nodes driven by 1.8V rail

550

Total current drawn by all

nodes driven by 3.3V rail

VIOIN

50⁽²⁾

(1) The specified current values are at Max supply voltage level (Recommended operating conditions).

(2) The exact value will depend on the system use case and design.

表7-4. Average Power Consumption at Power Terminals

PARAMETER

CONDITION⁽²⁾

DESCRIPTION

MIN

TYP⁽¹⁾

MAX UNIT

25% duty

cycle

Use Case:

1.37

1.98

1.44

76-77GHz chirps (for 50% duty cycle)

and 80-81GHz chirps (for 25% duty

cycle);

Regular mode, 37.5 Msps sampling

rate, 25.6 ms frame periodicity, 256

chirps/frame, 2-µs idle time, 50-µs

ramp end time, 7us ADC start time

and excess ramp time

3TX, 4RX

50% duty

cycle

25% duty

cycle

Average power consumption

in single chip mode.

W

Activity of cores :

•

70% MSS R5F

4TX, 4RX

50% duty

cycle

70% C66x DSP and HWA

50% Arm M4F

2.11

All the above cores under-clocked/

clock-gated during idle times);

Ethernet is enabled for data transfer

(1) The Power consumption numbers are for a typical usecase i.e. for a Nominal device at 25C ambient temperature and nominal voltage

conditions.

(2) Frame duty cycle represents the ratio of Frame Active and Total Framing time (including Interchirp and Interframe time).

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7.8 RF Specifications

over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)

PARAMETER

MIN

TYP

12

-10

44

20

2

MAX

UNIT

dB

Noise figure

1-dB compression point (Out Of Band)⁽¹⁾

dBm

dB

Maximum gain

Gain range

dB

Gain step size

dB

IF bandwidth⁽²⁾

15

MHz

Msps

Bits

dB

Receiver

ADC sampling rate

37.5

ADC resolution

12

-10

±0.5

±3

Return loss (S11)

Gain mismatch variation (over temperature)

Phase mismatch variation (over temperature)

Idle Channel Spurs

dB

°

-90

13.5

±5

dBFS

dBm

°

Output power

Phase shifter accuracy

Temperature sensor accuracy

Amplitude noise

Transmitter

±5

℃

-145

dBc/Hz

GHz

Frequency range

76

81

250⁽³⁾

Ramp rate

MHz/μs

Clock subsystem

Phase noise at 1- 76 to 77 GHz (VCO1)

MHz offset

-96

-95

dBc/Hz

76 to 81 GHz (VCO2)⁽⁴⁾

(1) 1-dB Compression Point (Out Of Band) is measured by feeding a continuous wave tone at 5% of the programmed HPF cut-off

frequency (i.e. blocker tone). The compression point is determined by the blocker power that results in a 1dB compression of the

blocker tone at the RX ADC.

(2) The analog IF stages include a second order high pass filter that can be configured to the following -6dB corner frequencies:

Available HPF Corner Frequencies (kHz)

HPF

300, 350, 700, 1400,

The filtering performed by the digital baseband chain is targeted to provide:

•

Less than ±0.5 dB pass-band ripple/droop, and

Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

(3) The max ramp rate depends on the PLL bandwidth configuration set using the"AWR_APLL_SYNTH_BW_CONTROL_SB" API. For

more details, refer to the mmWave Radar Interface Control document.

(4) VCO2 supports a maximum continuous range of 4.5GHz. The supported range can span 76-80.5GHz or 76.5-81GHz through

VCO2_RANGE_CONFIG in AWR_ CAL_MON_FREQUENCY_* API.

图7-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed

English Data Sheet: SWRS273

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14.1

13.8

13.5

13.2

12.9

12.6

12.3

12.0

11.7

-22

NF (dB)

In-band P1dB (dBm)

-24

-26

-28

-30

-32

-34

-36

-38

30

32

34

36

38

40

42

44

RX Gain (dB)

图7-1. Noise Figure, In-band P1dB vs Receiver Gain

7.9 Thermal Resistance Characteristics

THERMAL METRICS^{(1) (4)}

°C/W^{(2) (3)}

3.3

Junction-to-case

Junction-to-board

Junction-to-free air

Junction-to-case

Junction-to-board

RΘ_JC

RΘ_JB

RΘ_JA

Psi_JC

Psi_JB

2.9

14.9

0.1

2.8

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

A junction temperature of 140°C is assumed.

(4) Air flow = 1 m/s

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7.10 Power Supply Sequencing and Reset Timing

The AWR294x device expects all external 1.2V, 1.8V and 3.3V voltage rails as well as all SOP[4:0] lines to be

stable before NRESET is deasserted for a successful device bootup. IO state is not guaranteed until the VIOIN

and VIOIN_18 supplies are available. 图7-2 describes the device wake-up sequence.

备注

Hardware platform must support supplying 1.7V on the VPP pin only during OTP eFuse programming.

SOP

Setup

Time

SOP

Hold time to

nRESET

DC power

Stable before

nRESET

MSS

BOOT

START

nRESET

ASSERT

tPGDEL

DC

Power

notOK

DC

Power

OK

QSPI

READ

release

VDD,

VDD_SRAM

VNWA

VIOIN_18

VDDA_18CLK

VIOIN_18CSI

VIOIN_18LVDS

VDDA_18BB

VDDA_10RF1

VDDA_10RF2

VIOIN

SOP IO

Reuse

SOP[4.3.2.1.0]

SOP IO‘s can be used as functional IO‘s

nRESET

WARMRESET

OUTPUT

VBGAP

OUTPUT

CLKP, CLKM

Using Crystal

QSPI_CS

OUTPUT

8 ms (XTAL Mode)

图7-2. Device Wake-up Sequence

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7.11 Input Clocks and Oscillators

7.11.1 Clock Specifications

An external crystal is connected to the device pins. 图7-3 shows the crystal implementation.

C_f1

CLKP

C_p

40 MHz

CLKM

C_f2

图7-3. Crystal Implementation

备注

The load capacitors, C_f1and C_f2in 图 7-3, can be chosen such that 方程式 1 is satisfied. C_Lin the

equation is the load specified by the crystal manufacturer. All discrete components used to implement

the oscillator circuit can be placed as close as possible to the associated oscillator CLKP and CLKM

pins. Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.

备注

The board routing parasitics between CLKP/CLKM pins also need to be included in the estimates of

C_P

C _f2

C_L= C _f1

´

+C_P

C

_f1+C _f2

(1)

表7-5 lists the electrical characteristics of the clock crystal.

表7-5. Crystal Electrical Characteristics (Oscillator Mode)

NAME

DESCRIPTION

Parallel resonance crystal frequency

Crystal load capacitance

MIN

TYP

40

8

MAX

UNIT

MHz

pF

f_p

C_L

ESR

5

12

50

Crystal ESR

Ω

℃

Temperature range

Expected temperature range of operation

Crystal frequency tolerance^{(1) (2)}

-40

140

Frequency

tolerance

ppm

-100

100⁽³⁾

200

Drive level

50

μW

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

(3) For Ethernet operation, tighter specifications of less than 100 PPM frequency error is required. If the Ethernet interface is not used , a

PPM error up to 200 PPM can be tolerated.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM

is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. 表 7-6 lists

the electrical characteristics of the external clock signal.

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UNIT

表7-6. External Clock Mode Specifications

SPECIFICATION

PARAMETER

MIN

TYP

MAX

Frequency

40

MHz

mV (pp)

ns

AC-Amplitude

700

1200

10

DC-trise/fall

Phase Noise at 1 kHz

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Duty Cycle

-132

–143

–152

–153

65

dBc/Hz

%

Input Clock: External AC-

coupled sine wave or DC-

coupled square wave Phase

Noise referred to 40 MHz

35

Freq Tolerance

-100

100

ppm

7.12 Peripheral Information

Initial peripheral descriptions and features are provided in the following sections. Additional peripheral details

and interface timing information shall be provided in a later product preview or datasheet release.

7.12.1 QSPI Flash Memory Peripheral

The device includes a Quad-Serial Peripheral Interface for external flash memory access. Flash memory can be

utilized for many purposes including: Secondary boot-loader memory, application program memory, security

keys storage, and long-term data logs for security and error conditions.

Following features are supported by the QSPI Interface on the device:

• Loopback skew cancellation for clock signal to supported faster flash interface clock rates

• Two chip-select signals to connect two external flash devices

• Memory mapped 'direct' mode and software triggered 'indirect' mode of operation for performing flash data

transfers

7.12.1.1 QSPI Timing Conditions

PARAMETER

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOADOutput load capacitance

5

15

pF

7.12.1.2 QSPI Timing Requirements^{(1) (2)}

SPECIFICATION

NUMBER

PARAMETER

MIN

TYP

MAX

UNIT

Q12

t_su(D-SCLK)

Setup time, D[3:0] valid before falling SCLK edge

(Q12)

ns

5

1

Q13

Q14

t_h(SCLK-D)

t_su(D-SCLK)

Hold time, D[3:0] valid after falling SCLK edge (Q13)

ns

Setup time, final D[3:0] bit valid before final falling

SCLK edge

5-P⁽³⁾

Q15

t_h(SCLK-D)

Hold time, final D[3:0] bit valid after final falling SCLK

edge

ns

1+P⁽³⁾

(1) Clock Mode 0 (clock polarity = 0 ; clock phase = 0) is the mode of operation.

(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although

nonstandard, The falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Mode 0.

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(3) P = SCLK period in ns.

7.12.1.3 QSPI Switching Characteristics^{(1) (2)}

SPECIFICATION

NUMBER

PARAMETER

MIN

TYP

MAX UNIT

Q1

t_c(SCLK)

Cycle time, sclk

12.5

ns

t_w(SCLKL)

Pulse duration, sclk low

0.5*P –

0.625

Q2

t_w(SCLKH)

Pulse duration, sclk high

ns

0.5*P –

0.625

Q3

Q4

t_d(CS-SCLK)

Delay time, sclk falling edge to cs active edge

ns

–M*P +

–M*P –1

2.5

t_d(SCLK-CS)

t_d(SCLK-D1)

t_ena(CS-D1LZ)

t_dis(CS-D1Z)

Delay time, sclk falling edge to cs inactive edge

Delay time, sclk falling edge to d[0] transition

Enable time, cs active edge to d[0] driven (lo-z)

ns

Q5

Q6

Q7

N*P + 2.5

2

N*P –1

–4.5

–P –4

–P +1

Disable time, cs active edge to d[0] tri-stated (hi-

z)

Q8

Q9

–P –4

–P +1

2 –P

t_d(SCLK-D1)

Delay time, sclk first falling edge to first d[1]

transition (for PHA = 0 only)

ns

–4.5–P

(1) P = SCLK period in ns.

(2) M = QSPI_SPI_DC_REG.DDx + 1, N = 2

图7-4. QSPI Read (Clock Mode 0)

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PHA=0

cs

Q5

Q4

Q1

Q2

Q3

POL=0

sclk

Q8

Q6

Q7

Q9

Q6

Command

Bit n-1

Command

Bit n-2

Write Data

Bit 1

Write Data

Bit 0

d[0]

d[3:1]

SPRS85v_TIMING_OSPI1_04

图7-5. QSPI Write (Clock Mode 0)

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7.12.2 Multibuffered / Standard Serial Peripheral Interface (MibSPI)

7.12.2.1 MibSPI Peripheral Description

The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The

device includes two, Multi-Buffered Serial Peripheral Interface (MIBSPI) in the Main Sub-System (MSS). These

are intended for external MCU, PMIC, EEPROM and Watchdog communication.

Standard and MibSPI modules have the following features:

• 16-bit shift register

• Receive buffer register

• 8-bit baud clock generator

• SPICLK can be internally-generated (Controller mode) or received from an external clock source

(Peripheral mode)

• Maximum clock rate supported over each MIBSPI module shall be 40MHz.

• Each word transferred can have a unique format.

• SPI I/Os not used in the communication can be used as digital input/output signals

7.12.2.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit

transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be

partitioned into multiple transfer group with variable number of buffers each.

节7.12.2.2.2 and 节7.12.2.2.3 assume the operating conditions stated in 节7.12.2.2.1.

7.12.2.2.1 SPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOADOutput load capacitance

2

20

pF

7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^{(1) (2) (3)}

NO.

PARAMETER

MIN

20

TYP

MAX UNIT

1

t_c(SPC)M

Cycle time, SPICLK⁽⁴⁾

256_tc(VCLK)

ns

t_w(SPCH)M

Pulse duration, SPICLK high (clock

polarity = 0)

0.5t_c(SPC)M+ 2

0.5t_c(SPC)M–2

2⁽⁴⁾

3⁽⁴⁾

4⁽⁴⁾

5⁽⁴⁾

ns

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK low (clock

polarity = 1)

0.5t_c(SPC)M–2

0.5t_c(SPC)M–7

0.5t_c(SPC)M–8

Pulse duration, SPICLK low (clock

polarity = 0)

ns

Pulse duration, SPICLK high (clock

polarity = 1)

t_d(SPCH-

Delay time, SPISIMO valid before

SPICLK low, (clock polarity = 0)

SIMO)M

t_d(SPCL-

Delay time, SPISIMO valid before

SPICLK high, (clock polarity = 1)

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after

SPICLK low, (clock polarity = 0)

SIMO)M

t_v(SPCH-

Valid time, SPISIMO data valid after

SPICLK high, (clock polarity = 1)

SIMO)M

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MAX UNIT

NO.

PARAMETER

MIN

TYP

CSHOLD =

0

(C2TDELAY+2) * t_c(VCLK)+ 7

(C2TDELAY+2)*t_c(VCLK)

–

Setup time CS active

until SPICLK high

(clock polarity = 0)

7.5

CSHOLD =

1

(C2TDELAY+3) * t_c(VCLK)+ 7

(C2TDELAY+2) * t_c(VCLK)+ 7

(C2TDELAY+3) * t_c(VCLK)+ 7

(C2TDELAY +3) * t_c(VCLK)

–

7.5

6⁽⁵⁾

t_C2TDELAY

ns

CSHOLD =

0

(C2TDELAY+2)*t_c(VCLK)

–

Setup time CS active

until SPICLK low

(clock polarity = 1)

7.5

CSHOLD =

1

(C2TDELAY +3) * t_c(VCLK)

–

7.5

Hold time, SPICLK low until CS

inactive (clock polarity = 0)

0.5*t_c(SPC)M+ (T2CDELAY +

1) * t_c(VCLK)+ 7.5

1) *t_c(VCLK)–7

7⁽⁵⁾

t_T2CDELAY

ns

Hold time, SPICLK high until CS

inactive (clock polarity = 1)

0.5*t_c(SPC)M+ (T2CDELAY +

1) * t_c(VCLK)+ 7.5

1) *t_c(VCLK)–7

t_su(SOMI-

Setup time, SPISOMI before

SPICLK low

(clock polarity = 0)

5

2

SPCL)M

8⁽⁴⁾

t_su(SOMI-

Setup time, SPISOMI before

SPICLK high

(clock polarity = 1)

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after

SPICLK low

(clock polarity = 0)

SOMI)M

9⁽⁴⁾

ns

t_h(SPCH-

Hold time, SPISOMI data valid after

SPICLK high

SOMI)M

(clock polarity = 1)

(1) The Controller bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).

(2) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, refer to the device Technical Reference Manual.

(3) When the SPI is in controller mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥(PS +1)t_{c(MSS_VCLK)}≥25ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥25ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

图7-6. SPI Controller Mode External Timing (CLOCK PHASE = 0)

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图7-7. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 0)

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MAX UNIT

7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^{(1) (2) (3)}

NO.

PARAMETER

MIN

20

TYP

1

t_c(SPC)M

Cycle time, SPICLK⁽⁴⁾

256t_c(VCLK)

ns

t_w(SPCH)M

Pulse duration, SPICLK high (clock

polarity = 0)

0.5t_c(SPC)M+ 2

0.5t_c(SPC)M–2

2⁽⁴⁾

3⁽⁴⁾

4⁽⁴⁾

5⁽⁴⁾

ns

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK low (clock

polarity = 1)

0.5t_c(SPC)M–2

0.5t_c(SPC)M–7

0.5t_c(SPC)M–8

Pulse duration, SPICLK low (clock

polarity = 0)

ns

Pulse duration, SPICLK high (clock

polarity = 1)

t_d(SPCH-

Delay time, SPISIMO valid before

SPICLK low, (clock polarity = 0)

SIMO)M

t_d(SPCL-

Delay time, SPISIMO valid before

SPICLK high, (clock polarity = 1)

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after

SPICLK low, (clock polarity = 0)

SIMO)M

t_v(SPCH-

Valid time, SPISIMO data valid after

SPICLK high, (clock polarity = 1)

SIMO)M

t_C2TDELAY

Setup time CS active

until SPICLK high

(clock polarity = 0)

CSHOLD =

0

0.5*t_c(SPC)M

(C2TDELAY + 2)*t_c(VCLK)

+

0.5*t_c(SPC)M

(C2TDELAY+2) * t_c(VCLK)

+

7.5

–7

CSHOLD =

1

0.5*t_c(SPC)M

(C2TDELAY + 2)*t_c(VCLK)

+

0.5*t_c(SPC)M

(C2TDELAY+2) * t_c(VCLK)

+

7.5

–7

6⁽⁵⁾

ns

CSHOLD =

0

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M

(C2TDELAY+2) * t_c(VCLK)

+

(C2TDELAY+2)*t_c(VCLK)

Setup time CS active

until SPICLK low

(clock polarity = 1)

7.5

–7

CSHOLD =

1

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M

(C2TDELAY+3) * t_c(VCLK)

+

(C2TDELAY+3)*t_c(VCLK)

7.5

–7

Hold time, SPICLK low until CS inactive (T2CDELAY + 1) *t_c(VCLK)

(T2CDELAY + 1) *t_c(VCLK)

+ 7

(clock polarity = 0)

–7.5

7⁽⁵⁾

t_T2CDELAY

ns

Hold time, SPICLK high until CS

inactive (clock polarity = 1)

(T2CDELAY + 1) *t_c(VCLK)

+ 7

–7.5

t_su(SOMI-

Setup time, SPISOMI before SPICLK

low

(clock polarity = 0)

5

2

SPCL)M

8⁽⁴⁾

t_su(SOMI-

Setup time, SPISOMI before SPICLK

high

(clock polarity = 1)

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after

SPICLK low

(clock polarity = 0)

SOMI)M

9⁽⁴⁾

ns

t_h(SPCH-

Hold time, SPISOMI data valid after

SPICLK high

SOMI)M

(clock polarity = 1)

(1) The Controller bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).

(2) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, refer to the device Technical Reference Manual.

(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥(PS +1)t_{c(MSS_VCLK)}≥25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥25 ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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图7-8. SPI Controller Mode External Timing (CLOCK PHASE = 1)

图7-9. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 1)

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7.12.2.3 SPI Peripheral Mode I/O Timings

7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input,

and SPISOMI = output)^{(1) (2) (3)}

SPECIFICATIO

N NUMBER

PARAMETER⁽⁵⁾

MIN

TYP

MAX

UNIT

1

t_c(SPC)S

Cycle time, SPICLK ⁽⁴⁾

20

8

ns

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

t_{d(SPCH-SOMI)S}

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

2

8

3

4

ns

8

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0)

10

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

t_{d(SPCH-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

2

5

4

ns

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

14

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

2

5

6

7

ns

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

Setup time, SPISIMO before SPICLK low (clock

polarity = 0; clock phase = 0) OR (clock polarity =

1; clock phase = 1)

t_{su(SIMO-SPCL)S}

2.1

1

Setup time, SPISIMO before SPICLK high (clock

t_{su(SIMO-SPCH)S}polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)

Hold time, SPISIMO data valid after SPICLK low

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

t_{h(SPCL-SIMO)S}

Hold time, SPISIMO data valid after SPICLK high

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

t_{h(SPCL-SIMO)S}

1

(1) The Controller bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).

(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.

(3) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, refer to the device Technical Reference Manual.

(4) When the SPI is in Peripheral mode, the following must be true: For PS values from 1 to 255: t_c(SPC)S≥(PS +1)t_{c(MSS_VCLK)}≥25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: t_c(SPC)S= 2t_{c(MSS_VCLK)}≥25 ns.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

English Data Sheet: SWRS273

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

图7-10. SPI Peripheral Mode External Timing (CLOCK PHASE = 0)

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

图7-11. SPI Peripheral Mode External Timing (CLOCK PHASE = 1)

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7.12.3 Ethernet Switch (RGMII/RMII/MII) Peripheral

The device integrates a two port Ethernet with one external RGMII/RMII/MII port and another port servicing the

Main Sub-System (MSS). This interface is intended to operate primarily as a 100Mbps ECU interface. It can also

be used as an instrumentation interface.

• Full Duplex 10/100Mbps wire rate interface to Ethernet PHY over RGMII, RMII, or MII parallel interface

• MDIO Clause 22 and 45 PHY management interface

• IEEE 1588 Synchronous Ethernet support

• AWR synchronous trigger output allowing Ethernet to trigger radar frames

7.12.3.1 RGMII/MII Timing Conditions

SPECIFIC

ATION

PARAMETER

MIN

TYP

MAX

UNIT

NUMBER

Input Conditions

1

2

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOADOutput load capacitance

3

2

20

pF

7.12.3.2 RGMII Transmit Clock Switching Characteristics

NO.

PARAMETER

DESCRIPTION

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

MAX

440

44

UNIT

1

t_c(TXC)

Cycle time, rgmiin_txc

360

36

ns

2

3

4

t_w(TXCH)

t_w(TXCL)

t_t(TXC)

Pulse duration, rgmiin_txc high

Pulse duration, rgmiin_txc low

Transition time, rgmiin_txc

160

16

240

24

160

16

240

24

0.75

7.12.3.3 RGMII Transmit Data and Control Switching Characteristics

NO.⁽¹⁾PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

5

t_osu(TXD-TXC)

Output Setup time, transmit selected signals valid to

MSS_RGMII_TCLK high/low

RGMII, Internal Delay

Enabled, 10/100 Mbps

1.2

ns

6

t_oh(TXC-TXD)

Output Hold time, transmit selected signals valid

after MSS_RGMII_TCLK high/low

RGMII, Internal Delay

Enabled, 10/100 Mbps

1.2

ns

(1) For RGMII, transmit selected signals include: MSS_RGMII_TXD[3:0] and MSS_RGMII_TCTL.

English Data Sheet: SWRS273

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1

4

2

4

3

rgmiin_txc^(A)

[internal delay enabled]

rgmiin_txd[3:0]^(B)

rgmiin_txctl^(B)

5

1st Half-byte

TXEN

2nd Half-byte

TXERR

6

A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.

B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the rising edge of

rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on rising edge of rgmiin_txc and

TXERR of falling edge of rgmiin_txc.

图7-12. RGMII Transmit Interface Switching Characteristics

7.12.3.4 RGMII Recieve Clock Timing Requirements

NO.

PARAMETER

DESCRIPTION

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

360

36

MAX

440

44

UNIT

ns

1

t_c(RXC)

Cycle time, rgmiin_rxc

ns

2

3

4

t_w(RXCH)

t_w(RXCL)

t_t(RXC)

Pulse duration, rgmiin_rxc high

Pulse duration, rgmiin_rxc low

Transition time, rgmiin_rxc

160

16

240

24

ns

160

16

240

24

ns

0.75

ns

7.12.3.5 RGMII Receive Data and Control Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

5

t_su(RXD-RXCH)

Setup time, receive selected signals valid before MSS_RGMII_RCLK

high/low

1

ns

6

t_h(RXCH-RXD)

Hold time, receive selected signals valid after MSS_RGMII_RCLK

high/low

1

ns

1

4

2

4

3

rgmiin_rxc^(A)

5

1st Half-byte

6

2nd Half-byte

rgmiin_rxd[3:0]^(B)

rgmiin_rxctl^(B)

RGRXD[3:0]

RXDV

RGRXD[7:4]

RXERR

A. rgmiin_rxc must be externally delayed relative to the data and control pins.

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B. Data and control information is received using both edges of the clocks. MSS_RGMII_RXD[3:0] carries data bits 3-0 on the rising edge

of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on rising edge of rgmiin_rxc and

RXERR on falling edge of rgmiin_rxc.

图7-13. MAC Receive Interface Timing, RGMIIn operation

7.12.3.6 RMII Transmit Clock Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

20

7

MAX

UNIT

ns

RMII7 t_{c(REF_CLK)}

RMII8 t_{w(REF_CLKH)}

RMII9 t_{w(REF_CLKL)}

RMII10 t_{t(REF_CLK)}

Cycle time, REF_CLK

Pulse duration, REF_CLK high

Pulse duration, REF_CLK low

Transition time, REF_CLK

13

3

ns

7

ns

7.12.3.7 RMII Transmit Data and Control Switching Characteristics

NO.

RMII11 t_{d(REF_CLK-TXD)}

t_{dd(REF_CLK-TXEN)}

PARAMETER

DESCRIPTION

MIN

MAX

14.2

UNIT

Delay time, REF_CLK high to selected transmit signals valid

2

ns

RMII7

RMII8

RMII9

RMII10

RMII11

REF_CLK (PRCM)

rmiin_txd1−rmiin_txd0,

rmiin_txen (Outputs)

SPRS8xx_GMAC_RMIITX_06

图7-14. MAC Transmit Interface Timing, RMIIn Operation

7.12.3.8 RMII Receive Clock Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

ns

RMII1 t_{c(REF_CLK)}

RMII2 t_{w(REF_CLKH)}

RMII3 t_{w(REF_CLKL)}

RMII4 t_{tt(REF_CLK)}

Cycle time, REF_CLK

20

7

Pulse duration, REF_CLK high

Pulse duration, REF_CLK low

Transition time, REF_CLK

13

3

ns

7

ns

7.12.3.9 RMII Receive Data and Control Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

RMII5

t_{su(RXD-REF_CLK)}

t_{su(CRS_DV-REF_CLK)}

t_{su(RX_ER-REF_CLK)}

t_{h(REF_CLK-RXD)}

Setup time, receive selected signals valid before REF_CLK

4

ns

RMII6

Hold time, receive selected signals valid after REF_CLK

2

ns

t_{h(REF_CLK-CRS_DV)}

t_{h(REF_CLK-RX_ER)}

English Data Sheet: SWRS273

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RMII1

RMII3

RMII2

RMII4

RMII6

RMII5

REF_CLK (PRCM)

rmiin_rxd1−rmiin_rxd0,

rmiin_crs, rmin_rxer (inputs)

SPRS8xx_GMAC_RMIIRX_05

图7-15. MAC Receive Interface Timing, RMIIn operation

7.12.3.10 MII Transmit Switching Characteristics

NO.

PARAMETER

t_{d(TX_CLK-TXD)}

t_{d(TX_CLK-TX_EN)}

t_{d(TX_CLK-TX_ER)}

DESCRIPTION

MIN

MAX

UNIT

1

Delay time, miin_txclk to transmit selected signals valid

0

25

ns

1

miin_txclk (input)

miin_txd3 − miin_txd0,

miin_txen, miin_txer (outputs)

图7-16. MAC Transmit Interface Timing, MIIn operation

7.12.3.11 MII Receive Clock Timing Requirements

NO.

PARAMETER

DESCRIPTION

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

400

40

MAX

UNIT

ns

1

t_{c(RX_CLK)}

Cycle time, miin_rxclk

ns

2

3

4

t_{w(RX_CLKH)}

t_{w(RX_CLKL)}

t_{t(RX_CLK)}

Pulse duration, miin_rxclk high

Pulse duration, miin_rxclk low

Transition time, miin_rxclk

140

14

260

26

260

26

3

ns

140

14

ns

3

ns

1

4

2

3

miin_rxclk

4

图7-17. Clock Timing (MAC Receive) - MIIn operation

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7.12.3.12 MII Receive Timing Requirements

NO.

PARAMETER

t_{su(RXD-RX_CLK)}

DESCRIPTION

MIN

MAX

UNIT

1

Setup time, receive selected signals valid before miin_rxclk

8

ns

t_{su(RX_DV-RX_CLK)}

t_{su(RX_ER-RX_CLK)}

t_{h(RX_CLK-RXD)}

2

Hold time, receive selected signals valid after miin_rxclk

8

ns

t_{h(RX_CLK-RX_DV)}

t_{h(RX_CLK-RX_ER)}

1

2

miin_rxclk (Input)

miin_rxd3−miin_rxd0,

miin_rxdv, miin_rxer (Inputs)

图7-18. MAC Receive Interface Timing, MIIn operation

7.12.3.13 MII Transmit Clock Timing Requirements

NO.

PARAMETER

DESCRIPTION

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

MAX

UNIT

ns

1

t_{c(TX_CLK)}

Cycle time, miin_txclk

400

40

ns

2

3

4

t_{w(TX_CLKH)}

t_{w(TX_CLKL)}

t_{t(TX_CLK)}

Pulse duration, miin_txclk high

Pulse duration, miin_txclk low

Transition time, miin_txclk

140

14

260

26

260

26

3

ns

140

14

ns

3

ns

1

4

2

3

miin_txclk

4

图7-19. Clock Timing (MAC Transmit) - MIIn operation

7.12.3.14 MDIO Interface Timings

CAUTION

The IO Timings provided in this section are only valid for some MAC usage modes when the

corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables

found in this section.

表7-7, 表7-8 and 图7-20 present switching characteristics and timing requirements for the MDIO interface.

English Data Sheet: SWRS273

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表7-7. Timing Requirements for MDIO Input

No

PARAMETER

t_c(MDC)

t_w(MDCH)

DESCRIPTION

MIN

400

160

90

MAX

UNIT

ns

MDIO1

MDIO2

MDIO3

MDIO4

MDIO5

Cycle time, MDC

Pulse Duration, MDC High

ns

t_w(MDCL)

Pulse Duration, MDC Low

ns

t_su(MDIO-MDC)

t_{h(MDIO_MDC)}

Setup time, MDIO valid before MDC High

Hold time, MDIO valid from MDC High

ns

0

ns

表7-8. Switching Characteristics Over Recommended Operating Conditions for MDIO Output

NO

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

MDIO6

MDIO7

t_t(MDC)

Transition time, MDC

5

ns

t_d(MDC-MDIO)

Delay time, MDC low to MDIO valid

10

(P * 0.5) - 10

ns

1

MDIO2

MDIO3

MDCLK

MDIO6

MDIO4

MDIO5

MDIO

(input)

MDIO7

MDIO

(output)

图7-20. MAC MDIO diagrams

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7.12.4 LVDS/Aurora Instrumentation and Measurement Peripheral

The device supports a set of LVDS interfaces in two different modes.

• Legacy LVDS mode

• STM-TWP Aurora interface

The LVDS IO are shared between the above two measurement interface options.

Following features are supported :

• 2-data lane LVDS interface (two additional lanes for Data Clock and Frame Clock)

• 4-Lane STM-TWP-Aurora-LVDS interface mode. It has the following features:

– Configurable 4/2/1 lane of operation.

– Transmit data compliant to Aurora 8B/10B Serial Simplex Operation

– Transmit data compliant to Aurora 64B/66B Serial Simplex Operation

Please see the device TRM for information regarding programming options for both LVDS interfaces.

7.12.4.1 LVDS Interface Configuration

The supported LVDS lane configuration is 2-data lane (LVDS_TXP/M), one Bit Clock lane

(LVDS__TXxx_CLKP/M) and one Frame clock lane (LVDS_TXxx_FRCLKP/M). The LVDS interface supports

programmable data rates with the maximum being 900 Mbps (450 MHz DDR Clock).

Note that the bit clock is in DDR format and hence the number of toggles in the clock is equivalent to data.

LVDS_TXP/M

LVDS_FRCLKP/M

Data bitwidth

LVDS_CLKP/M

图7-21. LVDS Interface Lane Configuration And Relative Timings

7.12.4.2 LVDS Interface Timings

Trise

LVDS_CLK

Clock Jitter = 6sigma

LVDS_TXP/M

LVDS_FRCLKP/M

1100 ps

图7-22. Timing Parameters

表7-9. LVDS Electrical Characteristics

PARAMETER

Duty Cycle Requirements

TEST CONDITIONS

MIN

TYP

MAX

UNIT

max 1 pF lumped capacitive load on

LVDS lanes

48%

52%

English Data Sheet: SWRS273

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表7-9. LVDS Electrical Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

450

UNIT

Output Differential Voltage

peak-to-peak single-ended with 100 Ω

resistive load between differential pairs

250

mV

Output Offset Voltage

Trise and Tfall

1125

1275

mV

ps

20%-80%, 900 Mbps

900 Mbps

330

80

Jitter (pk-pk)

ps

7.12.5 UART Peripheral

The device includes four UART interfaces. One UART is intended as a secondary boot loader source, one is

intended for use as a register debug interface (with XDS110 emulator) and the remaining two are meant for

general UART communication support.

• Maximum baud-rate supported shall be at least 1536K baud in all the different clock frequency modes

• UART interfaces multiplexed with other I/O to allow for widest peripheral use flexibility

7.12.5.1 SCI Timing Requirements

MIN

TYP

MAX

UNIT

f(baud)

Supported baud rate at 20 pF

921.6

kHz

7.12.6 Inter-Integrated Circuit Interface (I2C)

The device supports one Controller/Target Inter-integrated Circuit interface and is intended to be connected to

an external PMIC or EEPROM device (alternative control SPI).

The I2C has the following features:

• Standard/fast mode I2C interface compliant with Philips I2C bus specification, v2.1 (The I2C Specification,

Philips document number 9398 393 40011)

– Bit/Byte format transfer

– 7-bit and 10-bit device addressing modes

– General call

– START byte

– Multi-controller transmitter/ target receiver mode

– Multi-controller receiver/ target transmitter mode

– Combined controller transmit/receive and receive/transmit mode

– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)

• Free data format

• Two DMA events (transmit and receive)

• DMA event enable/disable capability

• Module enable/disable capability

• The SDA and SCL are optionally configurable as general purpose I/O

• Slew rate control of the outputs

• Open drain control of the outputs

• Programmable pullup/pulldown capability on the inputs

• Supports Ignore NACK mode

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备注

This I2C module does not support:

• High-speed (HS) mode

• C-bus compatibility mode

• The combined format in 10-bit address mode (the I2C sends the target address second byte every

time it sends the target address first byte)

7.12.6.1 I2C Timing Requirements⁽¹⁾

STANDARD MODE

FAST MODE

UNIT

MIN

10

MAX

MIN

2.5

MAX

t_c(SCL)

Cycle time, SCL

μs

t_{su(SCLH-SDAL)}

Setup time, SCL high before SDA low

(for a repeated START condition)

4.7

0.6

t_h(SCLL-SDAL)

Hold time, SCL low after SDA low

4

0.6

μs

(for a START and a repeated START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

μs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0

(1)

t_h(SCLL-SDA)

3.45

0.9

t_w(SDAH)

Pulse duration, SDA high between STOP and START

conditions

4.7

1.3

t_{su(SCLH-SDAH)}

Setup time, SCL high before SDA high

(for STOP condition)

4

0.6

0

μs

t_w(SP)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

ns

(2) (3)

C_b

400

pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the

SCL signal.

(3) C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

图7-23. I2C Timing Diagram

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备注

• A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

• The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period

(tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode

I2C-bus system, but the requirement t_su(SDA-SCLH)≥250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA

line tr max + t_su(SDA-SCLH)

.

7.12.7 Controller Area Network - Flexible Data-rate (CAN-FD)

The device integrates two CAN-FD interfaces, MSS_MCANA and MSS_MCANB. This enables support of a

typical use case where one CAN-FD interface is used as ECU network interface while the other interface is used

as a local network interface, providing communication with the neighboring sensors.

• Support CAN-FD according to ISO 11898-7 protocol with data rate up to 8Mbps

• Multiplexed GPIO can be used for CAN-FD external driver control

• AWRx synchronous trigger output allows CAN-FD to trigger radar frames

7.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins

PARAMETER⁽¹⁾

MIN

TYP

MAX

UNIT

t_{d(MSS_CANA_TX)}

t_{d(MSS_CANB_TX)}

t_{d(MSS_MCANA_RX)}

t_{d(MSS_MCANB_RX)}

Delay time, transmit shift register to

MSS_CANA_TX pin

15

ns

Delay time, transmit shift register to

MSS_CANB_TX pin

15

10

ns

Delay time, MSS_MCANA_RX pin to receive

shift register

Delay time, MSS_MCANB_RX pin to receive

shift register

(1) These values do not include rise/fall times of the output buffer.

7.12.8 CSI2 Receiver Peripheral

The device integrates one 3-lane MIPI CSI2, D-PHY receiver peripheral in the Radio processing subsystem. The

CSI2 interface is primarily functional of operating as a hardware-in-the-loop (HIL) interface, allowing for the

playback of recorded radar data for development purposes.

• Interface is compliant with the MIPI CSI-2 D-PHY standard revision 1.2

• 1 x 3-lane (2 data lanes, 1 clock lane) CSI2 receiver interface, working simultaneously at 600 Mbps/lane

• 2-lane, or 1-lane CSI2 configurations

• Support for 4 simultaneous virtual channels and data types

• Support for 8/10/12/14/16-bit RAW data mode with capability of sign extension or zero padding to align with

16-bit memory addressing for RAW 10/12/14 modes

• Support for user defined data types

Please refer to the device Technical Reference Manual for a complete description of all the programmable

options.

7.12.8.1 CSI2 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

Low Power Receiver (LP-RX)

(1)

V_IL

Logic 0 input threshold

550

mV

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

880

25

TYP

MAX

UNIT

mV

(2)

V_IH

Logic 1 input threshold

Input Hysteresis

V_HYST

mV

High Speed Receiver (HS-RX)

V_IDTH

Differential input high threshold

Differential input low threshold

Maximum differential input voltage

Single-ended input low voltage

Single-ended input high voltage

Common-mode voltage

70

mV

V_IDTL

-70

V_IDMAX

270

mV

V_ILHS

-40

70

mV

V_IHHS

460

330

200

50

mV

V_CMRXDC

Δ_VCMRX(HF)

Δ_VCMRX(LF)

mV

Common-mode interference beyond 450 MHz

mVPP

-50

Common mode interference 50MHz –450MHz

HS DATA-CLOCK Timing Specification ^{(3) (5)}

UI_INST

T_SETUP

T_HOLD

T_R,, T_F

Data/Clock Unit Interval

1.11

166

ns

ps

Data to Clock setup time

Clock to Data hold time

Rise/Fall Times

(4)

0.4*UI_INST

(1) The input low-level voltage, VIL, is the voltage at which the receiver is required to detect a low state in the input signal. VIL is larger

than the maximum single-ended line voltage during HS transmission. Therefore, both LP receivers will detect low during HS signaling

(2) The input high-level voltage, VIH, is the voltage at which the receiver is required to detect a high state in the input signal.

(3) TSKEW in the figure is the skew between the clock and data HS signals that can be tolerated at the receiver input. It is only a

descriptive parameter. Rx timing is specified by TSETUP/THOLD only.

(4) Rise/Fall from V_IDTLto V_IDTH

.

(5) Setup/hold specification is assuming identical common mode and rise/fall time for both data and clock lane at receiver input. i.e.

V_CMRXDCand T_R, T_Fmust be same for clock lane and data lane while measuring T_SETUPand T_HOLD

图7-24. Clock and Data Timing in HS Transmission

English Data Sheet: SWRS273

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7.12.9 Enhanced Pulse-Width Modulator (ePWM)

The device includes three Enhanced Pulse-Width Modulation (ePWM) modules. These modules can be used to

generate duty-cycled controlled waveforms for a power regulator, or a power management systems, or more

complex waveforms for motor control applications.

The module supports the following features:

• Dedicated 16-bit time-base counter with period and frequency control for each PWM module

• Each module contains two PWM outputs (EPWMxA and EPWMxB) that shall be usable in the following

configurations:

– Two independent PWM outputs with single-edge operation

– Two independent PWM outputs with dual-edge symmetric operation

– One independent PWM output with dual-edge asymmetric operation

7.12.10 General-Purpose Input/Output

节7.12.10.1 lists the switching characteristics of output timing relative to load capacitance.

7.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (C_L)^{(1) (2)}

PARAMETER

TEST CONDITIONS

C_L= 20 pF

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

2.8

6.4

9.4

2.8

6.4

9.4

3.3

6.7

9.6

3.1

6.6

9.6

3.0

6.9

10.2

2.8

6.6

9.8

3.3

7.2

10.5

3.1

6.6

9.6

t_r

t_f

t_r

t_f

Max rise time

C_L= 50 pF

ns

C_L= 75 pF

Slew control = 0

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

Max fall time

Max rise time

Max fall time

ns

Slew control = 1

(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).

(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

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7.13 Emulation and Debug

7.13.1 Emulation and Debug Description

7.13.2 JTAG Interface

The JTAG interface implements the IEEE1149.1 standard interface for processor debug and boundary scan

testing.

节7.13.2.1 and 节7.13.2.2 assume the operating conditions stated in 图7-25.

7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG

表7-10. JTAG Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

表7-11. JTAG Timing Requirements

NO.

1

MIN

TYP

MAX

UNIT

ns

t_c(TCK)

Cycle time TCK

33.33

13.33

1a

t_w(TCKH)

Pulse duration

TCK high (40% of

tc)

ns

1b

3

t_w(TCKL)

Pulse duration

TCK low (40% of

tc)

13.33

2.5

18

ns

t_su(TDI-TCK)

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

Input setup time

TDI valid to TCK

high

3

Input setup time

TMS valid to TCK

high

4

Input hold time

TDI valid from

TCK high

4

Input hold time

TMS valid from

TCK high

18

7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG

NO.

PARAMETER

MIN

TYP

MAX

UNIT

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

21

ns

English Data Sheet: SWRS273

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1

1a

1b

TCK

TDO

2

3

4

TDI/TMS

SPRS91v_JTAG_01

图7-25. JTAG Timing

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7.13.3 ETM Trace Interface

The ETM Trace interface provides a means of exporting real time processor debug information to a host PC

through a compatible emulator toolset.

节7.13.3.1 and 节7.13.3.2 describe the operating conditions shown in 图7-26 and 图7-27.

7.13.3.1 ETM TRACE Timing Requirements

MIN

TYP

MAX

UNIT

Output Conditions

C_LOAD

Output load capacitance

2

20

pF

7.13.3.2 ETM TRACE Switching Characteristics

NO.

PARAMETER

MIN

TYP

MAX

UNIT

t_cyc(ETM)

t_h(ETM)

t_l(ETM)

Cycle time, TRACECLK

period

16

ns

1

Pulse Duration, TRACECLK

High

7

ns

2

3

Pulse Duration, TRACECLK

Low

4

5

t_r(ETM)

Clock and data rise time

Clock and data fall time

3.3

ns

t_f(ETM)

t_{d(ETMTRACECLKH-ETMDATAV)}

Delay time, ETM trace clock

high to ETM data valid

1

14.5

6

7

t_{d(ETMTRACECLKl-ETMDATAV)}

Delay time, ETM trace clock

low to ETM data valid

ns

14.5

t_l(ETM)

t_h(ETM)

t_r(ETM)

t_f(ETM)

t_cyc(ETM)

图7-26. ETMTRACECLKOUT Timing

图7-27. ETMDATA Timing

English Data Sheet: SWRS273

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8 Detailed Description

8.1 Overview

The AWR294x device includes the entire Millimeter Wave blocks, and analog baseband signal chain, for three or

four transmitters and four receivers, as well as a customer-programmable MCU and DSP. This device is

applicable as a radar-on-a-chip in use-cases with modest requirements for memory, processing capacity, and

application code size. These can be cost-sensitive automotive applications that are evolving from 24 GHz

narrowband implementation and some emerging, ultra-short-range radar applications.

To support additional scalability, the device can also be paired with an external host MCU, to provide additional

control and processing platform so as to address more complex applications. To interface to external host MCU,

the device provides SPI, CAN-FD and I2C for host control.

8.2 Functional Block Diagram

图8-1 represents the functional block diagram for the device.

9

GPADC

Main Subsystem

Serial Flash Interface

QSPI

SPI

(Customer Programmed)

LNA

IF

ADC

Optional External

MCU Interface

Arm Cortex-R5F

PMIC Control

(Lock Step)

at 300 MHz

Digital

Front-end

SPI / I2C

CAN-FD

Primary Communication

Interfaces (Automotive)

(Decimation

Filter Chain)

Prog

Cache

16KB

Data

Cache

16KB

L1 Data

RAM

128KB

L2 RAM

960KB

Debug

UARTs

For Debug

Test/

Debug

JTAG for Debug/

Development

DMA

Hardware Security

Module ^(A)

100-Mbps Alternate Data

Communication Interface

PA

Ethernet

ADC

Buffer

Mailbox

PA

DSP Subsystem

Synth

(20 GHz)

Ramp

Generator

(Customer Programmed)

x4

C66x DSP Core

at 360 MHz

Radio (BIST)

Processor

Aurora

LVDS

High-Speed ADC Output

Interface (for Recording)

High-Speed Interface to

enable playback of the

captured data

(For RF Calibration

and Self-Test – TI

Programmed)

CSI2 RX

L1P

L1D

L2

(384KB)

(32KB) (32KB)

Prog RAM

and ROM

Data

RAM

DMA

CRC

Osc.

Radar Data Memory

AWR2943 - 2.0MB /

AWR2944 - 2.5MB

GPADC

VMON

Temp

Radio Processor

Subsystem

(TI Programmed)

Radar Hardware Accelerator

(FFT, Log mag, and others)

RF/Analog Subsystem

A. Configurable memory can be switched from Radar Data memory to the Main Cortex-R5F program and Data RAMs per application

usecase needs.

B. This feature is only available in select part variants as indicated by the Device Type identifier in the 节3, Device Information table.

图8-1. Functional Block Diagram

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8.3 Subsystems

8.3.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,

IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The four transmit and

the receive channels can all be operated simultaneously for transmit beamforming purpose and receiving data

as required.

8.3.1.1 RF Clock Subsystem

The device clock subsystem generates 76 to 81 GHz from an input reference of 40 MHz crystal. It has a built-in

oscillator circuit followed by an Analog PLL and a RF synthesizer circuit. The output of the RF synthesizer is then

processed by an x4 multiplier to create the required frequency in the 76 to 81 GHz spectrum. The RF

synthesizer output can be modulated by the timing engine block to create the required waveforms for effective

sensor operation or it can input a fixed signal of 1GHz directly from APLL.

The Analog PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the

quality of the generated clock.

图8-2 describes the clock subsystem.

Self Test

RX LO

Timing

Engine

SYNC_OUT

SYNCIN

x4

MULT

TX LO

RF SYNTH

~1 GHz

(Fixed Clock Domain)

APLL

XO/

Slicer

40 MHz

图8-2. RF Clock Subsystem

English Data Sheet: SWRS273

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8.3.1.2 Transmit Subsystem

The device transmit subsystem consists of four parallel transmit chains, each with independent phase and

amplitude control. All four transmitters can be used simultaneously or in time-multiplexed fashion. The device

supports binary phase modulation and a 6 bit programmable phase shifter for beamforming control on a per

chirp basis for each channel as indicated in the figure below.

Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit chains also

support programmable backoff for system optimization.

图8-3 describes the transmit subsystem.

Self Test

LO Loopback

Path

Beamforming

Control

PA Loopback

Path

6 bits

PCB

12dBm

@ 50 Ω

û-

LO

0/180°

(from Timing Engine)

图8-3. Transmit Subsystem (Per Channel)

8.3.1.3 Receive Subsystem

The device Receive subsystem consists of four parallel channels. A single receive channel consists of an LNA,

mixer, IF filtering, ADC conversion, and decimation. All four receive channels can be operational at the same

time. An individual power-down option is also available for system optimization.

The device supports a real-only receiver. The band-pass IF chain has configurable cutoff frequencies above 350

kHz and can support bandwidths up to 15 MHz.

图8-4 describes the receive subsystem.

Self Test

RSSI

Loopback

Path

Saturation Detect

DAC

PCB

50 Ω

GSG

LNA

IFA

DSM

LORX

图8-4. Receive Subsystem (Per Channel)

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8.3.2 Processor Subsystem

图 8-5 shows the block diagram for customer programmable processor subsystems in the device. At a high level

there are two customer programmable subsystems. Left hand side shows the DSP Subsystem which contains

TI's high performance C66x DSP, HWA 2.0, a high-bandwidth interconnect for high performance (128-bit,

150MHz), and associated peripherals – six EDMAs for data transfer,Aurora and LVDS interface for

Measurement data output, L3 Radar data cube memory, ADC buffers, CRC engine, and data handshake

memory (additional memory provided on interconnect).

For more information, see the TMS320C66x DSP CorePac User Guide

The right side of the diagram shows the Main subsystem (MSS). The Main subsystem, as the name suggests, is

the primary controller of the device and controls all the device peripherals and house-keeping activities of the

device. The Main subsystem contains a Cortex-R5F (MSS R5F) processor and associated peripherals and

housekeeping components such as EDMAs, CRC, and peripherals (I²C, UART, SPIs, CAN-FD, EPWM, and

others) connected to the primary interconnect through the Peripheral Central Resource (PCR interconnect).

The Radio Processing Subsystem or the BIST Subsystem (RSS) is responsible for initializing and calibrating the

Analog/RF modules. RSS periodically monitors the Analog/RF functionality such that all the Analog/RF modules

work in their defined limits.

General-Purpose ADC (GPADC), Fast Fourier Transformation engine (FFT engine) and other modules are

provided to monitor the signal from different points in the transmitter and receiver chains. Digital front-end filters

(DFE), Ramp Generation module and Analog/DFE registers, which are mainly under the control of BSS, can be

indirectly controlled through the API calls from the Main Subsystem.

The device also integrates one two-lane CSI2 receiver interfaces in the radio processing subsystem. The prime

functionality of this interface is the Hardware in loop (HIL) functionality, that can be used to perform the radar

operations feeding the captured data from outside into the device without involving the RF subsystem.

Refer to the Device TRM (Technical Reference Manual) for MSS Cortex-R5F and DSP C66x memory map.

English Data Sheet: SWRS273

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DSP SS

Main SS

Uart#2

L2

384 KB

L3 Memory

Bank

UART

Cache/RAM

I2C

L1P

32 KB

2/2.5 MB

MPU

CAN FD #2

Uart#2

C66x

JTAG

L1D

32 KB

DSPSS L2

Interconnect

Uart#2

SPI #2

RS232

EPWM #3

I2C

Development Interfaces

I2C

CPSW

DSPSS L1 Interconnect (ECC)

MCU Interfaces

EDMA

TC

EDMA

TC

DSPSS L2 Interconnect

EDMA

TC

#3

EDMA

CRC

EDMA

TC

HWA 2.0

(CPUSS, FFT,

CFAR, Histogram etc)

#3

(TPCC #2)

TC

(TPCC #2)

#3

TC

#6

(TPCC #3)

QSPI

HSM

MCU Cortex 32 KB

R5F

Cache

R5F

Cache

FUSA

CRYPTO

ACCELERATORS

MSS R5F TCM (128 KB)

MSS R5F L2 (960 KB)

BSS

EDMA

TC

#1

Mailbox

Interrupts/

SW Triggers

(Complete SS including ARM

CR4F (Lockstep), DFE,

RF/Analog Control,

(TPCC #1)

Monitoring, Calibration)

ESM Signals

RSS L1 Interconnect (ECC)

Reset

Watch

Dog

VIM

#2

Clocks

RCSS L2 Interconnect

LBIST,

PBIST

RTI

#3

Interrupts/

SW Triggers

DCC

#4

GPIO/

MUX

#4

2L

CSI2

FUSE

ROM

ESM

CRC

RSS Radar Subsystem

DBG/

TRACE

GPADC

FUSA

DPLL

CNTRL

RF/ANALOG

FRONT END

77 GHz

WAKEUP SS

图8-5. Processor Subsystem

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8.3.3 Automotive Interfaces

The device communicates with the automotive network over the following main interfaces:

• CAN-FD

• Ethernet

8.4 Other Subsystems

8.4.1 Hardware Accelerator Subsystem

In addition to the DSP core, the device incorporates Radar Hardware Accelerators (HWA2.1) to offload the DSP

from pre-processing computations.

To understand the capabilities offered by the Radar Hardware Accelerator 2.0 so as to achieve the desired

functionality, please refer to the Hardware Accelerator 2.0 section in the Device Technical reference Manual.

8.4.2 Security –Hardware Security Module

A Hardware Security Module (HSM), which performs a secure zone operation, is provisioned in the device

(operational only in select part variants). A programmable Arm Cortex-M4 core is available to implement the

crypto-agility requirements.

The cryptographic algorithms can be accelerated using the hardware modules in the HSM. Functions include

acceleration of AES, SHA, and public key accelerator (PKA) to perform math operations for asymmetric key

cryptographic requirements and true random number generation.

The Main subsystem (MSS) Cortex-R5F processor interfaces with the HSM subsystem to perform the

cryptographic operations required for the secure boot and secure runtime communications.

Further details on Security can be found in the concerned collaterals. Please reach out to your local TI sales

representative for more information.

8.4.3 ADC Channels (Service) for User Application

The device includes provision for an ADC service for user application, where the GPADC engine present inside

the device can be used to measure up to nine external and internal voltages. The ADC1, ADC2, ADC3, ADC4,

ADC5, ADC6, ADC7, ADC8 and ADC9 pins are used for this purpose.

备注

GPADC structures are also used for measuring the output of internal temperature sensors.

GPADC Specifications:

• 625 Ksps SAR ADC

• 0 to 1.8V input range

• 10-bit resolution

English Data Sheet: SWRS273

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9

ADC 1-9

GPADC

9

表8-1. GP-ADC Parameter

PARAMETER

TYP

1.8

UNIT

V

ADC supply

ADC unbuffered input voltage range

ADC buffered input voltage range⁽¹⁾

ADC resolution

V

0 –1.8

0.4 –1.3

10

V

bits

LSB

Ksps

ns

ADC offset error

±5

ADC gain error

±5

ADC DNL

–1/+2.5

±2.5

625

ADC INL

ADC sample rate

ADC sampling time

ADC internal cap

400

10

pF

ADC buffer input capacitance

ADC input leakage current

2

pF

3

uA

(1) Outside of given range, the buffer output will become nonlinear.

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9 Monitoring and Diagnostics

9.1 Monitoring and Diagnostic Mechanisms

表9-1 is a list of the main monitoring and diagnostic mechanisms available in the device.

表9-1. Monitoring and Diagnostic Mechanisms for AWR294x

NO

FEATURE

DESCRIPTION

MAIN SUBSYSTEM

1

2

Lockstep operation of MSS R5F

Core

Device architecture supports lockstep operation of the MSS R5F core that is the operating

core in the Main subsystem that is provisioned as the safety island in the device.

Boot time LBIST For MSS R5F

Core and associated VIM

Device architecture supports hardware logic BIST (LBIST) engine self-test Controller

(STC). This logic is used to provide a very high diagnostic coverage (>90%) on the MSS

R5F CPU core and Vectored Interrupt Module (VIM) at a transistor level.

LBIST for the CPU and VIM need to be triggered by application code before starting the

functional safety application. A reset of the CPU is initiated at the end of the STC

operation and the reset cause register captures the status of reset. The STC registers can

then be read out to identify the status of the STC execution to determine if there were any

errors. CPU stays there in while loop and does not proceed further if a fault is identified.

There can be a fault injection test also performed which leads to a reset of the CPU with

the error status signaled in the STC registers.

3

Boot time PBIST for MSS R5F

Memories

MSS R5F has tightly coupled memories (TCM) Level 1 (L1) memories TCMA, TCMB0 and

TCMB1 as well as the level 2 (L2) memories. Device architecture supports a hardware

programmable memory BIST (PBIST) engine. This logic is used to provide a very high

diagnostic coverage (March-13n) on the implemented MSS R5F TCMs at a transistor

level.

PBIST for L1 and L2 memories is triggered by the bootloader at the boot time before

starting download of application from flash or a peripheral interface. The CPU is in a while

loop and does not proceed further if a fault is identified.

4

End to End ECC for MSS R5F

Memories

The TCMs and L2 memory diagnostic support a single error correction, double error

detection (SECDED) ECC diagnostic. For L2 memory, an 8-bit code word is used to store

the ECC data as calculated over the 64-bit data bus. For TCMs, a 7-bit code word is used

to store the ECC data for a 32-bit data bus. ECC evaluation for TCMs is done by the ECC

control logic inside the CPU. This scheme provides end-to-end diagnostics on the

transmissions between CPU and TCM. CPU can be configured to have predetermined

response (ignore or abort generation) to single and double bit error conditions.

5

MSS R5F bit multiplexing

Logical TCM and L2 memory word and the associated ECC code is split and stored in two

physical SRAM banks. This scheme provides an inherent diagnostic mechanism for

address decode failures in the physical SRAM banks. Faults in the bank addressing are

detected by the CPU as an ECC fault.

Further, bit multiplexing scheme is implemented such that the bits accessed to generate a

logical (CPU) word are not physically adjacent. This scheme helps to reduce the

probability of physical multi-bit faults resulting in logical multi-bit faults; rather the faults

manifest as multiple single bit faults. As the SECDED TCM ECC can correct a single bit

fault in a logical word, this scheme improves the usefulness of the TCM ECC diagnostic.

Both these features are hardware features and cannot be enabled or disabled by

application software.

6

Clock Monitor

Device architecture supports four digital clock comparators (EDCCs) and an internal

RCOSC. Dual functionality is provided by these modules –clock detection and clock

monitoring.

EDCCA is dedicated for ADPLL/APLL lock detection monitoring, comparing the ADPLL/

APLL output divided version with the Reference input clock of the device. Failure detection

for EDCCA can be programmed to cause the device to go into limp mode.

Additionally, there is a provision to feed an external reference clock to monitor the internal

clock using the EDCCA.

EDCCB, EDCCC, EDCCD module is one which is available for user software. Any two

clocks can be compared. One example is to compare the CPU clock with the reference or

internal RCOSC clock source. Failure detection is indicated to the MSS R5F CPU through

the Error Signaling Module (ESM).

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www.ti.com.cn

NO

表9-1. Monitoring and Diagnostic Mechanisms for AWR294x (continued)

FEATURE

DESCRIPTION

7

RTI/WDT for MSS R5F

Device architecture supports the use of an internal watchdog that is implemented in the

real-time interrupt (RTI) module. The internal watchdog has two modes of operation: digital

watchdog (DWD) and digital windowed watchdog (DWWD). The modes of operation are

mutually exclusive; the designer can elect to use one mode or the other but not both at the

same time.

Watchdog can issue either an internal (warm) system reset or a CPU non-mask able

interrupt upon detection of a failure.

The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot

process. When the application code takes control, the watchdog can be configured again

for the mode and timings based on the application requirements.

8

9

MPU for MSS R5F

The Cortex-R5F CPU includes an MPU. The MPU logic can be used to provide spatial

separation of software tasks in the device memory. The Cortex-R5F MPU supports 16

regions. The operating system controls the MPU and changes the MPU settings based on

the needs of each task. A violation of a configured memory protection policy results in a

CPU abort.

PBIST for Peripheral interface

SRAMs - SPIs,CANs, Ethernet,

EDMA, Mailbox

Device architecture supports a hardware programmable memory BIST (PBIST) engine for

Peripheral SRAMs as well.

PBIST for peripheral SRAM memories can be triggered by the application. User can elect

to run the PBIST on one SRAM or on groups of SRAMs based on the execution time,

which can be allocated to the PBIST diagnostic. The PBIST tests are destructive to

memory contents, and as such are typically run only at boot time. However, the user has

the freedom to initiate the tests at any time if peripheral communication can be hindered.

Any fault detected by the PBIST results in an error indicated in PBIST status registers.

10

11

ECC for Peripheral interface

SRAMs –SPIs, CANs, Ethernet,

EDMA, Mailbox

Peripheral interface SRAMs diagnostic is supported by Single error correction double error

detection (SECDED) ECC diagnostic. When a single or double bit error is detected, the

MSS R5F is notified via ESM (Error Signaling Module). This feature is disabled after reset.

Software must configure and enable this feature in the peripheral and ESM module. ECC

failure (both single bit corrected and double bit uncorrectable error conditions) is reported

to the MSS R5F as an interrupt via ESM module.

Configuration registers protection

for Main SS peripherals

All the Main SS peripherals (SPIs, CANs, Ethernet, I2C, DMAs, RTI/WD, DCCs, EDMA,

IOMUX etc.) are connected to interconnect via Peripheral Central resource (PCR). This

provides two diagnostic mechanisms that can limit access to peripherals. Peripherals can

be clock gated per peripheral chip select in the PCR. This can be utilized to disable

unused features such that the features cannot interfere. In addition, each peripheral chip

select can be programmed to limit access based on privilege level of transaction. This

feature can be used to limit access to entire peripherals to privileged operating system

code only.

These diagnostic mechanisms are disabled after reset. Software must configure and

enable these mechanisms. Protection violation also generates an error that result in abort

to MSS R5F or error response to other hosts such as DMAs.

12

Device architecture supports hardware CRC engine on Main SS implementing the below

polynomials.

Cyclic Redundancy Check–Main

SS

•

CRC16 CCITT –0x10

CRC32 Ethernet –0x04C11DB7

CRC64

CRC 32C –CASTAGNOLI –0x1EDC6F4

CRC32P4 –E2E Profile4 –0xF4ACFB1

The read operation of the SRAM contents to the CRC can be done by CPU or by DMA.

The comparison of results, indication of fault, and fault response are the responsibility of

the software managing the test.

13

14

MPU

Device architecture supports MPUs on certain peripheral ports in the Main SS that include

L2 Memory, PCR peripheral access, QSPI access, R5F AXI-peripheral access. This allows

configuring access permissions to these key regions in the Main SS.

By default, this control resides with the HSM.

MPU for DMAs

Device architecture supports MPUs on Main SS EDMAs. EDMAs also includes MPUs on

both read and writes host ports. EDMA MPUs supports 8 regions. Failure detection by

MPU is reported to the core as an interrupt via local ESM.

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English Data Sheet: SWRS273

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表9-1. Monitoring and Diagnostic Mechanisms for AWR294x (continued)

NO

FEATURE

DESCRIPTION

15

16

Interconnect ECC

Device architecture supports hardware based ECC protection mechanisms for transfers

over the system interconnect. Since code execution includes instruction fetches from

memories hosted on the interconnect, the transfers over the interconnect are designed to

be safe by a combination of ECC and redundancy based mechanisms. Any failures

detected in the transfers are reported over the ESM interface. This mechanism is enabled

by default in HW.

Error Signaling Module

When a diagnostic detects a fault, the error must be indicated. The Device architecture

provides aggregation of fault indication from internal monitoring/diagnostic mechanisms

using a peripheral logic known as the Error Signaling Module (ESM). The ESM provides

mechanisms to classify errors by severity and to provide programmable error response.

ESM module is configured by customer application code and specific error signals can be

enabled or masked to generate an interrupt (Low/High priority) for the MSS R5F CPU.

Device supports Nerror output signal (IO) which can be monitored externally to identify any

kind of high severity faults in the design which are not be handled by the R5F.

17

18

Temperature Sensor

Voltage Monitors

Device architecture supports various temperature sensors at temperature hotspots in

digital across the device that can be monitored by the application using an internal GPADC

channel.

Device architecture supports monitoring the supply rails connected to the chip, in

conjunction with external voltage monitors.

DSP SUB-SYSTEM

1

2

Boot time LBIST for DSP core

Device supports boot time LBIST for the DSP Core. LBIST can be triggered by the MSS

R5F secondary bootloader/application code before starting the functional safety

application.

Boot time PBIST for L1P, L1D, L2

Device architecture supports a hardware programmable memory BIST (PBIST) engine for

and L3 Memories, HWA memories, DSPSS and RSS memories which provide a very high diagnostic coverage (March-13n).

RSS Memories (ADCBUF, CQ

Memory), Mailbox

PBIST is triggered by MSS R5F secondary bootloader/application code before starting the

functional safety application.

3

4

Parity on L1P, ECC on L1D

Device architecture supports Parity diagnostic on DSP’s L1P memory. Parity error is

reported to the CPU as an interrupt.

L1D memory is covered by SECDED ECC.

Device architecture supports both Parity Single error correction double error detection

(SECDED) ECC diagnostic on DSP’s L1D and L2 memory. L2 Memory is a unified

384KB of memory used to store program and Data sections for the DSP. A 12-bit code

word is used to store the ECC data as calculated over the 256-bit data bus (logical

instruction fetch size). The ECC logic for the L2 access is located in the DSP and

evaluation is done by the ECC control logic inside the DSP. This scheme provides end-to-

end diagnostics on the transmissions between DSP and L2. Byte aligned Parity

mechanism is also available on L2 to take care of data section.

ECC on DSP’s L2 Memory

5

6

ECC on Radar Data Cube (L3)

Memory, HWA Memories, RSS

Memory (ADCBUF), Mailbox

L3 memory is used as Radar data section in the device. The architecture supports Single

error correction double error detection (SECDED) ECC diagnostic on L3 memory. A 12-bit

code word is used to store the ECC data as calculated over the 256-bit data bus.

The RSS memory (ADCBUF) too supports the SECDED ECC diagnostics.

Failure detection by ECC logic is reported to the DSP core as an interrupt via ESM.

RTI/WDT for DSP Core

Device architecture supports the use of an internal watchdog for DSP C66x that is

implemented in the real-time interrupt (RTI) module –replication of same module as used

in Main SS. This module supports same features as that of RTI/WD for MSS.

This watchdog is enabled by customer application code and Timeout condition is reported

via an interrupt to DSP and/or MSS R5F and rest is left to application code in MSS R5F to

take the device to a safe state.

88

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English Data Sheet: SWRS273

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www.ti.com.cn

NO

表9-1. Monitoring and Diagnostic Mechanisms for AWR294x (continued)

FEATURE

DESCRIPTION

7

CRC for DSP Sub-System

Device architecture supports hardware CRC engine on DSPSS implementing the below

polynomials.

•

CRC16 CCITT –0x10

CRC32 Ethernet –0x04C11DB7

CRC64

CRC 32C –CASTAGNOLI –0x1EDC6F4

CRC32P4 –E2E Profile4 –0xF4ACFB1

The read operation of the SRAM contents to the CRC can be done by CPU or by DMA.

The comparison of results, indication of fault, and fault response are the responsibility of

the software managing the test.

8

9

MPU for DSP

MPU

Device architecture supports MPUs for DSP memory accesses (L1D, L1P, and L2). L2

memory supports 64 regions and 16 regions for L1P and L1D each. Failure detection by

MPU is reported to the DSP core as an abort.

Device architecture supports MPUs on certain peripheral ports in the DSP SS that include

L3 Memory banks. This allows configuring access permissions to these key regions in the

DSP SS.

By default, this control resides with the HSM.

BIST (Within RADAR SUB-SYSTEM)

NOTE: BIST is handled by the TI firmware. Refer to the mmWave Interface Control Document (as a part of mmWave-MCUPLUS-SDK

package) and safety manual for information on safety mechanisms.

备注

Refer to the Device Safety Manual or other relevant collaterals for more details on applicability of all

diagnostics mechanisms.

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English Data Sheet: SWRS273

AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

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10 Applications, Implementation, and Layout

备注

Information in the following Applications section is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

Key device features driving the following applications are:

• Integration of Radar Front End and Programmable MCU

• Flexible boot modes: Autonomous application boot using a serial flash or external boot over SPI

• Hardware Security Module

• High speed 100Mbps Fast Ethernet Support

10.2 Short and Medium Range Radar

40-MHz

Crystal

Serial

Flash

Power Management

QSPI

Integrated MCU

ARM Cortex-R5F

Ethernet

PHY

Automotive

Network

Ethernet

Antenna

Structure

RX1

RX2

RX3

RX4

MCAN

PHY

Automotive

Network

CAN FD (2)

Radar

Front End

TX1

TX2

TX3

TX4

Integrated DSP

TI C66x

mmWave Sensor

图10-1. Short- and Medium-Range Radar

10.3 Reference Schematic

The reference schematic and power supply information can be found in the AWR2944 EVM Documentation.

Listed for convenience are: Design Files, Schematics, Layouts, and Stack up details for PCB at the AWR2944

EVM Product page.

English Data Sheet: SWRS273

90

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11 器件和文档支持

TI 提供大量的开发工具。下面列出了用于评估器件性能、生成代码和开发解决方案的工具和软件。

11.1 Device Support

11.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, XA2943BGALT). Texas Instruments recommends two of three possible prefix designators for its

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from

engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

X Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null

Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, your package), the temperature range (for example, blank is the default commercial temperature

range), and the device speed range, in megahertz (for example, your device speed range). Figure x provides a

legend for reading the complete device name for any your device device.

For orderable part numbers of your device devices in the your package package types, see the Package Option

Addendum of this document, ti.com, or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the AWR2944 Errata

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Product Folder Links: AWR2943 AWR2944

English Data Sheet: SWRS273

AWR2943, AWR2944

ZHCSP99A –NOVEMBER 2021 –REVISED MARCH 2023

www.ti.com.cn

2

9

44

B

XA

G

ALT

Q1

Qualification

Q1 = AEC-Q100

Blank = no special Qual

Prefix

XA = Pre-production Automotive

AWR = Production Automotive

Tray or Tape & Reel

Generation

1, 2 = 76 - 81 GHz

Variant

T = Small Reel

R = Big Reel

Blank = Tray

Package

ALT = BGA

Security

2 = FE

4 = FE + FFT + MCU

6 = FE + MCU + DSP

8 = FE + FFT + MCU + DSP

9 = FE + FFT + MCU + DSP

G = General

S = Secure

D = Development Secure

Num RX/TX Channels

Safety

RX = 1,2,3,4

TX = 1,2,3,4

Q = Quality Manage

A = ASIL A Targeted

B = ASIL B Targeted

Silicon PG Revision

Blank = Rev 1.0

A = Rev 2.0 / Rev 3.0

Features

Blank = Baseline

N = Narrow Band (76-77 GHz)

图11-1. Device Nomenclature

11.3 Tools and Software

The contents in this section will be updated in subsequent versions.

11.4 Documentation support

The contents in this section will be updated in subsequent versions.

11.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.6 Trademarks

TI E2E^™is a trademark of Texas Instruments.

Arm^®and Cortex-R5F^®are registered trademarks of Arm Limited.

所有商标均为其各自所有者的财产。

11.7 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.8 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

English Data Sheet: SWRS273

92

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: AWR2943 AWR2944

English Data Sheet: SWRS273

PACKAGE OUTLINE

ALT0266A

FCBGA - 1.2 mm max height

S

C

A

L

E

1

.

2

0

BALL GRID ARRAY

12.1

11.9

B

A

BALL A1

CORNER

12.1

11.9

0.15 C

0.2 C

1.2 MAX

C

SEATING PLANE

0.1 C

0.462

0.216

11.05 TYP

SYMM

(0.475)

V

U

T

R

P

N

M

L

SYMM

K

11.05 TYP

J

H

G

F

E

D

C

0.46

266X

0.36

0.15

0.08

C A B

C

B

A

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

0.65 TYP

4226546/A 02/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ALT0266A

FCBGA - 1.2 mm max height

BALL GRID ARRAY

(0.65) TYP

266X ( 0.35)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

A

B

C

D

E

F

(0.65) TYP

G

H

J

SYMM

K

L

M

N

P

R

T

U

V

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

EXPOSED METAL

(

0.35)

(

0.35)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED METAL

METAL EDGE

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4226546/A 02/2021

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

ALT0266A

FCBGA - 1.2 mm max height

BALL GRID ARRAY

(0.65) TYP

266X ( 0.35)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

A

B

C

D

E

F

(0.65) TYP

G

H

J

SYMM

K

L

M

N

P

R

T

U

V

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

4226546/A 02/2021

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AWR2944ABGALTRQ1
厂家：	TEXAS INSTRUMENTS
描述：	适用于角雷达和远距离雷达的汽车类第二代 76GHz 至 81GHz 高性能 SoC \| ALT \| 266 \| -40 to 140 雷达
文件：	总99页 (文件大小：2231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AWR2944ABGALTRQ1 [TI]

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