BQ2003S-NTR [TI]
Switch-mode NiCd/NiMH battery charger with negative dV and dT/dt termination 16-SOIC -40 to 85;
| 型号： | BQ2003S-NTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Switch-mode NiCd/NiMH battery charger with negative dV and dT/dt termination 16-SOIC -40 to 85 |
| 文件： | 总15页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2003
Fast-Charge IC
Features
General Description
Fast charge may begin on applica-
tion of the charging supply, replace-
ment of the battery, or switch de-
pression. For safety, fast charge is
inhibited unless/until the battery
temperature and voltage are within
configured limits.
➤
Fast charge and conditioning of
The bq2003 Fast Charge IC provides
comprehensive fast charge control
functions together with high-speed
switching power control circuitry on a
monolithic CMOS device.
nickel cadmium or nickel-metal
hydride batteries
➤
Hysteretic PWM switch-mode
current regulation or gated con-
trol of an external regulator
Integration of closed-loop current
control circuitry allows the bq2003
to be the basis of a cost-effective so-
lution for stand-alone and system-
integrated chargers for batteries of
one or more cells.
Temperature, voltage, and time are
monitored throughout fast charge.
Fast charge is terminated by any of
the following:
➤
➤
➤
➤
Easily integrated into systems
or used as a stand-alone charger
Pre-charge qualification of tem-
perature and voltage
n
Rate of temperature rise
(∆T/∆t)
Switch-activated discharge-before-
charge allows bq2003-based chargers
to support battery conditioning and
capacity determination.
Direct LED outputs display
battery and charge status
n
n
n
n
Negative delta voltage (-∆V)
Maximum voltage
Fast-charge termination by
∆ temperature/∆ time, -∆V, maxi-
mum voltage, maximum tem-
perature, and maximum time
Maximum temperature
Maximum time
High-efficiency power conversion is
accomplished using the bq2003 as a
hysteretic PWM controller for
switch-mode regulation of the charg-
ing current. The bq2003 may alterna-
tively be used to gate an externally
regulated charging current.
After fast charge, an optional top-off
phase is available. Constant-cur-
rent maintenence charge is provided
by an external trickle resistor.
➤
Optional top-off charge
Pin Connections
Pin Names
CCMD
DCMD
DVEN
TM1
Charge command/select
Discharge command
-∆V enable/disable
Timer mode select 1
Timer mode select 2
Temperature sense
Battery voltage
SNS
TCO
Sense resistor input
Temperature cutoff
Maximum voltage
CCMD
DCMD
DVEN
1
2
3
4
5
6
16
15
14
13
12
11
V
CC
MCV
TEMP
DIS
Temperature status
output
MOD
CHG
TEMP
MCV
TM2
TM
TM
1
CHG
MOD
DIS
Charging status output
Charge current control
Discharge control
TS
2
TS
BAT
VSS
BAT
7
8
10
9
TCO
SNS
System ground
V
SS
VCC
5.0V 10% power
16-Pin DIP or SOIC
PN200301.eps
SLUS095A - OCTOBER 1999 I
1
bq2003
Temperature cutoff threshold input
TCO
MCV
Pin Descriptions
Input to set maximum allowable battery
temperature. If the potential between TS
and SNS is less than the voltage at the TCO
input, then fast charge or top-off charge is
terminated.
Charge initiation and discharge-before-
charge control inputs
CCMD,
DCMD
These two inputs control the conditions that
begin a new charge cycle and enable
discharge-before-charge. See Table 1.
Maximum-Cell-Voltage threshold input
-∆V enable input
DVEN
Input to set maximum single-cell equivalent
voltage. If the voltage between BAT and SNS
is greater than or equal to the voltage at the
MCV input, then fast charge or top-off charge
is inhibited.
This input enales/disables -∆V charge termina-
tion. If DVEN is high, the -∆V test is enabled.
If DVEN is low, -∆V test is disabled. The state
of DVEN may be changed at any time.
Note: For valid device operation, the
voltage level on MCV must not exceed
Timer mode inputs
TM1–
TM2
0.6 ∗ VCC
.
TM1 and TM2 are three-state inputs that con-
figure the fast charge safety timer, -∆V hold-
off time, and that enhance/disable top-off.
See Table 2.
Temperature status output
TEMP
Push-pull output indicating temperature
status. TEMP is low if the voltage at the TS
pin is not within the allowed range to start
fast charge.
Temperature sense input
TS
Input, referenced to SNS, for an external
thermistor monitoring battery temperature.
Charging status output
CHG
MOD
Single-cell voltage input
BAT
Push-pull output indicating charging status.
See Figure 1.
The battery voltage sense input, referenced
to SNS. This is created by a high-impedance
resistor divider network connected between
the positive and the negative terminals of
the battery.
Current-switching control output
MOD is a push/pull output that is used to
control the charging current to the battery.
MOD switches high to enable charging cur-
rent flow and low to inhibit charging current
flow.
Ground
Vss
Charging current sense input
SNS
Discharge FET control output
DIS
VCC
SNS controls the switching of MOD based on
the voltage across an external sense resistor
in the current path of the battery. SNS is the
reference potential for the TS and BAT pins.
If SNS is connected to VSS, MOD switches
high at the beginning of charge and low at
the end of charge.
Push-pull output used to control an external
transistor to discharge the battery before
charging.
VCC supply input
5.0 V, 10% power input.
2
bq2003
the resistor connected to the positive battery terminal,
and RB2 is the resistor connected to the negative bat-
tery terminal. See Figure 1.
Functional Description
Figure 3 shows a state diagram and Figure 4 shows a
block diagram of the bq2003.
Note: This resistor-divider network input impedance to
end-to-end should be at least 200kΩ and less than 1MΩ.
Battery Voltage and Temperature
Measurements
A ground-referenced negative temperature coefficient
thermistor placed in proximity to the battery may be used
as a low-cost temperature-to-voltage transducer. The tem-
perature sense voltage input at TS is developed using a re-
sistor-thermistor network between VCC and battery’s nega-
tive terminal See Figure 1. Both the BAT and TS inputs
are referenced to SNS, so the signals used inside the IC are:
Battery voltage and temperature are monitored for
maximum allowable values. The voltage presented on
the battery sense input, BAT, should represent a
single-cell potential for the battery under charge.
resistor-divider ratio of:
A
RB1
RB2
V
BAT - VSNS = VCELL
and
TS - VSNS = VTEMP
= N - 1
is recommended to maintain the battery voltage within
the valid range, where N is the number of cells, RB1 is
V
Table 1. New Charge Cycle and Discharge Stimulus
CCMD
DCMD
New Charge Cycle
Started by:
Discharge-Before-Charge
Started by:
Pulled Up/Down to:
VCC rising to valid level
Battery replacement
(VCELL falling through VMCV
VSS
VSS
A rising edge on DCMD
)
A rising edge on CCMD
VCC rising to valid level
Battery replacement
(VCELL falling through VMCV
VCC
VCC
A rising edge on DCMD
)
A falling edge on CCMD or DCMD
A rising edge on CCMD
VCC
VSS
VSS
VCC
A rising edge on DCMD
A rising edge on DCMD
A falling edge on CCMD
External Trickle Resistor
Negative Temperature
Coefficient Thermister
V
DC
V
CC
Pass Element
MOD
PACK +
RT1
PACK+
PACK-
T
S
RB1
RB2
bq2003
N
T
C
bq2003
RT2
BAT
SNS
PACK -
SNS
Fg2003a2.eps
Figure 1. Voltage and Temperature Monitoring and Trickle Resistor
3
bq2003
3. A rising edge on CCMD if it is pulled down, or a fal-
ling edge on CCMD if it is pulled up.
Discharge-Before-Charge
The DCMD input is used to command discharge-before-
charge via the DIS output. Once activated, DIS becomes
active (high) until VCELL falls below VEDV, at which time
DIS goes low and a new fast charge cycle begins. See
Table 1 for the conditions that initiate discharge-before-
charge. Discharge-before-charge is qualified by the
same voltage and temperature conditions that qualify a
new charge cycle start (see below). If a discharge is ini-
tiated but the pack voltage or temperature is out of
range, the chip enters the charge pending mode and
trickle charges the battery until the voltage and tem-
perature qualification conditions are met, and then
starts to discharge.
Starting a new charge cycle may be limited to a push-
button or logical pulse input only by pulling one member
of the DCMD and CCMD pair up while pulling the other
input down. In this configuration a new charge cycle
will be started only by a falling edge on CCMD if it is
pulled up, and by a falling edge on CCMD if it is pulled
down. See Table 1.
If the battery is within the configured temperature and
voltage limits, the IC begins fast charge. The valid bat-
tery voltage range is VEDV < VBAT < VMCV where:
VEDV = 0.2 ∗ VCC 30mV
The valid temperature range is VHTF < VTEMP < VLTF
,
Starting A Charge Cycle
where:
The stimulus required to start a new charge cycle is de-
termined by the configuration of the CCMD and DCMD
inputs. If CCMD and DCMD are both pulled up or
pulled down, then a new charge cycle is started by (see
Figure 2):
VLTF = 0.4 ∗ VCC 30mV
VHTF = [(1/8 ∗ VLTF) + (7/8 ∗ VTCO)] 30mV
V
TCO is the voltage presented at the TCO input pin, and is
configured by the user with a resistor divider between VCC
and ground. The allowed range is 0.2 to 0.4 ∗ VCC
1.
VCC rising above 4.5V
.
2. VCELL falling through the maximum cell voltage,
If the temperature of the battery is out of range, or the
voltage is too low, the chip enters the charge pending
state and waits for both conditions to fall within their
allowed limits. There is no time limit on the charge
pending state; the charger remains in this state as long
as the voltage or temperature conditons are outside of
VMCV VMCV is the voltage presented at the MCV
.
input pin, and is configured by the user with a re-
sistor divider between VCC and ground. The al-
lowed range is 0.2 to 0.4 ∗ VCC
.
Charge
Pending
Discharge
(Optional)
Fast Charging
Top-Off
(Optional)
DIS
MOD Switch-Mode Configuration
or
4
sec
MOD External Regulation
(SNS Grounded)
.
34 sec.
CHG Status Output
TEMP Status Output
Battery discharged to 0.2
Battery within temperature limits.
V
CC
.
Charge cycle start.
TD200301a.eps
Battery outside temperature limits.
Figure 2. Charge Cycle Phases
4
bq2003
Table 2. Fast-Charge Safety Time/Hold-Off/Top-Off Table
Typical Fast Charge
and Top-Off
Typical -∆V/MCV
Corresponding
Hold-Off
Top-Off
Rate
Fast-Charge Rate
TM1
Low
Float
High
Low
Float
High
Low
Float
High
TM2
Low
Low
Time Limits
Time (seconds)
C/4
C/2
1C
2C
4C
C/2
1C
2C
4C
360
180
90
45
23
180
90
45
137
820
410
200
100
820
410
200
100
Disabled
Disabled
Disabled
Disabled
Disabled
C/16
Low
Float
Float
Float
High
High
High
C/8
C/4
C/2
23
Note:
Typical conditions = 25°C, VCC = 5.0V.
maximum temperature terminations are not affected by
the hold-off period.
the allowed limits. If the voltage is too high, the chip
goes to the battery absent state and waits until a new
charge cycle is started.
∆T/∆t Termination
Fast charge continues until termination by one or more
of the five possible termination conditions:
The bq2003 samples at the voltage at the TS pin every
34s, and compares it to the value measured two samples
earlier. If VTEMP has fallen 16mV 4mV or more, fast
charge is terminated. The ∆T/∆t termination test is
n
n
n
n
n
Delta temperature/delta time (∆T/∆t)
Negative delta voltage (-∆V)
Maximum voltage
valid only when VTCO < VTEMP < VLTF
.
Temperature Sampling
Maximum temperature
Maximum time
Each sample is an average of 16 voltage measurements
taken 57µs apart. The resulting sample period
(18.18ms) filters out harmonics around 55Hz. This tech-
nique minimizes the effect of any AC line ripple that
may feed through the power supply from either 50Hz or
60Hz AC sources. Tolerance on all timing is 16%.
-∆V Termination
If the DVEN input is high, the bq2003 samples the volt-
age at the BAT pin once every 34s. If VCELL is lower
than any previously measured value by 12mV 4mV,
fast charge is terminated. The -∆V test is valid in the
Maximum Voltage, Temperature, and Time
Anytime VCELL rises above VMCV, CHG goes high (the LED
goes off) immediately. If the bq2003 is not in the voltage
hold-off period, fast charging ceases if VCELL remains above
MCV for a minimum of tMCV. If VCELL then falls back be-
low VMCV before 1.5tMCV 50ms, the chip transitions to the
Charge Complete state (maximum voltage termination). If
VCELL remains above VMCV beyond 1.5tMCV, the bq2003
transitions to the Battery Absent state (battery removal).
See Figure 3.
range VMCV - (0.2 ∗ VCC) < VCELL < VMCV
.
Voltage Sampling
Each sample is an average of 16 voltage measurements
taken 57µs apart. The resulting sample period (18.18ms)
filters out harmonics around 55Hz. This technique mini-
mizes the effect of any AC line ripple that may feed
through the power supply from either 50Hz or 60Hz AC
sources. Tolerance on all timing is 16%.
If the bq2003 is in the voltage hold-off period when
VCELL rises above VMCV, the LED goes out but fast
charging continues until the expiration of the hold-off
period. Temperature sampling continues during the
hold-off period as well. If a new battery is inserted be-
fore the hold-off period expires, it continues in the fast
charge cycle started by its predecessor. No precharge
qualification is performed, and a temperature sample
Voltage Termination Hold-off
A hold-off period occurs at the start of fast charging.
During the hold-off period, -∆V termination is disabled.
This avoids premature termination on the voltage spikes
sometimes produced by older batteries when fast-charge
current is first applied. ∆T/∆t, maximum voltage and
5
bq2003
taken on the new battery is compared to ones taken be-
fore the original battery was removed and any that may
have been taken while no battery was present. If the IC
is configured for ∆T/∆t termination, this may result in a
premature fast-charge termination on the newly in-
serted battery.
Charge Status Indication
Charge status is indicated by the CHG output. The state
of the CHG output in the various charge cycle phases is
shown in Figure 3 and illustrated in Figure 1.
Temperature status is indicated by the TEMP output.
TEMP is in the high state whenever VTEMP is within the
temperature window defined by the VLTF and VHTF tem-
perature limits, and is low when the battery tempera-
ture is outside these limits.
Maximum temperature termination occurs anytime the
voltage on the TS pin falls below the temperature cut-off
threshold VTCO. Charge is also terminated if VTEMP rises
above the minimum temperature fault threshold, VLTF,
after fast charge begins.
In all cases, if VCELL exceeds the voltage at the MCV
pin, both CHG and TEMP outputs are held high regard-
less of other conditions. CHG and TEMP may both be used
to directly drive an LED.
Maximum charge time is configured using the TM pin.
Time settings are available for corresponding charge
rates of C/4, C/2, 1C, and 2C. Maximum time-out termi-
nation is enforced on the fast-charge phase, then reset,
and enforced again on the top-off phase, if selected.
There is no time limit on the trickle-charge phase.
Charge Current Control
The bq2003 controls charge current through the MOD
output pin. The current control circuitry is designed to
support implementation of a constant-current switching
regulator or to gate an externally regulated current
source.
Top-off Charge
An optional top-off charge phase may be selected to
follow fast charge termination for the C/2 through 4C
rates. This phase may be necessary on NiMH or other
battery chemistries that have a tendency to terminate
charge prior to reaching full capacity. With top-off en-
abled, charging continues at a reduced rate after
fast-charge termination for a period of time selected
by the TM1 and TM2 input pins. (See Table 2.) During
top-off, the MOD pin is enabled at a duty cycle of 4s
active for every 30s inactive. This modulation results
in an average rate 1/8th that of the fast charge rate.
Maximum voltage, time, and temperature are the only
termination methods enabled during top-off.
When used in switch-mode configuration, the nominal
regulated current is:
I
REG = 0.235V/RSNS
Charge current is monitored at the SNS input by the
voltage drop across a sense resistor, RSNS, between the
low side of the battery pack and ground. RSNS is sized to
provide the desired fast-charge current.
If the voltage at the SNS pin is less than VSNSLO, the
MOD output is switched high to pass charge current to
the battery.
External Trickle Resistor
When the SNS voltage is greater than VSNSHI, the MOD
output is switched low—shutting off charging current to
the battery.
Maintenance charging is provided by the use of an exter-
nal trickle resistor between the high side of the battery
pack and VDC, the input charging supply voltage. (See
Figure 1.) This resistor is sized to meet two criteria.
VSNSLO = 0.044 ∗ VCC 25mV
n
With the battery removed, the resistor must pull the
voltage at the BAT input above MCV for battery
insertion and removal detection.
VSNSHI = 0.05 ∗ VCC 25mV
When used to gate an externally regulated current
source, the SNS pin is connected to VSS, and no sense re-
sisitor is required.
n
With the battery at its fully charged voltage, the
trickle current should be approximately equal to the
self-discharge rate of the battery.
6
bq2003
New Charge Cycle Start or
Discharge-Before-Charge
Command
V
> V
< V
CELL
MCV
EDF
or
Battery Voltage?
V
CELL
Charge
Pending
V
EDV
< V
CELL
< V
MCV
V
V
> V
LTF
TEMP
Trickle
CHG =
1 3/8s high
1/8s low
V
CELL
< V
> V
HTF
MCV
TEMP
Battery
Temperature?
V
HTF
< V
TEMP
< V
LTF
V
< V
< V
EDV
and
CELL
MCV
No
Discharge-Before-Charge
Commanced?
V
HTF
< V
< V
LTF
TEMP
Discharge
CHG =
V
CELL
> V
MCV
1 3/8s low
1/8s high
V
CELL
V
EDV
<
Battery
Absent
t > 1.5tMCV
V
>
CELL
V
MCV
Yes
Fast
CHG =
Low
Trickle
CHG =
High
Hold-off
Trickle
CHG =
High
period
expired?
No
-
V or
V
<
CELL
V
T/ t or
MCV
Hold-off
period
expires
V
CELL
V
MCV
<
V
or
< V
TCO
TEMP
Fast
CHG =
High
V
V
>
Charge
Complete
CELL
MCV
Maximum
Time Out
V
CELL
V
MCV
>
Top-off
CHG =
1/8s low
1/8s high
Trickle
Top-off
selected?
CHG =
1/8s low
1/8s high
Yes
V
< V
TCO
TEMP
or Maximum
Time Out
No
SD2003.eps
Figure 3. State Diagram
7
bq2003
TM1 TM2
TCO
Timing
Control
TCO
Check
TS
OSC
LTF
Check
TEMP
CHG
Display
Control
V
- V
TS SNS
A/D
SNS
BAT
V
- V
CCMD
DCMD
DVEN
BAT SNS
Charge Control
State Machine
EDV
Check
MOD
MCV
Check
Discharge
Control
Control
DIS
MOD
MCV
V
V
SS
CC
BD200301.eps
Figure 4. Block Diagram
8
bq2003
Absolute Maximum Ratings
Symbol
VCC
Parameter
VCC relative to VSS
Minimum
Maximum
Unit
Notes
-0.3
+7.0
V
DC voltage applied on any pin ex-
cluding VCC relative to VSS
VT
-0.3
+7.0
V
TOPR
Operating ambient temperature
Storage temperature
0
-55
-
+70
+125
+260
+85
°C
°C
°C
°C
Commercial
TSTG
TSOLDER
TBIAS
Soldering temperature
10 sec max.
Temperature under bias
-40
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Thresholds (T = T
; V 10%)
OPR CC
A
Symbol
Parameter
Rating
Tolerance
Unit
Notes
High threshold at SNS re-
sulting in MOD = Low
Tolerance is common
mode deviation.
VSNSHI
0.05 ∗ VCC
0.025
V
Low threshold at SNS re-
sulting in MOD = High
Tolerance is common
mode deviation.
VSNSLO
VLTF
0.044 ∗ VCC
0.025
0.030
0.030
0.030
4
V
V
VTEMP ≥ VLTF inhibits/
terminates charge
0.4 ∗ VCC
Low-temperature fault
High-temperature fault
End-of-discharge voltage
VTEMP ≤ VHTF inhibits
fast charge
VHTF
(1/8 ∗ VLTF) + (7/8 ∗ VTCO
)
V
VCELL < VEDV inhibits
fast charge
VEDV
VTHERM
-∆V
0.2 ∗ VCC
-16
V
TS input change for
∆T/∆t detection
V
CC = 5V, TA = 25°C
CC = 5V, TA = 25°C
mV
mV
BAT input change for
-∆V detection
V
-12
4
9
bq2003
Recommended DC Operating Conditions (T = 0 to +70°C)
A
Symbol
VCC
Parameter
Supply voltage
Minimum
Typical Maximum
Unit
V
Notes
4.5
5.0
5.5
VCC
VBAT
Battery input
0
-
-
-
-
-
-
-
-
-
-
V
VCELL
VTS
BAT voltage potential
Thermistor input
TS voltage potential
Maximum cell voltage
Temperature cutoff
Logic input high
Logic input high
Logic input low
0
VCC
V
VBAT - VSNS
0
VCC
V
VTEMP
VMCV
VTCO
0
VCC
V
VTS - VSNS
V
0.2 ∗ VCC
0.2 ∗ VCC
VCC - 1.0
0.4 ∗ VCC
0.4 ∗ VCC
-
V
V
CCMD, DCMD, DVEN
TM1, TM2
VIH
VIL
V
CC - 0.3
-
V
-
-
1.0
V
CCMD, DCMD, DVEN
TM1, TM2
Logic input low
0.3
V
DIS, TEMP, CHG, MOD,
VOH
VOL
V
CC - 0.5
-
Logic output high
Logic output low
-
-
-
V
V
IOH ≤ -5mA
DIS, TEMP, CHG, MOD,
IOL ≤ 5mA
0.5
ICC
IOH
IOL
Supply current
-
0.75
2.2
mA Outputs unloaded
mA @VOH = VCC - 0.5V
mA @VOL = VSS + 0.5V
DIS, TEMP, MOD, CHG source
DIS, TEMP, MOD, CHG sink
-5.0
5.0
-
-
-
-
CCMD, DCMD, DVEN,
µA
Input leakage
-
-
-
-
-
1
70
-
V = VSS to VCC
IIL
TM1, TM2,
V = VSS to VSS + 0.3V
µA
Logic input low source
Logic input high source
TM1, TM2,
V = VCC - 0.3V to VCC
µA
IIH
-70
TM1, TM2 may be left dis-
TM1, TM2 tri-state open
detection
µA
IIZ
-2.0
-
2.0
connected (floating) for Z
logic input state
Note:
All voltages relative to VSS except as noted.
10
bq2003
Impedance
Symbol
Parameter
Minimum
Typical
Maximum
Unit
MΩ
MΩ
MΩ
MΩ
MΩ
RBAT
RMCV
RTCO
RSNS
RTS
Battery input impedance
MCV input impedance
TCO input impedance
SNS input impedance
TS input impedance
50
50
50
50
50
-
-
-
-
-
-
-
-
-
-
Timing (T = 0 to +70°C; V
10%)
CC
A
Symbol
tPW
Parameter
Minimum Typical Maximum
Unit
Notes
Pulse width for CCMD,
DCMD pulse commands
Pulse start for charge or discharge-
before-charge
µs
1
-16
-
-
-
-
-
dFCV
Time base variation
16
%
VCC = 4.5V to 5.5V
MOD output regulation
frequency
fREG
300
kHz
Maximum voltage
termination time limit
Time limit to distinguish battery re-
moved from charge complete
tMCV
200
250
300
ms
Note:
Typical is at TA = 25°C, VCC = 5.0V.
11
bq2003
PN: 16-Pin DIP Narrow
(
)
16-Pin PN DIP Narrow
Dimension
Minimum
0.160
0.015
0.015
0.055
0.008
0.740
0.300
0.230
0.300
0.090
0.115
0.020
Maximum
0.180
0.040
0.022
0.065
0.013
0.770
0.325
0.280
0.370
0.110
0.150
0.040
A
A1
B
B1
C
D
E
E1
e
G
L
S
All dimensions are in inches.
S: 16-Pin SOIC
(
)
16-Pin S SOIC
Dimension
Minimum
0.095
0.004
0.013
0.008
0.400
0.290
0.045
0.395
0.020
Maximum
0.105
0.012
0.020
0.013
0.415
0.305
0.055
0.415
0.040
A
A1
B
D
B
e
C
E
H
D
E
e
H
L
A
C
All dimensions are in inches.
.004
A1
L
12
bq2003
Data Sheet Revision History
Change No.
Page No.
Description
Changed block diagram
Nature of Change
Changed diagram.
5
5
6
2
8
Added top-off values to Table 2.
Added values.
Clarification
All
Revised and expanded format of this data sheet
Deleted industrial temperature
range.
TOPR
7
8
8
9
3
Corrected Table 1
Correction
Corrected and expanded the explanation for maxi-
mum voltage conditions
5, 7
Clarification
Notes:
Changes 1–4: Please refer to the 1997 Data Book.
Change 5 = Sept. 1996 F changes from Oct. 1993 E.
Change 6 = Oct. 1997 G changes from Sept. 1996 F.
Change 7 = June 1999 H changes from Oct. 1997 G.
Change 8 = Oct. 1999 I changes from June 1999 H.
Ordering Information
bq2003
Package Option:
PN = 16-pin narrow plastic DIP
S
= 16-pin SOIC
Device:
bq2003 Fast-Charge IC
13
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
Drawing
BQ2003PN
BQ2003PN-N
BQ2003S
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
N
16
16
16
16
16
16
25
25
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NA-NA-NA
N
Level-NA-NA-NA
DW
DW
DW
DW
40
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
BQ2003S-N
BQ2003S-NTR
BQ2003STR
46
2000
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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