BQ2204ASN [TI]
X4 SRAM Nonvolatile Controller Unit; X4非易失SRAM控制器单元
| 型号： | BQ2204ASN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | X4 SRAM Nonvolatile Controller Unit |
| 文件： | 总12页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2204A
X4 SRAM Nonvolatile Controller Unit
During a power failure, the external
General Description
Features
SRAMs are switched from the V
CC
supply to one of two 3V backup sup-
plies. On a subsequent power-up, the
SRAMs are write-protected until a
power-valid condition exists.
The CMOS bq2204A SRAM Non-
volatile Controller Unit provides all
necessary functions for converting
up to four banks of standard CMOS
SRAM into nonvolatile read/write
memory.
Power monitoring and switching
for 3-volt battery-backup applica-
tions
Du r in g power-va lid oper a t ion , a
two-input decoder transparently se-
lect s on e of u p t o fou r ba n ks of
SRAM.
Write-protect control
2-input decoder for control of up
to 4 banks of SRAM
A precision comparator monitors the 5V
V
CC
input for an out-of-tolerance condi-
3-volt primary cell inputs
tion. When out-of-tolerance is detected,
the four conditioned chip-enable outputs
are forced inactive to write-protect up to
four banks of SRAM.
L e s s t h a n 1 0 n s ch ip -e n a b le
propagation delay
5% or 10% supply operation
Pin Connections
Pin Names
VOUT
BC1–BC2
THS
Supply output
3 volt primary backup cell inputs
Threshold select input
V
1
2
3
4
5
6
16
15
14
13
12
11
V
CC
OUT
BC
2
BC
CE
CE
CE
CE
1
CE
chip-enable active low input
Conditioned chip-enable outputs
NC
A
CECON1
CECON4
–
CON1
CON2
CON3
CON4
B
A–B
NC
Decoder inputs
No connect
NC
THS
7
8
10
9
CE
NC
VCC
VSS
+5 volt supply input
Ground
V
SS
16-Pin Narrow DIP or SOIC
PN220401.eps
Functional Description
Up to four banks of CMOS static RAM can be battery-
backed using the V and conditioned chip-enable out-
If THS is tied to V , power-fail detection occurs at
CC
4.37V typical for 10% supply operation. The THS pin
OUT
put pins from the bq2204A. As V
slews down during
must be tied to V or V for proper operation.
CC
SS CC
a power failure, the conditioned chip-enable outputs
CE through CE are forced inactive independ-
ent of the chip-enable input CE.
If a memory access is in process to any of the four external
banks of SRAM during power-fail detection, that memory
cycle continues to completion before the memory is write-
protected. If the memory cycle is not terminated within
CON1
CON4
This activity unconditionally write-protects the external
SRAM as V
falls below an out-of-tolerance threshold
time t
, all four chip-enable outputs are unconditionally
CC
WPT
V
PFD
. V
is selected by the threshold select input pin, driven high, write-protecting the controlled SRAMs.
PFD
THS. If THS is tied to V , the power-fail detection occurs
SS
at 4.62V typical for 5% supply operation.
Dec. 1992 B
1
bq2204A
As the supply continues to fall past V
, an internal
During power-valid operation, the CE input is passed
through to one of the four CE outputs with a propa-
PFD
switching device forces V
to one of the two external
OUT
CON
backup energy sources. CE
through CE
are
gation delay of less than 10ns. The CE input is output
on one of the four CE output pins depending on the
CON1
CON4
held high by the V
energy source.
OUT
CON
level of the decode inputs at A and B as shown in the
Truth Table.
During power-up, V
is switched back to the 5V sup-
OUT
ply as V
rises above the backup cell input voltage
CC
sourcing V
held inactive for time t
power supply has reached V
input, to allow for processor stabilization.
. Outputs CE
through CE are
The A and B inputs are usually tied to high-order ad-
dress pins so that a large nonvolatile memory can be de-
signed using lower-density memory devices. Nonvolatility
and decoding are achieved by hardware hookup as shown
in Figure 1.
OUT
CON1
CON4
(120ms maximum) after the
CER
, independent of the CE
PFD
5V
V
CC
V
OUT
V
CC
V
CC
V
CC
V
CC
bq2204A
CMOS
SRAM
CMOS
SRAM
CMOS
SRAM
CMOS
SRAM
A
B
CE
CE
CON1
CE
CE
CE
CE
From Address
Decoder
CE
BC
CON2
CE
CE
CON3
2
CON4
THS
BC
1
3V
Primary
Cell
3V
Primary
Cell
V
SS
FG220401.eps
Figure 1. Hardware Hookup (5% Supply Operation)
Dec. 1992 B
2
bq2204A
Energy Cell Inputs—BC1, BC2
Two backup energy source inputs are provided on the
bq2204A. The BC and BC inputs accept a 3V primary
1
2
battery (non-rechargeable), typically some type of lith-
ium chemistry. If no primary cell is to be used on either
V
PFD
BC or BC , the unused input should be tied to V
.
1
2
SS
V
falling below V
2
starts the comparison of BC
CC
PFD
1
V
and BC . The BC input comparison continues until V
CC
CC
rises above V
switches to BC only when V
.
Power to V
begins with BC and
SO
2
OUT
1
V
SO
is less than V
mi-
BC1
BC2
nus V
.
The controller alternates to the higher BC
voltage only when the difference between the BC input
voltages is greater than V Alternating the backup
BSO
.
BSO
0.5 V
CC
CE
batteries allows one-at-a-time battery replacement and
efficient use of both backup batteries.
700ns
TD220201.eps
To prevent battery drain when there is no valid data to
retain, V
and CE
are internally isolated from
OUT
CON1-4
BC and BC by either of the following conditions:
1
2
■
■
Initial connection of a battery to BC1 or BC2, or
Presentation of an isolation signal on CE.
A valid isolation signal requires CE low as V
crosses
CC
both V
and V
during a power-down. See Figure 2.
Figure 2. Battery Isolation Signal
PFD
SO
Between these two points in time, CE must be brought
to the point of (0.48 to 0.52) V and held for at least
700ns. The isolation signal is invalid if CE exceeds
CC
*
0.54 V
at any point between V
crossing V
and
CC
CC
PFD
*
V
.
SO
The a ppropria te ba ttery is connected to V
a nd
OUT
CE
immediately on subsequent application and
CON1–4
removal of V
.
CC
Truth Table
Input
Output
CE
H
L
A
X
L
B
X
L
CE
CE
CE
CE
CON4
CON1
CON2
CON3
H
L
H
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
L
H
H
H
H
L
H
H
Dec. 1992 B
3
bq2204A
Absolute Maximum Ratings
Symbol
Parameter
DC voltage applied on V relative to V
SS
Value
Unit
Conditions
V
V
-0.3 to +7.0
V
CC
CC
DC voltage applied on any pin excluding V
CC
-0.3 to +7.0
V
V
≤ V + 0.3
T CC
T
relative to V
SS
0 to 70
-40 to +85
-55 to +125
-40 to +85
260
°C
°C
Commercial
T
Operating temperature
OPR
Industrial “N”
T
T
T
Storage temperature
Temperature under bias
Soldering temperature
°C
STG
°C
BIAS
°C
For 10 seconds
SOLDER
OUT
I
V
OUT
current
200
mA
Note:
Permanent device damage may occur if Absolu te Maxim u m Ratin gs are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-
ditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (T = T
)
OPR
A
Symbol
Parameter
Supply voltage
Minimum Typical Maximum
Unit
V
Notes
4.75
4.50
0
5.0
5.0
0
5.5
THS = V
THS = V
SS
V
CC
5.5
0
V
CC
V
SS
V
IL
V
IH
Supply voltage
V
Input low voltage
Input high voltage
-0.3
2.2
-
0.8
V
-
V
V
+ 0.3
V
CC
V
BC1
V
BC2
,
Backup cell voltage
Threshold select
2.0
-
-
4.0
+ 0.3
V
V
V < V
CC BC
THS
-0.3
CC
Note:
Typical values indicate operation at T = 25°C, V
A
= 5V or V
.
CC
BC
Dec. 1992 B
4
bq2204A
DC Electrical Characteristics (T = T
, V
OPR CC
= 5V ± 10%)
A
Symbol
Parameter
Input leakage current
Output high voltage
Minimum
Typical
Maximum
Unit
µA
V
Conditions/Notes
I
-
-
± 1
V
= V to V
SS CC
LI
IN
V
V
V
2.4
-
-
-
I
= -2.0mA
> V , I
OH
OH
V
OH
, BC supply
V - 0.3
BC
-
-
V
V
BC
= -10µA
CC OH
OHB
OL
Output low voltage
-
0.4
6
V
I
= 4.0mA
OL
I
Operating supply current
-
3
mA
V
No load on outputs.
CC
4.55
4.30
-
4.62
4.37
4.75
4.50
-
THS = V
THS = V
SS
V
V
Power-fail detect voltage
Supply switch-over voltage
PFD
V
CC
V
BC
V
SO
V
data-retention current
OUT
Data-retention mode
current
I
-
-
100
nA
to additional memory not in-
cluded.
CCDR
-
V
V
-
-
V
V
V
BC1
V
BC2
> V
> V
+ V
+ V
BC1
BC2
BC1
BSO
BSO
Active backup cell
voltage
V
V
BC
-
BC2
Battery switch-over voltage
0.25
0.4
-
0.6
160
-
V
BSO
OUT1
OUT2
I
I
V
current
current
-
-
mA
µA
V
V
> V
> V
- 0.3V
- 0.2V
OUT
OUT
OUT
CC
V
100
OUT
BC
Note:
Typical values indicate operation at T = 25°C, V
= 5V or V
.
A
CC
BC
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
CC
A
Symbol
IN
Parameter
Input capacitance
Output capacitance
Minimum
Typical
Maximum
Unit
Conditions
C
C
-
-
-
-
8
pF
pF
Input voltage = 0V
Output voltage = 0V
10
OUT
Note:
This parameter is sampled and not 100% tested.
Dec. 1992 B
5
bq2204A
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
Input pulse levels
Input rise and fall times
5ns
Input and output timing reference levels
1.5V (unless otherwise specified)
5V
960
CE
CON
510
100pF
FG220102.eps
Figure 3. Output Load
Power-Fail Control (T = T
)
OPR
A
Symbol
Parameter
slew, 4.75V to 4.25V
Minimum
Typical
Maximum Unit
Notes
t
V
V
V
300
10
0
-
-
-
-
µs
µs
µs
ns
ns
PF
CC
CC
CC
t
t
t
t
slew, 4.25V to V
SO
FS
slew, 4.25V to 4.75V
-
-
PU
CED
AS
chip-enable propagation delay
A,B set up to CE
-
7
-
10
-
0
Time during which SRAM is
t
t
chip-enable recovery
Write-protect time
40
40
80
120
150
ms write-protected after V
CER
WPT
CC
passes V
on power-up.
PFD
Delay after V
slews down
CC
100
µs
past V
before SRAM is
PFD
write-protected.
Note:
Typical values indicate operation at T = 25°C, V
= 5V.
A
CC
Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e
m a y a ffect d a ta in tegr ity.
Dec. 1992 B
6
bq2204A
Power-Down Timing
t
PF
4.75
V
PFD
t
FS
4.25
V
CC
V
SO
CE
t
WPT
V
OHB
CE
CON
TD220102.eps
Power-Up Timing
t
PU
4.75
V
PFD
V
CC
4.25
V
SO
t
CER
CE
t
t
CED
CED
V
OHB
CE
CON
TD220103.eps
Address-Decode Timing
A,B
CE
t
AS
t
t
CED
CED
CE
CE
CON1
CON4
TD220402.eps
Dec. 1992 B
7
bq2204A
16-Pin DIP Narrow (PN)
(
)
16-Pin PN DIP Narrow
Dimension
Minimum
0.160
0.015
0.015
0.055
0.008
0.740
0.300
0.230
0.300
0.090
0.115
0.020
Maximum
0.180
0.040
0.022
0.065
0.013
0.770
0.325
0.280
0.370
0.110
0.150
0.040
A
A1
B
B1
C
D
E
E1
e
G
L
S
All dimensions are in inches.
Dec. 1992 B
8
bq2204A
16-Pin SOIC Narrow (SN)
(
)
16-Pin SN SOIC Narrow
Dimension
Minimum
0.060
0.004
0.013
0.007
0.385
0.150
0.045
0.225
0.015
Maximum
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
A
A1
B
D
B
e
C
D
E
E
e
H
L
H
All dimensions are in inches.
A
C
A1
.004
L
Dec. 1992 B
9
bq2204A
Data Sheet Revision History
Change No.
Page No.
All
Description of Change
bq2204A replaces bq2204.
Nature of Change
1
1
1, 4–5
10% tolerance requires the THS
pin to be tied to V , not V
.
CC
OUT
1
3
Energy cell input selection pro-
cess alternates between BC and
1
BC .
2
Note:
Change 1 = Dec. 1992 changes from Sept. 1991
Dec. 1992 B
10
bq2204A
Ordering Information
bq2204A
Tem p er a tu r e Ra n ge:
blank = Commercial (0 to 70°C)
N = Industrial (-40 to +85°C)
Pa ck a ge Op tion :
PN = 16-pin narrow plastic DIP
SN = 16-pin narrow SOIC
Device:
bq2204A Nonvolatile SRAM Controller
Dec. 1992 B
11
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