BQ24133 [TI]
1.6-MHz Synchronous Switch-Mode Li-Ion and Li-Polymer Stand-Alone Battery Charger with Integrated MOSFETs and Power Path Selector; 1.6 MHz的同步开关模式锂离子和锂聚合物独立型电池充电器,带有集成MOSFET和功率路径选择型号: | BQ24133 |
厂家: | TEXAS INSTRUMENTS |
描述: | 1.6-MHz Synchronous Switch-Mode Li-Ion and Li-Polymer Stand-Alone Battery Charger with Integrated MOSFETs and Power Path Selector |
文件: | 总35页 (文件大小:2391K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
bq24133
www.ti.com
SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
1.6-MHz Synchronous Switch-Mode Li-Ion and Li-Polymer Stand-Alone Battery Charger
with Integrated MOSFETs and Power Path Selector
Check for Samples: bq24133
1
FEATURES
APPLICATIONS
•
1.6MHz Synchronous Switch-Mode Charger
with 2.5A Integrated N-MOSFETs
Up to 92% Efficiency
30V Input Rating with Adjustable Over-Voltage
Protection
•
•
•
•
•
•
•
Tablet PC
Netbook and Ultra-Mobile Computers
Portable Data Capture Terminals
Portable Printers
Medical Diagnostics Equipment
Battery Bay Chargers
•
•
–
4.5V to 17V Input Operating Voltage
Battery Charge Voltage
1, 2, or 3-Cell with 4.2V/Cell
High Integration
•
•
Battery Back-Up Systems
–
DESCRIPTION
–
Automatic Power Path Selector Between
Adapter and Battery
The bq24133 is highly integrated stand-alone Li-ion
and Li-polymer switch-mode battery charger with two
integrated N-channel power MOSFETs. It offers a
constant-frequency synchronous PWM controller with
high accuracy regulation of input current, charge
current, and voltage. It closely monitors the battery
pack temperature to allow charge only in a preset
temperature window. It also provides battery
detection, pre-conditioning, charge termination, and
charge status monitoring. The thermal regulation loop
reduces charge current to maintain the junction
temperature of 120°C during operation.
–
–
–
–
–
Dynamic Power Management
Integrated 20-V Switching MOSFETs
Integrated Bootstrap Diode
Internal Loop Compensation
Internal Digital Soft Start
•
Safety
–
Thermal Regulation Loop Throttles Back
Current to Limit Tj = 120°C
–
–
Thermal Shutdown
Battery Thermistor Sense Hot/Cold Charge
The bq24133 charges a one, two, or three cell Li-Ion
battery in three phases: precondictioning, constant
current, and constant voltage.
Suspend & Battery Detect
–
–
Input Over-Voltage Protection with
Programmable Threshold
Cycle-by-Cycle Current Limit
Charge is terminated when the current reaches 10%
of the fast charge rate. A programmable charge timer
offers a safety back up. The bq24133 automatically
restarts the charge cycle if the battery voltage falls
below an internal threshold, and enters
low-quiescent current sleep mode when the input
voltage falls below the battery voltage.
•
Accuracy
–
–
–
±0.5% Charge Voltage Regulation
±5% Charge Current Regulation
±6% Input Current Regulation
a
•
•
•
Less than 15μA Battery Current with Adapter
Removed
Less than 1.5mA Input Current with Adapter
Present and Charge Disabled
Small QFN Package
The bq24133 features Dynamic Power Management
(DPM) to reduce the charge current when the input
power limit is reached to avoid over-loading the
adapter. A highly-accurate current-sense amplifier
enables precise measurement of input current from
adapter to monitor overall system power.
–
3.5mm × 5.5mm QFN-24 Pin
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
bq24133
SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The bq24133 provides power path selector gate driver ACDRV/CMSRC on input NMOS pair ACFET (Q1) and
RBFET (Q2), and BATDRV on a battery PMOS device (Q3). When the qualified adapter is present, the system is
directly connected to the adapter. Otherwise, the system is connected to the battery. In addition, the power path
prevents battery from boosting back to the input.
The bq24170/172 charges the battery from a DC source as high as 17V, including a car battery. The input
over-voltage limit is adjustable through the OVPSET pin. The AVCC, ACP, and ACN pins have a 30V rating.
When a high voltage DC source is inserted, Q1/Q2 remain off to avoid high voltage damage to the system.
For 1 cell applications, if the battery is not removable, the system can be directly connected to the battery to
simplify the power path design and lower the cost. With this configuration, the battery can automatically
supplement the system load if the adapter is overloaded.
The bq24133 is available in a 24-pin, 3.5mmx5.5 mm thin QFN package.
RGY PACKAGE
(TOP VIEW)
1
24
2
3
23
22
21
20
19
18
17
16
15
14
PVCC
PVCC
AVCC
ACN
PGND
PGND
BTST
4
5
REGN
BATDRV
OVPSET
ACSET
SRP
6
ACP
7
CMSRC
ACDRV
STAT
TS
AGND
8
9
10
11
SRN
TTC
CELL
12
13
PIN FUNCTIONS
PIN
TYPE
DESCRIPTION
NO.
NAME
SW
1,24
P
Switching node, charge current output inductor connection. Connect the 0.047-µF bootstrap capacitor
from SW to BTST.
2,3
4
PVCC
AVCC
P
P
Charger input voltage. Connect at least 10-µF ceramic capacitor from PVCC to PGND and place it as
close as possible to IC.
IC power positive supply. Place a 1-µF ceramic capacitor from AVCC to AGND and place it as close as
possible to IC. Place a 10-Ω resistor from input side to AVCC pin to filter the noise. For 5V input, a 5-Ω
resistor is recommended.
5
6
7
ACN
I
Adapter current sense resistor negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to
provide differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND
for common-mode filtering.
ACP
P/I
O
Adapter current sense resistor positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to
provide differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for
common-mode filtering.
CMSRC
Connect to common source of N-channel ACFET and reverse blocking MOSFET (RBFET). Place 4-kΩ
resistor from CMSRC pin to the common source of ACFET and RBFET to control the turn-on speed. The
resistance between ACDRV and CMSRC should be 500-kΩ or bigger.
2
Copyright © 2010–2011, Texas Instruments Incorporated
bq24133
www.ti.com
SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
PIN FUNCTIONS (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
8
ACDRV
O
AC adapter to system switch driver output. Connect to 4-kΩ resistor then to the gate of the ACFET
N-channel power MOSFET and the reverse conduction blocking N-channel power MOSFET. Connect
both FETs as common-source. The internal gate drive is asymmetrical, allowing a quick turn-off and
slower turn-on in addition to the internal break-before-make logic with respect to the BATDRV.
9
STAT
O
Open-drain charge status pin with 10-kΩ pull up to power rail. The STAT pin can be used to drive LED or
communicate with the host processor. It indicates various charger operations: LOW when charge in
progress. HIGH when charge is complete or in SLEEP mode. Blinking at 0.5Hz when fault occurs,
including charge suspend, input over-voltage, timer fault and battery absent.
10
11
TS
I
I
Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program
the hot and cold temperature window with a resistor divider from VREF to TS to AGND. The temperature
qualification window can be set to 5-40°C or wider. The 103AT thermistor is recommended.
TTC
Safety Timer and termination control. Connect a capacitor from this node to AGND to set the fast charge
safety timer(5.6min/nF). Pre-charge timer is internally fixed to 30 minutes. Pull the TTC to LOW to disable
the charge termination and safety timer. Pull the TTC to HIGH to disable the safety timer but allow the
charge termination.
12
13
VREF
ISET
P
I
3.3V reference voltage output. Place a 1-μF ceramic capacitor from VREF to AGND pin close to the IC.
This voltage could be used for programming ISET and ACSET and TS pins. It may also serve as the
pull-up rail of STAT pin and CELL pin.
Fast charge current set point. Use a voltage divider from VREF to ISET to AGND to set the fast charge
current:
V
ISET
ICHG
=
20´RSR
The pre-charge and termination current is internally as one tenth of the charge current. The charger is
disabled when ISET pin voltage is below 40mV and enabled when ISET pin voltage is above 120mV.
14
15
CELL
SRN
I
I
Cell selection pin. Set CELL pin LOW for 1-cell, Float for 2-cell (0.8V-1.8V), and HIGH for 3-cell with a
fixed 4.2V per cell.
Charge current sense resistor negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRN pin to AGND for
common-mode filtering.
16
17
SRP
I/P
I
Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to AGND for
common-mode filtering.
ACSET
Input current set point. Use a voltage divider from VREF to ACSET to AGND to set this value:
VACSET
IDPM
=
20´RAC
18
19
OVPSET
BATDRV
I
Valid input voltage set point. Use a voltage divider from input to OVPSET to AGND to set this voltage.
The voltage above internal 1.6V reference indicates input over-voltage, and the voltage below internal
0.5V reference indicates input under-voltage. In either condition, charge terminates, and input NMOS pair
ACFET/RBFET turn off. LED driven by STAT pin keeps blinking, reporting fault condition.
O
Battery discharge MOSFET gate driver output. Connect to 1kohm resistor to the gate of the BATFET
P-channel power MOSFET. Connect the source of the BATFET to the system load voltage node. Connect
the drain of the BATFET to the battery pack positive node. The internal gate drive is asymmetrical to
allow a quick turn-off and slower turn-on, in addition to the internal break-before-make logic with respect
to ACDRV.
20
REGN
P
PWM low side driver positive 6V supply output. Connect a 1-μF ceramic capacitor from REGN to PGND
pin, close to the IC. Generate high-side driver bootstrap voltage by integrated diode from REGN to BTST.
21
BTST
P
P
PWM high side driver positive supply. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
22,23
PGND
Power ground. Ground connection for high-current power converter node. On PCB layout, connect
directly to ground connection of input and output capacitors of the charger. Only connect to AGND
through the Thermal Pad underneath the IC.
Thermal AGND
Pad
P
Exposed pad beneath the IC. Always solder Thermal Pad to the board, and have vias on the Thermal
Pad plane star-connecting to AGND and ground plane for high-current power converter. It dissipates the
heat from the IC.
Copyright © 2010–2011, Texas Instruments Incorporated
3
bq24133
SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
www.ti.com
TYPICAL APPLICATIONS
Q2
Q1
RAC: 20m
System
12V Adapter
C12: 0.1µ
RIN
2
C11: 0.1µ
C4: 10µ
CIN
2.2?
PVCC
ACN
Q3
R14
1k
ACP
R12
4.02k
CMSRC
BATDRV
R11
4.02k
VBAT
ACDRV
VREF
L: 3.3?H
RSR:10m
C2: 1µ
VBAT
VREF
SW
D1
D2
R2
232k
VREF
bq24133
C8
0.1?
C5
0.047?
ISET
R4
100k
R3
32.4k
BTST
C9, C10
10? 10?
R1
10
C7
0.1?
R5
32.4k
ACSET
AVCC
REGN
C6
1?
C1
1µ
R6
1000k
PGND
SRP
OVPSET
C3: 0.1?
R7
100k
VREF
TTC
TS
SRN
R8
5.23k
CELL
Float
R10
1.5k
R9
30.1k
RT
103AT
THERMAL
PAD
STAT
VREF
D3
Figure 1. Typical Application Schematic (12V input, 2 cell battery 8.4V, 2A charge current, 0.2A
pre-charge/termination current, 2A DPM current, 18V input OVP, 0 – 45°C TS)
4
Copyright © 2010–2011, Texas Instruments Incorporated
bq24133
www.ti.com
SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
Q4
RevFET
RAC: 20m
Adapter
Or USB
0.1µ
System
0.1µ
4.7µ
PVCC
BATDRV
SW
ACN
ACP
CMSRC
ACDRV
VREF
RSR: 10m
VBAT
3.3?H
1µ
VREF
VREF
R2
100k
Selectable input
current limit
bq24133
R4
100k
0.1?
0.047?
0.1?
ISET
R3
32.4k
BTST
R5B
8.06k
10?10?
R11
5
R5A
32.4k
D1
Optional
ACSET
REGN
ILIM_500mA
1?
AVCC
R6
845k
C1
1µ
PGND
SRP
OVPSET
R7
100k
VREF
TTC
TS
SRN
R8
6.81k
CELL
R10
1.5k
R9
133k
RT
103AT
THERMAL
PAD
STAT
VREF
D3
Figure 2. Typical Application Schematic wth Single Cell Unremovable Battery (USB or adapter with input
OVP 15V, up to 2A charge current, 0.2A pre-charge current, 2A adapter current or 500mA USB current,
5 – 40°C TS, system connected before sense resistor)
ORDERING INFORMATION(1)
PART NUMBER
PART MARKING
PACKAGE
ORDERING NUMBER
bq24133RGYR
QUANTITY
3000
bq24133
bq24133
24-Pin 3.5mm×5.5mm QFN
bq24133RGYT
250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2010–2011, Texas Instruments Incorporated
5
bq24133
SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)(2)
VALUE
–0.3 to 30
–0.3 to 20
–0.3 to 26
–0.3 to 20
–2 to 20
UNIT
AVCC, ACP, ACN, ACDRV, CMSRC, STAT
PVCC
BTST
BATDRV, SRP, SRN
SW
Voltage range (with respect to AGND)
V
OVPSET, REGN, TS, TTC, CELL
VREF, ISET, ACSET
PGND
–0.3 to 7
–0.3 to 3.6
–0.3 to 0.3
–0.5 to 0.5
–40 to 155
–55 to 155
Maximum difference voltage
Junction temperature range, TJ
Storage temperature range, Tstg
SRP–SRN, ACP-ACN
V
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
THERMAL INFORMATION
bq24133
THERMAL METRIC(1)
RGY
24 PINS
35.7
UNITS
θJA
ψJT
ψJB
Junction-to-ambient thermal resistance(2)
Junction-to-top characterization parameter(3)
Junction-to-board characterization parameter(4)
0.4
°C/W
31.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNIT
Input voltage
VIN
4.5
17
13.5
2.5
V
V
Output voltage
VOUT
Output current (RSR 10mΩ)
IOUT
0.6
–200
–200
–40
A
ACP - ACN
SRP–SRN
200
200
85
mV
mV
°C
Maximum difference voltage
Operation free-air temperature range, TA
6
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Copyright © 2010–2011, Texas Instruments Incorporated
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bq24133
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SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
ELECTRICAL CHARACTERISTICS
4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
OPERATING CONDITIONS
AVCC input voltage operating range during
charging
VAVCC_OP
4.5
17
V
QUIESCENT CURRENTS
V
AVCC > VUVLO, VSRN > VAVCC (SLEEP), TJ = 0°C
15
25
to 85°C
BTST, SW, SRP, SRN, VAVCC > VUVLO, VAVCC
VSRN, ISET < 40mV, VBAT=12.6V, Charge
disabled
>
Battery discharge current (sum of currents
into AVCC, PVCC, ACP, ACN)
IBAT
µA
BTST, SW, SRP, SRN, VAVCC > VUVLO, VAVCC
VSRN, ISET > 120mV, VBAT=12.6V, Charge done
>
25
1.5
5
VAVCC > VUVLO, VAVCC > VSRN, ISET < 40mV,
1.2
2.5
VBAT=12.6V, Charge disabled
Adapter supply current (sum of current into
AVCC,ACP, ACN)
VAVCC > VUVLO, VAVCC > VSRN, ISET > 120mV,
IAC
mA
Charge enabled, no switching
AVCC > VUVLO, VAVCC > VSRN, ISET > 120mV,
V
15(1)
Charge enabled, switching
CHARGE VOLTAGE REGULATION
CELL to AGND, 1 cell, measured on SRN
CELL floating, 2 cells, measured on SRN
CELL to VREF, 3 cells, measured on SRN
TJ = 0°C to 85°C
4.2
8.4
V
V
V
VBAT_REG
SRN regulation voltage
12.6
–0.5%
0.5%
0.7%
Charge voltage regulation accuracy
CURRENT REGULATION – FAST CHARGE
TJ = –40°C to 125°C
-0.7%
VISET
KISET
ISET Voltage Range
RSENSE = 10mΩ
RSENSE = 10mΩ
0.12
0.5
V
Charge Current Set Factor (Amps of Charge
Current per Volt on ISET pin)
5
A/V
VSRP-SRN = 40 mV
VSRP-SRN = 20 mV
VSRP-SRN = 5 mV
ISET falling
-5%
-8%
-25%
40
5%
8%
Charge Current Regulation Accuracy
25%
VISET_CD
VISET_CE
IISET
Charge Disable Threshold
Charge Enable Threshold
Leakage Current into ISET
50
mV
mV
nA
ISET rising
100
120
100
VISET = 2V
INPUT CURRENT REGULATION
Input DPM Current Set Factor (Amps of
KDPM
RSENSE = 20mΩ
2.5
A/V
Input Current per Volt on ACSET)
Input DPM Current Regulation Accuracy
Leakage Current into ACSET pin
VACP-ACN = 80 mV
VACP-ACN = 40 mV
VACP-ACN = 20 mV
VACP-ACN = 5 mV
VACSET = 2V
-6%
-10%
–15%
–20%
6%
10%
15%
20%
100
IACSET
nA
CURRENT REGULATION – PRE-CHARGE
KIPRECHG
Precharge current set factor
Percentage of fast charge current
VSRP-SRN = 4 mV
10%(2)
–25%
–40%
25%
40%
Precharge current regulation accuracy
VSRP-SRN = 2 mV
(1) Specified by design
(2) The minimum current is 120 mA on 10mΩ sense resistor.
Copyright © 2010–2011, Texas Instruments Incorporated
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7
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SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
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ELECTRICAL CHARACTERISTICS (continued)
4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
CHARGE TERMINATION
KTERM
Termination current set factor
Percentage of fast charge current
VSRP-SRN = 4 mV
10%(3)
–25%
–40%
25%
40%
ms
Termination current regulation accuracy
VSRP-SRN = 2 mV
tTERM_DEG
tQUAL
Deglitch time for termination (both edges)
Termination qualification time
100
250
2
V
SRN > VRECH and ICHG < ITERM
ms
IQUAL
Termination qualification current
Discharge current once termination is detected
mA
INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)
VUVLO
AC under-voltage rising threshold
AC under-voltage hysteresis, falling
Measure on AVCC
Measure on AVCC
3.4
50
3.6
3.8
V
VUVLO_HYS
300
mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
SLEEP mode threshold
VAVCC – VSRN falling
VAVCC – VSRN rising
VAVCC – VSRN falling
VAVCC – VSRN falling
90
200
1
150
mV
mV
ms
ms
VSLEEP_HYS
SLEEP mode hysteresis
tSLEEP_FALL_CD
tSLEEP_FALL_FETOFF
SLEEP deglitch to disable charge
SLEEP deglitch to turn off input FETs
5
Deglitch to enter SLEEP mode, disable
VREF and enter low quiescent mode
tSLEEP_FALL
V
AVCC – VSRN falling
AVCC – VSRN rising
100
30
ms
ms
Deglitch to exit SLEEP mode, and enable
VREF
tSLEEP_PWRUP
V
ACN-SRN COMPARATOR
VACN-SRN
Threshold to turn on BATFET
VACN-SRN falling
VACN-SRN rising
VACN-SRN falling
VACN-SRN rising
150
220
100
2
300
mV
mV
ms
µs
VACN-SRN_HYS
tBATFETOFF_DEG
tBATFETON_DEG
Hysteresis to turn off BATFET
Deglitch to turn on BATFET
Deglitch to turn off BATFET
50
BAT LOWV COMPARATOR
CELL to AGND, 1 cell, measure on SRN
CELL floating, 2 cells, measure on SRN
CELL to VREF, 3 cells, measure on SRN
CELL to AGND, 1 cell, measure on SRN
CELL floating, 2 cells, measure on SRN
CELL to VREF, 3 cells, measure on SRN
Delay to start fast charge current
2.87
5.74
8.61
2.9
5.8
8.7
200
400
600
25
2.93
5.86
8.79
VLOWV
Precharge to fast charge transition
V
VLOWV_HYS
Fast charge to precharge hysteresis
mV
tpre2fas
tfast2pre
VLOWV rising deglitch
VLOWV falling deglitch
ms
ms
Delay to start precharge current
25
RECHARGE COMPARATOR
CELL to AGND, 1 cell, measure on SRN
CELL floating, 2 cells, measure on SRN
CELL to VREF, 3 cells, measure on SRN
SRN decreasing below VRECHG
70
140
210
100
200
300
10
130
260
390
Recharge Threshold, below regulation
voltage limit, VBAT_REG-VSRN
VRECHG
mV
tRECH_RISE_DEG
tRECH_FALL_DEG
VRECHG rising deglitch
VRECHG falling deglitch
ms
ms
SRN increasing above VRECHG
10
(3) The minimum current is 120 mA on 10mΩ sense resistor.
8
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Product Folder Link(s): bq24133
bq24133
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SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
ELECTRICAL CHARACTERISTICS (continued)
4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
BAT OVER-VOLTAGE COMPARATOR
VOV_RISE
VOV_FALL
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
Over-voltage rising threshold
As percentage of VBAT_REG
104%
102%
Over-voltage falling threshold
As percentage of VSRN
AC Over-Voltage Rising Threshold to turn
off ACFET
VACOV
OVPSET rising
OVPSET falling
OVPSET rising
1.55
1.6
50
1
1.65
V
VACOV_HYS
tACOV_RISE_DEG
AC over-voltage falling hysteresis
mV
µs
AC Over-Voltage Rising Deglitch to turn off
ACFET and Disable Charge
AC Over-Voltage Falling Deglitch to Turn on
ACFET
tACOV_FALL_DEG
OVPSET falling
30
ms
INPUT UNDER-VOLTAGE COMPARATOR (ACUV)
AC Under-Voltage Falling Threshold to turn
off ACFET
VACUV
OVPSET falling
OVPSET rising
OVPSET falling
0.45
0.5
100
1
0.55
V
VACUV_HYS
tACOV_FALL_DEG
AC Under-Voltage Rising Hysteresis
mV
µs
AC Under-Voltage Falling Deglitch to turn
off ACFET and Disable Charge
AC Under-Voltage Rising Deglitch to turn on
ACFET
tACOV_RISE_DEG
OVPSET rising
30
ms
THERMAL REGULATION
TJ_REG Junction Temperature Regulation Accuracy ISET > 120mV, Charging
THERMAL SHUTDOWN COMPARATOR
120
°C
TSHUT
Thermal shutdown rising temperature
Temperature rising
Temperature falling
Temperature rising
Temperature falling
150
20
°C
°C
µs
TSHUT_HYS
Thermal shutdown hysteresis
Thermal shutdown rising deglitch
Thermal shutdown falling deglitch
tSHUT_RISE_DEG
tSHUT_FALL_DEG
100
10
ms
THERMISTOR COMPARATOR
Cold Temperature Threshold, TS pin
Voltage Rising Threshold
Charger suspends charge. As percentage to
VVREF
VLTF
72.5%
0.2%
73.5% 74.5%
0.4% 0.6%
Cold Temperature Hysteresis, TS pin
Voltage Falling
VLTF_HYS
VHTF
As percentage to VVREF
As percentage to VVREF
As percentage to VVREF
Hot Temperature TS pin voltage rising
Threshold
46.6%
44.2%
47.2% 48.8%
Cut-off Temperature TS pin voltage falling
Threshold
VTCO
44.7% 45.2%
Deglitch time for Temperature Out of Range
Detection
V
V
TS > VLTF, or VTS < VTCO, or
TS < VHTF
tTS_CHG_SUS
tTS_CHG_RESUME
20
ms
ms
Deglitch time for Temperature in Valid
Range Detection
VTS < VLTF – VLTF_HYS or VTS >VTCO, or VTS >
400
VHTF
CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
Charge Over-Current Rising Threshold,
VOCP_CHRG
Current as percentage of fast charge current
Measure VSRP-SRN
160%
VSRP>2.2V
VOCP_MIN
VOCP_MAX
HSFET OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
IOCP_HSFET Current limit on HSFET
CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
VUCP Charge under-current falling threshold
Charge Over-Current Limit Min, VSRP<2.2V
45
75
mV
mV
Charge Over-Current Limit Max, VSRP>2.2V Measure VSRP-SRN
Measure on HSFET
6
1
A
Measure on V(SRP-SRN)
5
9
mV
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ELECTRICAL CHARACTERISTICS (continued)
4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
BAT SHORT COMPARATOR
VBATSHT
Battery short falling threshold
Battery short rising hysteresis
Deglitch on both edges
Measure on SRN
2
200
V
VBATSHT_HYS
tBATSHT_DEG
VBATSHT
Measure on SRN
mV
µs
1
Charge Current during BATSHORT
Percentage of fast charge current
10%(4)
VREF REGULATOR
VVREF_REG
IVREF_LIM
VREF regulator voltage
VREF current limit
V
AVCC > VUVLO, No load
3.267
35
3.3
6.0
3.333
90
V
VVREF = 0 V, VAVCC > VUVLO
mA
REGN REGULATOR
VREGN_REG
IREGN_LIM
REGN regulator voltage
REGN current limit
VAVCC > 10 V, ISET > 120 mV
5.7
40
6.3
V
VREGN = 0 V, VAVCC > 10 v, ISET > 120 mV
120
mA
TTC INPUT
tprechrg
Precharge Safety Timer
Fast Charge Timer Range
Fast Charge Timer Accuracy
Timer Multiplier
Precharge time before fault occurs
Tchg=CTTC*KTTC
1620
1
1800
5.6
1980
10
Sec
hr
tfastchrg
-10%
10%
KTTC
min/nF
VTTC_LOW
ITTC
VTTC_OSC_HI
VTTC_OSC_LO
TTC Low Threshold
TTC falling
0.4
55
V
µA
V
TTC Source/Sink Current
TTC oscillator high threshold
TTC oscillator low threshold
45
50
1.5
1
V
BATTERY SWITCH (BATFET) DRIVER
RDS_BAT_OFF BATFET Turn-off Resistance
RDS_BAT_ON
V
AVCC > 5V
AVCC > 5V
100
20
Ω
BATFET Turn-on Resistance
BATFET Drive Voltage
V
kΩ
VBATDRV_REG =VACN - VBATDRV when VAVCC > 5V
and BATFET is on
VBATDRV_REG
tBATFET_DEG
4.2
7
V
BATFET Power-up Delay to turn off
BATFET after adapter is detected
30
ms
AC SWITCH (ACFET) DRIVER
IACFET
ACDRV Charge Pump Current Limit
VACDRV - VCMSRC = 5V
60
6
µA
VACDRV_REG
Gate Drive Voltage on ACFET
VACDRV - VCMSRC when VAVCC > VUVLO
4.2
V
Maximum load between ACDRV and
CMSRC
RACDRV_LOAD
500
kΩ
µs
AC/BAT SWITCH DRIVER TIMING
tDRV_DEAD Driver Dead Time
BATTERY DETECTION
Dead Time when switching between ACFET and
BATFET
10
tWAKE
Wake timer
Max time charge is enabled
RSENSE = 10 mΩ
500
125
1
ms
mA
sec
mA
mA
IWAKE
Wake current
50
200
tDISCHARGE
IDISCHARGE
IFAULT
Discharge timer
Max time discharge current is applied
Discharge current
8
Fault current after a timeout fault
2
Wake threshold with respect to VREG To
detect battery absent during WAKE
VWAKE
VDISCH
Measure on SRN
Measure on SRN
100
2.9
mV/cell
V/cell
Discharge Threshold to detect battery
absent during discharge
(4) The minimum current is 120 mA on 10mΩ sense resistor.
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ELECTRICAL CHARACTERISTICS (continued)
4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
INTERNAL PWM
fsw
PWM Switching Frequency
Driver Dead Time(5)
1360
1600
30
1840
kHz
ns
Dead time when switching between LSFET and
HSFET no load
tSW_DEAD
RDS_HI
RDS_LO
High Side MOSFET On Resistance
Low Side MOSFET On Resistance
VBTST – VSW = 4.5 V
80
95
150
160
mΩ
mΩ
V
BTST – VSW when low side refresh pulse is
3
4
requested, VAVCC=4.5V
Bootstrap Refresh Comparator Threshold
Voltage
VBTST_REFRESH
V
VBTST – VSW when low side refresh pulse is
requested, VAVCC>6V
INTERNAL SOFT START (8 steps to regulation current ICHG)
SS_STEP
TSS_STEP
Soft start steps
8
step
ms
Soft start step time
1.6
3
CHARGER SECTION POWER-UP SEQUENCING
Delay from ISET above 120mV to start
tCE_DELAY
1.5
s
charging battery
INTEGRATED BTST DIODE
VF
VR
Forward Bias Voltage
Reverse breakdown voltage
IF=120mA at 25°C
IR=2uA at 25°C
0.85
V
V
20
LOGIC IO PIN CHARACTERISTICS
VOUT_LO
VCELL_LO
VCELL_MID
VCELL_HI
STAT Output Low Saturation Voltage
Sink Current = 5 mA
0.5
0.5
1.8
V
V
V
V
CELL pin input low threshold, 1 cell
CELL pin input mid threshold, 2 cells
CELL pin input high threshold, 3 cells
CELL pin voltage falling edge
CELL pin voltage rising for MIN, falling for MAX
CELL pin voltage rising edge
0.8
2.5
(5) Specified by design
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs(1)
FIGURE
DESCRIPTION
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
AVCC, VREF, ACDRV and STAT Power Up (ISET=0)
Charge Enable by ISET
Current Soft Start
Charge Disable by ISET
Continuous Conduction Mode Switching
Discontinuous Conduction Mode Switching
BATFET to ACFET Transition during Power Up
System Load Transient (Input Current DPM)
Battery Insertion and Removal
Battery to Ground Short Protection
Battery to Ground Short Transition
Efficiency vs Output Current (VOUT = 3.8 V)
Efficiency vs Output Current (2-3 cell)
(1) All waveforms and data are measured on HPA715 EVM.
ISET
500mV/div
AVCC
10V/div
REGN
5V/div
VREF
2V/div
STAT
10V/div
ACDRV
5V/div
IL
STAT
1A/div
10V/div
20 ms/div
400 ms/div
Figure 3. Power Up (ISET = 0)
Figure 4. Charge Enable by ISET
ISET
500mV/div
PH
5V/div
PH
5V/div
IL
IOUT
2A/div
0.5A/div
4 ms/div
2 ms/div
Figure 5. Current Soft Start
Figure 6. Charge Disable by ISET
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PH
PH
5V/div
5V/div
IL
1A/div
IL
1A/div
200 ns/div
200 ns/div
Figure 7. Continuous Conduction Mode Switching
Figure 8. Discontinuous Conduction Mode Switching
AVCC
10V/div
ACDRV
10V/div
IIN
1A/div
ISYS
2A/div
VSYS
10V/div
BATDRV
10V/div
IOUT
1A/div
10 ms/div
Figure 9. BATFET to ACFET Transition During Powerup
200 ms/div
Figure 10. System Load Transient (Input current DPM)
SRN
SRN
5V/div
5V/div
PH
10V/div
PH
10V/div
IL
IL
1A/div
1A/div
2 ms/div
400 ms/div
Figure 11. Battery Insertion and Removal
Figure 12. Battery to Ground Short Protection
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EFFICIENCY
vs
OUTPUT CURRENT
95
90
85
80
V
= 3.8 V
OUT
AVCC = 5 V
SRN
5V/div
AVCC = 9 V
PH
10V/div
IL
1A/div
75
70
4 ms/div
0
0.5
1
1.5
2
2.5
I
- Output Current - A
OUT
Figure 13. Battery to Ground Short Transition
Figure 14.
EFFICIENCY
vs
OUTPUT CURRENT
95
90
85
80
AVCC = 12 V, 2 cell
AVCC = 15 V, 3 cell
AVCC = 15 V, 2 cell
75
70
0
0.5
1
1.5
2
2.5
3
I
- Output Current - A
OUT
Figure 15.
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SLUSAF7B –DECEMBER 2010–REVISED MAY 2011
FUNCTIONAL BLOCK DIAGRAM
CMSRC+6V
ACDRV
CHARGE PUMP
SLEEP
VSRN+100mV
ACN-SRN
bq24133
SYSTEM
VACN
ACDRV
CMSRC
8
7
POWER
UVLO
SELECTOR
3.6V
ACOV
ACUV
CONTROL
UVLO
ACN
4
AVCC
19
BATDRV
VSRN+90mV
ACN-6V
SLEEP
1.35V
2.05V
LOWV
VREF
LDO
12
VREF
RCHRG
Thermal PAD
AVCC
CE
REGN
LDO
20
BAT_OVP
REGN
2.184V
21 BTST
EAI
FBO
SRN
2
3
PVCC
PVCC
CELL 14
1V
LEVEL
SHIFTER
2.1V
1
SW
24 SW
IC TJ
120C
PWM
CONTROL
REGN
20μA
PWM
EAO
6
5
ACP
ACN
20xIAC
22
PGND
20X
23 PGND
5mV
UCP
17
ACSET
CE
VSRP-VSRN
OCP
VSRP-VSRN
120mV
160%xVISET/20
REFRESH
13
ISET
IBAT_REG
VSW+4.2V
VBTST
Fast-Chrg
Pre-Chrg
Selection
20μA
LOWV
EN_CHARGE
STAT
9
CE
RCHRG
Charge
16
15
SRP
SRN
20xICHG
20X
Discharge
Termination
10%xVISET
Termination
Qualification
VREF
STATE
MACHINE
2V
VSRN
Discharge
IDISCHARGE
Termination
Qualification
Fault
LTF
BAT_SHORT
IQUAL
IFAULT
SUSPEND
HTF
TCO
Fast Charge Timer
(TTC)
Timer Fault
TTC 11
TS
10
Precharge Timer
(30 mins)
ACOV
ACUV
OVPSET 18
ACOV
ACUV
1.6V
0.5V
SLEEP
UVLO
IC TJ
TSHUT
TSHUT
Figure 16. Functional Block Diagram
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DETAILED DESCRIPTION
Precharge
Current
Fastcharge Current
Regulation Phase
Fastcharge Voltage
Regulation Phase
Termination
Regulation
Phase
Regulation Voltage
VRECH
ICHRG
Charge
Current
Charge
Voltage
VLOWV
10% ICHRG
Precharge
Timer
Fast Charge Safety Timer
Figure 17. Typical Charging Profile
BATTERY VOLTAGE REGULATION
The bq24133 offers a high accuracy voltage regulator on for the charging voltage. The bq24133 uses CELL pin
to select number of cells with a fixed 4.2V/cell. Connecting CELL to AGND sets 1 cell output, floating CELL pin
sets 2 cell output, and connecting to VREF sets 3 cell output.
Table 2. bq24133 CELL Pin Settings
CELL PIN
AGND
VOLTAGE REGULATION
4.2V
8.4 V
12.6 V
Floating
VREF
BATTERY CURRENT REGULATION
The ISET input sets the maximum charging current. Battery current is sensed by current sensing resistor RSR
connected between SRP and SRN. The equation for charge current is:
V
ISET
ICHARGE
=
20 ´ RSR
(1)
The valid input voltage range of ISET is up to 0.5V. With 10mΩ sense resistor, the maximum output current is
2.5A.
The charger is disabled when ISET pin voltage is below 40mV and is enabled when ISET pin voltage is above
120mV. For 10mΩ current sensing resistor, the minimum fast charge current must be higher than 600mA.
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Under high ambient temperature, the charge current will fold back to keep IC temperature not exceeding 120°C.
BATTERY PRECHARGE CURRENT REGULATION
On Power-up, if the battery voltage is below the VLOWV threshold, the bq24133 applies the pre-charge current to
the battery. This pre-charge feature is intended to revive deeply discharged cells. If the VLOWV threshold is not
reached within 30 minutes of initiating pre-charge, the charger turns off and a fault is indicated on the status pin.
For bq24133, the pre-charge current is set as 10% of the fast charge rate set by ISET voltage.
V
ISET
IPRECHARGE
=
200 ´ RSR
(2)
INPUT CURRENT REGULATION
The total input current from an AC adapter or other DC sources is a function of the system supply current and
the battery charging current. System current normally fluctuated as portions of the systems are powered up or
down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system
current and the maximum available charger input current simultaneously. By using DPM, the input current
regulator reduces the charging current when the summation of system power and charge power exceeds the
maximum input power. Therefore, the current capability of the AC adapter can be lowered, reducing system cost.
Input current is set by the voltage on ACSET pin using the following equation:
VACSET
IDPM
=
20 ´ RAC
(3)
The ACP and ACN pins are used to sense across RAC with default value of 20mΩ. However, resistors of other
values can also be used. A larger sense resistor will give a larger sense voltage and higher regulation accuracy,
at the expense of higher conduction loss.
CHARGE TERMINATION, RECHARGE, AND SAFETY TIMERS
The charger monitors the charging current during the voltage regulation phase. Termination is detected when the
SRN voltage is higher than recharge threshold and the charge current is less than the termination current
threshold, as calculated below:
V
ISET
ITERM
=
200 ´ RSR
(4)
where VISET is the voltage on the ISET pin and RSR is the sense resistor. There is a 25ms deglitch time during
transition between fast-charge and pre-charge.
As a safety backup, the charger also provides an internal fixed 30 minutes pre-charge safety timer and a
programmable fast charge timer. The fast charge time is programmed by the capacitor connected between the
TTC pin and AGND, and is given by the formula:
tTTC = CTTC ´KTTC
(5)
Where CTTC is the capacitor connected to TTC and KTTC is the constant multiplier.
A new charge cycle is initiated when one of the following conditions occurs:
•
•
•
The battery voltage falls below the recharge threshold
A power-on-reset (POR) event occurs
ISET pin toggled below 40mV (disable charge) and above 120mV (enable charge)
Pull TTC pin to AGND to disable both termination and fast charge safety timer (reset timer). Pull TTC pin to
VREF to disable the safety timer, but allow charge termination.
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POWER UP
The charge uses a SLEEP comparator to determine the source of power on the AVCC pin, since AVCC can be
supplied either from the battery or the adapter. With the adapter source present, if the AVCC voltage is greater
than the SRN voltage, the charger exits SLEEP mode. If all conditions are met for charging, the charger then
starts charge the battery (see the Enabling and Disabling Charging section). If SRN voltage is greater than
AVCC, the charger enters low quiescent current SLEEP mode to minimize current drain from the battery. During
SLEEP mode, the VREF output turns off and the STAT pin goes to high impedance.
If AVCC is below the UVLO threshold, the device is disabled.
INPUT UNDER-VOLTAGE LOCK-OUT (UVLO)
The system must have a minimum AVCC voltage to allow proper operation. This AVCC voltage could come from
either input adapter or battery, since a conduction path exists from the battery to AVCC through the high side
NMOS body diode. When AVCC is below the UVLO threshold, all circuits on the IC are disabled.
INPUT OVER-VOLTAGE/UNDER-VOLTAGE PROTECTION
ACOV provides protection to prevent system damage due to high input voltage. In bq24133, once the voltage on
OVPSET is above the 1.6V ACOV threshold or below the 0.5V ACUV threshold, charge is disabled and input
MOSFETs turn off. The bq24133 provides flexibility to set the input qualification threshold.
ENABLE AND DISABLE CHARGING
The following conditions have to be valid before charging is enabled:
•
•
•
•
•
•
•
•
•
ISET pin above 120mV
Device is not in Under-Voltage-Lock-Out (UVLO) mode (i.e. VAVCC > VUVLO
Device is not in SLEEP mode (i.e. VAVCC > VSRN
OVPSET voltage is between 0.5V and 1.6V to qualify the adapter
1.5s delay is complete after initial power-up
REGN LDO and VREF LDO voltages are at correct levels
Thermal Shut down (TSHUT) is not valid
TS fault is not detected
)
)
ACFET turns on (See System Power Selector for details)
One of the following conditions stops on-going charging:
•
•
•
•
•
•
•
•
•
ISET pin voltage is below 40mV
Device is in UVLO mode
Adapter is removed, causing the device to enter SLEEP mode
OVPSET voltage indicates the adapter is not valid
REGN or VREF LDO voltage is overloaded
TSHUT temperature threshold is reached
TS voltage goes out of range indicating the battery temperature is too hot or too cold
ACFET turns off
TTC timer expires or pre-charge timer expires
SYSTEM POWER SELECTOR
The IC automatically switches adapter or battery power to the system load. The battery is connected to the
system by default during power up or during SLEEP mode. When the adapter plugs in and the voltage is above
the battery voltage, the IC exits SLEEP mode. The battery is disconnected from the system and the adapter is
connected to the system after exiting SLEEP. An automatic break-before-make logic prevents shoot-through
currents when the selectors switch.
The ACDRV is used to drive a pair of back-to-back n-channel power MOSFETs between adapter and ACP with
sources connected together to CMSRC. The n-channel FET with the drain connected to the ACP (Q2, RBFET)
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provides reverse battery discharge protection, and minimizes system power dissipation with its low-RDSON. The
other n-channel FET with drain connected to adapter input (Q1, ACFET) separates battery from adapter, and
provides a limited dI/dt when connecting the adapter to the system by controlling the FET turn-on time. The
/BATDRV controls a p-channel power MOSFET (Q3, BATFET) placed between battery and system with drain
connected to battery.
Before the adapter is detected, the ACDRV is pulled to CMSRC to keep ACFET off, disconnecting the adapter
from system. /BATDRV stays at ACN-6V (clamp to ground) to connect battery to system if all the following
conditions are valid:
•
•
V
V
AVCC > VUVLO (battery supplies AVCC)
ACN < VSRN + 200 mV
After the device comes out of SLEEP mode, the system begins to switch from battery to adapter. The AVCC
voltage has to be 300mV above SRN to enable the transition. The break-before-make logic keeps both ACFET
and BATFET off for 10us before ACFET turns on. This prevents shoot-through current or any large discharging
current from going into the battery. The /BATDRV is pulled up to ACN and the ACDRV pin is set to CMSRC + 6V
by an internal charge pump to turn on n-channel ACFET, connecting the adapter to the system if all the following
conditions are valid:
•
•
V
V
ACUV < VOVPSET < VACOV
AVCC > VSRN + 300 mV
When the adapter is removed, the IC turns off ACFET and enters SLEEP mode.
BATFET keeps off until the system drops close to SRN. The BATDRV pin is driven to ACN - 6V by an internal
regulator to turn on p-channel BATFET, connecting the battery to the system.
Asymmetrical gate drive provides fast turn-off and slow turn-on of the ACFET and BATFET to help the
break-before-make logic and to allow a soft-start at turn–on of both MOSFETs. The delay time can be further
increased, by putting a capacitor from gate to source of the power MOSFETs.
CONVERTER OPERATION
The bq24133 employs a 1.6MHz constant-frequency step-down switching regulator. The fixed frequency
oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,
charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region.
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal
saw-tooth ramp is compared to the internal error control signal to vary the duty-cycle of the converter. The ramp
height is proportional to the AVCC voltage to cancel out any loop gain variation due to a change in input voltage,
and simplifies the loop compensation. Internal gate drive logic allows achieving 97% duty-cycle before pulse
skipping starts.
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts around 1.6ms, for a typical rise time of 12.8ms. No external components are needed for this
function.
CHARGE OVER-CURRENT PROTECTION
The charger monitors top side MOSFET current by high side sense FET. When peak current exceeds MOSFET
limit, it will turn off the top side MOSFET and keep it off until the next cycle. The charger has a secondary
cycle-to-cycle over-current protection. It monitors the charge current, and prevents the current from exceeding
160% of the programmed charge current. The high-side gate drive turns off when either over-current condition is
detected, and automatically resumes when the current falls below the over-current threshold.
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CHARGE UNDER-CURRENT PROTECTION
After the recharge, if the SRP-SRN voltage decreases below 5mV, the low side FET will be turned off for the rest
of the switching cycle. During discontinuous conduction mode (DCM), the low side FET will only turn on for a
short period of time when the boostrap capacitor voltage drops below 4V to provide refresh charge for the
capacitor. This is important to prevent negative inductor current from causing any boost effect in which the input
voltage increases as power is transferred from the battery to the input capacitors. This can lead to an
over-voltage on the AVCC node and potentially cause damage to the system.
BATTERY DETECTION
For applications with removable battery packs, IC provides a battery absent detection scheme to reliably detect
insertion or removal of battery packs. The battery detection routine runs on power up, or if battery voltage falls
below recharge threshold voltage due to removing a battery or discharging a battery.
POR or RECHARGE
Apply 8mA discharge
current, start 1s timer
1s timer
expired
No
VSRN < VBATOWV
No
Yes
Yes
Battery Present,
Begin Charge
Disable 8mA
discharge current
Enable 125mA charge
current, start 0.5s timer
0.5s timer
expired
No
> V
No
VSRN
RECH
Yes
Yes
Battery Present,
Begin Charge
Disable 125mA
charge current
Battery Absent
Figure 18. Battery Detection Flowchart
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Once the device has powered up, a 8-mA discharge current is applied to the SRN terminal. If the battery voltage
falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on
at low charge current (125mA). If the battery voltage gets up above the recharge threshold within 500ms, there is
no battery present and the cycle restarts. If either the 500ms or 1 second timer time out before the respective
thresholds are hit, a battery is detected and a charge cycle is initiated.
Battery
Absent
Battery
Absent
VBAT_RE
VRECH
Battery
Present
VLOW
Figure 19. Battery Detect Timing Diagram
Care must be taken that the total output capacitance at the battery node is not so large that the discharge current
source cannot pull the voltage below the LOWV threshold during the 1 second discharge time. The maximum
output capacitances can be calculated according to the following equations:
IDISCH ´ tDISCH
CMAX
=
(4.1 V - 2.9 V) ´ Number of cells
(6)
Where CMAX is the maximum output capacitance, IDISCH is the discharge current, tDISCH is the discharge time.
Example
For a 3-cell Li+ charger, IDISCH = 8mA, tDISCH = 1 second.
8 mA ´ 1 sec
CMAX
=
= 2.2 mF
1.2 V ´ 3
(7)
Based on these calculations, no more than 2200 µF should be allowed on the battery node for proper operation
of the battery detection circuit.
BATTERY SHORT PROTECTION
When SRN pin voltage is lower than 2V it is considered as battery short condition during charging period. The
charger will shut down immediately for 1ms, then soft start back to the charging current the same as precharge
current. This prevents high current may build in output inductor and cause inductor saturation when battery
terminal is shorted during charging. The converter works in non-synchronous mode during battery short.
BATTERY OVER-VOLTAGE PROTECTION
The converter will not allow the high-side FET to turn-on until the battery voltage goes below 102% of the
regulation voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load
is removed or the battery is disconnected. A total 6mA current sink from SRP/SRN to AGND allows discharging
the stored output inductor energy that is transferred to the output capacitors. If battery over-voltage condition
lasts for more than 30ms, charge is disabled.
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TEMPERATURE QUALIFICATION
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
AGND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. If battery
temperature is outside of this range, the controller suspends charge and waits until the battery temperature is
within the VLTF to VHTF range. During the charge cycle the battery temperature must be within the VLTF to VTCO
thresholds. If battery temperature is outside of this range, the controller suspends charge and waits until the
battery temperature is within the VLTF to VHTF range. The controller suspends charge by turning off the PWM
charge MOSFETs. Figure 20 summarizes the operation.
TEMPERATURE RANGE
TO INITIATE CHARGE
TEMPERATURE RANGE
DURING A CHARGE CYCLE
VREF
VREF
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTF
VLTFH
VLTFH
CHARGE at full C
CHARGE at full C
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
AGND
AGND
Figure 20. TS Pin, Thermistor Sense Thresholds
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 21, the values of RT1 and RT2 can
be determined by using Equation 8 and Equation 9:
æ
ç
è
ö
÷
ø
1
1
VVREF ´ RTHCOLD ´ RTHHOT
´
-
VLTF VTCO
RT2 =
æ
ç
è
ö
æ
ç
è
ö
VVREF
VVREF
RTHHOT
´
-1 -RTH
´
-1
÷
÷
COLD
VTCO
VLTF
ø
ø
(8)
(9)
VVREF
-1
VLTF
+
RT1 =
1
1
RT2
RTHCOLD
Select 0°C to 45°C range for Li-ion or Li-polymer battery,
RTHCOLD = 27.28 kΩ
RTHHOT = 4.911 kΩ
RT1 = 5.23 kΩ
RT2 = 30.1 kΩ
After select closest standard resistor value, by calculating the thermistor resistance at temperature threshold, the
final temperature range can be gotten from thermistor datasheet temperature-resistance table.
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VREF
RT1
RT2
bq24133
TS
RTH
103AT
Figure 21. TS Resistor Network
MOSFET SHORT CIRCUIT AND INDUCTOR SHORT CIRCUIT PROTECTION
The IC has a short circuit protection feature. Its cycle-by-cycle current monitoring feature is achieved through
monitoring the voltage drop across Rdson of the MOSFETs. The charger will be latched off, but the ACFET keep
on to power the system. The only way to reset the charger from latch-off status is remove adapter then plug
adapter in again. Meanwhile, STAT is blinking to report the fault condition.
THERMAL REGULATION AND SHUTDOWN PROTECTION
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. The internal thermal regulation loop will fold back the charge
current to keep the junction temperature from exceeding 120°C. As added level of protection, the charger
converter turns off and self-protects whenever the junction temperature exceeds the TSHUT threshold of 150°C.
The charger stays off until the junction temperature falls below 130°C.
TIMER FAULT RECOVERY
The IC provides a recovery method to deal with timer fault conditions. The following summarizes this method:
Condition 1: The battery voltage is above the recharge threshold and a timeout fault occurs.
Recovery Method: The timer fault will clear when the battery voltage falls below the recharge threshold, and
battery detection will begin. A POR or taking ISET below 40mV will also clear the fault.
Condition 2: The battery voltage is below the recharge threshold and a timeout fault occurs.
Recovery Method: Under this scenario, the IC applies the fault current to the battery. This small current is used
to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge
threshold. If the battery voltage goes above the recharge threshold, the IC disabled the fault current and
executes the recovery method described in Condition 1. A POR or taking ISET below 40mV will also clear the
fault.
INDUCTOR, CAPACITOR, AND SENSE RESISTOR SELECTION GUIDELINES
The IC provides internal loop compensation. With this scheme, the best stability occurs when the LC resonant
frequency, fo, is approximately 15kHz – 25kHz for the IC.
1
fo
=
2p LC
(10)
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Table 3 provides a summary of typical LC components for various charge currents.
Table 3. Typical Values as a Function of Charge Current
CHARGE CURRENT
1A
2A
3.3 µH
20 µF
Output inductor L
Output capacitor C
6.8 µH
10 µF
CHARGE STATUS OUTPUTS
The open-drain STAT outputs indicate various charger operations as listed in Table 4. These status pins can be
used to drive LEDs or communicate with the host processor. Note that OFF indicates that the open-drain
transistor is turned off.
Table 4. STAT Pin Definition
CHARGE STATE
STAT
ON
Charge in progress (including recharging)
Charge complete, Sleep mode, Charge disabled
OFF
Charge suspend, Input over-voltage, Battery over-voltage, timer fault, , battery absent
BLINK
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APPLICATION INFORMATION
INDUCTOR SELECTION
The bq24133 has a 1600-kHz switching frequency to allow the use of small inductor and capacitor values.
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG+(1/2)IRIPPLE
(11)
Inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs), and
inductance (L):
V
IN ´D´(1- D)
IRIPPLE
=
fs × L
(12)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of 20% to 40% of the maximum charging current as a trade-off between inductor size and efficiency for
a practical design.
INPUT CAPACITOR
The input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst
case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate
at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50%
and can be estimated by the following equation:
ICIN = ICHG ´ D´(1- D)
(13)
A low ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be
placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25V rating or higher
capacitor is preferred for a 15V input voltage. A 20μF capacitance is suggested for a typical 2.5A charging
current.
OUTPUT CAPACITOR
The output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given as:
IRIPPLE
ICOUT
=
» 0.29´IRIPPLE
2 ´
3
(14)
The output capacitor voltage ripple can be calculated as follows:
æ
ö
÷
÷
ø
VOUT
VOUT
DVO
=
ç1-
8LCfs2
ç
è
V
IN
(15)
At certain input/output voltages and switching frequencies, the voltage ripple can be reduced by increasing the
output filter LC.
The bq24133 has an internal loop compensator. To achieve good loop stability, the resonant frequency of the
output inductor and output capacitor should be designed between 15 kHz and 25 kHz. The preferred ceramic
capacitor has a 25V or higher rating, X7R or X5R.
INPUT FILTER DESIGN
During adapter hot plug-in, the parasitic inductance and the input capacitor from the adapter cable form a second
order system. The voltage spike at the AVCC pin may be beyond the IC maximum voltage rating and damage
the IC. The input filter must be carefully designed and tested to prevent an over-voltage event on the AVCC pin.
There are several methods to damping or limiting the over-voltage spike during adapter hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the over-voltage spike well below the IC
maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over-voltage level to an
IC safe level. However, these two solutions may not be lowest cost or smallest size.
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A cost effective and small size solution is shown in Figure 22. R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result, the over-voltage spike is limited to a safe level. D1 is
used for reverse voltage protection for the AVCC pin. C2 is the AVCC pin decoupling capacitor and it should be
placed as close as possible to the AVCC pin. R2 and C2 form a damping RC network to further protect the IC
from high dv/dt and high voltage spike. The C2 value should be less than the C1 value so R1 can dominant the
equivalent ESR value to get enough damping effect for hot plug-in. R1 and R2 must be sized enough to handle
in-rush current power loss according to the resistor manufacturer’s datasheet. The filter component values
always need to be verified with a real application and minor adjustments may be needed to fit in the real
application circuit.
If the input is 5V (USB host or USB adapter), then D1 can be saved. R2 has to be 5Ω or higher to limit the
current if the input is reversely inserted.
D1
R2(1206)
R1(2010)
2W
4.7 - 30 W
Adapter
Connector
AVCC pin
C1
2.2 mF
C2
0.1 - 1 mF
Figure 22. Input Filter
INPUT ACFET AND RBFET SELECTION
N-type MOSFETs are used as input ACFET(Q1) and RBFET(Q2) for better cost effective and small size solution,
as shown in Figure 22. Normally, there are around 50uF capacitor totally connected at PVCC node --- 10uF
capacitor for buck converter of bq24133 and 40uF capacitor for system side. There is a surge current during Q1
turn-on period when a valid adapter is inserted. Decreasing the turn-on speed of Q1 can limit this surge current
in desirable range by selecting a MOSFET with relative bigger CGD and/or CGS. At the case Q1 turn on too fast,
we need add external CGD and/or CGS. For example, 4.7nF CGD and 47nF CGS are adopted on EVM while using
NexFET CSD17313 as Q1.
Q2
Q1
ADAPTER
SYS
RSNS
C4
1m
SYS
C
40
R
IN
?
2
RGS
499k
CGS
C
IN
CGD
PVCC
CMSRC
ACDRV
?
2.2
R12
4.02k
R11
4.02k
Figure 23. Input ACFET and RBFET
PCB LAYOUT
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high frequency current path loop (see Figure 24) is important to prevent electrical
and magnetic field radiation and high frequency resonant problems. The following is a PCB layout priority list for
proper layout. Layout of the PCB according to this specific order is essential.
1. Place input capacitor as close as possible to the PVCC supply and ground connections and use the shortest
copper trace connection. These parts should be placed on the same layer of the PCB instead of on different
layers and using vias to make this connection.
2. Place the inductor input terminal as close as possible to the SW terminal. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging
current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this
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area to any other trace or plane.
3. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize
loop area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection
for best current accuracy). Place decoupling capacitor on these traces next to the IC.
4. Place output capacitor next to the sensing resistor output and ground.
5. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
6. Route analog ground separately from power ground and use a single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins
to reduce inductive and capacitive noise coupling. Use the thermal pad as a single ground connection point
to connect analog ground and power ground together, or use a 0-Ω resistor to tie analog ground to power
ground. A star-connection under the thermal pad is highly recommended.
7. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
8. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
9. The number and physical size of the vias should be enough for a given current path.
L1
R1
VBAT
SW
High
Frequency
Current
Path
VIN
BAT
C1
C3
C2
PGND
Figure 24. High Frequency Current Path
Current Direction
RSNS
Current Sensing Direction
To SRP and SRN pin
Figure 25. Sensing Resistor PCB Layout
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REVISION HISTORY
Changes from Revision A (March 2011) to Revision B
Page
•
•
•
•
Added 30V Input Rating with Adjustable Over-Voltage Protection ....................................................................................... 1
Added new paragraph to Description (Continued) ............................................................................................................... 2
Changed Voltage range (with respect to AGND) pins in ABSOLUTE MAXIMUM RATINGS table ..................................... 6
Added paragraph at the end of INPUT FILTER DESIGN section ...................................................................................... 26
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Apr-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
BQ24133RGYR
BQ24133RGYT
ACTIVE
ACTIVE
VQFN
VQFN
RGY
RGY
24
24
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24133RGYR
BQ24133RGYT
VQFN
VQFN
RGY
RGY
24
24
3000
250
330.0
180.0
12.4
12.4
3.8
3.8
5.8
5.8
1.2
1.2
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24133RGYR
BQ24133RGYT
VQFN
VQFN
RGY
RGY
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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