BQ24740RHDT [TI]
Host-controlled Multi-chemistry Battery Charger with Low Input Power Detect; 主机控制的多化合物电池充电器具有低输入功率检测
| 型号： | BQ24740RHDT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Host-controlled Multi-chemistry Battery Charger with Low Input Power Detect |
| 文件： | 总32页 (文件大小：1256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24740
www.ti.com
SLUS736–DECEMBER 2006
Host-controlled Multi-chemistry Battery Charger with Low Input Power Detect
FEATURES
APPLICATIONS
•
•
•
•
•
•
Notebook and Ultra-Mobile Computers
Portable Data-Capture Terminals
Portable Printers
Medical Diagnostics Equipment
Battery Bay Chargers
•
•
•
NMOS-NMOS Synchronous Buck Converter
with 300 kHz Frequency and >95% Efficiency
30-ns Minimum Driver Dead-time and 99.5%
Maximum Effective Duty Cycle
High-Accuracy Voltage and Current
Regulation
Battery Back-up Systems
–
–
–
–
±0.5% Charge Voltage Accuracy
±3% Charge Current Accuracy
DESCRIPTION
The bq24740 is
a high-efficiency, synchronous
±3% Adapter Current Accuracy
±2% Input Current Sense Amp Accuracy
battery charger with integrated compensation and
system power selector logic, offering low component
count for space-constrained multi-chemistry battery
charging applications. Ratiometric charge current
and voltage programming allows very high regulation
accuracies, and can be either hardwired with
•
•
Integration
–
–
Internal Loop Compensation
Internal Soft Start
Safety
resistors
or
programmed
by
the
system
–
–
Input Overvoltage Protection (OVP)
power-management microcontroller using a DAC or
GPIOs.
Dynamic Power Management (DPM) with
Status Indicator
The bq24740 charges two, three, or four series Li+
cells, supporting up to 10 A of charge current, and is
available in a 28-pin, 5x5-mm thin QFN package.
–
Reverse-Conduction Protection Input FET
•
•
•
Supports Two, Three, or Four Li+ Cells
5 – 24 V AC/DC-Adapter Operating Range
Analog Inputs with Ratiometric Programming
via Resistors or DAC/GPIO Host Control
–
–
Charge Voltage (4-4.512 V/cell)
28 27 26 25 24 23 22
Charge Current (up to 10 A, with 10-mΩ
sense resistor)
1
2
3
4
5
6
7
21
20
19
18
17
16
15
CHGEN
ACN
DPMDET
CELLS
SRP
–
Adapter Current Limit (DPM)
bq24740
28 LD QFN
TOP VIEW
ACP
•
Status and Monitoring Outputs
LPMD
ACDET
ACSET
LPREF
SRN
–
AC/DC Adapter Present with
Programmable Voltage Threshold
BAT
SRSET
IADAPT
–
Low Input-Power Detect with Adjustable
Threshold and Hysteresis
8
9
10 11 12 13 14
–
–
DPM Loop Active
Current Drawn from Input Source
•
•
Battery Discharge Current Sense with No
Adapter, or Selectable Low-Iq mode
Supports Any Battery Chemistry: Li+, NiCd,
NiMH, Lead Acid, etc.
•
•
•
Charge Enable
10-µA Off-State Current
28-pin, 5x5-mm QFN package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
bq24740
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SLUS736–DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The bq24740 features Dynamic Power Management (DPM) and input power limiting. These features reduce
battery charge current when the input power limit is reached to avoid overloading the AC adapter when
supplying the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables
precise measurement of input current from the AC adapter to monitor the overall system power. If the adapter
current is above the programmed low-power threshold, a signal is sent to host so that the system optimizes its
power performance according to what is available from the adapter.
TYPICAL APPLICATION
C16 C17
10 mF 10 mF
C18
10 mF
SYSTEM
ADAPTER+
ADAPTER-
R
C6 C7
10 mF 10 mF
C1
10 mF
AC
P
P
0.010 W
Q1 (ACFET) Q2 (ACFET)
SI4435 SI4435
Controlled by
HOST
R1
432 kW
1%
C2
0.1 mF
C3
0.1 mF
ACN
ACP
PVCC
C8
1 mF
Q3(BATFET)
SI4435
Controlled by
HOST
ACDET
AGND
P
Q4
FDS6680A
R2
66.5 kW
1%
HIDRV
VREF
R3
N
R
0.010 W
SR
bq24740
PH
L1
10 kW
C9
BTST
PACK+
PACK-
EXTPWR
EXTPWR
C12
10 mF
0.1 mF
8.2 mH
D1
BAT54
C11
10 mF
REGN
C10
1 mF
SRSET
ACSET
VREF
DAC
C13
0.1 mF
C14
Q5
FDS6680A
LODRV
PGND
0.1 mF
N
C4
1 mF
R4
10 kW
R5
10 kW
IADSLP
SRP
HOST
DPMDET
LPMD
SRN
BAT
VREF
C15
0.1 mF
CELLS
R7
200 kW
CHGEN
LPREF
R8
24.9 kW
VDAC
VADJ
DAC
ADC
ISYNSET
R6
33 kW
PowerPad
IADAPT
C5
100 pF
R9 1.8 MW
(1) Pull-up rail could be either VREF or other system rail .
(2) SRSET/ACSET could come from either DAC or resistor dividers
.
VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A
Figure 1. Typical System Schematic, Voltage and Current Programmed by DAC
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SLUS736–DECEMBER 2006
C16 C17
10 mF 10 mF
C18
10 mF
SYSTEM
ADAPTER+
ADAPTER-
R
C6 C7
10 mF 10 mF
C1
10 mF
AC
P
P
0.010 W
Q1 (ACFET) Q2 (ACFET)
SI4435 SI4435
Controlled by
HOST
R1
432 kW
1%
C2
0.1 mF
C3
0.1 mF
ACN
ACP
PVCC
C8
1 mF
Q3(BATFET)
SI4435
Controlled by
ACDET
AGND
HOST
P
Q4
FDS6680A
R2
66.5 kW
1%
HIDRV
VREF
R3
10 kW
N
R
0.010 W
SR
bq24740
PH
L1
C9
BTST
PACK+
PACK-
EXTPWR
EXTPWR
C12
10 mF
0.1 mF
8.2 mH
D1
C10
BAT54
C11
10 mF
REGN
SRSET
R9
42 kW
R10
100 kW
1 mF
R11
66.5 kW
C13
0.1 mF
C14
ACSET
VREF
Q5
FDS6680A
LODRV
PGND
0.1 mF
R12 100 kW
N
HOST
C4
1 mF
R4
10 kW
R5
10 kW
SRP
IADSLP
SRN
BAT
DPMDET
LPMD
GPIO
VREF
C15
0.1 mF
R7
200 kW
CELLS
CHGEN
LPREF
R8
24.9 kW
ISYNSET
VDAC
VADJ
R6
33 kW
IADAPT
PowerPad
ADC
C5
100 pF
R9 1.8 MW
(1) Pull-up rail could be either VREF or other system rail .
(2) SRSET/ACSET could come from either DAC or resistor dividers
.
A. VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A
Figure 2. Typical System Schematic, Voltage and Current Programmed by Resistor
3
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SLUS736–DECEMBER 2006
C17 C18
10 mF 10 mF
C19
10 mF
ADAPTER +
SYSTEM
C1
10 mF
RAC
0.010 W
C7
10mF
C6
10 mF
P
P
ADAPTER -
Q1 (ACFET) Q2 (ACFET)
SI4435 SI4435
Controlled by
HOST
C3
C2
0.1 mF
ACN
ACP
432 kW
1%
PVCC
0.1 mF
R1
C8
1mF
Q3(BATFET)
SI4435
Controlled by
HOST
ACDET
AGND
P
Q4
FDS6680A
HIDRV
66.5 kW
1%
R2
N
VREF
10 kW
RSR
0.010 W
PH
bq24740
R3
L1
C9
BTST
PACK+
PACK-
/EXTPWR
EXTPWR
0.1 mF
8.2 mH
C12
D1
BAT54
10 mF
REGN
C11
10 mF
SRSET
ACSET
VREF
1 mF
C10
DAC
C13
0.1 mF
Q5
FDS6680A
C14
LODRV
PGND
0.1
mF
N
C4 1 mF
R4 10 kWR5 10 kW
IADSLP
SRP
SRN
HOST
DPMDET
LPMD
BAT
VREF
CELLS
CHGEN
VDAC
C15
0.1 mF
R7
200 kW
LPREF
R8
24.9 kW
ISYNSET
DAC
ADC
R6
33 kW
VADJ
IADAPT
PowerPad
C5
100 pF
R9
(1) Pull-up rail could be either VREF or other system rail
1.8 MW
.
(2) SRSET/ACSET could come from either DAC or resistor dividers
.
VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A
Figure 3. Typical System Schematic: Sensing Battery Discharge Current, When Adapter Removed. (Set
IADSLP at logic high)
ORDERING INFORMATION
Part number
Package
Ordering Number
(Tape and Reel)
Quantity
bq24740RHDR
bq24740RHDT
3000
250
bq24740
28-PIN 5 x 5 mm QFN
PACKAGE THERMAL DATA
PACKAGE
QFN – RHD(1)(2)
θJA
TA = 70°C POWER RATING
2.36 W
DERATING FACTOR ABOVE TA = 25°C
0.028 W/°C
39°C/W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
4
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SLUS736–DECEMBER 2006
Table 1. TERMINAL FUNCTIONS – 28-PIN QFN
TERMINAL
DESCRIPTION
NAME
NO.
CHGEN
1
Charge enable active-low logic input. LO enables charge. HI disables charge.
Adapter current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND
for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering.
ACN
2
3
ACP
Adapter current sense resistor, positive input. (See comments with ACN description)
Low power mode detect active-high open-drain logic output. Place a 10-kΩ pullup resistor from LPMD pin to the
pullup-voltage rail. Place a positive-feedback resistor from LPMD pin to LPREF pin for programming hysteresis (see
design example for calculation). The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The
output is LO when IADAPT pin voltage is higher than LPREF pin voltage.
LPMD
4
5
6
7
8
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from
adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The
IADAPT current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. Input overvoltage, ACOV,
disables charge and ACDRV when ACDET > 3.1 V. ACOV does not latch
ACDET
ACSET
LPREF
IADSLP
Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC
to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply
to the VDAC pin.
Low power voltage set input. Connect a resistor divider from VREF to LPREF and AGND to program the reference for
the LOPWR comparator. The LPREF-pin voltage is compared to the IADAPT-pin voltage and the logic output is given
on the LPMD open-drain pin. Connecting a positive-feedback resistor from LPREF pin to LPMD pin programs the
hysteresis.
Enable IADAPT to enter sleep mode; active-low logic input. Allows low Iq sleep mode when adapter not detected.
Logic low turns off the Input Current Sense Amplifier (IADAPT) when adapter is not detected and ACDET pin is <0.6
V - allows lower battery discharge current. Logic high keeps IADAPT current-sense amplifier on when adapter is not
detected and ACDET pin is <0.6 V - this allows measuring battery discharge current.
Analog ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the power
pad underneath the IC.
AGND
VREF
9
3.3-V regulated voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
could be used for ratiometric programming of voltage and current regulation.
10
Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery
voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ,
VDAC
11 SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET pins
to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output
to VADJ, SRSET, or ACSET.
Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage
regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the
output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the
VADJ
12
default of 4.2 V per cell.
Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed
13 threshold, OR input current is greater than 1.25 A with 10-mΩ sense resistor. Connect a 10-kΩ pullup resistor from
EXTPWR pin to pullup supply rail.
EXTPWR
Synchronous mode voltage set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent
14 threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor
current. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).
ISYNSET
IADAPT
SRSET
Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
100-pF or less ceramic decoupling capacitor from IADAPT to AGND.
15
Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current
16 regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the
output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT
17 pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND close to the IC to filter
high-frequency noise.
BAT
SRN
Charge current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from SRN pin to AGND
18 for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering.
SRP
19 Charge current sense resistor, positive input. (See comments for SRN.)
CELLS
20 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.
5
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Table 1. TERMINAL FUNCTIONS – 28-PIN QFN (continued)
TERMINAL
DESCRIPTION
NAME
NO.
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input
DPMDET
21 current is being limited by reducing the charge current. Connect 10-kΩ pullup resistor from DPMDET to VREF or a
different pullup-supply rail.
Power ground. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input
and output capacitors of the charger. Only connect to AGND through the power pad underneath the IC.
PGND
LODRV
REGN
22
23 PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
PWM low side driver positive 6-V supply output. Connect a 1-µF ceramic capacitor from REGN to PGND, close to the
IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.
24
PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFET
PH
25 drain, high-side power MOSFET source, and output inductor). Connect the 0.1-µF bootstrap capacitor from from PH to
BTST.
HIDRV
BTST
26 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
PWM high side driver positive supply. Connect a 0.1-µF bootstrap ceramic capacitor from BTST to PH. Connect a
27
small bootstrap Schottky diode from REGN to BTST.
IC power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET
28 and source of reverse-blocking power P-channel MOSFET. Place a 1-µF ceramic capacitor from PVCC to PGND pin
close to the IC.
PVCC
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)(2)
VALUE
–0.3 to 30
–1 to 30
–0.3 to 7
UNIT
PVCC, ACP, ACN, SRP, SRN, BAT
PH
REGN, LODRV, VADJ, ACSET, SRSET, ACDET, ISYNSET, LPMD,
LPREF, CHGEN, CELLS, EXTPWR, DPMDET
Voltage range
V
VDAC
–0.3 to 5.5
–0.3 to 3.6
–0.3 to 36
–0.5 to 0.5
–40 to 155
–55 to 155
VREF
BTST, HIDRV with respect to AGND and PGND, IADAPT
ACP–ACN, SRP–SRN, AGND–PGND
Maximum difference voltage
Junction temperature range
Storage temperature range
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
6
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
–1
0
NOM
MAX
24
UNIT
PH
PVCC, ACP, ACN, SRP, SRN, BAT
24
REGN, LODRV
VREF
0
6.5
3.3
3.6
5.5
0
VDAC, IADAPT
0
Voltage range
V
ACSET, SRSET, ACDET, ISYNSET, LPMD, LPREF, CHGEN, CELLS,
EXTPWR, DPMDET
0
VADJ
0
0
6.5
30
BTST, HIDRV with respect to AGND and PGND
AGND, PGND
–0.3
0.3
5.5
125
150
Maximum difference voltage: ACP–ACN, SRP–SRN
Junction temperature range
–40
–55
°C
Storage temperature range
PACKAGE THERMAL DATA
PACKAGE
QFN– RHD(1)
θJA
TA = 70°C POWER RATING
DERATING FACTOR ABOVE TA = 25°C
0.028 W/°C
39°C/W
2.36W
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
ELECTRICAL CHARACTERISTICS
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
OPERATING CONDITIONS
VPVCC_OP PVCC Input voltage operating range
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG BAT voltage regulation range
VVDAC_OP
TEST CONDITIONS
MIN
TYP MAX
UNIT
5.0
24.0
V
4V-4.512V per cell, times 2,3,4 cell
8
2.6
18
3.6
V
V
V
VDAC reference voltage range
VADJ voltage range
VADJ_OP
0
REGN
0.5
Charge voltage regulation accuracy
8 V, 8.4 V, 9.024 V
–0.5
–0.5
–0.5
–0.5
12 V, 12.6 V, 13.536 V
16 V, 16.8 V, 18.048 V
0.5
%
%
0.5
Charge voltage regulation set to default to VADJ connected to REGN, 8.4 V,
0.5
4.2 V per cell
CHARGE CURRENT REGULATION
VIREG_CHG Charge current regulation differential
12.6 V, 16.8 V
VIREG_CHG = VSRP– VSRN
0
100
mV
V
voltage range
VSRSET_OP
SRSET voltage range
0
–3
VDAC
VIREG_CHG = 40–100 mV
VIREG_CHG = 20 mV
VIREG_CHG = 5 mV
3
5
–5
Charge current regulation accuracy
%
–25
–33
25
33
VIREG_CHG = 1.5 mV
7
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ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
INPUT CURRENT REGULATION
TEST CONDITIONS
MIN
TYP MAX
UNIT
VIREG_DPM
Adapter current regulation differential
voltage range
VIREG_DPM = VACP– VACN
0
200
mV
V
VACSET_OP
ACSET voltage range
0
–3
2
3
VIREG_DPM = 40–100 mV
VIREG_DPM = 20 mV
VIREG_DPM = 5 mV
–5
5
Input current regulation accuracy
%
–25
–33
25
33
VIREG_DPM = 1.5 mV
VREF REGULATOR
VVREF_REG VREF regulator voltage
IVREF_LIM VREF current limit
REGN REGULATOR
VREGN_REG REGN regulator voltage
VACDET > 0.6 V, 0-30 mA
3.267
35
3.3 3.333
75
V
VVREF = 0 V, VACDET > 0.6 V
mA
VACDET > 0.6 V, 0-75 mA, PVCC > 10
V
5.6
90
5.9
6.2
V
IREGN_LIM
REGN current limit
VREGN = 0 V, VACDET > 0.6 V
135
mA
ADAPTER CURRENT SENSE AMPLIFIER
VACP/N_OP
VIADAPT
IIADAPT
Input common mode range
IADAPT output voltage range
IADAPT output current
Voltage on ACP/SRN
0
0
0
24
2
V
V
1
mA
V/V
AIADAPT
Current sense amplifier voltage gain
AIADAPT = VIADAPT / VIREG_DPM
VIREG_DPM = 40–100 mV
VIREG_DPM = 20 mV
20
–2
–3
2
3
Adapter current sense accuracy
%
VIREG_DPM = 5 mV
–25
–30
1
25
30
VIREG_DPM = 1.5 mV
IIADAPT_LIM
Output current limit
VIADAPT = 0 V
mA
pF
CIADAPT_MAX
Maximum output load capacitance
For stability with 0 mA to 1 mA load
100
24
ACDET COMPARATOR
VPVCC-BAT_OP Differential Voltage from PVCC to BAT
VACDET_CHG ACDET adapter-detect rising threshold
–20
V
V
Min voltage to enable charging,
VACDET rising
2.376
2.40 2.424
VACDET_CHG_HYS ACDET falling hysteresis
ACDET rising deglitch(1)
VACDET falling
VACDET rising
VACDET falling
40
mV
ms
µs
V
518
700
10
908
ACDET falling deglitch
VACDET_BIAS
ACDET enable-bias rising threshold
Min voltage to enable all bias, VACDET
rising
0.56
0.62
0.68
VACDET_BIAS_HYS Adapter present falling hysteresis
VACDET falling
VACDET rising
VACDET falling
20
10
10
mV
(1)
ACDET rising deglitch
µs
ACDET falling deglitch
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV
AC Over-voltage rising threshold on
ACDET
3.007
3.1 3.193
V
(See ACDET in erminal Functions)
VACOV_HYS
AC Over-voltage rising deglitch
AC Over-voltage falling deglitch
1.3
1.3
ms
(1) Verified by design.
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ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
AC CURRENT DETECT COMPARATOR (INPUT UNDER_CURRENT)
VACIDET
Adapter current detect rising threshold
Adapter current detect hysteresis
VACI = IAC× RAC× 20, falling edge
200
250
50
300
240
mV
mV
VACIDET_HYS
Rising edge
PVCC / BAT COMPARATOR (REVERSE DISCHARGING PROTECTION)
VPVCC-BAT_FALL PVCC to BAT falling threshold
VPVCC-BAT__HYS PVCC to BAT hysteresis
PVCC to BAT Rising Deglitch
VPVCC– VBAT to turn off ACFET
140
3.5
185
50
10
6
mV
mV
VPVCC– VBAT > VPVCC-BAT_RISE
VPVCC– VBAT < VPVCC-BAT_FALL
µs
PVCC to BAT Falling Deglitch
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
VUVLO
AC Under-voltage rising threshold
AC Under-voltage hysteresis, falling
Measure on PVCC
4
4.5
V
VUVLO_HYS
260
mV
BAT OVER-VOLTAGE COMPARATOR
(2)
(2)
VOV_RISE
VOV_FALL
Over-voltage rising threshold
Over-voltage falling threshold
104
102
As percentage of VBAT_REG
As percentage of IREG_CHG
%
CHARGE OVER-CURRENT COMPARATOR
VOC
Charge over-current falling threshold
Minimum Current Limit (SRP-SRN)
145
50
%
mV
INPUT CURRENT LOW-POWER MODE COMPARATOR
VACLP_HYS
AC low power hysteresis
2.8
1
mV
VACLP_OFFSET
AC low power rising threshold
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
Thermal shutdown hysteresis, falling
Temperature Increasing
155
20
°C
TSHUT_HYS
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON High side driver turn-on resistance
RDS_HI_OFF High side driver turn-off resistance
VBTST– VPH = 5.5 V, tested at 100 mA
VBTST– VPH = 5.5 V, tested at 100 mA
3
6
Ω
0.7
1.4
VBTST_REFRESH Bootstrap refresh comparator threshold
voltage
VBTST– VPH when low side refresh
pulse is requested
4
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
RDS_LO_OFF
Low side driver turn-on resistance
Low side driver turn-off resistance
REGN = 6 V, tested at 100 mA
REGN = 6 V, tested at 100 mA
3
6
Ω
0.6
1.2
PWM DRIVERS TIMING
Driver Dead Time — Dead time when
30
ns
switching between LODRV and HIDRV.
No load at LODRV and HIDRV
PWM OSCILLATOR
FSW
PWM switching frequency
PWM ramp height
240
360
kHz
VRAMP_HEIGHT
As percentage of PVCC
6.6
%PVCC
(2) Verified by design.
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ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
QUIESCENT CURRENT
TEST CONDITIONS
MIN
TYP MAX
UNIT
IOFF_STATE
Total off-state battery current from SRP,
SRN, BAT, VCC, BTST, PH, etc.
VBAT = 16.8 V, VACDET < 0.6 V,
VPVCC > 5 V, TJ = 85°C
7
7
1
3
10
11
µA
VBAT = 16.8 V, VACDET < 0.6 V,
VPVCC > 5 V, TJ = 125°C
IBAT_ON
Battery on-state quiescent current
VBAT = 16.8V, 0.6V < VACDET < 2.4V,
VPVCC > 5V
mA
mA
IBAT_LOAD_CD
Internal battery load current, charge
disbled
Charge is disabled:
VBAT = 16.8 V, VACDET > 2.4 V,
VPVCC > 5 V
5
12
4
IBAT_LOAD_CE
Internal battery load current, charge
enabled
Charge is enabled:
VBAT = 16.8 V, VACDET > 2.4 V,
VPVCC > 5 V
6
10
mA
IAC
Adapter quiescent current
VPVCC = 20 V, charge disabled
2.8
25
mA
mA
IAC_SWITCH
Adapter switching quiescent current
VPVCC = 20 V, Charge enabled,
converter running, total gate charge =
2 × 10 nC
INTERNAL SOFT START (8 steps to regulation current)
Soft start steps
8
step
ms
Soft start step time
1.7
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up
Delay from when adapter is detected
to when the charger is allowed to turn
on
518
700
908
20
ms
ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYSNCHRONOUS TRANSITION)
Accuracy
5 mV
–20
%
V/I
V
AISYNSET
Gain
ISYNSET amplifier gain
250
1
ISYNSET pin voltage
ISYNSET rising deglitch
ISYNSET falling deglitch
VISYNSET
20
µs
µs
640
LOGIC IO PIN CHARACTERISTICS (CHGEN, IADSLP )
VIN_LO
VIN_HI
VBIAS
Input low threshold voltage
Input high threshold voltage
Input bias current
0.8
1
V
2.1
0.8
VCHGEN = 0 to VREGN
µA
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
VIN_LO
Input low threshold voltage, 3 cells
Input mid threshold voltage, 2 cells
CELLS voltage falling edge
0.5
1.8
VIN_MID
CELLS voltage rising for MIN,
CELLS voltage falling for MAX
V
VIN_HI
Input high threshold voltage, 4 cells
CELLS voltage rising
2.5
–1
IBIAS_FLOAT
Input bias float current for 2-cell selection
V
1
µA
= 0 to V
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (EXTPWR)
VOUT_LO
Output low saturation voltage
Delay, EXTPWR falling
Delay, EXTPWR rising
Sink Current = 4 mA
0.5
V
518
700
10
908
ms
µs
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (DPMDET, LPMD)
VOUT_LO
Output low saturation voltage
Delay, rising/falling
Sink Current = 5 mA
0.5
V
10
ms
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TYPICAL CHARACTERISTICS
Table of Graphs(1)
Y
X
FIgure
VREF Load and Line Regulation
REGN Load and Line Regulation
BAT Voltage
vs Load Current
vs Load Current
vs VADJ/VDAC Ratio
vs SRSET/VDAC Ratio
vs ACSET/VDAC Ratio
vs Charge Current
Figure 4
Figure 5
Figure 6
Charge Current
Figure 7
Input Current
Figure 8
BAT Voltage Regulation Accuracy
BAT Voltage Regulation Accuracy
Charge Current Regulation Accuracy
Input Current Regulation (DPM) Accuracy
VIADAPT Input Current Sense Amplifier Accuracy
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Input Regulation Current (DPM), and Charge Current vs System Current
Transient System Load (DPM) Response
Charge Current Regulation
vs BAT Voltage
Efficiency
vs Battery Charge Current
Battery Removal (from Constant Current Mode)
REF and REGN Startup
Charger on Adapter Removal
Charge Enable / Disable and Current Soft-Start
Nonsynchronous to Synchronous Transition
Synchronous to Nonsynchronous Transition
Near 100% Duty Cycle Bootstrap Recharge Pulse
Battery Shorted Charger Response, Over Current Protection (OCP) and Charge Current Regulation
Continuous Conduction Mode (CCM) Switching Waveforms
Discontinuous Conduction Mode (DCM) Switching Waveforms
(1) Test results based on Figure 2 application schematic. VIN = 20 V, VBAT = 3-cell LiIon, ICHG = 3 A, IADAPTER_LIMIT = 4 A, TA = 25°C, unless
otherwise specified.
VREF LOAD AND LINE REGULATION
REGN LOAD AND LINE REGULATION
vs
vs
Load Current
LOAD CURRENT
0
0.50
0.40
-0.50
-1
0.30
0.20
0.10
PVCC = 10 V
-1.50
-2
PVCC = 10 V
0
PVCC = 20 V
-2.50
-3
-0.10
-0.20
PVCC = 20 V
40 50
0
10
20
30
40
50
0
10
20
30
60
70
80
VREF - Load Current - mA
REGN - Load Current - mA
Figure 4.
Figure 5.
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BAT VOLTAGE
vs
VADJ/VDAC RATIO
CHARGE CURRENT
vs
SRSET/VDAC RATIO
10
9
18.2
VADJ = 0 -VDAC,
18
4-Cell,
17.8
SRSET Varied,
4-Cell,
Vbat = 16 V
No Load
8
7
6
5
4
3
2
17.6
17.4
17.2
17
16.8
16.6
16.4
1
0
16.2
16
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
SRSET/VDAC Ratio
VADJ/VDAC Ratio
Figure 6.
Figure 7.
INPUT CURRENT
vs
ACSET/VDAC RATIO
BAT VOLTAGE REGULATION ACCURACY
vs
CHARGE CURRENT
0.2
10
9
ACSET Varied,
4-Cell,
Vbat = 16 V
V
= 16.8 V
reg
8
7
6
5
4
3
2
1
0
0.1
0
-0.1
-0.2
0
4000
2000
8000
6000
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Charge Current - mA
ACSET/VDAC Ratio
Figure 8.
Figure 9.
BAT VOLTAGE REGULATION ACCURACY
CHARGE CURRENT REGULATION ACCURACY
0.10
0.08
0.06
0.04
0.02
0
2
4-Cell, VBAT = 16 V
SRSET Varied
1
0
VADJ = 0 -VDAC
-1
-2
-3
-4
-5
-6
4-Cell, no load
-0.02
-0.04
-7
-8
-0.06
-0.08
-0.10
-9
-10
0
2
4
6
8
16.5
17
17.5
18
18.5
19
I
- Setpoint - A
V
- Setpoint - V
(CHRG)
(BAT)
Figure 10.
Figure 11.
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INPUT CURRENT REGULATION (DPM) ACCURACY
VIADAPT INPUT CURRENT SENSE AMPLIFIER ACCURACY
5
10
9
8
7
6
5
4
3
2
1
0
ACSET Varied
0
V
= 20 V, CHG = EN
I
-5
4-Cell, VBAT = 16 V
V
= 20 V, CHG = DIS
I
-10
-15
-20
-25
Iadapt Amplifier Gain
-1
-2
0
1
2
3
4
5
6
- A
7
8
9
10
0
1
2
3
4
5
6
I
Input Current Regulation Setpoint - A
(ACPWR)
Figure 12.
Figure 13.
INPUT REGULATION CURRENT (DPM), AND CHARGE
CURRENT
vs
SYSTEM CURRENT
TRANSIENT SYSTEM LOAD (DPM) RESPONSE
5
V
= 20 V,
I
4-Cell,
= 16 V
V
4
3
bat
Input Current
Charge Current
2
1
0
0
1
2
3
4
System Current - A
Figure 14.
Figure 15.
CHARGE CURRENT REGULATION
EFFICIENCY
vs
BATTERY CHARGE CURRENT
vs
BAT VOLTAGE
5
100
90
V
= 16.8 V
(BAT)
4
3
2
V
= 12.6 V
reg
V
= 8.4 V
reg
80
70
1
0
Ichrg_set = 4 A
8000
0
2
4
6
8
10
12
14
16
18
0
6000
2000
4000
Battery Voltage - V
Battery Charge Current - mA
Figure 16.
Figure 17.
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BATTERY REMOVAL
REF AND REGN STARTUP
Figure 18.
Figure 19.
CHARGE ENABLE / DISABLE AND CURRENT
SOFT-START
CHARGER ON ADAPTER REMOVAL
Figure 20.
Figure 21.
NONSYNCHRONOUS TO SYNCHRONOUS TRANSITION
SYNCHRONOUS TO NONSYNCHRONOUS TRANSITION
Figure 22.
Figure 23.
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BATTERY SHORTED CHARGER RESPONSE,
OVERCURRENT PROTECTION (OCP) AND CHARGE
CURRENT REGULATION
NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE
PULSE
Figure 24.
Figure 25.
CONTINUOUS CONDUCTION MODE (CCM) SWITCHING
WAVEFORMS
DISCONTINUOUS CONDUCTION MODE (DCM)
SWITCHING WAVEFORMS
Figure 26.
Figure 27.
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FUNCTIONAL BLOCK DIAGRAM
ENA_BIAS_CMP
700 ms
-
0.6V
EXTPWR
CHGEN
AC VGOOD
-
Delay
Rising
+
2.4V
+
ACDET
V(IADAPT)
EAO
+
3.3V
LDO
AC IGOOD
ENA_BIAS
PVCC
EAI
VREF
IADSLP
ACP
-
+
-
250mV
/IADSLP
PVCC
BTST
FBO
+
V(ACP-ACN)
IIN_REG
IIN_ER
-
-
COMP
ERROR
AMPLIFIER
+
ACN
CHGEN
-
+
1V
LEVEL
SHIFTER
BAT_ER
HIDRV
BAT
SRP
-
10mA
VBAT_REG
+
BAT_SHORT
ACOP
20 mA
CHRG_ON
PH
DC-DC
CONVERTER
PWM LOGIC
+
20X
-
V(SRP-SRN)
ICH_ER
-
IBAT_ REG
+
PVCC
6V LDO
SRN
REGN
LODRV
PGND
IADAPT
20 mA
SYNCH
+
-
V(SRP - SRN)
SYNCH
ENA_BIAS
REFRESH
C
ISYNSET
ACSET
SRSET
VADJ
BTST
4 V
-
BTST
+
+
_
BAT
–
+
BAT_SHORT
PH
+
-
2.9 V/Cell
IC Tj
155°C
BAT
TSHUT
+
–
ACP
ACN
+
V(IADAPT)
20x
-
+
–
VBATSET
IBATSET
IINSET
BAT_OVP
CHG_OCP
VBAT_REG
IBAT_REG
IIN_REG
104% X VBAT_REG
RATIO
PROGRAM
+
–
V(SRP-SRN)
145% X IBAT_REG
+
–
VDAC
CELLS
LPREF
DPMDET
ACDET
DPM_LOOP_ON
ACOV
UVLO
+
-
3.1V
2, 3, 4
–
+
–
+
PVCC
V(IADAPT)
AGND
+
-
4 V
LPMD
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TYPICAL APPLICATIONS
DETAILED DESCRIPTION
BATTERY VOLTAGE REGULATION
The bq24740 uses a high-accuracy voltage regulator for charging voltage. Internal default battery voltage setting
VBATT=4.2 V × cell count. The regulation voltage is ratio-metric with respect to VADC. The ratio of VADJ and
VDAC provides extra 12.5% adjust range on VBATT regulation voltage. By limiting the adjust range to 12.5% of
the regulation voltage, the external resistor mismatch error is reduced from ±1% to ±0.1%. Therefore, an overall
voltage accuracy as good as 0.5% is maintained, while using 1% mis-match resistors. Ratio-metric conversion
also allows compatibility with D/As or microcontrollers (µC). The battery voltage is programmed through VADJ
and VDAC using Equation 1.
V
VADJ
V
+ cell count 4V )
ǒ
0.5
Ǔ
ƪ
ƫ
BATT
V
VDAC
(1)
The input voltage range of VDAC is between 2.6 V and 3.6 V. VADJ is set between 0 and VDAC. VBATT defaults
to 4.2 V × cell count when VADJ is connected to REGN.
CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2,3, or 4 Li+ cells. When
charging other cell chemistries, use CELLS to select an output voltage range for the charger.
CELLS
Float
CELL COUNT
2
3
4
AGND
VREF
The per-cell battery termination voltage is function of the battery chemistry. Consult the battery manufacturer to
determine this voltage.
The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is
recommended to be as close to the BAT pin as possible to decouple high frequency noise.
BATTERY CURRENT REGULATION
The SRSET input sets the maximum charging current. Battery current is sensed by resistor RSR connected
between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 0.010
Ω sense resistor, the maximum charging current is 10 A. SRSET is ratio-metric with respect to VDAC using
Equation 2:
V
SRSET 0.10
I
+
CHARGE
V
R
VDAC
SR
(2)
The input voltage range of SRSET is between 0 and VDAC, up to 3.6 V.
The SRP and SRN pins are used to sense across RSR with default value of 10 mΩ. However, resistors of other
values can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation
accuracy; but, at the expense of higher conduction loss.
INPUT ADAPTER CURRENT REGULATION
The total input from an AC adapter or other DC sources is a function of the system supply current and the
battery charging current. System current normally fluctuates as portions of the systems are powered up or down.
Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current
and the maximum charger input current simultaneously. By using DPM, the input current regulator reduces the
charging current when the input current exceeds the input current limit set by ACSET. The current capability of
the AC adapter can be lowered, reducing system cost.
Similar to setting battery regulation current, adapter current is sensed by resistor RAC connected between ACP
and ACN. Its maximum value is set ACSET, which is ratio-metric with respect to VDAC, using Equation 3.
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V
ACSET 0.10
I
+
ADAPTER
V
R
VDAC
AC
(3)
The input voltage range of ACSET is between 0 and VDAC, up to 3.6 V.
The ACP and ACN pins are used to sense RAC with default value of 10mΩ. However, resistors of other values
can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation
accuracy; but, at the expense of higher conduction loss.
ADAPTER DETECT AND POWER UP
An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect
threshold should typically be programmed to a value greater than the maximum battery voltage and lower than
the minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense
the true adapter input voltage whether the ACFET is on or off. Before adapter is detected, BATFET stays on and
ACFET turns off.
If PVCC is below 5 V, the device is disabled, and both ACFET and BATFET turn off.
If ACDET is below 0.6 V but PVCC is above 5 V, part of the bias is enabled, including a crude bandgap
reference, ACFET drive and BATFET drive. IADAPT is disabled and pulled down to GND. The total quiescent
current is less than 10µA.
Once ACDET rises above 0.6 V and PVCC is above 5 V, all the bias circuits are enabled and REGN output
goes to 6 V and VREF goes to 3.3 V. IADAPT becomes valid to proportionally reflect the adapter current.
When ACDET keeps rising and passes 2.4 V, a valid AC adapter is present. 500ms later, the following occurs:
•
•
ACGOOD becomes high through external pull-up resistor to the host digital voltage rail;
Charger turns on if all the conditions are satisfied and STAT becomes valid. (refer to Enable and Disable
Charging)
ENABLE AND DISABLE CHARGING
The following conditions have to be valid before charge is enabled:
•
•
•
•
•
•
•
CHGEN is LOW;
Adapter is detected;
Adapter is higher than PVCC-BAT threshold;
Adapter is not over voltage;
500ms delay is complete after adapter detected;
REGNGOOD and VREFGOOD are valid;
Thermal Shut (TSHUT) is not valid;
One of the following conditions will stop on-going charging:
•
•
•
•
•
•
CHGEN is HIGH;
Adapter is removed;
Adapter is less than 250mV above battery;
Adapter is over voltage;
Adapter is over current;
TSHUT IC temperature threshold is reached (145°C on rising-edge with 15°C hysteresis).
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure
there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of
stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts around 1ms, for a typical rise time of 8 ms. No external components are needed for this function.
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CONVERTER OPERATION
The synchronous buck PWM converter uses a fixed frequency (300 kHz) voltage mode with feed-forward control
scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 8–12.5 kHz nominal.
1
fo +
Ǹ
2p LoCo
Where resonant frequency, fo, is given by:
where (from Figure 1 schematic)
•
•
CO = C11 + C12
LO = L1
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional to
the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 250 mV in order to allow zero percent duty-cycle, when
the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order
to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while
ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin
voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and
the low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor.
Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low
again due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.
The 300 kHz fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of
the audible noise region. The charge current sense resistor RSR should be placed with at least half or more of
the total output capacitance placed before the sense resistor contacting both sense resistor and the output
inductor; and the other half or remaining capacitance placed after the sense resistor. The output capacitance
should be divided and placed onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives
the best performance; but the node in which the output inductor and sense resistor connect should have a
minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching
noise and give better current sense accuracy. The type III compensation provides phase boost near the
cross-over frequency, giving sufficient phase margin.
SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET value.
Otherwise, the charger operates in synchronous mode.
During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power
MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent
shoot-through currents. During the 30ns dead time where both FETs are off, the back-diode of the low-side
power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation
low, and allows safely charging at high currents. During synchronous mode the inductor current is always
flowing and operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.
During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the
break-before-make dead-time, the low-side n-channel power MOSFET will turn-on for around 80ns, then the
low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side
power MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrap
capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is
important for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a
voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between
high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value.
After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. The
inductor current is blocked by the off low-side MOSFET, and the inductor current will become discontinuous.
This mode is called Discontinuous Conduction Mode (DCM).
19
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SLUS736–DECEMBER 2006
During the DCM mode the loop response automatically changes and has a single pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage. At very low currents during non-synchronous operation, there may be
a small amount of negative inductor current during the 80 ns recharge pulse. The charge should be low enough
to be absorbed by the input capacitance.
Whenever the converter goes into 0% duty-cycle mode, and BTST – PH < 4 V, the 80-ns recharge pulse occurs
on LODRV, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (no 80-ns
recharge pulse), and there is no discharge from the battery.
ISYNSET CONTROL (CHARGE UNDER-CURRENT)
In bq24740, ISYN is internally set as the charge current threshold at which the charger changes from
non-synchronous operation into synchronous operation. The low side driver turns on for only 80 ns to charge the
boost cap. This is important to prevent negative inductor current, which may cause a boost effect in which the
input voltage increases as power is transferred from the battery to the input capacitors. This can lead to an
over-voltage on the PVCC node and potentially cause some damage to the system. This programmable value
allows setting the current threshold for any inductor current ripple, and avoiding negative inductor current. The
minimum synchronous threshold should be set from ½ the inductor current ripple to the full ripple current, where
the inductor current ripple is given by
I
RIPPLE_MAX
v I
v I
RIPPLE_MAX
SYN
2
V
BAT_MIN
1
ǒV
Ǔ
ǒ Ǔ
ǒ Ǔ
* V
IN_MAX
BAT_MIN
V
f
s
IN_MAX
and
I
+
RIPPLE_MAX
L
MIN
(4)
where
VIN_MAX: maximum adapter voltage
VBAT_MIN: minimum BAT voltage
fS: switching frequency
LMIN: minimum output inductor
The ISYNSET comparator, or charge under-current comparator, compares the voltage between SRP-BAT and
internal threshold on the cycle-to-cycle base. The threshold is set to 13 mV on the falling edge with 8 mV
hysteresis on the rising edge with 10% variation.
HIGH ACCURACY IADAPT USING CURRENT SENSE AMPLIFIER (CSA)
An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the
host or some discrete logic through the analog voltage output of the IADAPT pin. The CSA amplifies the input
sensed voltage of ACP – ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 times
the input differential voltage. Once PVCC is above 5 V and ACDET is above 0.6V, IADAPT no longer stays at
ground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from IOUT
to AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients.
A 200-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, after the 200-pF capacitor, if additional filtering is desired. Note that adding filtering also
adds additional response delay.
INPUT OVER VOLTAGE PROTECTION (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. The controller enters ACOV
when ACDET > 3.1 V. Charge is disabled, the adapter is disconnected from the system by turning off ACDRV,
and the battery is connected to the system by turning on BATDRV. ACOV is not latched—normal operation
resumes when the ACDET voltage returns below 3.1 V. ACOV threshold is 130% of the adapter-detect
threshold.
20
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SLUS736–DECEMBER 2006
INPUT UNDER VOLTAGE LOCK OUT (UVLO)
The system must have a minimum 5V PVCC voltage to allow proper operation. This PVCC voltage could come
from either input adapter or battery, using a diode-OR input. When the PVCC voltage is below 5 V the bias
circuits REGN and VREF stay inactive, even with ACDET above 0.6 V.
INPUT CURRENT LOW-POWER MODE DETECTION
In order to optimize the system performance, the HOST keeps an eye on the adapter current. Once the adapter
current is above threshold set via LPREF, LPMD pin sends signal to HOST. The signal alarms the host that
input power has exceeded the programmed limit, allowing the host to throttle back system power by reducing
clock frequency, lowering rail voltages, or disabling certain parts of the system. The LPMD pin is an open-drain
output. Connect a pull-up resistor to LPMD. The output is logic HI when the IADAPT output voltage (IADAPT =
20 x VACP-ACN) is lower than the LPREF input voltage. The LPREF threshold is set by an external resistor divider
using VREF. A hysteresis can be programmed by a positive feedback resistor from LPMD pin to the LPREF pin.
ACDET
Comparator
ACDET_DG
t_dg
rising
700 ms
ACDET
ACDET_DET
+
-
TO ACDET
Logic
2.4 V
EXT_PWR_DG
EXTPWR
ACP
ACN
Adaptor
Current Sense
Amplifier
1 kW
+
-
LOIAC
Comparator
-
250 mV
LOIAC_DET
+
IADAPT Error
Amplifier
Disable
20 kW
-
IADAPT
+
IADAPT
Disable
LOPWRMODE
Comparator
LPMD
+
-
LOPWR_DET
LPREF
Program Hysteresis of comparator
by putting a resistor in feedback
from LPMD pin to LPREF pin.
Figure 28. EXTPWR, LPREF and LPMD Logic
BATTERY OVER-VOLTAGE PROTECTION
The converter stops switching when BAT voltage goes above 104% of the regulation voltage. The converter will
not allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. This
allows one-cycle response to an overvoltage condition, such as when the load is removed or the battery is
disconnected. A 10-mA current sink from BAT to PGND is on only during charge, and allows discharging the
stored output-inductor energy into the output capacitors.
CHARGE OVER-CURRENT PROTECTION
The charger has a secondary over-current protection. It monitors the charge current, and prevents the current
from exceeding 145% of regulated charge current. The high-side gate drive turns off when the over-current is
detected, and automatically resumes when the current falls below the over-current threshold.
21
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SLUS736–DECEMBER 2006
THERMAL SHUTDOWN PROTECTION
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C.
Status Outputs (EXTPWR, LPMD, DPMDET pin)
Four status outputs are available, and they all, except for LPMD, require external pull up resistors to pull the pins
to system digital rail for a high level.
EXTPWR open-drain output goes low under either of the two conditions:
1. ACDET is above 2.4 V
2. Adapter current is above 1.25 A using a 10-mΩ sense resistor (IADAPT voltage above 250 mV). Internally,
the AC current detect comparator looks between IADAPT and an internal 250-mV threshold. It indicates a
good adapter is connected because of valid voltage or current.
STAT open-drain output goes low when charging. A high level on STAT indicates the charger is not charging;
therefore, either, CHGEN pin is not low, or the charger is not able to charge because input voltage is still
powering up and the 700-ms delay has not finished, or because of a fault condition such as overcurrent, input
over voltage, or TSHUT over temperature.
LPMD push-pull output goes low when the input current is higher than the programmed threshold via LPREF
pin. Hysteresis can be programmed by putting a resistor from LPREF pin to LPMD pin.
DPMDET open-drain output goes low when the DPM loop is active to reduce the battery charge current (after a
10-ms delay).
Table 2. Component List for Typical System Circuit of Figure 1
PART DESIGNATOR
QTY
3
DESCRIPTION
P-channel MOSFET, –30V,-6A, SO-8, Vishay-Siliconix, Si4435
N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680A
Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C
Sense Resistor, 10 mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100F
Inductor, 10µH, 7A, 31mΩ, Vishay-Dale, IHLP5050FD-01
Capacitor, Ceramic, 10µF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106M
Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K
Capacitor, Ceramic, 0.1µF, 50V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU
Resistor, Chip, 10 kΩ, 1/16W, 5%, 0402
Q1, Q2, Q3
Q4, Q2
2
D1
1
RAC, RSR
2
L1
1
C1, C6, C7, C11, C12
5
C4, C8, C10
3
C2, C3, C9, C13, C14, C15
6
R3, R4, R5
4
R1
R2
R6
R7
R8
R9
1
Resistor, Chip, 432 kΩ, 1/16W, 1%, 0402
1
Resistor, Chip, 66.5 kΩ, 1/16W, 1%, 0402
1
Resistor, Chip, 33 kΩ, 1/16W, 1%, 0402
1
Resistor, Chip, 200 kΩ, 1/16W, 1%, 0402
1
Resistor, Chip, 24.9 kΩ, 1/16W, 1%, 0402
1
Resistor, Chip, 1.8 MΩ, 1/16W, 1%, 0402
22
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SLUS736–DECEMBER 2006
APPLICATION INFORMATION
Input Capacitance Calculation
During the adapter hot plug-in, the ACDRV has not been enabled. The AC switch is off and the simplified
equivalent circuit of the input is shown in Figure 29.
Ii
Li
Ri
Ci
Vi
Vc
A. Ri and Li are the equivalent input inductance and resistance. C1 and C8 are the input capacitance.
Figure 29. Simplified Equivalent Circuit During Adapter Insertion
The voltage on the input capacitor(s) is given by:
Ri
-
t æ
ç
è
ö
÷
÷
ø
Vi × w
Vi
Ri
2Li
VC (t) = VC (0) +
+
e
-
sinwt - w × cos wt
ç
Z0 × Ci × w20 Z0 × Ci × w02
2Li
(5)
æ
ö2
Ri
1
Li
1
ç
ç
è
÷
÷
ø
w =
-
Z0
=
w0
=
LiCi
2Li
Ci
LiCi
where
,
, and
23
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SLUS736–DECEMBER 2006
APPLICATION INFORMATION (continued)
For a typical notebook charger application, the total stray inductance of the adapter output wire and the PCB
connections is normally 5–12 µH, and the total effective resistance of the input connections is 0.15–0.5 Ω.
Figure 30(a) demonstrates that a higher Ci helps to damp the voltage spike. Figure 30(b) demonstrates the
effect of the input stray inductance Li on the input voltage spike. The dashed curve in Figure 30(b) represents
the worst case for Ci=40 µF. Figure 30(c) shows how the resistance helps to suppress the input voltage spike.
35
35
Ci = 20 mF
Li = 5 mF
Ri = 0.15 W,
Ci = 40 mF
Ri = 0.21 W,
Li = 9.3 mH
30
25
20
15
10
30
25
20
15
10
Ci = 40 mF
Li = 12 mF
5
0
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
Time - ms
(b) Vc with various Li values
3
3.5
4
4.5
5
Time - ms
(a) Vc with various Ci values
35
30
25
20
15
10
5
Li = 9.3 mH,
Ci = 40 mF
Ri = 0.15 W
Ri = 0.50 W
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time - ms
(c) Vc with various Ri values
Figure 30. Parametric Study Of The Input Voltage
Minimizing the input stray inductance, increasing the input capacitance and using high-ESR input capacitors
helps to suppress the input voltage spike.
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APPLICATION INFORMATION (continued)
Figure 31 shows the measured input voltages and currents with different input capacitances. The voltage spike
drops by about 5 V after increasing Ci from 20 µF to 40 µF. The input voltage spike has been dramatically
damped by using a 47 F electrolytic capacitor.
Ci = 20 mF
Ci = 40 mF
(c) Ci=49 mF (47 mF electrolytic and 2xmF ceramic)
Figure 31. Adapter DC Side Hot Plug-In With Various Input Capacitances
Since the input voltage to the IC is PVCC which is 0.7 V (diode voltage drop) lower than Vc during the adapter
insertion, a 40-µF input capacitance is normally adequate to keep the PVCC voltage well below the maximum
voltage rating under normal conditions. In case of a higher input stray inductance, the input capacitance may be
increased accordingly. An electrolytic capacitor will help reduce the input voltage spike due to its high ESR.
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APPLICATION INFORMATION (continued)
PCB Layout Design Guideline
1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
2. The control stage and the power stage should be routed separately. At each layer, the signal ground and the
power ground are connected only at the power pad.
3. The AC current-sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact. The
area of this loop must be minimized. The decoupling capacitors for these pins should be placed as close to
the IC as possible.
4. The charge-current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact.
The area of this loop must be minimized. The decoupling capacitors for these pins should be placed as close
to the IC as possible.
5. Decoupling capacitors for PVCC (pin 28), VREF (pin 10), REGN (pin 24) should be placed underneath the IC
(on the bottom layer) with the interconnections to the IC as short as possible.
6. Decoupling capacitors for BAT (pin 17), IADAPT (pin 15) must be placed close to the corresponding IC pins
with the interconnections to the IC as short as possible.
7. Decoupling capacitor CX for the charger input must be placed very close to the Q4 drain and Q5 source.
Figure 32 shows the recommended component placement with trace and via locations.
(a) Top Layer
(b) Bottom Layer
Figure 32. Layout Example
26
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PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
MLA
MLA
Reel
Diameter Width
(mm)
Reel
A0 (mm)
5.3
B0 (mm)
5.3
K0 (mm)
1.5
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
BQ24740RHDR
BQ24740RHDT
RHD
RHD
28
28
330
12
8
8
12 PKGORN
T2TR-MS
P
180
12
5.3
5.3
1.5
12 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
BQ24740RHDR
BQ24740RHDT
RHD
RHD
28
28
MLA
MLA
346.0
190.0
346.0
212.7
29.0
31.75
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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