BQ24741RHDT_技术文档

bq24741

www.ti.com ...................................................................................................................................................... SLUS875A–MARCH 2009–REVISED MARCH 2009

Li-Ion or Li-Polymer Battery Charger with Low I_qand Accurate Trickle Charge

1

FEATURES

APPLICATIONS

•

Notebook and Ultra-Mobile Computers

Portable Data Capture Terminals

Portable Printers

Medical Diagnostics Equipment

Battery Bay Chargers

•

NMOS-NMOS Synchronous Buck Converter

•

Resistor-Programmable Switching Frequency

between 300 kHz and 800 kHz

•

8 V-24 V Input Voltage Operation Range

Cells Pin Support Two to Four Li-Ion Cells up

to 18 V Battery Voltage

Battery Back-up Systems

•

Analog Inputs with Ratiometric Programming

via Resistors or DAC/GPIO

DESCRIPTION

The bq24741 is

a high-efficiency, synchronous

–

Charge Voltage (4-4.512 V/cell)

Charge Current (up to 10 A)

Adapter Current Limit for DPM

battery charger with integrated compensation,

offering low component count for space-constrained

Li-ion or Li-polymer battery charging applications.

Ratiometric charge current and voltage programming

allows high regulation accuracies, and can be either

hardwired with resistors or programmed by the

system power-management microcontroller using a

DAC or GPIOs.

•

High-Accuracy Voltage and Current Regulation

–

±0.5% Charge Voltage Accuracy

±3% Charge Current Accuracy

±3% Adapter Current Accuracy

±2% Input Current Sense Amp Accuracy

The bq24741 charges two, three, or four series Li+

cells, supporting up to 10 A of charge current, and is

available in a 28-pin, 5x5-mm²thin QFN package.

•

150 mA Trickle-charge Current with ±33%

Accuracy Down to Zero Battery Voltage

Safety Protection

Text for space

–

Input Overvoltage Protection

Battery Overvoltage Protection

Charger Overcurrent Protection

Thermal Shutdown Protection

Text for space

28 27

26 25

24 23

22

•

Status and Monitoring Outputs

–

Adapter Present Indicator

21

20

1

2

CE

ACN

DPMDET

CELLS

Programmable Input Power Detect with

Adjustable Threshold

19

18

3

4

5

6

CSP

CSN

ACP

–

Dynamic Power Management (DPM) with

Status Indicator

bq24741

QFN-28

TOP VIEW

LPMOD

ACDET

ACSET

17

BAT

Current Drawn from Input Source

•

Charge Enable Pin

16

15

ISET

Internal Soft-Start

7

IADAPT

LPREF

Internal Loop Compensation

8

9

10

11

12

13 14

25 ns Minimum Driver Dead-Time and 99.5%

Maximum Effective Duty Cycle

28-pin, 5x5-mm²QFN package

•

Energy Star Low I_q

–

< 10 µA Off-State Battery Discharge Current

< 1.5 mA Off-State Input Quiescent Current

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24741

SLUS875A–MARCH 2009–REVISED MARCH 2009...................................................................................................................................................... www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

The bq24741 features resistor-programmable PWM switching frequency and accurate 150mA trickle charge (with

20 mΩ sensing resistor), which can be enabled via the TRICKLE pin. The bq24741 also features Dynamic Power

Management (DPM) and input power limiting. These features reduce battery charge current when the input

power limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger

simultaneously. A high-accuracy current sense amplifier enables accurate measurement of input current from the

AC adapter, allowing monitoring the overall system power. If the adapter current is above the programmed

low-power threshold, a signal is sent to host so that the system optimizes its power performance according to

what is available from the adapter.

Text for space

SYSTEM

ADAPTER +

ADAPTER -

R

R11

2 Ω

C7

AC

0.010 Ω

C6

P

10 µF

Q1 (ACFET) Q2 (ACFET)

SI4435 SI4435

Controlled by

HOST

D2

BAT54

C1

2.2 µF

C3

C2

ACN

ACP

PVCC

R1

0.1 µF

432 kΩ

1%

Q3(BATFET)

SI4435

C8

0.1 µF

Controlled by

HOST

ACDET

AGND

R2

P

Q4_A

FDS8978

66.5 kΩ

1%

HIDRV

VREF

R3

10kΩ

N

RSR

0.020 Ω

SW

EXTPWR

VREF

EXTPWR

L1

C9

BTST

PACK+

PACK-

10µH

D1

BAT54

C12

10 µF

0.1 µF

R4

10 kΩ

R5

C4

1 µF

REGN

C11

10 µF

bq24741

10kΩ

C10

TRICKLE

DPMDET

1 µF

C13

0.1 µF

LODRV

PGND

GPIO

C14

0.1 µF

N

LPMOD

CELLS

CE

Q4_B

FDS8978

R15

SRP

SRN

HOST

10 kΩ

VDAC

ISET

120 kΩ

BAT

ISET_PWM

(D = 0.72, V_peak= VDAC)

VREF

R14

C13

100nF

C15

0.1 µF

R7

73.2 kΩ

1%

LPREF

ADC

IADAPT

VADJ

VREF

C5

100pF

R9

60.4 kΩ

1%

R8

26.7 kΩ

1%

ACSET

FSET

R12

102kΩ

1%

PowerPad

R10

40.2 kΩ

1%

R6

97.6 kΩ

R13

64.9 kΩ

1%

Text for space

F_S= 400 kHz, 90 W Adapter, V_ADAPTER= 19 V, V_BAT= 3-cell Li-Ion (4.2V/cell), I_charge= 3.6 A, I_{adapter_limit}= 4.0 A

Figure 1. Typical System Schematic, Voltage, and Current Programmed by Resistor

Text for space

2

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SYSTEM

ADAPTER +

ADAPTER -

R11

2 Ω

C7

R_AC

0.010 Ω

C6

P

10 µF

D2

BAT54

Q1 (ACFET) Q2 (ACFET)

SI4435 SI4435

Controlled by

HOST

C1

2.2 µF

C3

C2

R1

ACN

ACP

PVCC

0.1 µF

432 kΩ

1%

Q3 (BATFET)

SI4435

C8

0.1 µF

Controlled by

HOST

ACDET

AGND

bq24741

R2

66.5 kΩ

1%

P

Q4_A

FDS8978

HIDRV

VREF

R3

10 kΩ

N

R^SR

0.020 Ω

SW

EXTPWR

VREF

L1

C9

BTST

PACK+

PACK-

4.7 µH

D1

BAT54

C12

10 µF

0.1 µF

R4

10 kΩ

R5

C4

1 µF

REGN

C11

10 µF

10kΩ

C10

TRICKLE

DPMDET

1 µF

C13

0.1 µF

LODRV

PGND

GPIO

C14

0.1 µF

N

LPMOD

CELLS

CE

Q4_B

FDS8978

R15

SRP

SRN

10 kΩ

HOST

VDAC

ISET

120 kΩ

BAT

ISET_PWM

VREF

R14

C13

100nF

C15

0.1 µF

(D = 0.72, V_peak= VDAC)

R7

73.2 kΩ

1%

LPREF

ACSET

VADJ

R8

26.7 kΩ

1%

DAC

ADC

FSET

IADAPT PowerPad

R6

56.2 kΩ

C5

100 pF

Text for space

(1) Pull-up rail could be either VREF or other system rail.

(2) SRSET/ACSET could come from either DAC or resistor dividers.

F_S= 650 kHz, 90 W Adapter, V_ADAPTER= 19 V, V_BAT= 3-cell Li-Ion (4.2V/cell), I_charge= 3.6 A, I_{adapter_limit}= 4.0 A

Figure 2. Typical System Schematic, Voltage and Current Programmed by DAC

ORDERING INFORMATION

Part number

Package

Ordering Number

(Tape and Reel)

Quantity

bq24741RHDR

bq24741RHDT

3000

250

bq24741

28-PIN 5 x 5 mm²QFN

PACKAGE THERMAL DATA

PACKAGE

QFN – RHD⁽¹⁾⁽²⁾

θ_JA

T_A= 70°C POWER RATING

2.36 W

DERATING FACTOR ABOVE T_A= 25°C

39°C/W

0.028 W/°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2x3 via matrix.

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Table 1. TERMINAL FUNCTIONS – 28-PIN QFN

TERMINAL

DESCRIPTION

NAME

NO.

Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1 MΩ pull-down

resistor. A 10 KΩ external resistor is required to connect the CE pin to the external pull-up rail other than VREF.

CE

1

Adapter current sense resistor, negative input. A 0.1 µF ceramic capacitor is placed from ACN to ACP to provide

differential-mode filtering. An optional 0.1 µF ceramic capacitor is placed from ACN pin to AGND for common-mode

filtering.

ACN

2

3

4

Adapter current sense resistor, positive input. A 0.1 µF ceramic capacitor is placed from ACN to ACP to provide

differential-mode filtering. A 0.1 µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.

ACP

Low-power-mode-detect active-LOW open-drain logic output. Place a 10kohm pull-up resistor from LPMOD pin to the

pull-up voltage rail. The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The output is LOW

when IADAPT pin voltage is higher than LPREF pin voltage. Internal 6% hysteresis.

LPMOD

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter

input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET pin voltage is greater than 2.4 V. IADAPT

current sense amplifier is active when ACDET pin voltage is greater than 0.6V and PVCC > VUVLO. ACOV is input

over-voltage protection; it disables charge when ACDET > 3.1 V. ACOV does not latch, and normal operation resumes

when ACDET < 3.1 V.

ACDET

5

Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current

regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC

to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to

the VDAC pin.

ACSET

LPREF

6

7

Low power voltage set input. Connect a resistor divider from VREF to LPREF, and AGND to program the reference for

the LOPWR comparator. The LPREF pin voltage is compared to the IADAPT pin voltage and the logic output is given

on the LPMOD open-drain pin. Connect LPREF to ACSET through a resistor divider to track the adapter power.

Trickle current enable logic input. When CE is HIGH, a HIGH level on this pin enables accurate 150 mA trickle charge

with 20 mΩ sense resistor. A LOW level on this pin enables the ISET pin to program the charge current. It has an

internal 1 MΩ pull-down resistor.

TRICKLE

AGND

8

9

Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the

analog ground plane, and only connect to PGND through the PowerPad underneath the IC.

3.3 V regulated voltage output. Place a 1 µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage

VREF

10 could be used for ratio-metric programming of voltage and current regulation and for programming the LPREF

threshold. VREF is also the voltage source for the interal circuit.

Charge voltage set reference input. Connect the VREF or external DAC voltage source to VDAC pin. Battery voltage,

charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the voltage on VADJ, and

11 ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, ISET, and ACSET pins to AGND for

programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output to VADJ,

ISET, or ACSET.

VDAC

Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage

12 regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the

output of an external DAC to VADJ pin and connect the DAC supply to VDAC pin.

VADJ

Valid adapter active-low detect logic open-drain output. Pulled LO when Input voltage is above ACDET programmed

13 threshold OR input current is greater than 1.25 A with 10 mΩ sense resistor. Connect a 10 kΩ pull-up resistor from

EXTPWR pin to pull-up supply rail.

EXTPWR

PWM switching frequency (F_s) program pin. Program the switching frequency by placing a resistor to AGND on this

pin.

FSET

14

Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a

100 pF (max) or less ceramic decoupling capacitor from IADAPT to AGND.

IADAPT

15

Charge current set input. The voltage ratio of ISET voltage versus VDAC voltage programs the charge current

16 regulation set-point. Program by connecting a resistor divider from VDAC to ISET, to AGND; or, by connecting the

output of an external DAC to ISET pin and connect the DAC supply to VDAC pin.

ISET

BAT

CSN

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT

17 pin to accurately sense the battery pack voltage. Place a 0.1 µF capacitor from BAT to AGND close to the IC to filter

high frequency noise.

Charge current sense resistor, negative input. A 0.1 µF ceramic capacitor is placed from CSN to CSP to provide

18 differential-mode filtering. An optional 0.1 µF ceramic capacitor is placed from CSN pin to AGND for common-mode

filtering.

Charge current sense resistor, positive input. A 0.1 µF ceramic capacitor is placed from CSN to CSP to provide

differential-mode filtering. A 0.1 µF ceramic capacitor is placed from CSP pin to AGND for common-mode filtering.

CSP

19

CELLS

20 2, 3 or 4 cells selection logic input. Logic Lo programs 3–cell. Logic HI programs 4-cell. Floating programs 2–cell.

4

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Table 1. TERMINAL FUNCTIONS – 28-PIN QFN (continued)

TERMINAL

DESCRIPTION

NAME

NO.

Dynamic power management (DPM) input current loop active, open-drain output status. Logic low (LO) indicates input

DPMDET

21 current is being limited by reducing the charge current. Connect 10-kohm pull-up resistor from DPMDET pin to VREF

or a different pull-up supply rail.

Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of

22 low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to AGND

through the PowerPad underneath the IC.

PGND

LODRV

REGN

23 PWM low side driver output. Connect to the gate of the low–side power MOSFET with a short trace.

PWM low side driver positive 6 supply output. Connect a 1 µF ceramic capacitor from REGN to PGND pin, close to the

24 IC. Use for low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from

REGN to BTST. REGN is disabled when CE is LOW.

PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET

SW

25 drain, high-side power MOSFET source, and output inductor). Connect the 0.1 µF bootstrap capacitor from SW to

BTST.

HIDRV

26 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

PWM high side driver positive supply. Connect a 0.1 µF bootstrap ceramic capacitor from BTST to SW. Connect a

bootstrap Schottky diode from REGN to BTST. A optional 2.0Ω - 5.1Ω bootstrap resistor can be inserted between the

BTST pin and the common point of the bootstrap capactor and bootstrap diode, thus dampening the SW node voltage

BTST

27

ring and spike.

IC power positive supply. Connect to the adapter input through a schottky diode. Place a 0.1 uF ceramic capacitor

from PVCC to PGND pin close to the IC.

PVCC

28

Exposed pad beneath the IC. AGND and PGND star-connected only at the PowerPad plane. Always solder PowerPad

to the board, and have vias on the PowerPad plane connecting to AGND and PGND planes. It also serves as a

thermal pad to dissipate the heat.

PowerPad

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

(2)

VALUE

–0.3 to 30

–1 to 30

–0.3 to 7

UNIT

PVCC, ACP, ACN, SRP, SRN, BAT

SW

REGN, LODRV, VADJ, ACSET, ISET, ACDET, FSET, IADAPT, /LPMOD,

LPREF, CE, CELLS, EXTPWR, DPMDET, TRICKLE

Voltage range

V

VDAC, VREF

–0.3 to 3.6

–0.3 to 36

–1 to 1

BTST, HIDRV with respect to AGND and PGND

AGND, PGND

Maximum difference voltage ACP–ACN, CSP–CSN

Junction temperature range

-0.5 to 0.5

–40 to 155

–55 to 155

°C

Storage temperature range

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

–0.8

0

NOM

MAX

24

UNIT

V

SW

PVCC, ACP, ACN, CSP, CSN, BAT

24

V

REGN, LODRV

VREF

0

6.5

V

3.3

3.6

V

Voltage range

VDAC

V

VADJ, ACSET, ISET, ACDET, FSET, IADAPT, LPMOD, LPREF, CE, CELLS,

EXTPWR, DPMDET, TRICKLE

0

5.5

V

BTST, HIDRV with respect to AGND and PGND

AGND, PGND

0

–0.3

–40

30

0.3

V

Maximum difference voltage: ACP–ACN, CSP–CSN

Junction temperature range

0.3

V

125

150

°C

Storage temperature range

–55

ELECTRICAL CHARACTERISTICS

8.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

(1)(2)(3)

otherwise noted)

PARAMETER

OPERATING CONDITIONS

V_{PVCC_OP}PVCC input voltage operating range

CHARGE VOLTAGE REGULATION

TEST CONDITIONS

MIN TYP

MAX

UNIT

8

24

V

V_{BAT_OP}

BAT input voltage operating range

0

8

PVCC

18.048

3.6

V

V_{BAT_REG_RNG}

V_{VDAC_OP}

V_{VADJ_OP}

BAT voltage regulation range

VDAC reference voltage range

VADJ voltage range

4-4.512 V per cell, times 2,3,4 cells

2.6

0

VDAC

0.5

8 V, 8.4 V, 9.024 V

–0.5

Charge voltage regulation accuracy

12 V, 12.6 V, 13.536 V

16 V, 16.8 V, 18.048 V

0.5

%

0.5

CHARGE CURRENT REGULATION (ENABLE CE & DISABLE TRICKLE)

V_{IREG_CHG}

Charge current regulation differential V_{IREG_CHG}= V_CSP– V_CSN

voltage range

0

100

mV

V

V_{ISET_OP}

SRSET voltage range

V_{IREG_CHG}= 40 mV

V_{IREG_CHG}= 20 mV

0

–3%

VDAC

3%

–5%

5%

Charge current regulation accuracy

V_{IREG_CHG}= 5 mV

–25%

–33%

–50%

–1.0

25%

33%

50%

1.0

V_{IREG_CHG}= 3 mV (V_BAT≥ 4 V)

V_{IREG_CHG}= 3 mV (V_BAT< 4 V)

V_BAT≥ 4 V

Off-set Voltage of Amplifier

mV

V_BAT< 4 V

–1.5

1.5

(1) Verified by design

(2) Deglitch time and delay are propotional to the period of oscillator, unless specified.

(3) When CE=HIGH, the oscillator frequency is equal to external setting F_s; when CE=LOW, the oscillator frequency is fixed internal setting

700 kHz.

6

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ELECTRICAL CHARACTERISTICS (continued)

8.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

TRICKLE CHARGE CURRENT REGULATION (ENABLE CE & TRICKLE)

Charge Current Regulation Accuracy V_{IREG_CHG}= 3 mV

Off-set Voltage of Amplifier

–33%

33%

1.0

–1.0

mV

INPUT CURRENT REGULATION

V_{IREG_DPM}

Adapter current regulation differential V_{IREG_DPM}= V_ACP– V_ACN

voltage range

0

100

mV

V

V_{ACSET_OP}

ACSET voltage range

0

–3%

VDAC

3%

V_{IREG_DPM}= 40 mV

V_{IREG_DPM}= 20 mV

Input current regulation accuracy

–5%

5%

V_{IREG_DPM}= 5 mV

–25%

–33%

-500

25%

33%

500

V_{IREG_DPM}= 1.5 mV

Off-set Voltage of Amplifier

µV

VREF REGULATOR

V_{VREF_REG}VREF regulator voltage

I_{VREF_LIM}VREF current limit

REGN REGULATOR

V_{REGN_REG}REGN regulator voltage

I_{REGN_LIM}REGN current limit

ADAPTER CURRENT SENSE AMPLIFIER

V_ACDET> 0.6 V, 0-30 mA

3.267

35

3.3

5.9

3.333

80

V

V_VREF= 0 V, V_ACDET> 0.6 V

mA

V_ACDET> 0.6 V, 0-75 mA, PVCC > 10 V

V_REGN= 0 V, V_ACDET> 0.6 V

5.6

90

6.2

V

145

V_{ACP/N_OP}

V_IADAPT

I_IADAPT

Input common mode range

IADAPT output voltage range

IADAPT output current

Voltage on ACP/ACN

0

24

2

V

1

mA

V/V

A_IADAPT

Current sense amplifier voltage gain

A_IADAPT= V_IADAPT/ V_{IREG_DPM}

V_{IREG_DPM}= 40 mV

20

–2%

–4%

–25%

–33%

1

2%

4%

V_{IREG_DPM}= 20 mV

Adapter current sense accuracy

V_{IREG_DPM}= 5 mV

25%

33%

V_{IREG_DPM}= 1.5 mV

I_{IADAPT_LIM}

Output current limit

V_IADAPT= 0 V

mA

pF

C_{IADAPT_MAX}

Maximum output load capacitance

For stability with 0 mA to 1 mA load

100

ACDET COMPARATOR (INPUT UNDER_VOLTAGE, ACVGOOD)

V_{ACDET_CHG}

ACDET adapter-detect rising

threshold

Min voltage to enable charging, V_ACDET

rising

2.376 2.40

2.424

V

V_{ACDET_CHG_HYS}

ACDET falling hysteresis

V_ACDETfalling, PVCC>8V

V_ACDETrising, PVCC>8V

40

mV

ms

ACDET rising deglitch to turn on

EXTPWR FET⁽⁴⁾

1.2

ACDET rising deglitch to enable

charge

V_ACDETrising, PVCC>8V, CE=HIGH

V_ACDETfalling, PVCC>8V

333

80

ms

µs

(4)

ACDET falling deglitch to turn off

EXTPWR FET⁽⁴⁾

ACDET falling deglitch to disable

charge⁽⁴⁾

V_ACDETfalling, PVCC>8V

80

µs

T_{ACDET_EXTPWR}

Power-up delay from V_ACDET>2.4V to First time power up, F_s=300 kHz - 800

2

ms

EXTPWR FET turn-on⁽⁴⁾

kHz

(4) Verified by design

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ELECTRICAL CHARACTERISTICS (continued)

8.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

AC CURRENT DETECT COMPARATOR (INPUT UNDER_CURRENT, ACIGOOD)

V_ACIDET

Adapter current detect falling

threshold

V_ACI= 20 X I_ACx R_AC, falling edge

200 250

300

mV

V_{ACIDE_HYS}

Adapter current detect hysteresis

Rising edge

50

10

mV

µs

IADAPT rising

IADAPT falling

Adapter current detect deglitch

µs

PVCC / BAT COMPARATOR

V_{PVCC_BAT_OP}

Differential Voltage from PVCC to

-20

24

V

BAT

V_{PVCC-BAT_FALL}

V_{PVCC-BAT__HYS}

PVCC to BAT falling threshold

PVCC to BAT hysteresis

PVCC to BAT rising deglitch

PVCC to BAT ralling deglitch

V_PVCC– V_BATto disable charge

850 900

200 225

4.5

950

250

mV

ms

µs

V_PVCC– V_BAT> V_{PVCC-BAT_RISE}

V_PVCC– V_BAT< V_{PVCC-BAT_FALL}

10

BAT OVERVOLTAGE COMPARATOR

V_{OV_RISE}

Overvoltage rising threshold⁽⁵⁾

As percentage of V_{BAT_REG}

104

%

V_{OV_FALL}

Overvoltage falling threshold⁽⁵⁾

102

%

BATSHORT COMPARATOR

V_{BATSHORT_RISE}Battery rising voltage for BATSHORT

2

V/Cell

exit

V_{BATSHORT_FALL}

Battery falling voltage for BATSHORT

entry

1.7

CHARGE OVERCURRENT COMPARATOR

V_{OC_peak}Peak charge over-current threshold

V_(CSP-CSN), when V_ISET/ VDAC < 0.8

90 110

130

150

mV

V_(CSP-CSN), when V_ISET/ V_DAC≥ 0.8

100 125

CHARGE UNDERCURRENT PROTECTION COMPARATOR (UCP)

V_UCP

Charge under-current threshold,

falling edge

V_(CSP-CSN)from synchronous to

non-synchronous operation

25

35

30

40

35

45

mV

Charge under-current threshold,

rising edge

V_(CSP-CSN)from non-synchronous to

synchronous operation

Charge under-current rising deglitch

Charge under-current falling deglitch

10

µs

320

INPUT OVERVOLTAGE COMPARATOR (ACOV)

V_ACOV

AC over-voltage rising threshold on

ACDET

Measure on ACDET pin

3.007

3.1

3.193

V

V_{ACOV_HYS}

AC over-voltage deglitch (rising edge)

650

µs

AC over-voltage deglitch (falling

edge)

INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)

V_UVLO

AC under-voltage rising threshold

AC under-voltage hysteresis, falling

Measured on PVCC pin

7

8

9

V

V_{UVLO_HYS}

260

mV

INPUT LOW POWER MODE COMPARATOR (LPMOD)

V_{ACLP_HYS}

AC low power mode comparator

internal hysteresis

5%

7%

V_{ACLP_OFFSET}

AC low power mode comparator

offset voltage

1

mV

(5) Verified by design

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ELECTRICAL CHARACTERISTICS (continued)

8.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

THERMAL SHUTDOWN COMPARATOR

T_SHUT

Thermal shutdown rising temperature Temperature Increasing

Thermal shutdown hysteresis, falling

155

20

°C

T_{SHUT_HYS}

PWM HIGH SIDE DRIVER (HIDRV)

R_{DS_HI_ON}

High side driver turn-on resistance

V_BTST– V_PH= 5.5 V, tested at 100 mA

6

Ω

R_{DS_HI_OFF}

V_{BTST_REFRESH}

High side driver turn-off resistance

1.4

Bootstrap refresh comparator

threshold voltage

V_BTST– V_PHwhen low side refresh pulse

is requested

4

V

I_{BTST_LEAK}

BTST leakage current

High side is on; charge enabled

200

µA

PWM LOW SIDE DRIVER (LODRV)

R_{DS_LO_ON}Low side driver turn-on resistance

R_{DS_LO_OFF}Low side driver turn-off resistance

PWM DRIVERS TIMING

Driver Dead Time between HIDRV

and LODRV

PWM OSCILLATOR

F_S

REGN = 6 V, tested at 100 mA

6

Ω

1.2

25

ns

Programmable PWM switching

frequency range

R_FSET=130 kΩ - 45 kΩ

300

800

kHz

PWM switching frequency accuracy

RAMP amplitude

-20%

1.33

300

20%

V

DC offset of RAMP

mV

QUIESCENT CURRENT

Total off-state quiescent current into

V_BAT= 16.8 V, V_ACDET< 0.6 V,

V_PVCC> 8 V, T_J= 0 to 125°C

I_{OFF_STATE}

pins: CSP, CSN, BAT, VCC, BTST,

SW, PVCC, ACP, ACN

7

11

1

µA

Total off-state battery current from

ACP, ACN

V_BAT= 16.8 V, V_ACDET< 0.6 V,

V_PVCC> 8 V, T_J= 0 to 125°C

µA

Battery on-state quiescent current

V_BAT= 16.8 , 0.6 V < V_ACDET< 2.4 V,

V_PVCC> 8V

I_{BAT_ON}

I_{BATQ_CD}

I_AC

1

mA

Total quiescent current into CSP,

CSN, BAT, VCC, BTST, SW

Adapter present, V_ACDET> 2.4 V, charge

disabled

100

1

200

1.5

µA

Adapter quiescent current

V_PVCC= 20 V, charge disabled

mA

INTERNAL SOFT START (8 steps to regulation current)

Soft start steps

8

step

Soft start time of each step (512

PWM cycles)

853

µs

LOGIC INPUT PIN CHARACTERISTICS (CE, TRICKLE)

V_{IN_LO}

Input low threshold voltage

0.8

V

V_{IN_HI}

Input high threshold voltage

PIN pull down resistance inside IC

2.1

R_PULLDOWN

T_{CE_ENCHARGE}

V = 0 to V_REGN

1

MΩ

Delay from CE=HIGH to charge

enable

F_s=300 kHz - 800 kHz

2

ms

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ELECTRICAL CHARACTERISTICS (continued)

8.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

LOGIC INPUT PIN CHARACTERISTICS (CELLS)

V_{IN_LO}

Input low threshold voltage, 3 cells

Input mid threshold voltage, 2 cells

CELLS voltage falling edge

0.5

1.8

CELLS voltage rising for MIN,

CELLS voltage falling for MAX

V_{IN_MID}

0.8

V

V_{IN_HI}

Input high threshold voltage, 4 cells

CELLS voltage rising

VCE = 0 to VREGN

2.5

–1

I_{BIAS_FLOAT}

Input bias float current for 2 cell

selection

1

µA

OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( EXTPWR, DPMDET, LPMOD)

V_{OUT_LO}

Output low saturation voltage

Leakage current

Sink Current = 5 mA

Pull up to 3.3 v

0.5

1

V

µA

ms

DPMDET delay, both edge

5

10

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TYPICAL CHARACTERISTICS

Table of Graphs⁽¹⁾F_s=400 kHz, Ta = 25 °C

Y

X

Figure

VREF Load and Line Regulation

REGN Load and Line Regulation

BAT Voltage

vs Load Current

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

vs Load Current

vs VADJ/VDAC Ratio

vs Setpoint

BAT Voltage Regulation Accuracy

Charge Current

vs ISET/VDAC Ratio

vs V(CSP-CSN) Setpoint

vs ACSET/VDAC Radio

vs V(ACP-ACN) Setpoint

vs Charge Current

vs V(ACP-ACN) Voltage

vs BAT Voltage

Charge Current Regulation Accuracy

Input Current

DPM Accuracy

BAT Voltage Regulation Accuracy

V_IADAPT Accuracy

Trickle Charge Current

DPM and Charge Current

vs System Current

REF, REGN, and EXTPWR Startup (CE=HIGH)

Transient System Load (DPM) Response Transistion

Transient Response of IADAPT and LPMOD

Battery Overcurrent Protection (OCP)

Battery to Ground Short Transistion

Battery to Ground Short Protection

Charge Enable and Current Soft-Start

Charge Disable

Trickle Disable and Current Soft-Start

Synchronous to Non-synchronous Transistion

Non-synchronous to Synchronous Transistion

Continuous Conduction Mode Switching Waveforms

Efficiency

vs Battery Charge Current

vs Setting Resistor

Switch Frequency

(1) Test results based on Figure 2 application schematic. V_IN= 20 V, V_BAT= 3-cell LiIon, I_CHG= 3 A, I_{ADAPTER_LIMIT}= 4 A, T_A= 25°C, unless

otherwise specified.

VREF LOAD AND LINE REGULATION

REGN LOAD AND LINE REGULATION

vs

Load Current

LOAD CURRENT

0

0.50

0.40

-0.50

-1

0.30

0.20

0.10

PVCC = 10 V

-1.50

-2

PVCC = 10 V

0

PVCC = 20 V

-2.50

-3

-0.10

-0.20

PVCC = 20 V

40 50

0

10

20

30

40

50

0

10

20

30

60

70

80

VREF - Load Current - mA

REGN - Load Current - mA

Figure 3.

Figure 4.

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BAT VOLTAGE

vs

VADJ/VDAC RATIO

BAT VOLTAGE REGULATION ACCURACY

vs

SETPOINT

0.06

0.05

0.04

13.6

3-Cell

13.4

13.2

13

0.03

0.02

0.01

12.8

12.6

0

12.4

12.2

12

-0.01

-0.02

12

12.2

12.4

12.6

12.8

13

13.2

13.4

13.6

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

VADJ/VDAC Ratio

1

VBAT_reg Setpoint (V)

Figure 5.

Figure 6.

CHARGE CURRENT

vs

CHARGE CURRENT REGULATION ACCURACY

vs

ISET/VDAC

V(CSP-CSN) SETPOINT

5

25

20

15

10

5

4.5

3-Cell

4

3.5

3

2.5

2

1.5

1

0.5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0

10

20

30

40

50

60

70

80

90

100

ACSET/VDAC Ratio

ICHG_reg Setpoint (mV)

Figure 7.

Figure 8.

INPUT CURRENT

vs

ACSET/VDAC RATIO

DPM ACCURACY

vs

V(ACP-ACN) SETPOINT

10

9

2

3-Cell

0

8

7

6

5

4

3

2

1

-2

-4

-6

-8

-10

0

10

20

30

40

50

60

70

80

90

100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

IIN_reg Setpoint (mV)

VACSET/VDAC

Figure 9.

Figure 10.

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BAT VOLTAGE REGULATION ACCURACY

V_IADAPT ACCURACY

vs

V(ACP-ACN) VOLTAGE

vs

CHARGE CURRENT

0.030

0.025

0.020

0.015

0.010

0.005

0.00%

-0.50%

-1.00%

-1.50%

-2.00%

-2.50%

-3.00%

-3.50%

-4.00%

-4.50%

-5.00%

0.000

0

10

20

30

40

50

60

70

80

90

100

0

0.5

1

1.5

2

2.5

3

3.5

4

Charge Current (A)

V(ACP-ACN) (mV)

Figure 11.

Figure 12.

TRICKLE CHARGE CURRENT

DPM and CHARGE CURRENT

vs

BAT VOLTAGE

SYSTEM CURRENT

4.5

0.165

4

VBAT 0 V to 12.6 V

3.5

0.16

Input Current 3 A

3

2.5

0.155

2

1.5

1

Charge Current 3 A

0.15

VBAT 12.6 V to 0 V

0.5

0.145

0

2

4

6

8

10

12

14

0.5

1

1.5

2

2.5

3

3.5

4

BAT Voltage (V)

System Current (A)

Figure 13.

Figure 14.

REF, REGN, and EXTPWR

STARTUP (CE=HIGH)

TRANSIENT SYSTEM LOAD

(DPM) RESPONSE TRANSISTION

Isys

EXTPWR

I_IN

Ibat

Time = 200 μs/div

Time =400 μs/div

Figure 15.

Figure 16.

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TRANSIENT RESPONSE

of

BATTERY OVERCURRENT PROTECTION

(OCP)

IADAPT and LPMOD

VBAT

ISYS

I_L

Iadapt

SW

LPMOD

LODRV

Time = 20 μs/div

Time = 100 μs/div

Figure 17.

Figure 18.

BATTERY TO GROUND

SHORT TRANSISTION

BATTERY TO GROUND

SHORT PROTECTION

I_L

VBAT

Vbat

SW

LODRV

Time = 10 μs/div

Time = 2 ms/div

Figure 19.

Figure 20.

CHARGE ENABLE

and

CURRENT SOFT-START

CHARGE DISABLE

CE

I_L

SW

LODRV

Time = 4 μs/div

Time = 2 ms/div

Figure 21.

Figure 22.

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TRICKLE DISABLE

and

CURRENT SOFT-START

SYNCHRONOUS

to

NON-SYNCHRONOUS TRANSIsTION

TRICKLE

SW

LODRV

I_L

Time = 2 ms/div

Time = 2 μs/div

Figure 23.

Figure 24.

NON-SYNCHRONOUS

to

SYNCHRONOUS TRANSISTION

CONTINUOUS CONDUCTION MODE

SWITCHING WAVEFORMS

SW

HIDRV

LODRV

SW

LODRV

I_L

Time = 200 ns/div

Time = 2 μs/div

Figure 25.

Figure 26.

EFFICIENCY

vs

BATTERY CHARGE CURRENT

SWITCH FREQUENCY

vs

SETTING RESISTOR

1200

100

4-Cell 16.8 V

Measurment

Calculation

1000

95

90

85

80

800

600

3-Cell 12.6 V

400

200

0

50

100

150

200

250

300

0

0.5

1

1.5

2

2.5

3

3.5

4

R_FET (kOhm)

Charge Current (A)

Figure 27.

Figure 28.

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FUNCTIONAL BLOCK DIAGRAM

ENA_BIAS_CMP

-

0.6V

AC_VGOOD

AC_IGOOD

EXTPWR

-

2.4V

+

ACGOOD

+

ACDET

VREF

+

-

VAC20X

250mV

3.3V

LDO

ENA_BIAS

PVCC

VREFGOOD

+

-

UVLO

PVCC

+

EAI

BAT

PVCC-BAT

-

ACP

ACN

FBO

EAO

900mV

+

VAC20X

IIN_REG

IIN_ER

20X

-

CE

-

COMP

ERROR

AMPLIFIER

+

1 MΩ

BTST

CE

-

+

BAT_ER

ICH_ER

-

BAT

CSP

1V

VBAT_REG

VSR20X

LEVEL

SHIFTER

HIDRV

SW

+

3.5 mA

20 µA

DC-DC

CONVERTER

PWM LOGIC

+

20X

-

BAT_SHORT

+

CSN

PVCC-BAT

SYNCH

3.5 mA

20 µA

PVCC

AC_VGOOD

CLK

REGN

LODRV

PGND

IADAPT

CHRG_ON

6V LDO

IBAT_ REG

60mV

VREFGOOD

CE

REFRESH

TRICKLE

FSET

-

BTST

4V

CBTST

+

1 MΩ

+

_

OSC

CLK

SW

ACSET

SRSET

IC Tj

TSHUT

+

-

155 °C

+

VAC20X

V(IADAPT)

20x

-

VBATSET

IBATSET

IINSET

VBAT_REG

IBAT_REG

IIN_REG

-

104% X VBAT_REG

BAT

BAT_OVP

+

VADJ

RATIO

PROGRAM

DPMDET

DPM_LOOP_ON

-

2.08 V / 2.5 V

VSR20X

CHG_OCP

ACOV

+

VDAC

+

-

VSR20X

30mV

SYNCH

ACDET

+

-

CELLS

+

-

3.1V

VAC20X

+

-

+

-

1.7 V

BAT

BAT_SHORT

LPREF

PVCC

-

AGND

PGND

UVLO

+

LPMOD

+

8V

-

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DETAILED DESCRIPTION

Converter Operation

The synchronous buck PWM converter uses a programmable-frequency (300 kHz to 800 kHz) voltage mode

control scheme. A type III compensation network allows using ceramic capacitors at the output of the converter.

The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier

input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error

amplifier output (EAO). The LC output filter should be selected to give a nominal resonant frequency within 8 kHz

to 12.5 kHz to have good loop compensation.

Where resonant frequency, f_o, is give by:

1

f_o=

2p L_oC_o

(1)

An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the

converter. The ramp height is fixed 1.33 V. The ramp is offset by 300 mV in order to allow zero percent

duty-cycle, when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth

ramp signal in order to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98%

duty-cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin

to SW pin voltage falls below 4 V, then the high-side n-channel power MOSFET is turned off and the low-side

n-channel power MOSFET is turned on to pull the SW node down and recharge the BTST capacitor. Then the

high-side driver returns to 100% duty-cycle operation until the (BTST-SW) voltage is detected to fall low again

due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.

The oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,

charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region.

The charge current sense resistor RSR should be placed with at least half or more of the total output capacitance

placed before the sense resistor contacting both sense resistor and the output inductor; and the other half or

remaining capacitance placed after the sense resistor. The output capacitance should be divided and placed

onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives the best performance; but the

node in which the output inductor and sense resistor connect should have a minimum of 50% of the total

capacitance. This capacitance provides sufficient filtering to remove the switching noise and give better current

sense accuracy. The type III compensation provides Phase boost near the cross-over frequency, giving sufficient

Phase margin.

Synchronous and Non-Synchronous Operation

The charger operates in non-synchronous mode when the sensed charge current is below the charge

under-current comparator threshold (30 mV). Otherwise, the charger operates in synchronous mode. This part is

designed for 20 mΩ charge current sense resistor and the SYNC/NON-SYNC threshold is 1.5 A. If 10 mΩ is

used, the SYNC/NON-SYNC threshold will be 3 A.

During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power

MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent

shoot-through currents. During the 25 ns dead time where both FETs are off, the back-diode of the low-side

power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low,

and allows safely charging at high currents. During synchronous mode the inductor current is always flowing and

operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.

During non-synchronous operation, the low side MOSFET will stay off during the off-time unless the voltage on

the bootstrap capacitor drops below 4 V. If this occurs, the high side FET will be turned off and the 80ns low-side

MOSFET recharge pulse will be initiated. The 80 ns pulse pulls the SW node (connection between high and

low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80

ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. The inductor current is

blocked by the off low-side MOSFET, and the inductor current will become discontinuous. This mode is called

Discontinuous Conduction Mode (DCM).

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During the DCM mode the loop response automatically changes and has a single pole system at which the pole

is proportional to the load current, because the converter does not sink current, and only the load provides a

current sink. This means at very low currents the loop response is slower, as there is less sinking current

available to discharge the output voltage. At very low currents during non-synchronous operation, there may be a

small amount of negative inductor current during the 80ns recharge pulse. The charge should be low enough to

be absorbed by the input capacitance.

Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the

low-side MOSFET does not turn on (no 80ns recharge pulse) either, and there is no discharge from the battery.

Battery Voltage Regulation

The bq24741 uses a high-accuracy voltage regulator for charging voltage. The regulation voltage is ratio-metric

with respect to VDAC. The ratio of VADJ and VDAC provides extra 12.5% adjust range on V_BATTregulation

voltage. By limiting the adjust range to 12.5% of the regulation voltage, the external resistor mismatch error is

reduced from ±1% to ±0.1%. Therefore, an overall voltage accuracy as good as 0.5% is maintained, while using

1% mis-match resistors. Ratio-metric conversion also allows compatibility with D/As or microcontrollers (µC). The

battery voltage is programmed through VADJ and VDAC using the following equation:

é

ù

ú

û

æ

ö

÷

ø

V_VADJ

V_BATT= cell count ´ 4 V + 0.512´

ê

ç

V_VDAC

ê

ë

è

(2)

The input voltage range of VDAC is between 2.6V and 3.6V. VADJ is set between 0 and VDAC.

CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2, 3, or 4 Li+ cells. When

charging other cell chemistries, use CELLS to select an output voltage range for the charger.

Table 2. Cell-Count Selection

CELLS

Float

CELL COUNT

2

3

4

AGND

VREF

The per-cell battery termination voltage is function of the battery chemistry. Consult the battery manufacturer to

determine this voltage.

The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the

battery as possible, or directly on the output capacitor. A 0.1µF ceramic capacitor from BAT to AGND is

recommended to be as close to the BAT pin as possible to decouple high frequency noise.

Battery Current Regulation

The ISET input sets the maximum charging current. Battery current is sensed by resistor RSR connected

between CSP and CSN. The full-scale differential voltage between CSP and CSN is 100 mV. Thus, for a 0.020 Ω

sense resistor, the maximum charging current is 5 A. ISET is ratio-metric with respect to VDAC using the

following equation:

V

0.10

ISET

´

I_CHARGE

=

V_VDACR_SR

The input voltage range of ISET is between 0 and VDAC, up to 3.6 V.

The CSP and CSN pins are used to sense across R_SRwith default value of 20 mΩ. However, resistors of other

values can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation

accuracy; but, at the expense of higher conduction loss.

18

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Trickle Charge Current Regulation

The TRICKLE pin is provided to allow accurate current regulation at very low charge current. When CE is set to

HIGH, a logic HIGH level is applied to the TRICKLE pin, the charger will regulate 3 mV from CSP to CSN (150

mA with a 20 mΩ sense resistor), regardless of the voltage applied to the ISET pin. When TRICKLE is LOW,

ISET is used to program the charge current.

Input Adapter Current Regulation

The total input current from an AC adapter or other DC sources is a function of the system supply current and

the battery charging current. System current normally fluctuates as portions of the systems are powered up or

down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system

current and the maximum charger input current simultaneously. By using DPM, the input current regulator

reduces the charging current when the input current exceeds the input current limit set by ACSET. The current

capacity of the AC adapter can be lowered, reducing system cost.

Similar to setting battery-regulation current, adapter current is sensed by resistor R_ACconnected between ACP

and ACN. Its maximum value is set by ACSET, which is ratiometric with respect to VDAC, using Equation 3.

V_ACSET

´

0.10

I_ADAPTER

=

V_VDACR_AC

(3)

The input voltage range of ACSET is between 0 and V_DAC, up to 3.6 V.

The ACP and ACN pins are used to sense R_ACwith a default value of 10 mΩ. However, resistors of other values

can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy.

However, this is at the expense of a higher conduction loss.

Adapter Detect and Power Up

An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect

threshold should typically be programmed to a value greater than the maximum battery voltage and lower than

the minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense

the true adapter input voltage whether the ACFET is on or off.

If ACDET is below 0.6 V but PVCC is above 8 V, part of the bias is enabled, including a crude bandgap

reference, IADAPT is disabled and pulled down to GND. The total quiescent current is less than 10 µA.

Once ACDET rises above 0.6 V and PVCC is above 8 V, all the bias circuits are enabled and VREF goes to 3.3

V; and REGN output goes to 6 V if CE is HIGH. IADAPT becomes valid to proportionally reflect the adapter

current.

When ACDET keeps rising and passes 2.4 V, a valid AC adapter is present. 8 ms later, charge is allowed to turn

on.

Programming the PWM Switching Frequency

To program the PWM switching frequency, place a resistor from the FSET pin to ground, according to the

following formula:

41´10³

R_FSET

=

- 6.25 (kW)

F_s

Where R_FSET(kΩ) is the resistor from the FSET pin to ground, and F_s(kHz) is the desired switching frequency.

The switching frequency should be programmed between 300 kHz and 800 kHz.

Enable and Disable Charging

The following conditions must be valid before the charge function is enabled:

•

CE is HIGH

Adapter is detected

Adapter voltage is higher than PVCC-BAT threshold

Adapter is not over voltage

The VREF and REGEN regulators are above 90% of the final values

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•

Thermal Shut (TSHUT) is not active

The PWM frequency is programmed inside the allowable range

There’s a 8ms charge enable delay from when adapter is detected to when the charger is allowed to turn on.

One of the following conditions will stop on-going charging:

•

CE is LOW

Adapter is removed

Adapter Voltage is lower than PVCC-BAT threshold

Adapter is over voltage

Adapter is over current

TSHUT IC temperature threshold is reached (155 °C on rising-eduge with 20 °C hysteresis).

Automatic Internal Soft-Start Charger Current

The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure

there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of

stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current. Each

step lasts around 1ms, for a typical rise time of 8ms. No external components are needed for this function.

High Accuracy IADAPT Using Current Sense Amplifier (CSA)

An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the

host or some discrete logic through the analog voltage output of the IADAPT pin. The CSA amplifies the input

sensed voltage of ACP–ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 times

the input differential voltage. Once PVCC is above 8 V and ACDET is above 0.6 V, IADAPT no longer stays at

ground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from IOUT to

AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients.

Input Overvoltage Protection (ACOV)

ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage is 30%

above adapter detect voltage, (ACDET pin voltage is 30% above 2.4 V (2.4 V X 130% = 3.1 V), charge is

disabled. ACOV does not latch, and normal operation resumes when ACDET < 3.1 V.

Input Undervoltage Lock Out (UVLO)

The system must have a minimum 8 V PVCC voltage to allow proper operation. This PVCC voltage could come

from either input adapter or battery, using a diode-OR input. When the PVCC voltage is below 8 V the bias

circuits REGN and VREF stay inactive, even with ACDET above 0.6 V.

Battery Overvoltage Protection

The converter will not allow the high-side FET to turn-on until the BAT voltage goes below 102% of the regulation

voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load is removed

or the battery is disconnected.

Charge Overcurrent Protection

The charger has a secondary over-current protection. It monitors the charge current, and prevents the current

from exceeding 6.25A peak value with a 20 mΩ sensing resistor. The high-side gate drive turns off when the

over-current is detected, and automatically resumes at the next switching cycle that occurs after the current falls

below the OCP threshold. When the BAT-GND short is detected, the charger will be automatically shut down

immediately and then restarts again 100 µs later..

Thermal Shutdown Protection

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the

ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and

self-protects whenever the junction temperature exceeds the TSHUT threshold of 155 °C. The charger stays off

until the junction temperature falls below 135 °C.

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Input Low Power Detection

In order to optimize the system performance, the HOST keeps an eye on the adapter current. Once the adapter

current is above a threshold set via LPREF, the LPMOD pin sends a signal to the HOST. The signal alarms the

host that input power has exceeded the programmed limit. The LPMOD pin is an open-drain output. Connect a

pull-up resistor to LPMOD. The LPMOD output is logic LOW when the 20X current sense voltage (20 x

V_(ACP-ACN)) is higher than the LPREF input voltage. The LPREF threshold may be set by an external resistor

divider using VREF, or may be programmed from a resistor divider off of ACSET to maintain an LPREF voltage

proportional to the adapter current. The LPMOD comparator has an internal 6% hysteresis built in.

ACDET

AC_VGOOD

+

-

2.4 V

ACVDET

Comparator

EXTPWR

ACP

ACN

Adaptor

Current Sense

Amplifier

1 kΩ

+

-

ACIDET

Comparator

250 mV

(1.25 A)

-

AC_IGOOD

+

IADAPT Error

Amplifier

Disable

20 kΩ

20xV(ACP-ACN)

-

IADAPT

+

IADAPT

Disable

IADAPT

OUTPUT

BUFFER

LPMOD

Comparator

LPMOD

+

-

LOPWR_DET

LPREF

Hysteresis = 6%

Figure 29. EXTPWR, LPREF, and LPMOD Logic

Status Outputs (EXTPWR, LPMOD, DPMDET Pin)

Three status outputs are available, and they all require external pull up resistors to pull the pins to system digital

rail for a high level.

EXTPWR open-drain output goes low under each of the three conditions:

1. ACDET is above 2.4 V

2. Adapter current is above 1.25 A using a 10mohm sense resistor (IADAPT voltage above 250 mV)

Internally, the AC current detect comparator looks between the output of the 20x adapter current amplifier and an

internal 250mV threshold. EXTPWR indicates a good adapter is connected because of valid voltage or current.

LPMOD output goes low when the input current is higher than the programmed threshold via LPREF pin.

Hysteresis is internally set to 6% of the programmed LPMOD threshold.

DPMDET open-drain output goes low when the DPM loop is active to reduce the battery charge current.

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Table 3. Component List for Typical System Circuit of Figure 1

PART DESIGNATOR

QTY

3

DESCRIPTION

Q1, Q2, Q3

P-channel MOSFET, -30V,-6A, SO-8, Vishay-Siliconix, Si4435

N-channel Dual-MOSFET, 30V, 7.5A, SO-8, Fairchild, FDS8978

Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C

Sense Resistor, 10mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100F

Sense Resistor, 20mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0200F

Inductor, 10µH, 24.8mΩ Vishay-Dale, IHLP5050CE-01

Capacitor, Ceramic, 2.2µF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E225M

Capacitor, Ceramic, 10µF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106M

Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K

Capacitor, Ceramic, 100nF, 25V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU

Capacitor, Ceramic, 0.1µF, 50V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU

Capacitor, Ceramic, 100pF, 25V, 10%, X7R, 0805, Kemet, C0805C101K5RACTU

Resistor, Chip, 10kΩ, 1/16W, 5%, 0402

Q4

1

D1, D2

2

R_AC

1

R_SR

1

L1

1

C1

1

C6, C7, C11, C12

4

C4, C10

2

C13

1

C2, C3, C8, C9, C13, C14, C15, C16

6

C5

1

R3, R4, R5, R15

4

R1

1

Resistor, Chip, 464kΩ, 1/16W, 1%, 0402

R2

1

Resistor, Chip, 66.5kΩ, 1/16W, 1%, 0402

R6

1

Resistor, Chip, 97.6kΩ, 1/16W, 1%, 0402

R7

1

Resistor, Chip, 73.2kΩ, 1/16W, 1%, 0402

R8

1

Resistor, Chip, 26.7kΩ, 1/16W, 1%, 0402

R14

R11

R9

1

Resistor, Chip, 120kΩ, 1/16W, 1%, 0402

1

Resistor, Chip, 2Ω, 1W, 5%, 2012

1

Resistor, Chip, 60.4KΩ, 1/16W, 1%, 0402

R10

R12

R13

1

Resistor, Chip, 40.2KΩ, 1/16W, 1%, 0402

1

Resistor, Chip, 102KΩ, 1/16W, 1%, 0402

1

Resistor, Chip, 64.9KΩ, 1/16W, 1%, 0402

22

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APPLICATION INFORMATION

PCB Layout Design Guideline

1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.

Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the

other layers.

2. The control stage and the power stage should be routed separately. At each layer, the signal ground and the

power ground are connected only at the power pad.

3. The AC current-sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact. The

area of this loop must be minimized. An additional 0.1µF decoupling capacitor for ACN is reqired to further

reduce the noise. The decoupling capacitors for these pins should be placed as close to the IC as possible.

4. The charge-current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact.

The area of this loop must be minimized. An additional 0.1µF decoupling capacitor for SRN is required to

further reduce the noise. The decoupling capacitors for these pins should be placed as close to the IC as

possible.

5. Decoupling capacitors for PVCC (pin 28), VREF (pin 10), REGN (pin 24) should be placed underneath the IC

(on the bottom layer) with the interconnections to the IC as short as possible.

6. Decoupling capacitors for BAT (pin 17), IADAPT (pin 15) must be placed close to the corresponding IC pins

with the interconnections to the IC as short as possible.

7. Decoupling capacitor CX for the charger input must be placed very close to the MOSFET's drain and source.

Refer to the EVM design (SLUU284) for the recommended component placement with trace and via locations.

For the QFN information, please refer to SCBA017 and SLUA271.

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PACKAGE OPTION ADDENDUM

www.ti.com

3-Apr-2009

PACKAGING INFORMATION

Orderable Device

BQ24741RHDR

BQ24741RHDT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RHD

28

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

RHD

28

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Apr-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

BQ24741RHDR

BQ24741RHDT

QFN

RHD

28

3000

250

330.0

180.0

12.4

5.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Apr-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24741RHDR

BQ24741RHDT

QFN

RHD

28

3000

250

346.0

190.5

346.0

212.7

29.0

31.8

Pack Materials-Page 2

IMPORTANT NOTICE

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型号：	BQ24741RHDT
厂家：	TEXAS INSTRUMENTS
描述：	Li-Ion or Li-Polymer Battery Charger with Low Iq and Accurate Trickle Charge 锂离子或锂聚合物电池充电器具有低Iq和准确的涓流充电电池
文件：	总30页 (文件大小：1379K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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