BQ25180YBGR [TI]
采用 WCSP 封装且具有稳压电源路径的 1A 锂离子和磷酸铁锂 I²C 可编程线性充电器 | YBG | 8 | -40 to 85;
| 型号： | BQ25180YBGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 WCSP 封装且具有稳压电源路径的 1A 锂离子和磷酸铁锂 I²C 可编程线性充电器 | YBG | 8 | -40 to 85 |
| 文件： | 总58页 (文件大小：2016K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ25180
ZHCSPC2C –SEPTEMBER 2021 –REVISED JANUARY 2023
BQ25180 具有电源路径和运输模式的I2C 控制型1 节电池1A 线性电池充电器
1 特性
2 应用
• 1A 电源路径线性电池充电器
• TWS 耳机和充电盒
• 智能眼镜、AR 和VR
• 智能手表和其他可穿戴设备
• 零售自动化和支付
• 楼宇自动化
– 已针对电池间充电和USB 适配器优化的3.0V
至5.9V 输入电压工作范围
– 可耐受25V 的输入电压
– 可配置的电池调节电压，精度为0.5%，范围为
3.6V 至4.65V，阶跃为10mV
– 5mA 至1A 的可配置快速充电电流
3 说明
BQ25180 是一款线性电池充电器 IC，专注于小解决方
案尺寸和低静态电流以延长电池寿命。该器件采用 8
焊球芯片级封装，无需采用 HDI PCB 工艺进行制造，
从而降低了 PCB 成本。该器件可支持高达 1A 的充电
电流和高达2.5A 的系统负载。
– 55mΩ电池FET 导通电阻
– 高达2.5A 的放电电流，支持高系统负载
– 可配置的终止电流，支持低至0.5mA
– 可配置的NTC 充电曲线阈值，包括JEITA 支持
– 用于恢复系统的下电上电和高级复位机制
• 电源路径管理，用于系统供电和电池充电
器件信息
封装(1)
封装尺寸（标称值）
– 稳定系统电压(SYS) 范围为4.4V 至4.9V，此外
还具有电池电压跟踪功能和输入直通选项
– 可配置的输入电流限制
器件型号
BQ25180
DSBGA (8)
1.6 mm x 1.1 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 系统可选择适配器或电池电源
– 动态电源路径管理可以对通过弱适配器充电进行
优化
• 超低静态电流模式
SYS
IN
Regulated
Load
VBUS
– 关断模式下为15nA
10uF
1uF
– 运输模式下为3.2μA，支持按钮唤醒
– 仅电池模式下为3μA
– 睡眠模式下输入适配器Iq 为30μA
• 单按钮唤醒和复位输入
• 集成故障保护
/INT
Device
Control
SCL
SDA
BAT
Host
1uF
+
–
VIO
TS/MR
– 输入过压保护(VIN_OVP
– 电池欠压保护(VBUVLO
)
)
NTC
BQ25180
– 电池短路保护(BATSC)
– 电池过流保护(BATOCP)
– 输入电流限制保护(ILIM)
– 热调节(TREG) 和热关断(TSHUT)
– 电池热故障保护(TS)
– 看门狗和安全计时器故障
– 系统短路保护
GND
简化版原理图
– 系统过压保护
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSE99
BQ25180
www.ti.com.cn
ZHCSPC2C –SEPTEMBER 2021 –REVISED JANUARY 2023
Table of Contents
8.4 Device Functional Modes..........................................25
8.5 Register Maps...........................................................26
9 Application and Implementation..................................41
9.1 Application Information............................................. 41
9.2 Typical Application.................................................... 41
10 Power Supply Recommendations..............................48
11 Layout...........................................................................49
11.1 Layout Guidelines................................................... 49
11.2 Layout Example...................................................... 49
12 Device and Documentation Support..........................50
12.1 Device Support....................................................... 50
12.2 接收文档更新通知................................................... 50
12.3 支持资源..................................................................50
12.4 Trademarks.............................................................50
12.5 静电放电警告.......................................................... 50
12.6 术语表..................................................................... 50
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Thermal Information....................................................5
7.4 Recommended Operating Conditions.........................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements................................................10
7.7 Typical Characteristics.............................................. 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................16
8.3 Feature Description...................................................16
Information.................................................................... 51
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (January 2022) to Revision C (January 2023)
Page
• Removed figure from 节8.3.1 ..........................................................................................................................16
Changes from Revision A (December 2021) to Revision B (January 2022)
Page
• Removed operating ambient...............................................................................................................................5
• Removed OTP_VLOWV.....................................................................................................................................6
• Removed Standalone......................................................................................................................................... 6
• Removed /PG Isink.............................................................................................................................................6
• Removed tHW_RESET and FI2C_CLK ....................................................................................................................10
• Updated conditions for Typical Characteristics ................................................................................................ 11
• Added legend for 图7-1 ...................................................................................................................................11
• Changed 图8-4 and 图8-5 ..............................................................................................................................21
• Changed MR input to Pushbutton input in 表8-6 ............................................................................................ 25
• Updated Section 8.5 Register Maps reset values.............................................................................................26
• Changed Device_ID description in the 表8-21 ................................................................................................26
Changes from Revision * (September 2021) to Revision A (December 2021)
Page
• 将“预告信息”更改为“量产数据”.................................................................................................................. 1
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ZHCSPC2C –SEPTEMBER 2021 –REVISED JANUARY 2023
5 说明（续）
该器件采用标准锂离子或磷酸铁锂充电曲线分三个阶段对电池进行充电：预充电、恒流和恒压。通过热调节提供
最大充电电流，同时管理器件温度。该充电器还针对电池间充电进行了优化，具有3V 的最低输入电压，并且可以
承受25V 的绝对最大线路瞬变。该器件集成了单按钮输入和复位电路，以减小解决方案的总尺寸。
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ZHCSPC2C –SEPTEMBER 2021 –REVISED JANUARY 2023
6 Pin Configuration and Functions
1
2
A
B
C
/INT
IN
SCL
SYS
SDA
BAT
D
TS/MR
GND
图6-1. YBG Package 8-Pin DSBGA (Top View)
表6-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
IN
A2
P
DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with at
least 1 μF of capacitance using a ceramic capacitor.
SYS
BAT
B2
C2
P
P
Regulated System Output. Connect at least 10-μF ceramic capacitor (at least >1 μF of
ceramic capacitance with DC bias derating) from SYS to GND as close to the SYS and GND
pins as possible.
Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at
least 1 μF of ceramic capacitance.
GND
SCL
SDA
/INT
D2
B1
C1
A1
-
Ground connection. Connect to the ground plane of the circuit.
I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ pullup resistor.
I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ pullup resistor.
I/O
I/O
O
INT is an open-drain output that signals fault interrupts. When a fault occurs, a 128-μs active
low pulse is sent out as an interrupt for the host. INT is enabled/disabled using the MASK_INT
bit in the control register. Can be pulled up to the logic rail through a 1-kΩ to 20-kΩ resistor.
TS/MR
D1
I/O
Manual Reset Input/ NTC thermistor pin. TS/MR is a general purpose input that must be held
low for greater than tLPRESS to go into Ship mode or perform a hardware reset. It can also be
used to detect shorter button press durations such as tWAKE1 and tWAKE2 TSMR may be driven
by a momentary push-button or a MOS switch. The TSMR pin can also have an NTC thermistor
connected on to it.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
MAX
25
UNIT
Input Voltage
IN
V
V
A
A
Voltage
All other pins
5.5
1.1
1.5
Input Current (DC)
SYS Discharge Current(DC)
IN
SYS
SYS Discharge Current (tpulse
<20ms)
SYS
2.5
A
Output Sink Current
/INT
20
150
150
mA
°C
TJ
Junction temperature
Storage temperature
-40
-65
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Thermal Information
BQ25180
THERMAL METRIC
YBG (DSBGA)
UNIT
8 PIN
65
RθJA
Junction-to-ambient thermal resistance (EVM(2)
)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance (JEDEC(1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
)
107.1
0.9
RθJC(top)
RθJB
30.3
0.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
30.3
N/A
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) 1oz Copper, 2-layer board
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2
NOM
MAX
4.6
UNIT
V
VBAT
VIN
Battery Voltage Range
Input Voltage Range
2.7
5.5
V
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7.4 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
A
IIN
Input Current Range (IN to SYS)
1.1
1.5
IBAT
TJ
Battery Discharge Current (BAT to SYS)
Operating Junction Temperature Range
A
-40
125
°C
7.5 Electrical Characteristics
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VBAT = 3.6V, VIN = 5V, Charge enabled,
ICHG = 0mA, SYSREG = 4.5V
IQ_IN
IQ_IN
Input supply quiescent current
Input supply quiescent current
0.75
1
mA
VBAT = 3.6V, VIN = 5V, Charge enabled,
ICHG = 0mA, SYSREG = Passthrough
0.660
30
0.850
mA
µA
ISLEEP_IN SLEEP input current
VIN = 3.6V, VBAT = 3.7V
VIN <VUVLO or floating, Watchdog
disabled, Push button disabled, I2C
functional. VBAT =3.6V TJ = 25°C
IQ_BAT
Battery quiescent current
3
3.5
5
µA
VIN <VUVLO , VBAT =3.6V, Push-button
function enabled, 0°C < TJ < 85°C
IQ_BAT
Battery quiescent current
4
µA
nA
IBAT_SHUT
VIN = 0V, Ship Mode, VBAT = 3.6V,
Adapter Sense wake enabled.
Battery discharge current in Ship Mode
15
DOWN
VBAT = 3.6V, Push button function
enabled (average current), 0°C < TJ <
85°C
IBAT_SHIP Battery discharge current in Ship Mode
3.2
4.5
µA
POWER-PATH MANAGEMENT AND INPUT
VIN_OP
Input voltage operating range
Exit IN undervoltage lock-out
3
5.5
3
V
V
VIN_UVLO
IN rising
Z
VIN_UVLO Enter IN undervoltage lock-out
VIN_LOWV IN voltage to start charging
IN falling
IN rising
2.7
V
V
3
3.15
VIN_LOWV
IN voltage to stop charging
IN falling
2.95
3.1
V
Z
VIN_PORZ IN voltage threshold to enter shipmode
IN falling
1.09
100
1.3
135
72
1.66
185
V
mV
mV
V
VSLEEPZ Exit sleep mode threshold
IN rising, VIN - VBAT, VBAT= 4V
IN falling, VIN - VBAT, VBAT= 4V
IN rising
VSLEEP
Sleep mode threshold hysteresis
VIN_OVP VIN overvoltage rising threshold
5.5
5.7
5.9
VIN_OV_H
IN overvoltage hysteresis
IN falling
125
mV
YS
VBAT = 3.6V, IBAT_OCP= 00
VBAT = 3.6V, IBAT_OCP= 01
VBAT = 3.6V, IBAT_OCP= 10
VBAT = 3.6V, IBAT_OCP= 11
0.5
1
A
A
A
A
IBAT_OCP BATOCP(Reverse OCP only)
1.5
Disabled
VBAT = 3.6V, VBAT > VBUVLO, VSYS<
VBAT-VBSUP1
VBSUP1 Enter supplement mode threshold
VBSUP2 Exit supplement mode threshold
40
20
mV
mV
VBAT > VBUVLO, VSYS>VBAT-VBSUP2
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7.5 Electrical Characteristics (continued)
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
50
MAX
60
UNIT
mA
mA
mA
mA
mA
mA
mA
mA
VIN = 5V, ILIM =50mA
40
VIN = 5V, ILIM =100mA
VIN = 5V, ILIM= 200mA
VIN = 5V, ILIM= 300mA
VIN = 5V, ILIM= 380mA
VIN = 5V, ILIM= 500mA
VIN = 5V, ILIM =665mA
VIN = 5V, ILIM= 1050mA
80
90
98
180
270
360
450
630
995
200
300
380
475
665
1050
220
330
400
498
700
1100
ILIM
Input Current Limit
VINDPM_A
VINDPM accuracy
VINDPM target is not disabled
VINDPM target =4.2V
VINDPM target =4.5V
VINDPM target =4.7V
-3
3
%
V
V
V
V
CC
Input voltage threshold when input current
is reduced
4.2
4.5
4.7
0.1
Input voltage threshold when input current
is reduced
VINDPM
Input voltage threshold when input current
is reduced
SYS voltage threshold when charge
current is reduced
VBAT = 3.6V, VSYS = VDPPM + VBAT
before charge current is reduced.
VDPPM
VSYS_REG
Programmable SYS voltage regulation
accuracy
VIN = 5V, VBAT = 3.6V, RSYS = 100ohm,
SYS regulation target = 4.4V to 4.9V
-2
2
%
V
_ACCURAC
Y
Minimum SYS voltage when in battery
tracking mode
VMINSYS
VBAT < 3.6V
3.8
Voltage regulation threshold for SYS
when VBAT >3.6V in battery tracking
mode
VSYS_TRA
VBAT = 4V, VSYS = VBAT + VSYS_TRACK
VSYS = 3.6V
225
25
mV
CK
RSYS_PD SYS pull down resistance
BATTERY CHARGER
Ω
RON_BAT Battery FET on-resistance
VBAT = 4.5V, IBAT =500mA
IN = 5V, IIN = 1A
55
90
mΩ
mΩ
RON_IN
VREG_RA Typical BAT charge voltage regulation
range
Input FET on-resistance
270
470
10mV steps, programmabe through I2C
3.5
–0.5
5
4.65
0.5
V
%
NGE
VREG_AC BAT charge voltage accuracy, summary
All VBATREG settings, typical
measurement at VBATREG = 4.2V
for all settings
C
ICHG_RAN
Typical charge current regulation range
VOUT > VLOWV
1000
mA
GE
ICHG_ACC Charge current accuracy
VIN = 5V, Fastcharge >=40mA
Fastcharge current = 40mA
Fastcharge current = 630mA
10
44
%
–10
36
ICHG_ACC Charge current accuracy
ICHG_ACC Charge current accuracy
40
mA
mA
567
630
693
Typical pre-charge current, as percentage
IPRECHG
of ICHG
VOUT < VLOWV
20
%
%
IPRECHG_
Precharge current accuracy
Fastcharge current >=40mA
VOUT = VBATREG
10
–10
ACC
Typical termination current, as percentage
of ICHG
% of
Icharge
ITERM
10
ITERM_AC
Termination current accuracy
IBAT = 3mA (IFCHG = 30mA) Tj = 25°C
IBAT = 3mA (IFCHG = 30mA) Tj = 25°C
10
%
–10
C
ITERM_AC
Termination current accuracy
2.7
3.3
mA
C
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7.5 Electrical Characteristics (continued)
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pre-charge to fast-charge transition
threshold
VLOWV
VLOWV
VLOWVSEL = 3.0V, VBAT rising
2.9
3
3.1
2.9
V
Pre-charge to fast-charge transition
threshold
VLOWVSEL = 2.8V, VBAT rising
All settings
2.7
2.8
V
VLOWV_H
Battery LOWV hysteresis
100
mV
YS
Battery UVLO, VBAT falling
Battery UVLO, VBAT falling
Battery UVLO, VBAT falling
Battery UVLO, VBAT falling
Battery UVLO, VBAT falling
Battery UVLO, VBAT falling
BUVLO setting = b000
BUVLO setting = b011
BUVLO setting = b100
BUVLO setting = b101
BUVLO setting = b110
BUVLO setting = b111
3
2.8
2.6
2.4
2.2
2.0
V
V
V
V
V
V
VBUVLO
VBUVLO_H
Any BUVLO Setting, value above VBAT,
VIN = 5V
Battery UVLO hysteresis, VBAT rising
110
150
190
mV
V
YS
Battery only power up voltage, VBAT
rising
VBATPOR
-40C < Tj < 125C
3.08
3.21
3.46
BAT falling, VRCH bit = 0
BAT falling, VRCH bit = 1
75
100
200
130
230
mV
mV
VRCH
175
Short on battery threshold for trickle
charge, VBAT rising
VBATSC
1.6
1.8
2.0
V
VBATSC_H
Battery short circuit voltage hysteresis
Trickle Charge Current
200
8
mV
mA
YS
IBATSC
VBAT<VBATSC
TERMPERATURE REGULATION AND TEMPERATURE SHUTDOWN
TREG
TREG
Typical junction temperature regulation
Typical junction temperature regulation
THERM_REG = 00
THERM_REG = 11
100
°C
Disabled
TSHUT_RI
Thermal shutdown rising threshold
Thermal shutdown falling threshold
Temperature increasing
Temperature decreasing
150
135
°C
°C
SING
TSHUT_FA
LLING
BATTERY NTC MONITOR
ITS_BIAS TS nominal bias current
VT1_Entry Cold - 00 @ Approx. 0°C, default
VT2_Entry Cold - 01 @ Approx. 3°C
VT3_Entry Cold - 10 @ Approx. 5°C
VT4_Entry Cold - 11 @ Approx. -3°C
VT5_Entry Cool - 00 @ Approx. 10°C, default
VT6_Entry Warm - 00 @ Approx. 45°C, default
VT7_Entry Hot - 00 @ Approx. 60°C, default
VT8_Entry Hot - 01 @ Approx. 65°C
VT9_Entry Hot - 10 @ Approx. 50°C
VT10_Entry Hot - 11 @ Approx. 45°C
36.5
0.9575
0.8450
0.7775
1.0850
0.6350
0.1730
0.1050
0.0875
0.1475
0.1750
0.7775
0.6875
0.6350
0.8800
0.5225
38
1.0075
0.8900
0.8200
1.1425
0.6700
0.1850
0.1150
0.0975
0.1575
0.1850
0.8200
0.7250
0.6700
0.9275
0.5500
39.5
1.0575
0.9325
0.8600
1.2000
0.7025
0.198
µA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
0.1250
0.1075
0.1675
0.1950
0.8600
0.7600
0.7025
0.9725
0.5775
VT1_Exit
VT2_Exit
VT3_Exit
VT4_Exit
VT5_Exit
Cold - 00 @ Approx. 5°C, default
Cold - 01 @ Approx. 8°C
Cold - 10 @ Approx. 10°C
Cold - 11 @ Approx. 2°C
Cool - 00 @ Approx. 15°C, default
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7.5 Electrical Characteristics (continued)
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
0.2080
0.1250
0.1050
0.1750
0.2100
TYP
0.2200
0.1350
0.1150
0.1850
0.2200
MAX
0.235
UNIT
VT6_Exit
VT7_Exit
VT8_Exit
VT9_Exit
Warm - 00 @ Approx. 41°C, default
Hot - 00 @ Approx. 55°C, default
Hot - 01 @ Approx. 60°C
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
VIN = 5V
V
V
V
V
V
0.1450
0.1250
0.1950
0.23
Hot - 10 @ Approx. 45°C
VT10_Exit Hot - 11 @ Approx. 40°C
TS monitoring enable threshold
VTS_ENZ VTSMR<VTS_ENZ for TS function to be TS Rising, VIN = 5V
enabled
1.8
2.2
2.1
2.8
2.8
3.3
V
V
VTS_CLAM
TS maximum voltage clamp
TS open-circuit (float), VIN = 5V
P
PUSH BUTTON TIMERS AND THRESHOLDS
ITSMR
ITSMR
Adapter present
36.5
38
60
39.5
µA
µA
Battery only mode
TSMR voltage to detect a button press
event, battery only mode
VTSMR
VTSMR
90
90
mV
mV
TSMR voltage to detect a button press
event, adapter present
MR_WAKE1_TIMER = 0
MR_WAKE1_TIMER = 1
MR_WAKE2_TIMER = 0
MR_WAKE2_TIMER = 1
300
1
ms
s
WAKE1 Timer. Time from TSMR low
detection
tWAKE1
2
s
WAKE2 Timer. Time from TSMR low
detection
tWAKE2
3
s
tRESET_W RESET_WARN Timer. Time prior to HW
MR_RESET_WARN = 0
0.9
1
1.1
s
RESET
ARN
MR_LPRESS = 00
MR_LPRESS = 01
MR_LPRESS = 10
MR_LPRESS = 11
AUTOWAKE = 00
AUTOWAKE = 01
AUTOWAKE = 10
AUTOWAKE = 11
4.5
9
5
10
15
20
0.5
1
5.5
11
s
s
s
s
s
s
s
s
Long Press timer. Time from button press
tLPRESS
detection to long press action.
13.5
18
16.5
22
tRESTART(
RESTART Timer. Time from HW Reset to
SYS power up
AUTOWAKE
2
)
4
BATTERY CHARGING TIMERS
tMAXCHG Charge safety timer
tPRECHG Precharge safety timer
I2C INTERFACE
Programmable range
180
720
0.4
min
0.25 * tMAXCHG
VIL
Input low threshold level
Input high threshold level
Output low threshold level
High-Level leakage current
VPULLUP = 1.8V, SDA and SCL
VPULLUP = 1.8V, SDA and SCL
IL = 5mA, sink current, VPULLUP =1.8V
VPULLUP = 1.8V
V
V
VIH
VOL
ILKG
1.3
0.4
1
V
µA
LOGIC PINS
VOL Output low threshold level
ILKG High-Level leakage current
IL = 5mA, sink current, VPULLUP
=3.3V, /INT pin
0.4
1
V
VPULLUP = 3.3V, /INT pin
µA
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7.6 Timing Requirements
MIN
NOM
MAX
UNIT
INPUT
tVIN_OVPZ_DGL
tSLEEP_DGL
VIN_OVP deglitch, VIN falling
30
64
ms
µs
Deglitch time to enter SLEEP, VIN falling
BATTERY CHARGER
tREC_SC
Recovery time, BATOCP during Discharge Mode
250
2
ms
s
Retry window for SYS or BAT short circuit
recovery(BATOCP)
tRETRY_SC
tBUVLO
Deglitch time to disconnect the BATFET when VBAT <
VBUVLO setting
60
µs
tTS_DUTY_ON
tTS_DUTY_OFF
TS turnon-time (battery only mode)
TS turnoff time (battery only mode)
4
ms
ms
196
DIGITAL CLOCK, WATCHDOG and PUSHBUTTON
tWDOG
I2C interface reset timer, adjustable
40
160 Disabled
s
ms
s
tI2CRESET
tSHIPWAKE
I2C interface inactive reset timer
500
2
Wake timer to count for shipmode (WAKE2 DefaultTimer)
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7.7 Typical Characteristics
VIN = 5 V, CIN = 2.2 µF, COUT = 10 µF, CBAT = 1 µF (unless otherwise specified)
0.05%
0.025%
0
-1.74
-1.77
-1.8
TJ = 25C
TJ = -40C
TJ = 85C
TJ = 105C
-1.83
-1.86
-1.89
-1.92
-1.95
-1.98
-2.01
-2.04
-0.025%
-0.05%
-0.075%
-0.1%
TJ = 25C
TJ = 85C
TJ = 105C
TJ = -40C
-0.125%
-0.15%
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
0
100 200 300 400 500 600 700 800 900
ICHARGE (mA)
VBATREG (V)
VIN = 5 V
VIN = 5 V
VBAT = 3.1 V
图7-1. Battery Regulation Voltage Accurary vs. VBATREG
图7-2. Charge Current Accuracy vs. ICHARGE Setting
Setting
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
TJ = 25C
TJ = -40C
TJ = 85C
TJ = 105C
SYS_REG = 000
SYS_REG = 001
SYS_REG = 010
SYS_REG = 011
SYS_REG = 100
SYS_REG = 101
SYS_REG = 110
SYS_REG = 111
3.2
3
-1.2
-1.4
2.1
2.2
2.3
2.4
VBAT (V)
2.5
2.6
2.7
2.8
0
200
400
600
800
1000
SYS Load Current (mA)
VIN = 5 V
ICHG = 100 mA
VIN = 5 V
VBAT = 0 V
图7-3. Precharge Accuracy vs Battery Voltage
图7-4. SYS Load Regulation
4.5054
4.5052
4.505
4.5048
4.5046
4.5044
4.5042
4.504
TJ = 25C
TJ = -40C
TJ = 85C
TJ = 105C
4.5038
4.5036
4.5034
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
SYS Load (A)
VIN = 5 V
SYS_REG_CTRL = 010 (4.5 V)
图7-5. SYS Load Regulation vs. Temperature
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8 Detailed Description
8.1 Overview
The BQ25180 integrates a linear charger that allows the battery to be charged with a programmable charge
current of up to 1 A. In addition to the charge current, other charging parameters can be programmed through
I2C such as the precharge, termination, battery regulation voltage, and input current limit.
The power path allows the system to be powered from a regulated output, SYS, even when the battery is deeply
discharged or charging, by drawing power from IN pin. It also prioritizes the system load in SYS, reducing the
charging current, if necessary, in order support the load when input power is limited. If the input supply is
removed and the battery voltage level is above VBUVLO, SYS will automatically and seamlessly switch to battery
power.
Charging is done through the internal battery MOSFET. There are several loops that influence the charge
current: constant current loop (CC), constant voltage loop (CV), input current limit, thermal regulation, VDPPM
,
and VINDPM. During the charging process, all loops are enabled and the one that is dominant takes control.
The device supports multiple battery chemistries for single-cell applications, through adjustable battery
regulation voltage regulation (VBATREG) and charge current (ICHG) options.
8.1.1 Battery Charging Process
When a valid input source is connected (VIN > VUVLO and VBAT+VSLEEPZ ≤ VIN < VIN_OVP), the state of the
CHARGE_DISABLE bit and the TSMR pin determines whether a charge cycle is initiated. When the
CHARGE_DISABLE bit is set to disable charging, VHOT < VTS < VCOLD and a valid input source is connected, the
battery discharge FET is turned off, preventing any charging of the battery. Note that supplement behavior is
independent of the CHARGE_DISABLE bit.
The following figure illustrates a typical charge cycle.
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Connect VIN
VBAT < VLOWV
&
No
VBAT > VBATSC
No
Yes
Precharge safety timer
expired?
Start Precharge
Yes
Yes
Stop Charging and
interrupt
No
VBAT > VLOWV
Yes
Charging or VIN toggled
No
Start FastCharge
Icharge set by I2C
Yes
Fast Charge
safety timer
expired?
IBAT < ITERM
Yes
No
Charge Done (Set
bit, interrupt, and
disconnect
BATFET)
No
Yes
VBAT < VRCH
图8-1. Charger Flow Diagram
8.1.1.1 Trickle Charge
In order to prevent damage to the battery, the device will charge the battery at a much lower current level
(IBATSC) when the battery voltage (VBAT) is below the VBATSC threshold. During trickle charge, the device still
counts against the precharge safety timer. Rather trickle charge and precharge are counting against the same
duration of 25% of the fast charge timer.
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8.1.1.2 Precharge
When battery voltage is above the VBATSC but lower than VLOWV threshold, the battery is charged with the
precharge current level. The precharge current (IPRECHARGE) can be programmed through I2C and can be
adjusted by the host. Once the battery voltage reaches VLOWV, the charger will then operate in Fast Charge
mode, charging the battery at ICHG.
During precharge, the safety timer is set to 25% of the safety timer value during fast charge. In the case where
termination is disabled, precharge current is set to 20% of fast charge current setting.
8.1.1.3 Fast Charge
The charger has two main control loops that control charging when VBAT > VLOWV: the Constant Current (CC)
and Constant Voltage (CV) loops. When the CC loop is dominant, the battery is charged at the maximum charge
current level ICHG, unless there is a TS fault condition (JEITA operation), VINDPM is active, thermal regulation or
DPPM is active. (See respective sections for details on these modes of operation). Once the battery voltage
approaches the battery regulation target, the CV loops becomes more dominant and the charging current starts
tapering off. Once the charging current reaches the termination current (ITERM) the charge is done, Charge_done
status is set. If the I2C setting of VBATREG is set higher than 4.65 V, the battery regulation voltage is still
maintained at 4.65 V. The device will switch to fastcharge mode based on VLOWV setting on the register map.
8.1.1.4 Termination
The device will automatically terminate charging once the charge current reaches ITERM, which is
programmable through I2C. After termination the charger will operate in high impedance mode, disabling the
BATFET to disconnect the battery. Power is provided to the system (SYS) by IN supply as long as VIN > VUVLO
VIN > VBAT + VSLEEPZ and VIN < VIN_OVP
,
.
Termination is only enabled when the charger CV loop is active in fast charge operation. Termination is disabled
if the charge current reaches ITERM while the VINDPM, DPPM, or thermal regulation loops are active. The
charger will only go into the termination when the current drops to ITERM due to the battery reaching the target
voltage and not due to the charge current limitation imposed by the previously mentioned controlled loops.
Post termination, the battery FET is disabled and the voltage on BAT pin is monitored to check if it has dropped
to the VRCH threshold. If it does, a new charge cycle is established. The safety timers are reset. During charging
or even when charge is done, a higher SYS load will be supported through the supplement operation.
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Regulation Voltage
VSET
VRCH
Battery Voltage
Charge Current
Charge Current
ISET
VLOWV
VBATSC
IPRECHG
ITERM
IBATSC
Trickle Charge
Pre-charge
Re-
charge
Fast-Charge
CC
Taper-Charge
CV
Charge
Done
Precharge Timer
Safety Timer
图8-2. Typical Charging Profile of a Battery
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8.2 Functional Block Diagram
SYS
Q1/Q2
IN
GND
VIN_DPM
Power Path and Charge Control
IBATREG
VBATREG
BUVLO
VIN
SCL
SDA
I2C
Interface
Charge Control
SYS Control
Q3
Thermal
Shutdown
Device Control
BAT
–
+
/INT
VBUVLO
Interrupts
TS Interface and
Push button
controller
TS/MR
VTS_CLAMP
ITSMR
图8-3. Functional Block Diagram
8.3 Feature Description
8.3.1 Input Voltage Based Dynamic Power Management (VINDPM)
The VINDPM loop prevents the input voltage from collapsing to a point where charging could be interrupted due
to adapter voltage crashing below VINDPM value. This is done by reducing the current drawn by the charger
enough to keep VIN > VINDPM setting.
During the normal charging process, if the input power source is not able to support the programmed or default
charging current and system load, the supply voltage decreases. Once the supply drops to VINDPM, the input
DPM current and voltage loops will reduce the input current through the blocking FETs Q1 and Q2 to prevent the
further drop of the supply. The VINDPM threshold is programmable through the I2C register and can be
completely disabled. This is set through the VINDPM_0 and VINDPM_1 selection bits. When the device enters
this mode, the charge current may be lower than the set value and the VINDPM_ACTIVE_STAT bit is set. If the
2x timer is set through the 2XTMR_EN bit, the safety timer is extended while VINDPM is active. Additionally,
termination is disabled when VINDPM is active.
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8.3.2 Dynamic Power Path Management Mode (DPPM)
With a valid input source connected, the power path management circuitry monitors the input voltage and current
continuously. The current into IN is shared at SYS between charging the battery and powering the system load
at SYS. If the sum of the charging and load currents exceeds the preset maximum input current, the input DPM
loop reduces input current. If SYS drops below the DPPM voltage threshold, the charging current is reduced by
the DPPM loop through the BATFET (Q3). If SYS falls below the supplement mode threshold after BATFET
charging current is reduced to zero, the part will enter supplement mode. SYS voltage is maintained above
battery voltage when the DPPM loop is in control. Battery termination is disabled when the DPPM loop is active.
The VDPPM threshold is typically 100 mV above VBAT. The VDPPM disable bit (VDPPM_DIS = b1) will allow
the charger to operate with lower headroom on VSYS. In VBAT tracking mode where VSYS is VBAT+225 mV,
disabling this bit will have no effect.
8.3.3 Battery Supplement Mode
While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the
programmed input current limit, the voltage at SYS reduces further. When the SYS voltage drops below the
battery voltage to VBSUP1, the battery supplements the system load. The battery stops supplementing the system
load when the voltage on the SYS pin rises within the battery voltage to VBSUP2. During supplement mode, the
battery supplement current is not regulated, however, the BATOCP protection circuit is active if enabled. Battery
termination is disabled while in supplement mode. Battery voltage has to be higher than the battery undervoltage
lockout threshold (VBUVLO) in order to supplement the system.
8.3.4 SYS Power Control (SYS_MODE bit control)
The device also offers the option to control SYS through the I2C SYS_MODE bits. These bits can force SYS to
be supplied by BAT instead of IN (even if VIN > VBAT + VSLEEP), disconnect SYS from either supply, pull SYS
down or leave it floating. The table below shows the device behavior based on SYS_MODE setting:
表8-1. Settings
SYS_MODE
DESCRIPTION
SYS SUPPLY
SYS PULLDOWN
00
Normal Operation
IN or BAT
Off except during HW reset
Force BAT power (IN
disconnected)
01
BAT
Off except during HW reset
10
11
None
None
Off
On
SYS Off –Floating
SYS Off –Pulled Down
SYS_MODE = 00
This is the default state/normal operation of the device. SYS will be powered from IN if VIN > VUVLO, VIN > VBAT
+ VSLEEPZ, and VIN < VIN_OVP. SYS will powered by BAT if these conditions are not met. SYS will only be
disconnected from IN or BAT and pulled down when a HW Reset occurs or the device goes into Ship mode.
SYS_MODE = 01
When this configuration is set, SYS will be powered by BAT if VBAT > VBUVLO regardless of VIN state. This allows
the host to minimize the current draw from the adapter while it is still connected as needed in the system. If
SYS_MODE = 01 is set while VBAT < VBUVLO, the SYS_MODE = 01 setting will be ignored and the device will go
to SYS_MODE = 00. In the same manner, if the adapter (VIN) is removed and then connected the device will
also switch to SYS_MODE = 00. This prevents the device from needing a POR in order to restore power to the
system thereby allowing battery charging. If SYS_MODE = 01 is set during charging, charging will be stopped
and the battery will start to provide power to SYS as needed. The behavior is similar to that when the input
adapter is disconnected.
SYS_MODE = 10
When this configuration is set, SYS will be disconnected and left floating. The device remains on and active.
Toggling VIN(VIN <VINUVLO) will reset SYS_MODE to 00.
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SYS_MODE = 11
When this configuration is set, SYS will be disconnected and pulled down to ground. Toggling VIN will reset
SYS_MODE to 00.
8.3.4.1 SYS Pulldown Control
The device has an internal pulldown on the SYS pin which is enabled in the following cases:
表8-2. States
STATE
NOTES
Pulldown on SYS is enabled once the device enters shipmode and
after disconnecting the BATFET
Shipmode
Pulldown on SYS is enabled after the BATFET and input blocking
FETs are disconnected and retained until the autowake timer expires
HW_RESET
Pulldown on SYS is enabled after the BATFET and input blocking
FETs are disconnected and retained until either an I2C transaction is
issued to change SYS_MODE or VIN is toggled.
SYS_MODE = 11 (SYS pulldown mode)
8.3.5 SYS Regulation
The device includes a SYS voltage regulation loop. By regulating the SYS voltage the device prevents
downstream devices connected to SYS from being exposed to voltages as high as VIN_OVP. SYS regulation is
only active when VIN > VUVLO, VIN > VBAT + VSLEEPZ and VIN < VIN_OVP rather than meeting the VIN_Powergood
condition.
The SYS voltage regulation target can be controlled through the SYS_REG_CTRL_2:0 bits in the SYS_REG
register to either track the battery, set to a fixed voltage, or enable pass through modes.
In battery tracking mode, the minimum voltage is at the VMINSYS value for a battery < 3.6 V. As battery voltage
increases VSYS is regulated to 225 mV above battery. If VIN < VMINSYS and VIN_Powergood is still active, then
SYS will be in dropout.
In fixed voltage mode, SYS voltage is regulated to a target set by the host ranging from 4.4 V to 4.9 V. If VIN
voltage is less than the SYS target voltage, then the device will be in dropout mode.
In pass through mode, the SYS path is unregulated and the VSYS voltage is equal to VIN.
表8-3. SYS Voltage Regulation Settings
SYS_REG_CTRL
VSYS TARGET
000
VBAT + 225 mV (3.8 V minimum)
001
4.4
010 (default)
011
4.5
4.6
100
4.7
101
4.8
110
4.9
111
Pass through
8.3.6 ILIM Control
The input current limit can be controlled through I2C by selecting the the ILIM bits.
If the ILIM clamp is active, the ILIM_ACTIVE_STAT bit is set.
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MASK_ILIM will prevent an interrupt from being issued but does not override the ILIM behavior itself. The ILIM
value can be programmed dynamically through the I2C by the host. The ILIM settings of 100mA and 500mA are
designed to be the maximum value to support standard systems.
8.3.7 Protection Mechanisms
8.3.7.1 Input Overvoltage Protection
Input overvoltage protection protects the device and downstream components connected to SYS, and BAT
against damage from overvoltage on the input supply. When VIN > VIN_OVP, a VIN overvoltage condition is
determined to exist. During the VIN overvoltage condition, the device turns the input FET OFF, battery discharge
FET ON, sends a single 128-μs pulse on INT, and the fault bit (VIN_OVP_FAULT_FLAG) is updated over I2C.
The VIN_PGOOD_STAT bit also is affected by the VIN overvoltage condition as the VIN powergood condition
will fail. Once the VIN overvoltage condition is removed (VIN ≤VIN_OVP - VIN_OV_HYS ), the VIN_OVP_STAT bit is
cleared and the device returns to normal operation. Thereafter, a VIN powergood condition is determined if VIN
> VBAT + VSLEEPZ and VIN > VIN_UVLO
.
8.3.7.2 Battery Undervoltage Lockout
In order to prevent deep discharge of the battery the device integrates a battery undervoltage lockout feature
which will disengage the BAT to SYS path when voltage at the battery drops below the programmed BUVLO
setting present in the CHARGERCTRL1 register. BUVLO status can also be read when a valid voltage on VIN is
present.
8.3.7.3 System Overvoltage Protection
The system overvoltage protection is to prevent SYS from overshooting to a high voltage due to the input supply.
SYS_OVP will momentarily disconnect the blocking FETs and re-engage when the thresholds have dropped to
less than the SYS_OVP_FALLING threshold.
The SYS_OVP_RISING threshold is typically 105% of the target SYS voltage and the SYS_OVP_FALLING
threshold is 102.5% of the target SYS voltage.
8.3.7.4 System Short Protection
When a valid adapter is connected to the device, the device turns ON the input blocking FET for 5 ms and it
detects the SYS pin to be shorted (voltage on SYS <1.6V). In this scenario, the device will turn OFF the input
FET for ~200 μs and turn it back ON for 5 ms for SYS to rise above 1.6V. If after 10 tries, the SYS short still
persists, the device will turn OFF SYS until adapter is connected again.
8.3.7.5 Battery Overcurrent Protection
In order to protect the device from overcurrent and prevent excessive battery discharge current, the device
detects if the current on the battery FET exceeds IBAT_OCP. If the BATOCP limit is reached, the battery
discharge FET is turned off and the device starts operating in hiccup mode, re-enabling the BATFET tREC_SC
(250 ms) after being turned OFF by the overcurrent condition. If the overcurrent condition is triggered upon retry
for 4 to 7 consecutive times in a 2-s window, the BATFET shall then remain off until a valid VIN is connected
(VIN = VIN_POWERGOOD). If the overcurrent condition and hiccup operation occur while in supplement mode
where VIN is already present, VIN must be toggled in order for the BATFET to be enabled and start another
detection cycle.
8.3.7.6 Safety Timer and Watchdog Timer
At the beginning of each charge cycle mode (Precharge or Fast Charge), the device starts the respective mode
safety timer. If charging has not terminated before the programmed safety time, tMAXCHG expires or the device
does not exit the precharge mode before tPRECHG expires, charging is disabled. The precharge safety time,
tPRECHG, is 25% of tMAXCHG. When a safety timer fault occurs, a single 128-μs pulse is sent on the INT pin and
the STAT and FAULT bits of the status registers are updated over I2C.
The charge enable bit or input power must be toggled in order to clear the safety timer fault.
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If the safety timer has expired, the device will produce an interrupt and update the SAFETY_TMR_FAULT_FLAG
bit on the register map. The safety timer duration is programmable using the SAFETY_TIMER_1:0 bits. When
the safety timer is active, changing the safety timer duration resets the safety timer. The device also contains a
2XTMR_EN bit that doubles the safety timer duration to prevent premature safety timer expiration when the
charge current is reduced by a high load on SYS (DPM operation- causing VDPPM to be enabled), VINDPM,
thermal regulation, or a NTC (JEITA) condition. When the 2XTMR_EN bit is set, the timer is allowed to run at half
speed when any loop is active other than CC or CV. In the event where during CC mode the battery voltage
drops to push the charger into precharge mode, (due to a large load on battery, thermal events, and so forth) the
safety timer will reset counting through precharge and then resetting the fast charge safety timer. If the device
entered battery supplement mode while in precharge, CC or CV mode, while the charger is not disabled, the
device will suspend the safety timer until charging can resume again. This prevents the safety timer from
resetting when a supplement condition is caused.
In addition to the safety timer, the device contains a watchdog timer that monitors the host through the I2C
interface. The watchdog timer is enabled by default and may be disabled by the host through an I2C transaction.
Once the initial transaction is received, the watchdog timer is started. The watchdog timer is reset by any
transaction by the host using the I2C interface. If the watchdog timer expires without a reset from the I2C
interface, all charger parameters registers (ICHG, IPRECHARGE, ITERM,VLOWV, and so forth) are reset to the
default values. The watchdog timer can be set through the WATCHDOG_SEL_1:0 bits either in battery only
mode or when an adapter is present.
表8-4. Watchdog Settings
WATCHDOG_SEL_1:0
ACTION
00
Device will only perform a software reset after 160s of the last I2C transaction
01
10
11
Device will issue a HW_Reset after 160s of last I2C transation
Device will issue a HW_Reset after 40s of the last I2C transaction
Watchdog functionality is completely disabled
8.3.7.7 Thermal Protection and Thermal Regulation
During operation, to protect the device from damage due to overheating, the junction temperature of the die, TJ,
is monitored. When TJ reaches TSHUT_RISING, the device stops charging operation and VSYS is shutdown. If in
the case where TJ > TSHUT_RISING prior to power being applied to the device (either battery or adapter), the input
FET or BATFET will not turn ON, regardless of the TSMR pin. Thereafter if temperature falls below
TSHUT_FALLING, the device will automatically power up if VIN is present or if in battery only mode.
During the charging process, to prevent overheating in the device, the device monitors the junction temperature
of the die and reduces the charging current once TJ reaches the thermal regulation threshold (TREG) based on
bits set by the THERM_REG setting. If the charge current is reduced to 0, the battery supplies the current
needed to supply the SYS output. Thermal regulation can be disabled through I2C.
Ensure that system power dissipation is under the limit of the device. The power dissipated by the device can be
calculated using the following equation:
PDISS = PSYS + PBAT
Where:
PSYS = (VIN –VSYS) * IIN
PBAT = (VSYS –VBAT) * IBAT
The die junction temperature, TJ, can be estimated based on the expected board performance using the
following equation:
TJ = TA + θJA * PDISS
θJA is largely driven by board layout. For more information about traditional and new thermal metrics, see the IC
Package Thermal Metrics Application Report. Under typical conditions, the time spent in this state is very short.
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8.3.8 Pushbutton Wake and Reset Input
The pushbutton function implemented through the TSMR pin has three main functions. First, it serves as a
means to wake the device from ultra-low power modes like ship mode. Second, it serves as a short button press
detector, sending an interrupt to the host when the button driving the TSMR pin has been pressed for Wake1,
Wake2, or long press durations. This allows the implementation of different functions in the end application such
as menu selection and control. Finally it serves as a means to get the device into ship mode or reset the system
by performing a power cycle/ hardware reset (shut down SYS and automatically powering it back on) after
detecting a long button press. The timing for the short and long button press duration is programmable through
I2C for added flexibility and allows system designers to customize the end user experience of a specific
application. Note that if a specific timer duration is changed through I2C while that timer is active and has not
expired, the new programmed value will be ignored until the timer expires and/or is reset by new push button
action. In battery only mode the device will automatically pulse the TSMR current source ON for tTS_DUTY_ON
duration and turn it OFF for tTS_DUTY_OFF duration to check if a button is pressed. If a button press is registered,
the device will begin counting against Wake1, Wake2 or long press durations. This button press detection routine
in battery only mode is run as long as it is enabled by the EN_PUSH bit. When a valid adapter is present, the
TSMR current source is always ON to monitor charging.
8.3.8.1 Pushbutton Wake or Short Button Press Functions
There are two programmable wake or short button press timers, WAKE1 and WAKE2. There are no specific
actions taken by the tWAKE1 or tWAKE2 durations other than issuing an interrupt and updating the wake registers.
For a wake from shipmode event when the button press is enabled, the push button has to be low for tshipwake
before the device can turn ON the SYS rail.
In the case where a valid VIN (VIN > VUVLO) is connected prior to the tshipwake timer expiring, the device will exit
shipmode immediately regardless of the TS/MR or wake timer state. Refer to 节8.5 for more details.
8.3.8.2 Pushbutton Reset or Long Button Press Functions
Depending on the configuration set on the pushbutton long press action register bits, the device will perform a
shipmode entry or hardware reset or completely ignore the long button press action.
tRESTART
TS/MR
VIN
128us
INT
VSYS
SW Reset
PB_LPRESS_ACTION
01 – Hardware Reset
Don’t care
Default
图8-4. Pushbutton Long Press Reset
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Shipmode enabled when
TS/MR is high
TS/MR
VIN
INT
128 us
SYS
SHIPMODE
Ready to Enter Shipmode
Don’t care
PB_LPRESS_ACTION
图8-5. Pushbutton Long Press Shipmode
8.3.9 15-Second Timeout for HW Reset
Based on the I2C register bit WATCHDOG_15S_ENABLE the device can perform a HW reset/power cycle in the
same manner a long button press or HW_RESET would. This 15-second watchdog or timeout is gated upon
VIN> VVBAT + VSLEEPZ so that the HW reset would only occur if the host does not respond after a charger is
connected and VIN_PGOOD_STAT is set.
If the charger is connected and the host responds before the 15-second watchdog expires, the part continues in
normal operation and starts the normal 50-second watchdog timer if enabled. The 15-second watchdog may be
enabled/disabled through I2C with the WATCHDOG_15S_ENABLE bit.
8.3.10 Hardware Reset
The device is capable of a hardware reset to completely powercycle the system. This is partcularly useful when
a soft reset on the MCU or host fails to work. Below is a sequence of events during a hadware reset:
1. Turn OFF (if adapter is present) input blocking FET (Q1/Q2)
2. Turn OFF battery FET (Q3)
3. Engage pulldown on SYS
4. Start the Autowake timer
5. Once the Autowake timer expires, disconnect the pulldown on SYS
6. Reset all registers to default
7. Turn ON battery FET and input FET (if applicable)
8.3.11 Software Reset
When a software reset is issued either through a watchdog action configurable through the WATCHDOG_SEL
bits or register reset configurable through the REG_RST bit, the device will reset all of the registers to the
defaults. Any bits loaded through OTP memory are also loaded. If the device was waiting to go to shipmode (all
conditions for entering ship are fulfilled except adapter removal), a hardware or software reset will cancel the
pending shipmode request. If the shipmode request was written through I2C, the host can cancel the ship entry
by clearing the bit before shipmode entry has happened.
8.3.12 Interrupt Indicator (/INT) Pin
The device contains an open-drain output that signals its status and is valid only after the device has completed
start-up into a valid state. If the part starts into a fault, interrupts will not be sent.
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The /INT pin is normally in high impedance and is pulled low for 128 μs when an interrupt condition occurs.
When a fault or status change occurs or any other condition that generates an interrupt, a 128-μs pulse (/INT
pin pulled down) is sent on /INT to notify the host.
Interrupts can be masked through I2C. If the interrupt condition occurs while the interrupt is masked an interrupt
pulse will not be sent. If the interrupt is unmasked while the fault condition is still present, an interrupt pulse will
not be sent until the /INT trigger condition occurs while unmasked. Below are a list of interrupts that can be
masked through I2C.
表8-5. Mask Bit
MASK BIT
ACTION
ILIM_INT_MASK
Do not issue an /INT pulse when ILIM limiting occurs
VDPM_INT_MASK
TS_INT_MASK
Do not issue an /INT pulse when VINDPM or DDPM is active
Do not issue an /INT pulse when any of the TS events have occured.
TREG_INT_MASK
PG_INT_MASK
Do not issue an /INT pulse when TREG is actively reducing the current
Do not issue an /INT pulse when VIN meets VIN_PG condition
Do not issue an /INT pulse when BATOCP or BUVLO event is triggered
Do not send an interrupt anytime there is a charging status change.
BAT_INT_MASK
CHG_STATUS_INT_MASK
8.3.13 External NTC Monitoring (TS)
8.3.13.1 TS Biasing and Function
The device can be configured to meet JEITA requirements or a simpler HOT/COLD function only. Additionally,
the TS charger control function can be disabled through the TS_EN bit. This will only disable the TS charge
action but the faults are still reported based on the TS voltage. To satisfy the JEITA requirements, four
temperature thresholds are monitored: cold battery threshold, cool battery threshold, warm battery threshold,
and hot battery threshold. These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT
thresholds in the Electrical Characteristics table. Charging and safety timers are suspended when VTS < VHOT or
VTS > VCOLD. When VCOOL < VTS < VCOLD, the charging current is reduced to the value programmed in the
TS_Setting register/bit TS_ICHG_0. When VHOT < VTS < VWARM, the battery regulation voltage is reduced by 100
mV or 200 mV based on the value programmed in the TS_VRCG_0 bit within the TS_Setting register.
For devices where the TS function is not needed, tie a 10-kΩ resistor to the TS pin.
There is an active voltage clamp present on this device which will prevent the voltage on the TSMR pin from
rising above the VTS_CLAMP threshold. This will particularly be ON when the TSMR pin is floating. The bit
TS_OPEN_STAT is set when this clamp is active. This will also be ON regardless of the TS_EN bit. The interrupt
is asserted as long as the TS_INT mask is not written.
The bits TS_HOT/TS_COLD, TS_WARM, and TS_COOL will allow these thresholds to be adjusted. The
hysteresis will also move along with these thresholds. When the TS_WARM condition occurs, the device will
lower the battery target regulation voltage by TS_VRCG but will not modify the VBAT_CTRL register.
The TS_ICHG bit will reduce charging current based on the factor described in the register map when the TSMR
pin hits a TS_COOL condition. The TREG function will still be based on this reduced threshold.
The TS_VRCG_0 bit will reduce the charging voltage when the TSMR pin hits the TS_WARM threshold. The
factor will be based on the register map.
When the button is detected as pressed (TSMR pin low) during the charging process, charging will be
momentarily suspended until the button is high again. When charging is disabled in any of the TS faults, trickle
charging is also disabled. In a TS fault where the current is reduced (COOL), the trickle charging current is not
altered.
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8.3.14 I2C Interface
The device uses an I2C compatible interface to program and read control parameters, status bits, and so forth.
I2C ™ is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the
bus is idle, both SDA and SCL lines are pulled high. All of the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The device works as a preipheral and supports the following data transfer modes, as defined in the I2C Bus™
Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery
charge solution, enabling most functions to be programmed to new values depending on the instantaneous
application requirements.
Register contents remain intact as long as VBAT or VIN voltages remain above their respective undervoltage
lockout thresholds and the device is not in shutdown mode.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is 0x6A (8-bit
shifted address is 0xD4).
8.3.14.1 F/S Mode Protocol
The master initiates a data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图 8-6. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
图8-6. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see 图 8-7). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see 图 8-8) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
图8-7. Bit Transfer on the Serial Interface
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see 图 8-6). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section will result in FFh being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
9
8
1
2
Clock Pulse for
Acknowledgement
START
Condition
图8-8. Ackowledge on the I2C Bus
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
or
P
ACK
ACK
Sr
图8-9. Bus Protocol
8.4 Device Functional Modes
The BQ25180 has four main modes of operation: Battery Mode, Ship Mode, Charge/Adapter Mode when a
supply is connected to IN, and Shutdown mode. The table below summarizes the functions that are active for
each operation mode.
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表8-6. Function Availability Based on Primary Mode of Operation
FUNCTION
Input overvoltage
Input undervoltage
Battery overcurrent
Battery undervoltage
Input DPM
CHARGE/ADAPTER MODE
BATTERY MODE
SHIP MODE
SHUTDOWN MODE
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
No
No
No
Yes
Yes, if enabled
Yes
Yes, if enabled
No
No
Yes, if enabled
Dynamic power path
management
Yes, if enabled
No
No
No
BATFET
TS measurement
Battery charging
ILIM
Yes
Yes
No
No
No
No
Yes
No
No
No
No
No
No
No
No
No
Yes
No
Yes, if enabled
No
Yes (Register Value)
No
Yes, if enabled
Yes
Pushbutton input
INT output
Yes
Yes
Yes
I2C
Yes
8.5 Register Maps
8.5.1 I2C Registers
表 8-7 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in 表 8-7
should be considered as reserved locations and the register contents should not be modified.
表8-7. I2C Registers
Offset
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
Acronym
Register Name
Section
Go
STAT0
Charger Status
STAT1
Charger Status and Faults
Charger Flag Registers
Battery Voltage Control
Fast Charge Current Control
Charger Control 0
Go
FLAG0
Go
VBAT_CTRL
ICHG_CTRL
CHARGECTRL0
CHARGECTRL1
IC_CTRL
Go
Go
Go
Charger Control 1
Go
IC Control
Go
TMR_ILIM
SHIP_RST
SYS_REG
TS_CONTROL
MASK_ID
Timer and Input Current Limit Control
Shipmode, Reset and Pushbutton Control
SYS Regulation Voltage Control
TS Control
Go
Go
Go
Go
MASK and Device ID
Go
Complex bit access types are encoded to fit into small table cells. 表 8-8 shows the codes that are used for
access types in this section.
表8-8. I2C Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
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表8-8. I2C Access Type Codes (continued)
Access Type
Code
Description
RC
R
C
Read
to Clear
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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8.5.1.1 STAT0 Register (Offset = 0x0) [Reset = X]
STAT0 is shown in 图8-10 and described in 表8-9.
Return to the Summary Table.
图8-10. STAT0 Register
7
6
5
4
3
2
1
0
TS_OPEN_STA
T
CHG_STAT_1:0
R-X
ILIM_ACTIVE_ VDPPM_ACTIV VINDPM_ACTI THERMREG_A VIN_PGOOD_S
STAT
E_STAT
VE_STAT
CTIVE_STAT
TAT
R-X
R-X
R-X
R-X
R-X
R-X
表8-9. STAT0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TS_OPEN_STAT
R
X
TS Open Status
1b0 = TSMR pin is not Open
1b1 = TSMR pin is Open
6-5
CHG_STAT_1:0
R
X
Charging Status Indicator
2b00 = Not Charging while charging is enabled.
2b01 = Constant Current Charging (Trickle Charge/ Pre Charge or in
Fast Charge Mode)
2b10 = Constant Voltage Charging
2b11 = Charge Done or charging is disabled by the host.
4
3
2
1
0
ILIM_ACTIVE_STAT
R
R
R
X
X
X
X
X
Input Curent Limit Active
1b0 = Not Active
1b1 = Active
VDPPM_ACTIVE_STAT
VINDPM_ACTIVE_STAT
VDPPM Mode Active
1b0 = Not Active
1b1 = Active
VINDPM Mode Active
1b0 = Not Active
1b1 = Active
THERMREG_ACTIVE_ST R
AT
Thermal Regulation Active
1b0 = Not Active
1b1 = Active
VIN_PGOOD_STAT
R
VIN Power Good
1b0 = VIN Power Not Good
1b1 = VIN Power Good
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8.5.1.2 STAT1 Register (Offset = 0x1) [Reset = X]
STAT1 is shown in 图8-11 and described in 表8-10.
Return to the Summary Table.
图8-11. STAT1 Register
7
6
5
4
3
2
1
0
VIN_OVP_STA BUVLO_STAT
T
RESERVED
TS_STAT_1:0
R-2b00
SAFETY_TMR_ WAKE1_FLAG WAKE2_FLAG
FAULT_FLAG
R-1b0
R-X
R-X
RC-1b0
RC-1b0
RC-1b0
表8-10. STAT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
VIN_OVP_STAT
R
1b0
VIN_OVP Fault
1b0 = Not Active
1b1 = Active
6
BUVLO_STAT
R
X
Battery UVLO Status
1b0 = Not Active
1b1 = Active
5
RESERVED
R
R
X
Reserved
4-3
TS_STAT_1:0
2b00
TS Status
2b00 = Normal
2b01 = VTS < VHOT or VTS > VCOLD(charging suspended)
2b10 = VCOOL < VTS < VCOLD (Charging current reduced by value
set by TS_Registers)
2b11 = VWARM > VTS > VHOT (Charging voltage reduced by value
set by TS_Registers)
2
1
0
SAFETY_TMR_FAULT_F RC
LAG
1b0
1b0
1b0
Safety Timer Expired Fault Cleared only after CE is toggled.
1b0 = Not Active
1b1 = Active
WAKE1_FLAG
WAKE2_FLAG
RC
RC
Wake 1 Timer Flag
1b0 = Does not meet Wake 1 Condition
1b1 = Met Wake 1 Condition
Wake 2 Timer Flag
1b0 = Does not meet Wake 2 Condition
1b1 = Met Wake2 Condition
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8.5.1.3 FLAG0 Register (Offset = 0x2) [Reset = X]
FLAG0 is shown in 图8-12 and described in 表8-11.
Return to the Summary Table.
图8-12. FLAG0 Register
7
6
5
4
3
2
1
0
TS_FAULT
ILIM_ACTIVE_ VDPPM_ACTIV VINDPM_ACTI THERMREG_A VIN_OVP_FAU BUVLO_FAULT BAT_OCP_FAU
FLAG
E_FLAG
VE_FLAG
CTIVE_FLAG
LT_FLAG
_FLAG
LT
RC-X
RC-X
RC-X
RC-X
RC-X
RC-X
RC-X
RC-X
表8-11. FLAG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TS_FAULT
RC
X
TS_Fault
1b0 = No TS Fault detected
1b1 = TS Fault detected
6
5
4
3
2
1
0
ILIM_ACTIVE_FLAG
VDPPM_ACTIVE_FLAG
RC
RC
X
X
X
X
X
X
X
ILIM Active
1b0 = NO ILIM Fault detected
1b1 = ILIM Fault detected
VDPPM FLAG
1b0 = VDPPM fault not detected
1b1 = VDPPM fault detected
VINDPM_ACTIVE_FLAG RC
VINDPM FLAG
1b0 = VINDPM fault not detected
1b1 = VINDPM fault detected
THERMREG_ACTIVE_FL RC
AG
Thermal Regulation FLAG
1b0 = No thermal regulation detected
1b1 = Thermal regulation has occured
VIN_OVP_FAULT_FLAG RC
VIN_OVP FLAG
1b0 = VIN_OVP fault not detected
1b1 = VIN_OVP fault detected
BUVLO_FAULT_FLAG
BAT_OCP_FAULT
RC
RC
Battery undervoltage FLAG
1b0 = Battery undervoltage fault not detected
1b1 = Battery undervoltage fault detected
Battery overcurrent protection
1b0 = Battery overcurrent condition not detected
1b1 = Battery overcurrent condition detected
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8.5.1.4 VBAT_CTRL Register (Offset = 0x3) [Reset = 0x46]
VBAT_CTRL is shown in 图8-13 and described in 表8-12.
Return to the Summary Table.
图8-13. VBAT_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W-1b0
VBATREG_6:0
R/W-7b1000110
表8-12. VBAT_CTRL Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
1b0
Reserved
6-0
VBATREG_6:0
7b1000110 Battery Regulation Voltage VBATREG= 3.5V + VBATREG_CODE *
10mV.
Maximum programmable voltage = 4.65V
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8.5.1.5 ICHG_CTRL Register (Offset = 0x4) [Reset = 0x05]
ICHG_CTRL is shown in 图8-14 and described in 表8-13.
Return to the Summary Table.
图8-14. ICHG_CTRL Register
7
6
5
4
3
2
1
0
CHG_DIS
R/W-1b0
ICHG_6:0
R/W-7b0000101
表8-13. ICHG_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CHG_DIS
R/W
1b0
Charge Disable
1b0 = Battery Charging Enabled
1b1 = Battery Charging Disabled
6-0
ICHG_6:0
R/W
7b0000101 For ICHG <= 35mA = ICHGCODE +5mA For ICHG > 35mA = 40+
((ICHGCODE-31)*10)mA.
Maximum programmable current = 1000mA
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8.5.1.6 CHARGECTRL0 Register (Offset = 0x5) [Reset = 0x2C]
CHARGECTRL0 is shown in 图8-15 and described in 表8-14.
Return to the Summary Table.
图8-15. CHARGECTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-1b0
IPRECHG
R/W-1b0
ITERM_1:0
R/W-2b10
VINDPM_1:0
R/W-2b11
THERM_REG_1:0
R/W-2b00
表8-14. CHARGECTRL0 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
1b0
Reserved
6
IPRECHG
1b0
Precharge current = x times of term
1b0 = Precharge is 2x Term
1b1 = Precharge is Term
5-4
3-2
1-0
ITERM_1:0
R/W
R/W
R/W
2b10
2b11
2b00
Termination current = % of Icharge
2b00 = Disable
2b01 = 5% of ICHG
2b10 = 10% of ICHG
2b11 = 20% of ICHG
VINDPM_1:0
VINDPM Level Selection
2b00 = 4.2 V
2b01 = 4.5 V
2b10 = 4.7 V
2b11 = Disabled
THERM_REG_1:0
Thermal Regulation Threshold
2b00 = 100C
2b11 = Disabled
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8.5.1.7 CHARGECTRL1 Register (Offset = 0x6) [Reset = 0x56]
CHARGECTRL1 is shown in 图8-16 and described in 表8-15.
Return to the Summary Table.
图8-16. CHARGECTRL1 Register
7
6
5
4
3
2
1
0
IBAT_OCP_1:0
R/W-2b01
BUVLO_2:0
R/W-3b010
CHG_STATUS_ ILIM_INT_MAS VDPM_INT_MA
INT_MASK
K
SK
R/W-1b1
R/W-1b1
R/W-1b0
表8-15. CHARGECTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
IBAT_OCP_1:0
R/W
2b01
Battery Discharge Current Limit
2b00 = 500mA
2b01 = 1000mA
2b10 = 1500mA
2b11 = Disabled
5-3
BUVLO_2:0
R/W
3b010
Battery Undervoltage LockOut Falling Threshold.
3b000 = 3.0V
3b001 = 3.0V
3b010 = 3.0V
3b011 = 2.8V
3b100 = 2.6V
3b101 = 2.4V
3b110 = 2.2V
3b111 = 2.0V
2
CHG_STATUS_INT_MAS R/W
K
1b1
Mask Charging Status Interrupt
1b0 = Enable Charging Status Interrupt anytime there is a charging
status change.
1b1 = Mask Charging Status Interrupt
1
0
ILIM_INT_MASK
R/W
R/W
1b1
1b0
Mask ILIM Fault Interrupt
1b0 = Enable ILIM Interrupt
1b1 = Mask ILIM Interrupt
VDPM_INT_MASK
Mask VINDPM and VDPPM Interrupt
1b0 = Enable VINDPM and VDPPM Interrupt
1b1 = Mask VINDPM and VDPPM Interrupt
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8.5.1.8 IC_CTRL Register (Offset = 0x7) [Reset = 0x84]
IC_CTRL is shown in 图8-17 and described in 表8-16.
Return to the Summary Table.
图8-17. IC_CTRL Register
7
6
5
4
3
2
1
0
TS_EN
R/W-1b1
VLOWV_SEL
R/W-1b0
VRCH_0
R/W-1b0
2XTMR_EN
R/W-1b0
SAFETY_TIMER_1:0
R/W-2b01
WATCHDOG_SEL_1:0
R/W-2b00
表8-16. IC_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TS_EN
R/W
1b1
TS Auto Function
1b0 = TS auto function disabled (Only charge control is disabled. TS
monitoring is enabled)
1b1 = TS auto function enabled
6
5
4
VLOWV_SEL
VRCH_0
R/W
R/W
R/W
1b0
1b0
1b0
Precharge Voltage Threshold (VLOWV)
1b0 = 3V
1b1 = 2.8V
Recharge Voltage Threshold
1b0 = 100mV
1b1 = 200 mV
2XTMR_EN
Timer Slow
1b0 = The timer is not slowed at any time
1b1 = The timer is slowed by 2x when in any control other than CC
or CV
3-2
1-0
SAFETY_TIMER_1:0
WATCHDOG_SEL_1:0
R/W
R/W
2b01
2b00
Fast Charge Timer
2b00 = 3 hour fast charge
2b01 = 6 hour fast charge
2b10 = 12 hour fast charge
2b11 = Disable safety timer
Watchdog Selection
2b00 = 160s default register values
2b01 = 160s HW_RESET
2b10 = 40s HW_RESET
2b11 = Disable watchdog function
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8.5.1.9 TMR_ILIM Register (Offset = 0x8) [Reset = 0x4D]
TMR_ILIM is shown in 图8-18 and described in 表8-17.
Return to the Summary Table.
图8-18. TMR_ILIM Register
7
6
5
4
3
2
1
0
MR_LPRESS_1:0
MR_RESET_VI
N
AUTOWAKE_1:0
R/W-2b01
ILIM_2:0
R/W-2b01
R/W-1b0
R/W-3b101
表8-17. TMR_ILIM Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
MR_LPRESS_1:0
R/W
2b01
Push button Long Press duration timer
2b00 = 5s
2b01 = 10s
2b10 = 15s
2b11 = 20s
5
MR_RESET_VIN
AUTOWAKE_1:0
R/W
R/W
1b0
Hardware reset condition
1b0 = Reset sent when long press duration is met
1b1 = Reset sent when long press duration is met and
VIN_Powergood
4-3
2b01
Auto Wake Up Timer Restart
2b00 = 0.5s
2b01 = 1s
2b10 = 2s
2b11 = 4s
2-0
ILIM_2:0
R/W
3b101
Input Current Limit Setting
3b000 = 50mA
3b001 = 100mA(max.)
3b010 = 200mA
3b011 = 300mA
3b100 = 400mA
3b101 = 500mA(max.)
3b110 = 700mA
3b111 = 1100mA
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8.5.1.10 SHIP_RST Register (Offset = 0x9) [Reset = 0x11]
SHIP_RST is shown in 图8-19 and described in 表8-18.
Return to the Summary Table.
图8-19. SHIP_RST Register
7
6
5
4
3
2
1
0
REG_RST
R/W-1b0
EN_RST_SHIP_1:0
R/W-2b00
PB_LPRESS_ACTION_1:0
R/W-2b10
WAKE1_TMR
R/W-1b0
WAKE2_TMR
R/W-1b0
EN_PUSH
R/W-1b1
表8-18. SHIP_RST Register Field Descriptions
Bit
Field
Type
Reset
Description
7
REG_RST
R/W
1b0
Software Reset
1b0 = Do nothing
1b1 = Software Reset
6-5
4-3
EN_RST_SHIP_1:0
R/W
2b00
2b10
Shipmode Enable and Hardware Reset
2b00 = Do nothing
2b01 = Enable shutdown mode with wake on adapter insert only
2b10 = Enable shipmode with wake on button press or adapter insert
2b11 = Hardware Reset
PB_LPRESS_ACTION_1: R/W
0
Pushbutton long press action
2b00 = Do nothing
2b01 = Hardware Reset
2b10 = Enable shipmode
2b11 = Enable shutdown mode
2
1
0
WAKE1_TMR
WAKE2_TMR
EN_PUSH
R/W
R/W
R/W
1b0
1b0
1b1
Wake 1 Timer Set
1b0 = 300ms
1b1 = 1s
Wake 2 Timer Set
1b0 = 2s
1b1 = 3s
Enable Push Button and Reset Function on Battery Only
1b0 = Disable
1b1 = Enable
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8.5.1.11 SYS_REG Register (Offset = 0xA) [Reset = 0x40]
SYS_REG is shown in 图8-20 and described in 表8-19.
Return to the Summary Table.
图8-20. SYS_REG Register
7
6
5
4
3
2
1
0
SYS_REG_CTRL_2:0
RESERVED
SYS_MODE_1:0
R/W-2b00
WATCHDOG_1 VDPPM_DIS
5S_ENABLE
R/W-3b010
R/W-1b0
R/W-1b0
R/W-1b0
表8-19. SYS_REG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
SYS_REG_CTRL_2:0
R/W
3b010
SYS Regulation Voltgage
3b000 = Battery Tracking Mode
3b001 = 4.4V
3b010 = 4.5V
3b011 = 4.6V
3b100 = 4.7V
3b101 = 4.8V
3b110 = 4.9V
3b111 = Pass-Through (VSYS is VIN)
4
RESERVED
R/W
R/W
1b0
Reserved
3-2
SYS_MODE_1:0
2b00
Sets how SYS is powered in any state, except SHIPMODE
2b00 = SYS powered from VIN if present or VBAT
2b01 = SYS powered from VBAT only, even if VIN present
2b10 = SYS disconnected and left floating
2b11 = SYS disconnected with pulldown
1
0
WATCHDOG_15S_ENAB R/W
LE
1b0
1b0
I2C Watchdog
1b0 = Mode Disabled
1b1 = Do a HW reset after 15s if no I2C transaction after VIN
plugged
VDPPM_DIS
R/W
Disable VDPPM
1b0 = Enable VDPPM
1b1 = Disable VDPPM
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8.5.1.12 TS_CONTROL Register (Offset = 0xB) [Reset = 0x00]
TS_CONTROL is shown in 图8-21 and described in 表8-20.
Return to the Summary Table.
图8-21. TS_CONTROL Register
7
6
5
4
3
2
1
0
TS_HOT
TS_COLD
R/W-2b00
TS_WARM
R/W-1b0
TS_COOL
R/W-1b0
TS_ICHG
R/W-1b0
TS_VRCG
R/W-1b0
R/W-2b00
表8-20. TS_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
TS_HOT
R/W
2b00
TS Hot threshold register
2b00 = Default 60C
2b01 = 65C
2b10 = 50C
2b11 = 45C
5-4
TS_COLD
R/W
2b00
TS Cold threshold register
2b00 = Default 0C
2b01 = 3C
2b10 = 5C
2b11 = -3C
3
2
1
0
TS_WARM
TS_COOL
TS_ICHG
TS_VRCG
R/W
R/W
R/W
R/W
1b0
1b0
1b0
1b0
TS Warm threshold
1b0 = Default 45C
1b1 = Disabled
TS Cool threshold register
1b0 = Default 10C
1b1 = Disabled
Fast charge current when decreased by TS function
1b0 = 0.5*ICHG
1b1 = 0.2*ICHG
Reduced target battery voltage during Warm
1b0 = VBATREG -100mV
1b1 = VBATREG -200mV
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8.5.1.13 MASK_ID Register (Offset = 0xC) [Reset = 0xC0]
MASK_ID is shown in 图8-22 and described in 表8-21.
Return to the Summary Table.
图8-22. MASK_ID Register
7
6
5
4
3
2
1
0
TS_INT_MASK TREG_INT_MA BAT_INT_MAS PG_INT_MASK
Device_ID
R-4b0000
SK
K
R/W-1b1
R/W-1b1
R/W-1b0
R/W-1b0
表8-21. MASK_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TS_INT_MASK
TREG_INT_MASK
BAT_INT_MASK
PG_INT_MASK
Device_ID
R/W
1b1
Mask TS
1b0 = Enable TS Interrupt
1b1 = Mask TS Interrupt
6
5
R/W
R/W
R/W
R
1b1
Mask TREG
1b0 = Enable TREG Interrupt
1b1 = Mask TREG Interrupt
1b0
Mask BATOCP and BUVLO
1b0 = Enable BOCP and BUVLO Interrupt
1b1 = Mask BOCP and BUVLO Interrupt
4
1b0
Mask PG and VINOVP
1b0 = Enable PG and VINOVP Interrupt
1b1 = Mask PG and VINOVP Interrupt
3-0
4b0000
Device ID
4b0000 = BQ25180
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
A typical application of the BQ25180 consists of the device configured as an I2C controlled single cell Li-ion
battery charger and power path manager or battery applications such as smart watches and wireless headsets.
A battery thermistor may be connected to the TS pin to allow the device to monitor the battery temperature and
control charging as desired.
The system designer may connect the TS/MR pin input to a push button to send interrupts to the host as a
button is pressed or to allow the application end user to reset the system.
9.2 Typical Application
SYS
IN
Regulated
Load
VBUS
10uF
1uF
/INT
Device
Control
SCL
SDA
BAT
Host
1uF
+
–
VIO
TS/MR
NTC
BQ25180
GND
图9-1. Typical Application
9.2.1 Design Requirements
The design requirements for the following design example are shown in 表9-1.
表9-1. Design Parameters
PARAMETER
VALUE
IN supply voltage
5 V
Battery regulation voltage
4.2 V
9.2.2 Detailed Design Procedure
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9.2.2.1 Input (IN/SYS) Capacitors
Low ESR ceramic capacitors such as X7R or X5R are preferred for input decoupling capacitors and should be
placed as close as possible to the supply and ground pins for the IC. Due to the voltage derating of the
capacitors, it is recommended that 25-V rated capacitors are used for the IN and SYS pins which can normally
operate at 5 V. After derating the minimum capacitance must be higher than 1 µF.
9.2.2.2 TS
The ground connection for the NTC must be made as close as possible to the GND pin of the device or kelvin
connected to it to minimize any error in TS measurement due to IR drops on the ground board lines.
If the system designer does not wish to use the TS function for charging control, a 10-kΩ resistor must be
connected from TS to ground.
9.2.2.3 Recommended Passive Components
表9-2. Passive Components
MIN
NOM
10
1
MAX
100
-
UNIT
μF
CSYS
CBAT
CIN
Capacitance on SYS pin
Capacitance on BAT pin
IN input bypass capacitance
1
1
μF
1
1
10
μF
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9.2.3 Application Curves
CIN = 1 µF, COUT = 10 µF, VIN = 5 V, VOUT = 3.8 V, ICHG = 10 mA (unless otherwise specified)
VIN = 5 V
VBAT = Floating
VIN = 5 V
VBAT = 3.6 V
图9-2. Power Up with IN Supply Insertion with No
图9-3. Power Up from Shutdown Mode with VIN
Battery
Supply Insertion
VBAT = 3.8 V
MR_LPRESS = 00 (5s Long Press Timer)
VIN = 0 V →5 V
图9-5. Power Up from Shipmode with /TSMR
图9-4. Power Up from Shipmode with VIN Insertion
Button Press
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MR_LPRESS = 00 (5s Long Press Timer)
MR_LPRESS = 00 (5s Long Press Timer)
PB_LPRESS_ACTION = 10
PB_LPRESS_ACTION = 01 (Hardware Reset)
图9-6. Hardware Reset with /TSMR Press
图9-7. Enter Shipmode with Push Button Long
Press
图9-8. Hardware Reset Through I2C
EN_RST_SHIP = 01 (enable shutdown with wake on adapter
insert only)
图9-9. Shutdown Entry on VIN Removal
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EN_RST_SHIP = 10 (enable shutdown with wake on adapter
VIN = 0 V →5 V →0 V
insert only)
图9-11. Power Good Interrupt on /INT
图9-10. Shipmode Entry on VIN Removal
VIN = 0 V
SYS_REG_CTRL = 000 →111 in steps
PB_LPRESS_ACTION = 11 (enable shutown mode)
MR_LPRESS = 00 (5 seconds)
图9-13. SYS Regulation Sweep
图9-12. Shutdown Mode Entry with Push Button
Long Press
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VIN = 5 V
SYS_MODE = 00 →01 →10 →11
图9-15. Wake1 Interrupt with VIN Present
图9-14. SYS Mode Sweep
VIN = 5 V
VIN = 5 V
MR_LPRESS = 00 (5 seconds)
PB_LPRESS_ACTION = Hardware Reset
图9-16. Wake2 Interrupt with VIN Present
图9-17. Long Press Interrupt with VIN Present
VIN = 0 V
VIN = 5 V
图9-18. Wake1 Interrupt without VIN
图9-19. Wake2 Interrupt without VIN Present
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VIN = 0 V
MR_LPRESS = 00 (5 seconds)
PB_LPRESS_ACTION = 11 (Hardware Reset)
图9-20. Long Press Interrupt without VIN Present
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10 Power Supply Recommendations
The BQ25180 requires the adapter or IN supply to be between 2.7 V and 5.5 V. The battery voltage must be
higher than 3.15 V or VBUVLO to ensure proper operation.
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11 Layout
11.1 Layout Guidelines
• To obtain optimal performance, the decoupling capacitor from IN to GND, the capacitor from SYS to GND and
BAT to GND should be placed as close as possible to the device, with short trace runs to IN, SYS, BAT and
GND.Have solid ground plane that is tied to the GND bump
• The pushbutton GND should be connected close to the device as possible.
• The high current charge paths into IN, SYS and BAT pins must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces.
11.2 Layout Example
Bo om
Layer
Top
Layer
GND
0402
IN
0402
IN
/INT
SYS
SCL
SYS
BAT
SDA
0402
BAT
TS/MR
GND
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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ZHCSPC2C –SEPTEMBER 2021 –REVISED JANUARY 2023
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25180YBGR
ACTIVE
DSBGA
YBG
8
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
B180
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25180YBGR
DSBGA
YBG
8
3000
180.0
8.4
1.15
1.75
0.65
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YBG
SPQ
Length (mm) Width (mm) Height (mm)
182.0 182.0 20.0
BQ25180YBGR
8
3000
Pack Materials-Page 2
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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