BQ25600CYFFT [TI]
用于并联充电应用的 I2C 单节 3A 降压电池充电器 | YFF | 30 | -40 to 85;型号: | BQ25600CYFFT |
厂家: | TEXAS INSTRUMENTS |
描述: | 用于并联充电应用的 I2C 单节 3A 降压电池充电器 | YFF | 30 | -40 to 85 电池 |
文件: | 总51页 (文件大小:1011K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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bq25600C
ZHCSGR7 –SEPTEMBER 2017
用于并联充电应用的 bq25600C I2C 控制型 3.0A
单节电池 充电器
1 特性
•
•
17µA 低电池泄漏电流
高精度
1
•
•
在双充电器操作下,并联充电器提供快速充电
高效 1.5MHz 同步开关模式降压充电器
–
–
–
–
–
±0.5% 充电电压调节
±5% 1.5A 充电电流调节
±6% 1.38A 充电电流调节
±10% 0.9A 输入电流调节
用于快速充电的远程电池感应
–
–
–
在 2A 电流(5V 输入)下具有 92% 的充电效率
针对 USB 电压输入 (5V) 进行了优化
用于轻负载运行的低功耗脉冲频率调制 (PFM)
模式
•
单个输入,支持 USB 输入和高压适配器
2 应用
–
支持 3.9V 至 13.5V 输入电压范围,绝对最大输
入电压额定值为 22V
•
•
智能电话
平板电脑
–
可编程输入电流限制(100mA 至 3.2A,分辨率
为 100mA),支持 USB2.0、USB3.0 标准和高
压适配器 (IINDPM)
3 说明
–
–
通过高达 5.4V 的输入电压限制 (VINDPM) 进行
最大功率跟踪
bq25600C 器件是高度集成的 3.0A 开关模式电池充电
管理和系统电源路径管理器件,适用于单节锂离子和锂
聚合物电池。低阻抗电源路径可优化开关模式运行效率
并缩短电池充电时间。具有充电和系统设置的 I2C 串行
接口使得此器件成为一个真正的灵活解决方案。
VINDPM 阈值自动跟踪电池电压
•
•
采用 19.5mΩ 充电电流感应 MOSFET 实现高充电
效率
窄 VDC (NVDC) 电源路径管理
器件信息(1)
–
无需电池或深度放电的电池即可瞬时启动
器件型号
bq25600C
封装
封装尺寸(标称值)
–
电池充电模式下的理想二极管运行
灵活的自主和 I2C 模式,可实现最优系统性能
DSBGA (30)
2.2mm × 2.59mm
•
•
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
高集成度,包括所有 MOSFET、电流感应和环路补
偿
简化电路原理图
USB
Host
VBUS
SW
BTST
SYS
I2C
I2C
BAT
PMID
+
bq25600C
Parallel Charger
I2C Bus
V
VBUS
BAT
I2C
SYS
Main Charger
SYS
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSD36
bq25600C
ZHCSGR7 –SEPTEMBER 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 17
8.4 Register Maps......................................................... 27
Application and Implementation ........................ 38
9.1 Application information............................................ 38
9.2 Typical Application Diagram .................................. 39
9.3 Application Curves .................................................. 41
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal information .................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements.............................................. 12
7.7 Typical Characteristics............................................ 13
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
9
10 Power Supply Recommendations ..................... 43
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 44
12 器件和文档支持 ..................................................... 45
12.1 社区资源................................................................ 45
12.2 商标....................................................................... 45
12.3 静电放电警告......................................................... 45
12.4 Glossary................................................................ 45
13 机械、封装和可订购信息....................................... 45
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2017 年 9 月
*
初始发行版。
2
版权 © 2017, Texas Instruments Incorporated
bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
5 说明 (续)
bq25600C 是高度集成的 3.0A 开关模式电池充电管理和系统电源路径管理器件,适用于单节锂离子和锂聚合物电
池。该器件 通过 高输入电压和高效率实现快速充电, 支持 用于各种智能手机、平板电脑和便携式设备的并联充电
应用。bq25600C 具有与 bq25600 不同的 I2C 地址,因此在选择 bq25600 作为主充电器并选择 bq25600C 作为并
联充电器时,仅需要单个 I2C 总线。其低阻抗电源路径可优化开关模式运行效率并缩短电池充电时间。其输入电压
和电流调节以及电池远程感应可以为电池提供最大的充电功率。该解决方案在系统和电池之间高度集成输入反向阻
断 FET(RBFET,Q1)、高侧开关 FET(HSFET,Q2)、低侧开关 FET(LSFET,Q3)以及电池 FET
(BATFET、Q4)。它还集成了自举二极管以进行高侧栅极驱动,从而简化系统设计。具有充电和系统设置的 I2C
串行接口使得此器件成为一个真正的灵活解决方案。
该器件支持多种输入源,包括标准 USB 主机端口、USB 充电端口以及兼容 USB 的高电压适配器。该器件根据内
置 USB 接口设置默认输入电流限值。为了设置默认输入电流限值,器件使用内置 USB 接口或者从系统检测电路
(如 USB PHY 器件)中获取结果。该器件符合 USB 2.0 和 USB 3.0 电源规范,具有输入电流和电压调节功能。
此器件在无需软件控制情况下启动并完成一个充电周期。它感应电池电压并通过三个阶段为电池充电:预充电、恒
定电流和恒定电压。在充电周期的末尾,当充电电流低于预设限值并且电池电压高于再充电阈值时,充电器自动终
止。如果已完全充电的电池降至再充电阈值以下,则充电器自动启动另一个充电周期。
此充电器提供针对电池充电和系统运行的多种安全 特性, 其中包括充电安全计时器以及过压和过流保护。当结温
超过 110°C(可编程)时,热调节会减小充电电流。STAT 输出报告充电状态和任何故障状况。其他安全 特性 包
括热调节和热关断以及输入 UVLO 和过压保护。VBUS_GD 位指示电源是否正常。当发生故障时,INT 输出会立即
通知主机。
这些器件采用 30 个焊球、2.0mm × 2.4mm WCSP 封装。
Copyright © 2017, Texas Instruments Incorporated
3
bq25600C
ZHCSGR7 –SEPTEMBER 2017
www.ti.com.cn
6 Pin Configuration and Functions
bq25600C YFF Package
30-Pin DSBGA
Top View
1
2
3
4
5
A
B
C
D
E
F
GND
GND
BAT
BAT
BAT
BAT
SW
PMID
VBUS
VAC
SW
SYS
SYS
SYS
SYS
PMID
BTST
NC
VBUS
REGN
NC
NC
PSEL
PG
CE
SDA
INT
STAT
SCL
BAT
SNS
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
B5
C1
D1
E1
F1
NC
AO
No Connect. Must leave this pin floating.
Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is
connected between SYS and BAT. Connect a 10 µF closely to the BAT pin.
BAT
P
Battery voltage sensing pin for charge current regulation. in order to minimize the parasitic trace resistance
during charging, BATSNS pin is connected to the actual battery pack as close as possible.
BATSNS
F3
C3
AIO
PWM high side driver positive supply. internally, the BTST is connected to the cathode of the boost-strap diode.
Connect the 0.047-μF bootstrap capacitor from SW to BTST.
BTST
CE
P
E3
A1
B1
DI
Charge enable pin. When this pin is driven low, battery charging is enabled.
GND
INT
—
Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends active low,
256-µs pulse to host to report charger device status and fault.
F4
D5
DO
Open drain active low power good indicator. Connect to the pull up rail through 10 kΩ resistor. LOW indicates a
good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current
limit is above 30 mA.
PG
DO
A3
B3
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Given the total input
capacitance, put 1 μF on VBUS to GND, and the rest capacitance on PMID to GND.
PMID
PSEL
DO
DI
Power source selection input. High indicates 500 mA input current limit. Low indicates 2.4A input current limit.
Once the device gets into host mode, the host can program different input current limit to IINDPM register.
C5
C4
PWM low side driver positive supply output. internally, REGN is connected to the anode of the boost-strap diode.
Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed
close to the IC.
REGN
P
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P
= Power
4
Copyright © 2017, Texas Instruments Incorporated
bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
SCL
NO.
F5
I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
DI
SDA
E4
DIO
Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates
charger status.
STAT
SW
E5
DO
P
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): Blink at 1Hz
A2
B2
C2
D2
E2
F2
Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET
and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
Converter output connection point. The internal current sensing resistor is connected between SYS and BAT.
Connect a 20 µF closely to the SYS pin.
SYS
P
Ground reference for the device that is also the thermal pad used to conduct heat from the device. This
connection serves two purposes. The first purpose is to provide an electrical ground connection for the device.
The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad
should be tied externally to a ground plane.
Thermal Pad
—
P
NC
D3, D4
A5
AI
AI
No Connect. Leave this pin floating.
VAC
Input voltage sensing. This pin must be connected to VBUS.
A4
Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and
PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it as close as
possible to IC.
VBUS
P
B4
Copyright © 2017, Texas Instruments Incorporated
5
bq25600C
ZHCSGR7 –SEPTEMBER 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX
UNIT
V
VAC
22
22
22
16
7
VBUS (converter not switching)(2)
BTST, PMID (converter not switching)(2)
SW
–2
V
–0.3
–2
V
V
Voltage Range (with respect to
GND)
BTST to SW
–0.3
–0.3
–0.3
–0.3
–0.3
V
PSEL
7
V
BATSNS (converter not switching)
7
V
REGN, TS, CE, PG, BAT, SYS (converter not switching)
7
V
SDA, SCL, INT, STAT
STAT, INT
7
V
Output Sink Current
6
mA
°C
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
150
(1) Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) VBUS is specified up to 22 V for a maximum of one hour at room temperature
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
VBUS
Iin
Input voltage
3.9
13.5(1)
V
A
Input current (VBUS)
Output current (SW)
Battery voltage
3.25
3.25
4.624
3.0
ISWOP
VBATOP
IBATOP
IBATOP
TA
A
V
Fast charging current
Discharging current (continuous)
Operating ambient temperature
A
6
A
–40
85
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum voltage rating on either the BTST or SW pins. A
tight layout minimizes switching noise.
7.4 Thermal information
bq25600C
THERMAL METRIC
YFF (DSBGA)
30 Balls
58.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
0.2
8.3
6
Copyright © 2017, Texas Instruments Incorporated
bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
Thermal information (continued)
bq25600C
THERMAL METRIC
YFF (DSBGA)
UNIT
30 Balls
1.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
ΨJB
8.3
RθJC(bot)
N/A
7.5 Electrical Characteristics
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
QUIESCENT CURRENTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBAT = 4.5 V, VBUS < VAC-UVLOZ
leakage between BAT and VBUS,
TJ< 85°C
,
Battery discharge current (BAT, SW,
SYS) in buck mode
IBAT
5
µA
µA
VBAT = 4.5 V, HIZ Mode and
OVPFET_DIS = 1 or No VBUS, I2C
disabled, BATFET Disabled. TJ <
85°C
Battery discharge current (BAT) in
buck mode
IBAT
17
33
VBAT = 4.5 V, HIZ Mode and
Battery discharge current (BAT, SW, OVPFET_DIS = 1 or No VBUS, I2C
IBAT
58
24
85
37
µA
µA
SYS)
Disabled, BATFET Enabled. TJ <
85°C
IVAC_HIZ
Input supply current (VAC) in buck
mode
VVAC = 5 V, HIZ Mode and
OVPFET_DIS = 1, No battery
Input supply current (VAC) in buck
mode
VVAC = 12 V, HIZ Mode and
OVPFET_DIS = 1, No battery
IVAC_HIZ
41
37
61
50
µA
µA
IVACVBUS_HIZ
Input supply current (VAC and
VBUS short) in buck mode
VVAC = 5 V, HIZ Mode and
OVPFET_DIS = 1, No battery
Input supply current (VAC and
VBUS short) in buck mode
VVAC = 12 V, HIZ Mode and
OVPFET_DIS = 1, No battery
IVACVBUS_HIZ
IVBUS
68
90
3
µA
Input supply current (VBUS) in buck VVBUS = 12 V, VVBUS > VVBAT
mode
,
1.5
mA
converter not switching
VVBUS > VUVLO, VVBUS > VVBAT
converter switching, VBAT = 3.8V,
ISYS = 0A
,
Input supply current (VBUS) in buck
mode
IVBUS
3
mA
VBUS, VAC AND BAT PIN POWER-UP
VBUS_OP
VBUS operating range
VAC for active I2C, no battery
VVBUS rising
VVAC rising
3.9
13.5
3.7
V
V
VVAC_UVLOZ
3.3
Sense VAC pin voltage
VVAC_UVLOZ_HYS I2C active hysteresis
VAC falling from above VVAC_UVLOZ
VVAC rising
300
mV
V
VVAC_PRESENT
VAC to turn on REGN
3.65
3.9
VVAC_PRESENT_H
YS
mV
VAC to turn on REGN hysteresis
VVAC falling
500
60
(VVAC–VVBAT ), VBUSMIN_FALL ≤ VBAT
≤ VREG, VAC falling
VSLEEP
Sleep mode falling threshold
Sleep mode rising threshold
15
115
131
340
6.75
11.5
15
mV
mV
V
(VVAC–VVBAT ), VBUSMIN_FALL ≤ VBAT
≤ VREG, VAC rising
VSLEEPZ
220
6.42
11
VAC 6.5-V Overvoltage rising
threshold
VVAC_OV_RISE
VVAC_OV_RISE
VVAC_OV_RISE
VAC rising; OVP (REG06[7:6]) = '01'
VAC rising, OVP (REG06[7:6]) = '10'
VAC rising, OVP (REG06[7:6]) = '11'
6.1
VAC 10.5-V Overvoltage rising
threshold
10.35
13.5
V
VAC 14-V Overvoltage rising
threshold
14.2
V
Copyright © 2017, Texas Instruments Incorporated
7
bq25600C
ZHCSGR7 –SEPTEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VAC falling, OVP (REG06[7:6]) =
'01'
VVAC_OV_HYS
VVAC_OV_HYS
VVAC_OV_HYS
VAC 6.5-V Overvoltage hysteresis
130
mV
VAC falling, OVP (REG06[7:6]) =
'10'
VAC 10.5-V Overvoltage hysteresis
250
300
mV
mV
VAC falling, OVP (REG06[7:6]) =
'11'
VAC 14-V Overvoltage hysteresis
VBAT_UVLOZ
BAT for active I2C, no adapter
Battery Depletion Threshold
Battery Depletion Threshold
Battery Depletion rising hysteresis
VBAT rising
VBAT falling
VBAT rising
VBAT rising
2.5
2.18
2.34
V
V
VBAT_DPL_FALL
VBAT_DPL_RISE
VBAT_DPL_HYST
2.62
2.86
V
180
3.8
180
30
mV
Bad adapter detection falling
threshold
VBUSMIN_FALL
VBUSMIN_HYST
IBADSRC
VBUS falling
3.68
3.9
V
Bad adapter detection hysteresis
mV
mA
Bad adapter detection current
source
Sink current from VBUS to GND
POWER-PATH
VSYS_MIN
VVBAT < SYS_MIN[2:0] = 101,
BATFET Disabled (REG07[5] = 1)
System regulation voltage
System Regulation Voltage
3.5
4.4
3.68
V
V
ISYS = 0 A, VVBAT > VSYSMIN, VVBAT
= 4.400 V, BATFET disabled
(REG07[5] = 1)
VBAT
+
VSYS
50 mV
ISYS = 0 A, , Q4 off, VVBAT≤ 4.400 V,
VVBAT > VSYSMIN = 3.5V
VSYS_MAX
Maximum DC system voltage output
Top reverse blocking MOSFET on-
4.45
35
4.48
V
RON(RBFET)
resistance between VBUS and PMID -40°C≤ TA ≤ 125°C
mΩ
- Q1
Top switching MOSFET on-
RON(HSFET)
resistance between PMID and SW - VREGN = 5 V , -40°C≤ TA ≤ 125°C
Q2
55
60
mΩ
mΩ
Bottom switching MOSFET on-
RON(LSFET)
resistance between SW and GND -
Q3
VREGN = 5 V , -40°C≤ TA ≤ 125°C
BATFET forward voltage in
supplement mode
VFWD
30
mV
Measured from BAT to SYS, VBAT
4.2V, TJ = –40 - 125°C
=
RON(BAT-SYS)
SYS-BAT MOSFET on-resistance
19.5
mΩ
BATTERY CHARGER
VBATREG_RANGE Charge voltage program range
3.856
4.624
V
VBATREG_STEP
Charge voltage step
32
mV
VREG (REG04[7:3]) = 4.208 V
(01011), V, –40 ≤ TJ ≤ 85°C
4.187
4.330
4.208
4.229
4.374
V
V
VBATREG
Charge voltage setting
VREG (REG04[7:3]) = 4.352 V
(01111), V, –40 ≤ TJ ≤ 85°C
4.352
VBAT = 4.208 V or VBAT = 4.352 V,
–40 ≤ TJ ≤ 85°C
VBATREG_ACC
Charge voltage setting accuracy
–0.5%
0
0.5%
3000
ICHG_REG_RANGE Charge current regulation range
mA
mA
ICHG_REG_STEP
Charge current regulation step
60
ICHG = 240 mA, VVBAT = 3.1V or
VVBAT = 3.8 V
ICHG_REG
Charge current regulation setting
0.214
–11%
0.24
0.26
9%
A
ICHG = 240 mA, VVBAT = 3.1 V or
VVBAT = 3.8 V
ICHG_REG_ACC
Charge current regulation accuracy
8
Copyright © 2017, Texas Instruments Incorporated
bq25600C
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ZHCSGR7 –SEPTEMBER 2017
Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICHG_REG
Charge current regulation setting
ICHG = 720 mA, VVBAT = 3.1 V or
VVBAT = 3.8 V
0.68
0.720
0.76
A
ICHG_REG = 720 mA, VBAT = 3.1 V or
VBAT = 3.8 V
ICHG_REG
Charge current regulation accuracy
Charge current regulation setting
Charge current regulation accuracy
-6%
1.30
–6%
6%
1.45
6%
ICHG = 1.38 A, VVBAT = 3.1 V or
VVBAT = 3.8 V
ICHG_REG
1.380
A
ICHG = 720 mA or ICHG = 1.38 A,
VVBAT = 3.1 V or VVBAT = 3.8 V
ICHG_REG_ACC
VBATLOWV_FALL
VBATLOWV_RISE
IPRECHG
Battery LOWV falling threshold
Battery LOWV rising threshold
Precharge current regulation
ICHG = 240 mA
2.7
3
2.8
3.12
170
2.9
3.24
190
V
V
Pre-charge to fast charge
IPRECHG[3:0] = '0010' = 180 mA
150
mA
Precharge current regulation
accuracy
IPRECHG_ACC
ITERM
IPRECHG[3:0] = '0010' = 180 mA
–15
145
5
%
Termination current regulation
ICHG > 780 mA, ITERM[3:0] = '0010'
= 180 mA, VVBAT = 4.208 V
180
60
215
mA
Termination current regulation
accuracy
ICHG > 780 mA, , ITERM[3:0] =
'0010' = 180 mA, VVBAT = 4.208 V
ITERM_ACC
ITERM
-20%
44
20%
75
ICHG ≤ 780 mA, , ITERM[3:0] =
Termination current regulation
mA
'0000' = 60 mA, VVBAT = 4.208 V
Termination current regulation
accuracy
ICHG ≤ 780 mA, ,ITERM[3:0] = '0000'
= 60 mA, VVBAT = 4.208 V
ITERM_ACC
-27%
25%
VSHORT
VSHORTZ
ISHORT
Battery short voltage
Battery short voltage
Battery short current
VVBAT falling
1.85
2.15
50
2
2.25
90
2.15
2.35
117
V
V
VVBAT rising
VVBAT < VSHORTZ
mA
Recharge Threshold below
VBAT_REG
VRECHG
VBAT falling, REG04[0] = 0
90
120
150
265
mV
Recharge Threshold below
VBAT_REG
VRECHG
VBAT falling, REG04[0] = 1
VSYS = 4.2 V
200
230
30
mV
mA
ISYSLOAD
System discharge load current
INPUT VOLTAGE AND CURRENT REGULATION
VINDPM
Input voltage regulation limit
Input voltage regulation accuracy
Input voltage regulation limit
Input voltage regulation accuracy
VINDPM (REG06[3:0] = 0000) = 3.9 V
VINDPM (REG06[3:0] = 0000) = 3.9 V
VINDPM (REG06[3:0] = 0110) = 4.4 V
VINDPM (REG06[3:0] = 0110) = 4.4 V
3.78
–4.5%
4.268
–3%
3.95
4.4
4.1
4%
V
V
V
VINDPM_ACC
VINDPM
VINDPM_ACC
VDPM_VBAT
4.532
3%
Input voltage regulation limit tracking VINDPM = 3.9V,
4.17
4.3
4.46
VBAT
VDPM_VBAT_TRACK = 300mV,
VBAT = 4.0V
VDPM_VBAT_ACC
Input voltage regulation accuracy
tracking VBAT
VINDPM = 3.9V,
VDPM_VBAT_TRACK = 300mV,
VBAT = 4.0V
–3%
4%
VVBUS = 5 V, current pulled from
SW, IINDPM (REG[4:0] = 00100) =
500 mA, –40 ≤ TJ ≤ 85°C
450
750
500
900
1.5
mA
mA
VVBUS = 5 V, current pulled from
SW, IINDPM (REG[4:0] = 01000) =
900 mA, –40 ≤ TJ ≤ 85°C
IINDPM
USB input current regulation limit
VVBUS = 5 V, current pulled from
SW, IINDPM (REG[4:0] = 01110) =
1.5 A, –40 ≤ TJ ≤ 85°C
1.28
A
Input current limit during system
start-up sequence
IIN_START
200
mA
BAT PIN OVERVOLTAGE PROTECTION
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Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBAT rising, as percentage of
VBAT_REG
VBATOVP_RISE
Battery overvoltage threshold
103
104
105
%
VBAT falling, as percentage of
VBAT_REG
VBATOVP_Fall_HYS Battery overvoltage falling hysteresis
2
%
10
Copyright © 2017, Texas Instruments Incorporated
bq25600C
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ZHCSGR7 –SEPTEMBER 2017
Electrical Characteristics (continued)
VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL REGULATION AND THERMAL SHUTDOWN
Junction Temperature Regulation
Temperature Increasing, TREG
(REG05[1] = 1) = 110℃
TJUNCTION_REG
Threshold
110
90
°C
°C
TJUNCTION_REG
Junction Temperature Regulation
Threshold
Temperature Increasing, TREG
(REG05[1] = 0) = 90℃
Thermal Shutdown Rising
Temperature
TSHUT
Temperature Increasing
160
30
°C
°C
TSHUT_HYST
Thermal Shutdown Hysteresis
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
IBATFET_OCP
PWM
System over load threshold
6.0
A
fSW
PWM switching frequency
Maximum PWM duty cycle(1)
Oscillator frequency, buck mode
1320
1500
97%
1680
kHz
DMAX
REGN LDO
VREGN
REGN LDO output voltage
REGN LDO output voltage
VVBUS = 9V, IREGN = 40mA
VVBUS = 5V, IREGN = 20mA
5.6
6
6.65
4.8
V
V
VREGN
4.58
4.7
LOGIC I/O PIN CHARACTERISTICS (CE, PSEL, SCL, SDA,, INT)
VILO
VIH
Input low threshold CE
0.4
V
V
Input high threshold CE
1.3
1.3
IBIAS
VILO
VIH
High-level leakage current CE
Input low threshold PSEL
Input high threshold PSEL
High-level leakage current PSEL
Pull up rail 1.8 V
Pull up rail 1.8V
1
µA
V
0.4
V
IBIAS
1
µA
LOGIC I/O PIN CHARACTERISTICS (PG, STAT)
VOL Low-level output voltage
(1) Specified by design. Not production tested.
0.4
V
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UNIT
7.6 Timing Requirements
MIN
NOM
MAX
VBUS/BAT POWER UP
VAC rising above ACOV threshold to
turn off Q2
tACOV
VAC OVP reaction time
200
30
ns
tBADSRC
Bad adapter detection duration
ms
BATTERY CHARGER
tTERM_DGL
Deglitch time for charge termination
250
250
ms
ms
tRECHG_DGL
Deglitch time for recharge
System over-current deglitch time to
turn off Q4
tSYSOVLD_DGL
tBATOVP
100
1
µs
µs
Battery over-voltage deglitch time to
disable charge
tSAFETY
Typical Charge Safety Timer Range
Typical Top-Off Timer Range
8
10
30
12
36
hr
tTOP_OFF
TOP_OFF_TIMER[1:0] = 10 (30 min)
24
min
DIGITAL CLOCK AND WATCHDOG TIMER
tWDT
fLPDIG
fDIG
REG05[4]=1
REGN LDO disabled
REGN LDO disabled
REGN LDO enabled
40
30
s
Digital Low Power Clock
Digital Clock
kHz
kHz
kHz
500
fSCL
SCL clock frequency
400
12
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ZHCSGR7 –SEPTEMBER 2017
7.7 Typical Characteristics
100
97.5
95
5
4
3
92.5
90
2
1
87.5
85
0
-1
-2
-3
-4
-5
82.5
80
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
77.5
75
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Charge Current (A)
Charge Current (A)
D001
D001
fSW = 1.5 MHz
VBAT = 3.8 V
Inductor DCR = 18 mΩ
图 1. Charge Efficiency vs. Charge Current
图 2. Charge Current Accuracy
3.85
3.8
4.5
4.4
4.3
4.2
4.1
4
VBATREG = 4.208 V
VBATREG = 4.352 V
3.75
3.7
3.65
3.6
3.55
3.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
D001
D001
图 3. SYSMIN Voltage vs. Junction Temperature
图 4. BATREG Charge Voltage vs. Junction Temperature
2.5
2.25
2
2
IINDPM = 0.5 A
IINDPM = 0.9 A
IINDPM = 1.5 A
ICHG = 0.24 A
ICHG = 0.72 A
ICHG = 1.38 A
1.8
1.6
1.75
1.5
1.25
1
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.75
0.5
0.25
0
-40
-25
-10
5
20
35
50
65
80
95
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
D001
D001
图 5. Input Current Limit vs. Junction Temperature
图 6. Charge Current vs. Junction Temperature
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Typical Characteristics (接下页)
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
110 °C
90 °C
55
65
75
85
95
105
115
125
135
Junction Temperature (°C)
D001
图 7. Charge Current vs. Junction Temperature Under Thermal Regulation
14
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bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
8 Detailed Description
8.1 Overview
The bq25600C device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-
polymer battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate
drive.
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8.2 Functional Block Diagram
VBUS
PMID
VVVAC_PRESENT
RBFET (Q1)
+
UVLO
SLEEP
ACOV
VVAC
Q1 Gate
Control
œ
IIN
VBAT + VSLEEP
+
REGN
EN_REGN
EN_HIZ
VVAC
REGN
LDO
œ
VVAC
+
VVAC_OV
œ
BTST
FBO
VAC
VAC
BAT
+
BATOVP
UCP
VVBUS
104% × V BAT_REG
ILSFET_UCP
IQ3
œ
+
+
œ
+
œ
œ
+
HSFET (Q2)
LSFET (Q3)
œ
VINDPM
SW
+
IIN
CONVERTER
Control
REGN
œ
IINDPM
IC TJ
TREG
PGND
IQ2
BATSNS
VBAT_REG
Q2_OCP
+
œ
+
œ
+
IHSFET_OCP
SYS
œ
VSYSMIN
VBTST - VSW
ICHG
EN_HIZ
+
REFRESH
EN_CHARGE
VBTST_REFRESH
ICHG_REG
œ
SYS
ICHG
VBAT_REG
ICHG_REG
BATFET
(Q4)
Q4 Gate
Control
BAT
IBADSRC
IDC
BAD_SRC
+
REF
DAC
Converter
œ
Control State
Machine
IC TJ
TSHUT
+
TSHUT
œ
BATSNS
BATSNS
VBATGD
BAT_GD
+
Input
Source
œ
PSEL
USB
Detection
Adapter
VREG -VRECHG
BATSNS
ICHG
+
RECHRG
œ
INT
STAT
PG
+
TERMINATION
BATLOWV
ITERM
œ
CHARGE
CONTROL
STATE
VBATLOWV
+
BATSNS
VSHORT
MACHINE
œ
+
BATSHORT
SUSPEND
BATSNS
I2C
Interface
œ
SCL SDA CE
Copyright © 2017, Texas Instruments Incorporated
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ZHCSGR7 –SEPTEMBER 2017
8.3 Feature Description
8.3.1 Power-On-Reset (POR)
The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above
VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET
driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
8.3.2 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above depletion threshold (VBAT_DPL_RISE), the BATFET turns on and
connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET
and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
8.3.3 Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started. The power up
sequence from input source is as listed:
1. Power Up REGN LDO
2. Poor Source Qualification
3. IInput Source Type Detection is based on PSEL to set default input current limit (IINDPM) register or input
source type.
4. Input Voltage Limit Threshold Setting (VINDPM threshold)
5. Converter Power-up
8.3.3.1 Power Up REGN Regulation
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid:
•
•
•
above VVAC_PRESENT
VVAC above VBAT + VSLEEPZ in buck mode
After 220-ms delay is completed
If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off.
The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when
the device is in HIZ.
8.3.3.2 Poor Source Qualification
After REGN LDO powers up, the device confirms the current capability of the input source. The input source
must meet both of the following requirements in order to start the buck converter.
•
•
voltage below VVAC_OV
VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30 mA)
Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT
pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification
every 2 seconds.
8.3.3.3 Input Source Type Detection
After the VBUS_GD bit is set and REGN LDO is powered, the device runs input source detection through PSEL
pin. The bq25600C sets input current limit through PSEL pins.
After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following
registers and pin are changed:
1. Input Current Limit (IINDPM) register is changed to set current limit
2. PG_STAT bit is set
3. VBUS_STAT bit is updated to indicate USB or other input source
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Feature Description (接下页)
The host can over-write IINDPM register to change the input current limit if needed. The charger input current is
always limited by the IINDPM register.
8.3.3.3.1 PSEL Pins Sets Input Current Limit in bq25600C
The bq25600C has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB
PHY device output to decide whether the input is USB host or charging port. When the device operates in host-
control mode, the host needs to IINDET_EN bit to read the PSEL value and update the IINDPM register. When
the device is in default mode, PSEL value updates IINDPM in real time.
表 1. Input Current Limit Setting from PSEL
INPUT CURRENT LIMIT
Input Detection
PSEL Pin
VBUS_STAT
(ILIM)
500 mA
2.4 A
USB SDP
Adapter
High
Low
001
011
8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device supports wide range of input voltage limit (3.9 V – 5.4 V) for USBThe device's VINDPM is set at 4.5
V. The device supports dynamic VINDPM trackingsettings which tracks the battery voltage. This function can be
enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the actual input voltage limit will be the
higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.
8.3.3.5 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current is limited to is to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the
device limits input current to the value set by IINDPM register.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
The device switches to PFM control at light load or when battery is below minimum system voltage setting or
charging is disabled. The PFM_DIS bit can be used to prevent PFM operation in either buck configuration.
8.3.4 Host Mode and Standalone Power Management
8.3.4.1 Host Mode and Default Mode in bq25600C
The bq25600C is a host controlled charger, but it can operate in default mode without host management. In
default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode.
When the charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,
WATCHDOG_FAULT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings. During default mode, any change on PSEL pin will make real time IINDPM
register changes.
in default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end
of the 10-hour, the charging is stopped and the buck converter continues to operate to supply system load.
Writing a 1 to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters
can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by
writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog
timer by setting WATCHDOG bits = 00.
18
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ZHCSGR7 –SEPTEMBER 2017
When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all
registers are reset to default values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and
BATFET_DIS bits.
POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Y
I2C Write?
N
Start watchdog timer
Host programs registers
Default Mode
Reset watchdog timer
Reset selective registers
Y
N
WD_RST bit = 1?
N
N
Y
Y
I2C Write?
Watchdog Timer
Expired?
图 8. Watchdog Timer Flow Chart
8.3.5 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.3.6 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5-
mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.
8.3.6.1 Autonomous Charging Cycle
With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously
completes a charging cycle without host involvement. The device default charging parameters are listed in 表 2.
The host can always control the charging operations and optimize the charging parameters by writing to the
corresponding registers through I2C.
表 2. Charging Parameter Default Setting
PARAMETER
Charging voltage
Charging current
Pre-charge current
Termination current
Safety timer
SETTING
4.208 V
2.048 A
180 mA
180 mA
10 hours
A new charge cycle starts when the following conditions are valid:
•
•
•
•
Converter starts
Battery charging is enabled (CHG_CONFIG bit = 1 and ICHG register is not 0 mA and CE is low)
No safety timer fault
BATFET is not forced to turn off (BATFET_DIS bit = 0)
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The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation.
When a fully charged battery is discharged below recharge threshold (selectable through VRECHG bit), the
device automatically starts a new charging cycle. After the charge is done, toggle CE pin or CHG_CONFIG bit
can initiate a new charging cycle.
The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or
charging fault (Blinking). The STAT output can be disabled by setting EN_ICHG_MON bits = 11. in addition, the
status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast
charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an
INT is asserted to notify the host.
8.3.6.2 Battery Charging Profile
The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage
and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage
and regulates current and voltage accordingly.
表 3. Charging Current Setting
REGISTER DEFAULT
VBAT
CHARGinG CURRENT
CHRG_STAT
SETTinG
100 mA
180 mA
2.048 A
< 2.2 V
2.2 V to 3 V
> 3 V
ISHORT
IPRECHG
ICHG
01
01
10
If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. in this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate.
Regulation Voltage
VREG[7:3]
Battery Voltage
Charge Current
ICHG[5:0]
Charge Current
VBATLOWV (3 V)
VSHORTZ (2.2 V)
IPRECHG[7:4]
ITERM[3:0]
ISHORT
Fast Charge and Voltage Regulation
Trickle Charge
Pre-charge
Top-off Timer
(optional)
Safety Timer
Expiration
图 9. Battery Charging Profile
8.3.6.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
20
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ZHCSGR7 –SEPTEMBER 2017
When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.
Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation.
Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
At low termination currents (25 mA-50 mA), due to the comparator offset, the actual termination current may be
10 mA-20 mA higher than the termination target. in order to compensate for comparator offset, a programmable
top-off timer can be applied after termination is detected. The termination timer will follow safety timer
constraints, such that if safety timer is suspended, so will the termination timer. Similarly, if safety timer is
doubled, so will the termination timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The
host can read CHRG_STAT and TOPOFF_ACTIVE to find out the termination status.
Top off timer gets reset at one of the following conditions:
1. Charge disable to enable
2. Termination status low to high
3. REG_RST register bit is set
The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer
value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host
when entering top-off timer segment as well as when top-off timer expires.
8.3.6.4 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is 2 hours when the battery is below VBATLOWV threshold and 10 hours when the battery is higher
than VBATLOWV threshold.
The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the
fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be
disabled through I2C by setting EN_TIMER bit
During input voltage, current, or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the register setting. For example, if the charger is in input current regulation
(IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will
expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.
During the fault, timer is suspended. Once the fault goes away, fault resumes. If user stops the current charging
cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).
8.3.6.5 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by SYS_Min bits. Even with a fully depleted battery, the system is regulated
above the minimum system voltage.
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises
above the minimum system voltage, BATFET is fully on and the voltage difference between the system and
battery is the VDS of BATFET.
When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the
system is always regulated at typically 50mV above battery voltage. The status register VSYS_STAT bit goes
high when the system is in minimum system voltage regulation.
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4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
Charge Disabled
Charge Enabled
Minimum System Voltage
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
BAT (V)
D002
Plot1
图 10. System Voltage vs Battery Voltage
8.3.7 Shipping Mode
8.3.7.1 BATFET Disable Mode (Shipping Mode)
To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,
the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When
the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configured by
BATFET_DLY bit.
8.3.7.2 BATFET Enable (Exit Shipping Mode)
When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following
events can enable BATFET to restore system power:
1. Plug in adapter
2. Clear BATFET_DIS bit
3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
8.3.8 Status Outputs (PG, STAT)
8.3.8.1 Power Good indicator (PG Pin and PG_STAT Bit)
The PG_STAT bit goes HIGH and PG pin goes LOW to indicate a good input source when:
•
•
•
•
•
VBUS above VVBUS_UVLO
VBUS above battery (not in sleep)
VBUS below VVAC_OV threshold
VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
Completed input Source Type Detection
8.3.8.2 Charging Status indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin
function can be disabled by setting the EN_ICHG_MON bits = 11.
表 4. STAT Pin State
CHARGING STATE
STAT INDICATOR
Charging in progress (including recharge)
Charging complete
LOW
HIGH
HIGH
Sleep mode, charge disable
22
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ZHCSGR7 –SEPTEMBER 2017
表 4. STAT Pin State (接下页)
CHARGING STATE
STAT INDICATOR
Charge suspend (input overvoltage, TS fault, timer fault or system overvoltage)
Blinking at 1 Hz
8.3.8.3 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT pulse notifies the system
on the device operation. The following events will generate 256-μs INT pulse.
•
•
USB/adapter source identified (through PSEL or DPDMdetection)
Good input source detected
–
–
–
VBUS above battery (not in sleep)
VBUS below VVAC_OV threshold
VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
•
•
•
•
input removed
Charge Complete
Any FAULT event in REG09
VINDPM / IINDPM event detected (maskable)
When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads
the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send
any INT upon new faults. To read the current fault status, the host has to read REG09 two times consecutively.
The first read reports the pre-existing fault register status and the second read reports the current fault register
status.
8.3.9 Protections
8.3.9.1 Voltage and Current Monitoring in Converter Operation
The device closely monitors the input and system voltage, as well as internal FET currents for safe buck mode
operation.
8.3.9.1.1 Voltage and Current Monitoring in Buck Mode
8.3.9.1.1.1 Input Overvoltage (ACOV)
This device integrates the functionality of an overvoltage protector. The input voltage is sensed via the VAC pin.
The OVP threshold defaults to 6.2V, but can be programmed at 5.5V, 6.2V, 10.5V, or 14.3V via OVP register
bits. The ACOV circuit has a reaction time of tAC_OV_FLT
.
During input overvoltage event (ACOV), the fault register CHRG_FAULT bits are set to 01. An INT pulse is
asserted to the host. The device will automatically resume normal operation once the input voltage drops back
below the OVP threshold.
8.3.9.2 Thermal Regulation and Thermal Shutdown
8.3.9.2.1 Thermal Protection in Buck Mode
The bq25600C device monitors the internal junction temperature TJ to avoid overheat the chip and limits the
device surface temperature in buck mode. When the internal junction temperature exceeds thermal regulation
limit (110°C), the device lowers down the charge current. During thermal regulation, the actual charging current is
usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs
at half the clock rate, and the status register THERM_STAT bit goes high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when device surface
temperature exceeds TSHUT(160ºC). The fault register CHRG_FAULT is set to 1 and an INT is asserted to the
host. The BATFET and converter is enabled to recover when IC temperature is TSHUT_HYS (30ºC) below
TSHUT(160ºC).
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8.3.9.3 Battery Protection
8.3.9.3.1 Battery overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charging. The fault register BAT_FAULT bit goes high and an
INT is asserted to the host.
8.3.10 Serial interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP
Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices
can be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.
The device operates as a slave device with address 6AH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG0B. Register read beyond REG0B (0x0B)
returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).
connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines
are HIGH. The SDA and SCL pins are open drain.
8.3.10.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change of data
allowed
Figure 11. Bit Transfer on the I2C Bus
8.3.10.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the mAster. The
bus is considered busy after the START condition, and free after the STOP condition.
SDA
SCL
SDA
SCL
START (S)
STOP (P)
Figure 12. TS START and STOP conditions
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8.3.10.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the mAster into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement
signal from slave
Acknowledgement
signal from receiver
MSB
1
SDA
SCL
2
7
8
9
1
2
8
9
S or Sr
P or Sr
START or
Repeated
START
STOP or
Repeated
START
ACK
ACK
Figure 13. Data Transfer on the I2C Bus
8.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge ninth clock pulse, are generated by the mAster. The transmitter releases the SDA line during the
acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH
period of this clock pulse.
When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The mAster can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.3.10.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
1 - 7
8
9
1-7
8
9
1-7
8
9
S
P
SCL
START
ADDRESS
R / W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 14. Complete Data Transfer
8.3.10.6 Single Read and Write
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
1
7
1
0
1
8
1
8
1
1
S
Slave Address
ACK
Reg Addr
ACK
Data to Addr
ACK
P
Figure 15. Single Write
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1
7
1
0
1
8
1
1
7
1
1
1
S
Slave Address
ACK
Reg Addr
ACK
S
Slave Addr
ACK
8
1
1
Data
NCK
P
Figure 16. Single Read
8.3.10.7 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG0B.
1
7
1
0
1
8
1
S
Slave Address
ACK
Reg Addr
ACK
8
1
8
1
8
1
1
Data to Addr
ACK
Data to Addr + N
ACK
Data to Addr + N
ACK
P
Figure 17. Multi-Write
1
7
1
1
8
1
1
7
1
1
1
S
Slave Address
0
ACK
Reg Addr
ACK
S
Slave Address
ACK
8
1
8
1
8
1
1
Data @ Addr
ACK
Data @ Addr + 1
ACK
Data @ Addr + N NCK
P
Figure 18. Multi-Read
REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For
example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the
fault when it is read the first time, but returns to normal when it is read the second time. in order to get the fault
information at present, the host has to read REG09 for the second time. The only exception is NTC_FAULT
which always reports the actual condition on the TS pin. in addition, REG09 does not support multi-read and
multi-write.
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ZHCSGR7 –SEPTEMBER 2017
8.4 Register Maps
I2C Slave Address: 6AH
8.4.1 REG00
表 5. REG00 Field Descriptions
Bit
Field
POR
Type Reset
Description
Comment
7
Enable HIZ Mode
0 – Disable (default)
1 – Enable
by REG_RST
by Watchdog
EN_HIZ
0
R/W
0 – Disable, 1 – Enable
6
5
4
3
2
1
Reserved
Reserved
IINDPM[4]
IINDPM[3]
IINDPM[2]
IINDPM[1]
1
0
1
1
R/W by REG_RST 1600 mA
R/W by REG_RST 800 mA
R/W by REG_RST 400 mA
R/W by REG_RST 200 mA
Input Current Limit
Offset: 100 mA
Range: 100 mA (000000) – 3.2 A
(11111)
Default:, maximum input current
limit, not typical.
IINDPM bits are changed
automatically after input source
detection is completed
bq25600C
PSEL = Hi = 500 mA
PSEL = Lo =
0
IINDPM[0]
1
R/W by REG_RST 100 mA
Host can over-write IINDPM
register bits after input source
detection is completed.
LEGEND: R/W = Read/Write; R = Read only
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8.4.2 REG01
表 6. REG01 Field Descriptions
Bit
Field
POR
Type Reset
Description
Comment
0 – Enable PFM
1 – Disable PFM
7
PFM _DIS
0
R/W by REG_RST
Default: 0 - Enable
I2C Watchdog Timer Reset 0 –
Normal ; 1 – Reset
Default: Normal (0) Back to 0 after
watchdog timer reset
by REG_RST
R/W
6
5
WD_RST
Reserved
0
1
by Watchdog
Default: Charge Battery (1)
Note:
1. Charge is enabled when both
CE pin is pulled low AND
CHG_CONFIG bit is 1.
by REG_RST
R/W
0 - Charge Disable
1- Charge Enable
4
CHG_CONFIG
by Watchdog
3
2
SYS_Min[2]
SYS_Min[1]
1
0
R/W by REG_RST
R/W by REG_RST
000: 2.6 V
001: 2.8 V
010: 3 V
011: 3.2 V
100: 3.4 V
101: 3.5 V
110: 3.6 V
111: 3.7 V
Default: 3.5 V (101)
System Minimum Voltage
1
0
SYS_Min[0]
Reserved
1
R/W by REG_RST
LEGEND: R/W = Read/Write; R = Read only
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ZHCSGR7 –SEPTEMBER 2017
8.4.3 REG02
表 7. REG02 Field Descriptions
Bit
Field
POR
Type Reset
Description
Comment
7
Reserved
by REG_RST 0 – Use higher Q1 RDSON when
programmed IINDPM < 700mA
(better accuracy)
6
Q1_FULLON
0
R/W
1 – Use lower Q1 RDSON always
(better efficiency)
by REG_RST
by Watchdog
5
4
3
2
1
0
ICHG[5]
ICHG[4]
ICHG[3]
ICHG[2]
ICHG[1]
ICHG[0]
R/W
R/W
R/W
R/W
R/W
R/W
by REG_RST
by Watchdog
Fast Charge Current
Default: 2040mA (100010)
Range: 0 mA (0000000) – 3000
mA (110010)
0
1
by REG_RST
by Watchdog
Note:
by REG_RST
by Watchdog
ICHG = 0 mA disables charge.
ICHG > 3000 mA (110010 clamped
to register value 3000 mA
(110010))
by REG_RST
by Watchdog
by REG_RST
by Watchdog
LEGEND: R/W = Read/Write; R = Read only
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8.4.4 REG03
表 8. REG03 Field Descriptions
Bit
Field
POR
Type Reset
Description
Comment
7
IPRECHG[3]
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
by REG_RST
by Watchdog
Precharge Current
Default: 180 mA (0010)
Offset: 60 mA
Note: IPRECHG > clamped to
(1100)
6
5
4
3
2
1
0
IPRECHG[2]
IPRECHG[1]
IPRECHG[0]
ITERM[3]
0
by REG_RST
by Watchdog
by REG_RST
by Watchdog
by REG_RST
by Watchdog
0
0
by REG_RST
by Watchdog
Termination Current
Default: 180 mA (0010)
Offset: 60 mA
Note: ITERM > 780 mA clamped
to (1100)
ITERM[2]
by REG_RST
by Watchdog
ITERM[1]
by REG_RST
by Watchdog
ITERM[0]
by REG_RST
by Watchdog
LEGEND: R/W = Read/Write; R = Read only
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ZHCSGR7 –SEPTEMBER 2017
8.4.5 REG04
表 9. REG04 Field Descriptions
Bit
Field
POR
Type Reset
Description
Comment
by REG_RST
by Watchdog
7
VREG[4]
0
R/W
R/W
R/W
R/W
R/W
512 mV
Charge Voltage
Offset: 3.856 V
by REG_RST
by Watchdog
6
5
4
3
VREG[3]
VREG[2]
VREG[1]
VREG[0]
1
0
1
1
256 mV
128 mV
64 mV
32 mV
Range: 3.856
(11000)
V
to 4.624
V
by REG_RST
by Watchdog
Default: 4.208 V (01011)
Special Value:
by REG_RST
by Watchdog
(01111): 4.352 V
Note: Value above 11000 (4.624
V) is clamped to register value
11000 (4.624 V)
by REG_RST
by Watchdog
2
1
Reserved
Reserved
by REG_RST
by Watchdog
0 – 100 mV
1 – 200 mV
Recharge threshold
Default: 100mV (0)
0
VRECHG
0
R/W
LEGEND: R/W = Read/Write; R = Read only
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8.4.6 REG05
表 10. REG05 Field Descriptions
Bit
Field
POR
Type Reset
Description
Comment
by REG_RST 0 – Disable
by Watchdog 1 – Enable
7
EN_TERM
1
R/W
Default: Enable termination (1)
Default: Enable OVPFET (0)
Note: This bit only takes effect
when EN_HIZ bit is active
by REG_RST
by Watchdog
0 – Enable OVPFET
1 – Disable OVPFET
6
OVPFET_DIS
0
R/W
by REG_RST
by Watchdog
5
4
WATCHDOG[1]
WATCHDOG[0]
0
1
R/W
R/W
00 – Disable timer, 01 – 40 s, 10 –
80 s,11 – 160 s
Default: 40 s (01)
by REG_RST
by Watchdog
0 – Disable
1 – Enable both fast charge and
precharge timer
by REG_RST
by Watchdog
3
2
EN_TIMER
1
1
1
R/W
R/W
R/W
Default: Enable (1)
Default: 10 hours (1)
Default: 110°C (1)
by REG_RST 0 – 5 hrs
by Watchdog 1 – 10 hrs
CHG_TIMER
Thermal Regulation Threshold:
by REG_RST
by Watchdog
1
0
TREG
0 - 90°C
1 - 110°C
Reserved
LEGEND: R/W = Read/Write; R = Read only
32
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ZHCSGR7 –SEPTEMBER 2017
8.4.7 REG06
表 11. REG06 Field Descriptions
Bit
Field
POR
Type Reset
Description
Comment
7
OVP[1]
0
R/W by REG_RST
R/W by REG_RST
VAC OVP threshold:
00 - 5.5 V
01 – 6.5 V (5-V input)
10 – 10.5 V (9-V input)
11 – 14 V (12-V input)
Default: 6.5V (01)
6
OVP[0]
1
5
4
3
2
1
0
Reserved
Reserved
VINDPM[3]
VINDPM[2]
VINDPM[1]
VINDPM[0]
0
1
1
0
R/W by REG_RST 800 mV
R/W by REG_RST 400 mV
R/W by REG_RST 200 mV
R/W by REG_RST 100 mV
Absolute VINDPM Threshold
Offset: 3.9 V
Range: 3.9 V (0000) – 5.4 V
(1111)
Default: 4.5V (0110)
LEGEND: R/W = Read/Write; R = Read only
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8.4.8 REG07
表 12. REG07 Field Descriptions
Bit
Field
POR
Type Reset
Description
Comment
7
Reserved
0 – Disable
by REG_RST
by Watchdog
1 – Safety timer slowed by 2X
during input DPM (both V and I) or
thermal regulation
6
TMR2X_EN
1
0
R/W
0 – Allow Q4 turn on, 1 – Turn off
5
4
BATFET_DIS
Reserved
R/W by REG_RST Q4 with tBATFET_DLY delay time
(REG07[3])
Default: Allow Q4 turn on(0)
0 – Turn off BATFET immediately
when BATFET_DIS bit is set
R/W by REG_RST 1 –Turn off BATFET after
tBATFET_DLY (typ. 10 s) when
Default: 1
Turn off BATFET after tBATFET_DLY
(typ. 10 s) when BATFET_DIS bit
is set
3
BATFET_DLY
1
BATFET_DIS bit is set
by REG_RST
by Watchdog
0 – Disable BATFET reset function Default: 1
1 – Enable BATFET reset function Enable BATFET reset function
2
1
BATFET_RST_EN
1
0
R/W
VDPM_BAT_TRACK[1]
R/W by REG_RST 00 - Disable function (VINDPM set
Sets VINDPM to track BAT
voltage. Actual VINDPM is higher
of register value and VBAT +
VDPM_BAT_TRACK
by register)
01 - VBAT + 200mV
10 - VBAT + 250mV
11 - VBAT + 300mV
0
VDPM_BAT_TRACK[0]
0
R/W by REG_RST
LEGEND: R/W = Read/Write; R = Read only
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ZHCSGR7 –SEPTEMBER 2017
8.4.9 REG08
表 13. REG08 Field Descriptions
Bit
7
Field
POR
Type Reset
Description
VBUS_STAT[2]
VBUS_STAT[1]
x
x
R
R
NA
NA
VBUS Status register
bq25600C
000: No input
6
001: USB Host SDP (500 mA) → PSEL HIGH
010: Adapter → PSEL LOW
111: Reserved
5
VBUS_STAT[0]
x
R
NA
Software current limit is reported in IINDPM register
4
3
CHRG_STAT[1]
CHRG_STAT[0]
x
x
R
R
NA
NA
Charging status:
00 – Not Charging
01 – Pre-charge (< VBATLOWV
10 – Fast Charging
)
11 – Charge Termination
Power Good status:
0 – Power Not Good
1 – Power Good
2
PG_STAT
x
R
NA
0 – Not in ther mAl regulation
1 – in ther mAl regulation
1
0
THERM_STAT
VSYS_STAT
x
x
R
R
NA
NA
0 – Not in VSYSMin regulation (BAT > VSYSMin)
1 – in VSYSMin regulation (BAT < VSYSMin)
LEGEND: R/W = Read/Write
版权 © 2017, Texas Instruments Incorporated
35
bq25600C
ZHCSGR7 –SEPTEMBER 2017
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8.4.10 REG09
表 14. REG09 Field Descriptions
Bit
7
Field
POR
Type Reset
Description
WATCHDOG_FAULT
Reserved
x
R
NA
0 – Normal, 1- Watchdog timer expiration
6
5
CHRG_FAULT[1]
CHRG_FAULT[0]
BAT_FAULT
Reserved
x
x
x
R
R
R
NA
NA
NA
00 – Normal, 01 – input fault (VAC OVP or VBAT < VBUS < 3.8 V), 10 -
Thermal shutdown, 11 – Charge Safety Timer Expiration
4
3
0 – Normal, 1 – BATOVP
2
1
Reserved
0
Reserved
LEGEND: R/W = Read/Write; R = Read only
36
版权 © 2017, Texas Instruments Incorporated
bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
8.4.11 REG0A
表 15. REG0A Field Descriptions
Bit
Field
POR
Type Reset
Description
0 – Not VBUS attached,
1 – VBUS Attached
7
VBUS_GD
x
R
NA
6
5
4
3
VINDPM_STAT
IINDPM_STAT
Reserved
x
x
x
R
R
R
NA
NA
NA
0 – Not in VINDPM, 1 – in VINDPM
0 – Not in IINDPM, 1 – in IINDPM
Reserved
0 – Device is NOT in ACOV
1 – Device is in ACOV
2
1
0
ACOV_STAT
x
0
0
R
NA
0 - Allow VINDPM INT pulse
1 - Mask VINDPM INT pulse
VINDPM_INT_ MASK
IINDPM_INT_ MASK
R/W by REG_RST
R/W by REG_RST
0 - Allow IINDPM INT pulse
1 - Mask IINDPM INT pulse
LEGEND: R/W = Read/Write; R = Read only
版权 © 2017, Texas Instruments Incorporated
37
bq25600C
ZHCSGR7 –SEPTEMBER 2017
www.ti.com.cn
8.4.12 REG0B
表 16. REG0B Field Descriptions
Bit
Field
POR
Type Reset
Description
Register reset
0 – Keep current register setting
1 – Reset to default register value and reset safety timer
Note: Bit resets to 0 after register reset is completed
7
REG_RST
0
R/W NA
6
5
4
3
2
1
0
PN[3]
x
x
x
x
R
R
R
R
NA
NA
NA
NA
PN[2]
bq25600C: 0110
PN[1]
PN[0]
Reserved
DEV_REV[1]
DEV_REV[0]
x
x
R
R
NA
NA
LEGEND: R/W = Read/Write; R = Read only
9 Application and Implementation
注
information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application information
A typical application consists of the device configured as an I2C controlled parallel charger with a main charger
bq25600 to fast charge single cell Li-Ion and Li-polymer batteries used in a wide range of smart phones and
other portable devices. bq25600 and bq25660C have different I2C address so that two devices can share the
same I2C bus.
38
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bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
9.2 Typical Application Diagram
VIN
3.9V œ 13.5V
SYSTEM
3.5V œ 4.6V
1 ꢀH
VBUS
PMID
SW
1 ꢀF
10 ꢀF
47 nF
BTST
REGN
10 ꢀF
4.7 µF
GND
SYS
bq25600
(Main Charger)
BAT
VREF
10 ꢀF
REGN
5.23 kꢁ
SDA
SCL
/INT
TS
Host
+
30.1 kꢁ 10 kꢁ
/QON
Optional
1 ꢀH
VBUS
SW
10 ꢀF
1 ꢀF
47 nF
PMID
BTST
REGN
10 ꢀF
4.7 µF
GND
SYS
bq25600C
(Parallel Charger)
SDA
SCL
/INT
BAT
10 ꢀF
Copyright © 2017, Texas Instruments Incorporated
图 19. Parallel Charger Application
版权 © 2017, Texas Instruments Incorporated
39
bq25600C
ZHCSGR7 –SEPTEMBER 2017
www.ti.com.cn
Typical Application Diagram (接下页)
9.2.1 Design Requirements
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor
saturation current higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ≥ ICHG + (1/2) IRIPPLE
(1)
The inductor ripple current depends on the input voltage (VVBUS), the duty cycle (D = VBAT/VVBUS), the switching
frequency (fS) and the inductance (L).
VIN ´D ´ (1- D)
=
IRIPPLE
fs ´ L
(2)
The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually inductor
ripple is designed in the range between 20% and 40% maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
9.2.2.2 input Capacitor
Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The
worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst case capacitor RMS current ICin occurs where the duty cycle is closest
to 50% and can be estimated using 公式 3.
ICIN = ICHG ´ D ´ (1- D)
(3)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher capacitor is
preferred for 15 V input voltage. Capacitance of 22-μF is suggested for typical of 3A charging current.
9.2.2.3 Output Capacitor
Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.
公式 4 shows the output capacitor RMS current ICOUT calculation.
IRIPPLE
ICOUT
=
» 0.29 ´ IRIPPLE
2 ´
3
(4)
The output capacitor voltage ripple can be calculated as follows:
æ
ç
è
ö
VOUT
8LCfs2
VOUT
V
DVO =
1-
÷
IN ø
(5)
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensation optimized for >20μF ceramic output capacitance. The
preferred ceramic capacitor is 10V rating, X7R or X5R.
40
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bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
9.3 Application Curves
VVBUS = 5 V
VVBAT = 3.2 V
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
图 20. Power-Up with Charge Disabled
图 21. Power-Up with Charge Enabled
VVBUS = 5 V
ISYS = 50 mA
VVBUS = 9 V
ISYS = 50 mA
Charge Disabled
Charge Disabled
图 22. PFM Switching in Buck Mode
图 23. PFM Switching in Buck Mode
VVBUS = 12 V
ISYS = 50 mA
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.8 V
Charge Disabled
图 24. PFM Switching in Buck Mode
图 25. PWM Switching in Buck Mode
版权 © 2017, Texas Instruments Incorporated
41
bq25600C
ZHCSGR7 –SEPTEMBER 2017
www.ti.com.cn
Application Curves (接下页)
VVBUS = 12 V
ICHG = 2 A
VVBAT = 3.8 V
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
图 26. PWM Switching in Buck mode
图 27. Charge Enable
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
图 28. Charge Disable
42
版权 © 2017, Texas Instruments Incorporated
bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
10 Power Supply Recommendations
In order to provide an output voltage on the SYS pins, the bq25600C device requires a power supply between
3.9 V and 14.2 V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery
with voltage > VBATUVLO connected to BAT. The source current rating needs to be at least 3 A in order for the
buck converter of the charger to provide maximum output power to SYS.
版权 © 2017, Texas Instruments Incorporated
43
bq25600C
ZHCSGR7 –SEPTEMBER 2017
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see 图 29) is important to prevent electrical
andmagnetic field radiation and high frequency resonant problems.
IMPORTANT
It is essential to follow this specific layout PCB order.
•
Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
•
•
Put output capacitor near to the inductor and the device.
Decoupling capacitors should be placed next to the device pins and make trace connection as short as
possible.
•
Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
•
•
It is OK to connect all grounds together to reduce PCB size and improve thermal dissipation.
Try to avoid ground planes in parallel with high frequency traces in other layers.
See the EVM design for the recommended component placement with trace and via locations.
11.2 Layout Example
+
+
œ
图 29. High Frequency Current Path
44
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bq25600C
www.ti.com.cn
ZHCSGR7 –SEPTEMBER 2017
12 器件和文档支持
12.1 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.2 商标
E2E is a trademark of Texas Instruments.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更,恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本,请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
45
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25600CYFFR
BQ25600CYFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
30
30
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ25600C
BQ25600C
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
YFF0030
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
5
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
1.6 TYP
SYMM
F
E
D: Max = 2.392 mm, Min =2.332 mm
E: Max = 1.992 mm, Min =1.931 mm
D
C
SYMM
2
TYP
B
A
0.4 TYP
1
2
4
5
3
0.3
30X
0.4 TYP
0.2
0.015
C A B
4219433/A 03/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0030
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
30X ( 0.23)
(0.4) TYP
2
4
5
1
A
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219433/A 03/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0030
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
30X ( 0.25)
(R0.05) TYP
1
3
2
4
5
A
B
(0.4)
TYP
METAL
TYP
C
D
E
F
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219433/A 03/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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