BQ25616RTWR [TI]
具有电源路径和 1.2A 升压操作的独立式单节 3.0A 降压型电池充电器 | RTW | 24 | -40 to 85;
| 型号： | BQ25616RTWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源路径和 1.2A 升压操作的独立式单节 3.0A 降压型电池充电器 | RTW | 24 | -40 to 85 电池 |
| 文件： | 总50页 (文件大小：3335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ25616, BQ25616J
ZHCSKP6A –JANUARY 2020 –REVISED FEBRUARY 2022
BQ25616/616J 具有电源路径和1.2A 升压电流的独立单芯3.0A 降压电池充电器
1 特性
3 说明
• 高效1.5MHz 同步开关模式降压充电器
BQ25616/616J 是适用于单节锂离子电池和锂聚合物电
池、高度集成的 3A 开关模式电池充电管理和系统电源
路径管理器件。该解决方案在系统和电池之间高度集成
输入反向阻断 FET（RBFET，Q1）、高侧开关 FET
（HSFET，Q2）、低侧开关 FET（LSFET，Q3）以
及电池 FET（BATFET，Q4）。其低阻抗电源路径对
开关模式运行效率进行了优化，缩短了电池充电时间并
延长了放电阶段的电池运行时间。
– 在2A 电流（5V 输入）下具有92% 的充电效率
– ±0.5% 充电电压调节
– 通过VSET 引脚实现的可调节充电电压支持
4.1V、4.2V 和4.35 V 电压，稳压精度为±0.4%
– 充电电流调节范围为±6%
– 输入电流调节范围为±7.5%
– 支持JEITA (BQ25616J) 或热/冷(BQ25616) 温
度感应曲线
BQ25616/616J 是适用于锂离子电池和锂聚合物电池、
高度集成的 3A 开关模式电池充电管理和系统电源路径
管理器件。它可为扬声器、工业和医疗便携式设备等各
种应用提供快速充电功能和高输入电压。其低阻抗电源
路径对开关模式运行效率进行了优化，缩短了电池充电
时间并延长了放电阶段的电池运行时间。其输入电压和
电流调节可以为电池提供最大的充电功率。
– 10 小时充电安全计时器
• 支持USB On-The-Go (OTG)
– 具有高达1.2A 输出的5V 升压转换器
– 在1A 输出下具有92% 的升压效率
– 精确的恒定电流(CC) 限制
– 高达500µF 容性负载的软启动
– 用于轻负载运行的PFM 模式
• 单个输入，支持USB 输入以及高电压适配器或无线
电源
器件信息
封装(1)
封装尺寸（标称值）
器件型号
BQ25616/616J
WQFN (24)
4.00mm × 4.00mm
– 支持4V 至13.5V 输入电压范围，绝对最大输入
额定值为22V
– 130ns 快速关断输入过压保护，可选的外部
OVPFET 可承受高达30V 的输入电压
– 通过ILIM 引脚实现可编程输入电流限制
(IINDPM)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VAC
SYS 3.5V œ 4.35V
SW
USB
VBUS
BTST
SYS
BAT
– 通过VINDPM 阈值自动跟踪电池电压，从而实
现最大功率
– 自动检测USB SDP、CDP、DCP 以及非标准适
配器
ACDRV
ILIM
ICHG
CE
ICHG
REGN
+
• 窄VDC (NVDC) 电源路径管理
– 无需电池或使用深度放电的电池即可使系统瞬时
启动
VSET
TS
• 低RDSON 19.5mΩBATFET，可更大程度地降低充
电损耗和延长电池运行时间
• 在系统待机时具有9.5µA 的低电池泄漏电流
• 高集成度包括所有MOSFET、电流感应和环路补偿
• 安全相关认证：
简化版应用
– 经IEC 62368-1 CB 认证
2 应用
• 电子销售点(EPOS)
• 无线扬声器
• 工业、医疗便携式电子产品
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDF7
BQ25616, BQ25616J
ZHCSKP6A –JANUARY 2020 –REVISED FEBRUARY 2022
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Table of Contents
9.4 Device Functional Modes..........................................28
10 Application and Implementation................................29
10.1 Application Information........................................... 29
10.2 Typical Applications................................................ 29
11 Power Supply Recommendations..............................37
12 Layout...........................................................................38
12.1 Layout Guidelines................................................... 38
12.2 Layout Example...................................................... 38
13 Device and Documentation Support..........................40
13.1 Device Support....................................................... 40
13.2 Documentation Support.......................................... 40
13.3 接收文档更新通知................................................... 40
13.4 支持资源..................................................................40
13.5 Trademarks.............................................................40
13.6 Electrostatic Discharge Caution..............................40
13.7 术语表..................................................................... 40
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................7
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................13
8.7 Typical Characteristics..............................................14
9 Detailed Description......................................................16
9.1 Overview...................................................................16
9.2 Functional Block Diagram.........................................16
9.3 Feature Description...................................................17
Information.................................................................... 41
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (January 2020) to Revision A (February 2022)
Page
• 将“特性”中的20 小时充电安全计时器更改为10 小时充电安全计时器...........................................................1
• 添加了“安全相关认证：经IEC 62368-1 CB 认证............................................................................................. 1
• Changed charge safety timer accuracy from 20 hr to 10 hr for BQ25616/J in the Device Comparison Table....4
• Deleted deglitch time and added charge voltage limit in the Device Comparison Table.................................... 4
• Changes TS and VAC pin descriptions in 表7-1 ...............................................................................................5
• Changed voltage, BAT, SYS (converter not switching) MAX value from 17 V to 7 V in 节8.1 .......................... 7
• Added CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE) in 节8.5 ........................................ 8
• Deleted VBST_BAT and added VBATLOWV_OTG in 节8.5 .......................................................................................8
• Deleted numerous test conditions in D+/D- Detection section in 节8.5 ............................................................ 8
• Deleted IBST_OCP_Q1 in 节8.5 ............................................................................................................................ 8
• Deleted accuracy from tTOP_OFF and CHG_TIMER = 20hr from tSAFETY in 节8.6 ...........................................13
• Changed tSAFETY MIN/TYP/MAX values in 节8.6 ............................................................................................13
• Deleted VBATREG = 4.4 V curve from 图8-3 .....................................................................................................14
• Changed safety timer from 20 hours to 10 hours in 表9-4 ..............................................................................23
• Changed T2 from 20 to 10 in 图9-6 ................................................................................................................ 25
• Changed 节9.3.9.5.3 .......................................................................................................................................28
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5 说明（续）
该解决方案在系统和电池之间高度集成输入反向阻断 FET（RBFET，Q1）、高侧开关 FET（HSFET，Q2）、低
侧开关 FET（LSFET，Q3）以及电池 FET（BATFET、Q4）。它还集成了自举二极管以进行高侧栅极驱动，从
而简化系统设计。硬件设置和状态报告为充电解决方案提供了简单的配置。
该器件支持多种输入源，包括标准 USB 主机端口、USB 充电端口、兼容 USB 的高电压适配器和无线电源。该器
件符合 USB 2.0 和 USB 3.0 电源规格，具有输入电流和电压调节功能。该器件根据内置 USB 检测通过 D+/D- 引
脚设置默认输入电流限值。当器件内置 USB 接口确定输入适配器未知时，器件的输入电流限值是通过 ILIM 引脚
设置电阻器值来决定的。
该器件通过单个电感器将降压充电器和升压稳压器集成在一个解决方案中。它通过提供 5V 电压和高达 1.2A 的恒
定电流限值，符合USB On-the-Go (OTG) 运行功率额定值规格。
在应用适配器时，电源路径管理将系统电压调节至稍高于电池电压的水平，但不会降至 3.5V 最小系统电压以下。
借助于这个特性，即使在电池电量完全耗尽或者电池被拆除时，系统也能保持运行。当达到输入电流限值或电压
限值时，电源路径管理会自动减小充电电流。随着系统负载持续增加，电池开始放电，直到满足系统电源需求。
该补充模式可防止输入源过载。
此器件在无需软件控制情况下启动并完成一个充电周期。它感应电池电压并通过三个阶段为电池充电：预充电、
恒定电流和恒定电压。在充电周期的末尾，当充电电流低于预设限值并且电池电压高于再充电阈值时，充电器自
动终止。如果已完全充电的电池降至再充电阈值以下，则充电器自动启动另一个充电周期。
此充电器提供针对电池充电和系统运行的多种安全特性，其中包括电池负温度系数热敏电阻监视、充电安全性计
时器和过压/过流保护。当结温超过 110°C 时，热调节会减小充电电流。STAT 输出报告充电状态和任何故障状
况。
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6 Device Comparison Table
BQ25606
BQ25616
BQ25616J
Quiescent battery current (BAT,
SYS, SW)
58 µA
9.5 µA
9.5 µA
VBUS OVP Reaction-time
Input voltage regulation accuracy
TS profile
200 ns
±3%
130 ns
±2%
130 ns
±2%
JEITA
Hot/Cold
10 hr
JEITA
10 hr
Charge safety timer accuracy
Charge voltage limit
10 hr
4.2 V/4.35 V/4.4 V
±0.5%
4.1 V/4.2 V/4.35 V
±0.4%
4.1 V/4.2 V/4.35 V
Battery voltage regulation
ACDRV
±0.4%
Yes
No
Yes
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7 Pin Configuration and Functions
VAC
ACDRV
D+
1
2
3
4
5
6
18
17
16
15
14
13
GND
GND
SYS
SYS
BAT
BAT
Thermal
Pad
Dœ
STAT
OTG
Not to scale
图7-1. RTW Package 24-Pin WQFN Top View
表7-1. Pin Functions
PIN
TYPE(1)
AO
DESCRIPTION
NAME
NO.
Charge pump output to drive external N-channel MOSFET (ACFET). It provides 6V voltage
above VBUS as gate drive to turn on ACFET when VAC voltage is below ACOV threshold (14.2-
V) and above UVLO. Leave ACDRV floating if external OVP is not being used.
ACDRV
2
13
14
Battery connection point to the positive terminal of the battery pack. The internal current sensing
resistor is connected between SYS and BAT. Connect a 10 µF(2) closely to the BAT pin.
BAT
P
PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the
BTST
CE
21
9
P
boot-strap diode. Connect the 0.047-μF bootstrap capacitor(2) from SW to BTST.
DI
Charge enable pin. When this pin is driven LOW, battery charging is enabled.
Positive line of the USB data line pair. D+/D–based USB host/charging port detection. The
detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and
nonstandard adaptors
D+
3
4
AIO
Negative line of the USB data line pair. D+/D–based USB host/charging port detection. The
detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and
nonstandard adaptors
AIO
P
D–
17
18
GND
ICHG
Power ground and signal ground
ICHG pin sets the charge current limit. A resistor is connected from ICHG pin to ground to set
charge current limit as ICHG = KICHG/RICHG. The acceptable range for charge current is 300 mA
–3000 mA.
10
8
AI
ILIM sets the input current limit when the input adapter is detected as unknown. Otherwise, the
input current limit is set by D+/D–detection outcome. A resistor is connected from ILIM pin to
ground to set the input current limit as IINDPM = KILIM/RILIM. The acceptable range for ILIM
current is 500 mA - 3200 mA.
ILIM
AI
Boost mode enable pin. When this pin is pulled HIGH, boost mode is enabled. OTG pin cannot
be floating.
OTG
PG
6
7
DI
Open drain active low power good indicator. Connect to the pull up rail through 10 kΩresistor.
LOW indicates a good input if the input voltage is between UVLO and ACOV, above SLEEP
mode threshold, and input current limit is above 30 mA.
DO
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表7-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
PMID
NO.
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Place
a 10-µF capacitor(2) on PMID to GND.
23
P
PWM low side driver positive supply output. Internally, REGN is connected to the anode of the
boot-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor(2) from REGN to analog
GND. The capacitor should be placed close to the IC.
REGN
STAT
22
5
P
Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin
indicates charger status.
Charge in progress: LOW
DO
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): Blink at 1Hz
19
20
Switching node connecting to output inductor. Internally SW is connected to the source of the n-
channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap
capacitor from SW to BTST.
SW
P
P
15
16
System output connection point. The internal current sensing resistor is connected between SYS
and BAT. Connect a 10 µF (min) capacitor(2) close to the SYS pin.
SYS
Battery temperature qualification voltage input. Connect a negative temperature coefficient
thermistor (NTC). Program temperature window with a resistor divider from REGN to TS to GND.
Charge and boost mode suspend when TS pin voltage is out of range. When TS pin is not used,
connect a 10-kΩresistor from REGN to TS and a 10-kΩresistor from TS to GND. It is
recommended to use a 103AT-2 thermistor. BQ25616 supports hot/cold profile and BQ25616J
supports JEITA profile.
TS
11
AI
Charger input voltage sensing. Optional external n-channel ACFET is placed between VAC and
VBUS. When VAC voltage is below ACOV threshold (14.2-V) and above UVLO, ACFET turns on
to connect VAC to VBUS, and power up the charger IC. Connect VAC and VBUS if ACFET is not
to be used.
VAC
1
P
P
Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected
between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor(2) from VBUS
to GND and place it as close as possible to the device.
VBUS
24
VSET pin sets default battery charge voltage . Program battery regulation voltage with a resistor
pull-down from VSET to GND.
RVSET > 50kΩ(float pin) = 4.208 V
RVSET < 500Ω(short to GND) = 4.352 V
5kΩ< RVSET < 25kΩ= 4.100 V
VSET
12
AI
P
Ground reference for the device that is also the thermal pad used to conduct heat from the
device. This connection serves two purposes. The first purpose is to provide an electrical ground
connection for the device. The second purpose is to provide a low thermal-impedance path from
the device die to the PCB. This pad should be tied externally to a ground plane.
Thermal
Pad
—
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output,
P = Power
(2) All capacitors are ceramic unless otherwise specified
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX UNIT
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Output Sink Current
TJ
VAC (converter not switching)
VBUS (converter not switching)
PMID (converter not switching)
SW
30
22
22
16
7
V
V
-2
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
BAT, SYS (converter not switching)
BTST
V
22
40
7
V
ACDRV
V
D+. D-, STAT, OTG, PG, ILIM, CE, ICHG, TS, VSET
STAT, PG
V
6
mA
°C
°C
Junction temperature
Storage temperature
150
150
–40
–55
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
±2000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
13.5
4.35
3.2
3.2
3
UNIT
VVBUS
VBAT
IVBUS
ISW
Input voltage
4
V
V
Battery voltage
Input current
A
Output current (SW)
Fast charging current
RMS discharge current
Ambient temperature
A
A
IBAT
TA
6
A
85
°C
–40
8.4 Thermal Information
BQ25616/BQ25616J
THERMAL METRIC(1)
RTW (WQFN)
UNIT
24 Pins
31.9
27
RθJA
Junction-to-ambient thermal resistance (JEDEC(1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
)
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
9.2
Junction-to-top characterization parameter
0.4
ΨJT
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8.4 Thermal Information (continued)
BQ25616/BQ25616J
THERMAL METRIC(1)
RTW (WQFN)
24 Pins
9.2
UNIT
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
ΨJB
RθJC(bot)
2.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
VBAT = 4.5V, VBUS floating or VBUS
= 0V - 5V, SCL, SDA = 0V or 1.8V, TJ
< 85 °C, BATFET on.
Quiescent battery current (BAT, SYS,
SW)
IQ_BAT
IVBUS
IBST
9.5
2.3
2.4
15
µA
mA
mA
Input current (VBUS) in buck mode
when converter is switching
VBUS=5V, charge disabled, converter
switching, ISYS = 0A
Quiescent battery current (BAT, SYS, VBAT = 4.5V, VBUS = 4.9V, boost
SW) in boost mode when converter is mode enabled, converter switching,
switching
IVBUS = 0A
VBUS / VBAT SUPPLY
VVBUS_OP
VBUS operating range
4
13.5
3.85
V
V
VAC rising for ACFET turnon, no
battery
VVAC_UVLOZ
VAC rising
VAC falling
3.55
3.25
10
VAC falling for ACFET turnoff, no
battery
VVAC_UVLO
VACDRV
3.55
V
V
External ACFET gate drive voltage
with minimum 8nF CGS
VVBUS_UVLOZ
VVBUS_UVLO
VVBUS_PRESENT
VVBUS_PRESENTZ
VBUS rising for active bias, no battery VBUS rising
VBUS falling to turnoff bias, no battery VBUS falling
3.3
3
3.7
3.3
3.9
3.4
V
V
V
V
VBUS to enable REGN
VBUS to disable REGN
VBUS rising
VBUS falling
3.65
3.15
VBUS falling, VBUS - VBAT, VBAT =
4V
VSLEEP
Enter Sleep mode threshold
Exit Sleep mode threshold
15
115
60
220
110
340
mV
mV
V
VBUS rising, VBUS - VBAT, VBAT =
4V
VSLEEPZ
VAC overvoltage rising threshold to
turnoff ACFET and switching
VAC rising
13.5
14.2
13.9
14.85
14.5
VACOV
VAC overvoltage falling threshold to
turnon ACFET and switching
VAC falling,
13
2.5
V
V
V
VBAT_UVLOZ
VBAT_DPLZ
BAT voltage for active bias, no VBUS VBAT rising
BAT depletion rising threshold to turn
VBAT rising
2.35
2.8
on BATFET
BAT depletion falling threshold to turn
VBAT falling
VBAT_DPL
2.18
3.75
2.62
4.0
V
V
off BATFET
VPOORSRC
Bad adapter detection threshold
VBUS falling
3.9
POWER PATH MANAGEMENT
Typical minimum system regulation
VBAT=3.2V < SYS_MIN = 3.5V, ISYS
= 0A
VSYS_MIN
3.5
3.65
4.7
V
V
voltage
VREG = 4.35V, Charge disabled, ISYS
= 0A
VSYS_OVP
System overvoltage threshold
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RON_RBFET
RON_HSFET
RON_LSFET
Blocking FET on-resistance
High-side switching FET on-resistance
Low-side switching FET on-resistance
45
mΩ
62
mΩ
71
mΩ
BATFET forward voltage in
supplement mode
BAT discharge current 10mA,
converter running
VBATFET
_
30
mV
FWD
BATTERY CHARGER
VREG = 4.1V, RVSET=10kΩ, TJ = 0°C
- 85°C
4.0836
4.1832
4.3326
0
4.1 4.1164
4.2 4.2168
V
V
VREG = 4.2V, RVSET>50kΩ, TJ = 0°C
- 85°C
VREG_ACC
Charge voltage accuracy
VREG = 4.35V, RVSET<500Ω, TJ =
0°C - 85°C
4.35 4.3674
3
V
Typical charge current regulation
range
ICHG_RANGE
A
ICHG=KICHG/RICHG, VBAT = 3.1V, TJ =
–40°C - 85°C
639
677
677
715
715
AxΩ
AxΩ
A
KICHG
ICHG pin setting ratio
ICHG=KICHG/RICHG, VBAT = 3.8V, TJ =
–40°C - 85°C
639
RICHG = 1100 Ω, VBAT = 3.1V or 3.8V,
TJ = –40°C - 85°C
0.516
0.615
1.205
0.715
1.28
1.89
Fast charge current regulation
accuracy
RICHG = 562 Ω, VBAT = 3.1V or 3.8V,
TJ = –40°C - 85°C
ICHG_ACC
1.14
A
RICHG = 372 Ω, VBAT = 3.1V or 3.8V,
TJ = –40°C - 85°C
1.715
1.82
5
A
%
IPRECHG_RATIO
Precharge current accuracy
Precharge current accuracy
As percentage of ICHG, VBAT = 2.6V
RICHG = 1100 Ω, VBAT = 2.6V, TJ = –
40°C - 85°C
21
48
76
30
38
67
97
mA
RICHG = 562 Ω, VBAT = 2.6V, TJ = –
40°C - 85°C
IPRECHG_ACC
60
90
mA
mA
%
RICHG = 372 Ω, VBAT = 2.6V, TJ = –
40°C - 85°C
As percentage of ICHG, VBAT =
4.35V, (char, all codes)
ITERM_RATIO
Termination current accuracy
Termination current accuracy
5
RICHG = 1100 Ω, VBAT = 4.35V, TJ =
0°C - 85°C
9
36
31
57
85
mA
mA
mA
V
RICHG = 562 Ω, VBAT = 4.35V, TJ =
0°C - 85°C
ITERM_ACC
60
RICHG = 372 Ω, VBAT = 4.35V, TJ =
0°C - 85°C
56
91
126
2.35
Battery short voltage rising threshold
to start pre-charge
VBAT_SHORTZ
VBAT rising
2.13
2.25
Battery short voltage falling threshold
to stop pre-charge
VBAT_SHORT
IBAT_SHORT
VBAT falling
1.85
70
3
2
90
2.15
110
V
mA
V
Battery short trickle charging current
VBAT < VBAT_SHORTZ
VBAT rising
Battery LOWV rising threshold to start
fast-charge
3.12
3.24
VBATLOWV
Battery LOWV falling threshold to stop
fast-charge
VBAT falling
VBAT falling
2.7
90
2.8
2.9
V
VRECHG
Battery recharge threshold
100
150
mV
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
System discharge load current during
SYSOVP
ISYS_LOAD
30
mA
TJ = -40°C - 85°C
19.5
19.5
26
30
mΩ
mΩ
RON_BATFET
Battery FET on-resistance
TJ = -40°C - 125°C
BATTERY OVERVOLTAGE PROTECTION
Battery overvoltage rising threshold
Battery overvoltage falling threshold
VBAT rising, as percentage of VREG
VBAT falling, as percentage of VREG
103
101
104
102
105
103
%
%
VBAT_OVP
INPUT VOLTAGE / CURRENT REGULATION
Typical input voltage regulation
VINDPM_ACC
accuracy
4.171
4.45
4.3
4.429
4.74
V
V
VINDPM threshold to track battery
VINDPM_TRACK
voltage
VBAT = 4.35V
4.55
IINDPM_ACC
IINDPM_ACC
IINDPM_ACC
KILIM
Input current regulation accuracy
Input current regulation accuracy
Input current regulation accuracy
ILIM pin setting ratio
IINDPM = 500mA (TJ=-40°C - 85°C)
IINDPM = 900mA (TJ=-40°C-85°C)
IINDPM = 1500mA (TJ=-40°C-85°C)
450
750
465
835
500
900
mA
mA
1300
459
1390
478
1500
500
mA
A x Ω
D+ / D- DETECTION
VDP_SRC
D+ line source voltage
500
7
600
10
700
14
mV
µA
D+ line data contact detect current
source
IDP_SRC
VD+ = 200 mV
IDP_SINK
D+ line sink current
VD+ = 500 mV
D+ pin Rising
D+ pin Rising
VD+ = 500 mV
Pull up to 1.8 V
50
100
150
400
800
24.8
1
µA
mV
mV
kΩ
µA
mV
µA
mV
kΩ
µA
VDP_DAT_REF
VDP_LGC_LOW
RDP_DWN
ID+_LKG
D+ line data detect voltage
D+ line logic low.
250
D+ line pull-down resistance
Leakage current into D+ line
D- line source voltage
14.25
–1
500
VDM_SRC
IDM_SINK
600
100
700
150
400
24.8
1
D- line sink current
VD- = 500 mV
D- pin Rising
VD- = 500 mV
Pull up to 1.8 V
50
VDM_DAT_REF
RDM_DWN
ID-_LKG
D- line data detect voltage
D- line pull-down resistance
Leakage current into D- line
250
14.25
–1
D+ High comparator threshold for 2.8V
detection
VD+ _2p8_hi
VD+ _2p8_lo
VD+ _2p8
D+ pin rising
D+ pin rising
2.85
3
3.1
2.55
2.85
3.1
V
V
V
V
V
V
V
V
D+ Low comparator threshold for 2.8V
detection
2.35
2.55
2.85
2.35
2.55
2.15
1.6
2.45
D+ comparator threshold for non-
standard adapter
D- High comparator threshold for 2.8V
detection
VD- _2p8_hi
VD- _2p8_lo
VD- _2p8
D- pin rising
D- pin rising
3
D- Low comparator threshold for 2.8V
detection
2.45
2.55
2.85
2.35
1.85
D- comparator threshold for non-
standard adapter
D+ High comparator threshold for 2.0V
detection
VD+ _2p0_hi
VD+ _2p0_lo
D+ pin rising
D+ pin rising
2.25
1.7
D+ Low comparator threshold for 2.0V
detection
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
D+ comparator threshold for non-
standard adapter
VD+ _2p0
1.85
2.15
2.35
1.85
2.15
1.6
V
V
V
V
V
V
V
V
V
V
D- High comparator threshold for 2.0V
detection
VD- _2p0_hi
VD- _2p0_lo
VD- _2p0
D- pin rising
2.15
1.6
2.25
1.7
D- Low comparator threshold for 2.0V
detection
D- pin rising
D- comparator threshold for non-
standard adapter
1.85
1.35
0.85
1.05
1.35
0.85
1.05
D+ High comparator threshold for 1.2V
detection
VD+ _1p2_hi
VD+ _1p2_lo
VD+ _1p2
D+ pin rising
D+ pin rising
1.5
D+ Low comparator threshold for 1.2V
detection
0.95
1.05
1.35
1.6
D+ comparator threshold for non-
standard adapter
D- High comparator threshold for 1.2V
detection
VD- _1p2_hi
VD- _1p2_lo
VD- _1p2
D- pin rising
D- pin rising
1.5
D- Low comparator threshold for 1.2V
detection
0.95
1.05
1.35
D- comparator threshold for non-
standard adapter
THERMAL REGULATION AND THERMAL SHUTDOWN
Junction temperature regulation
accuracy
TREG
110
°C
TSHUT
Thermal Shutdown Rising threshold
Thermal Shutdown Falling threshold
Temperature Increasing
Temperature Decreasing
150
130
°C
°C
CHARGE MODE THERMISTOR COMPARATOR (JEITA 616J or HOT/COLD 616)
TS pin voltage rising threshold,
Charge suspended above this voltage. 103AT)
As Percentage to REGN (0°C w/
VT1_RISE%
72.4
71.5
73.3
72
74.2
72.5
%
%
TS pin voltage falling threshold.
Charge re-enabled to 20% of ICHG
and VREG below this
voltage.
VT1_FALL%
As Percentage to REGN
TS pin voltage rising threshold,
Charge back to 20% of ICHG and
VREG above this voltage (616J).
As Percentage to REGN (10°C w/
103AT)
VT2_RISE %
VT2_FALL%
VT3_FALL%
67.75
66.45
44.25
68.25
66.95
44.75
68.75
67.45
45.25
%
%
%
TS pin voltage falling threshold.
Charge back to ICHG and VREG
below this voltage (616J)
As Percentage to REGN
TS pin voltage falling threshold.
Charge back to ICHG and VREG
below this voltage (616J)
As Percentage to REGN (45°C w/
103AT)
TS pin voltage rising threshold.
Charge back to ICHG and VREG
above this voltage. (616J)
VT3_RISE%
VT5_FALL%
VT5_RISE%
As Percentage to REGN
45.55
33.7
35
46.05
34.2
35.5
46.55
35.1
36
%
%
%
TS pin voltage falling threshold,
charge suspended below this voltage. 103AT)
As Percentage to REGN (60°C w/
TS pin voltage rising threshold.
Charge back to ICHG and 4.1V above As Percentage to REGN
this voltage.
TS pin voltage rising threshold.
As Percentage to REGN (0°C w/
Charge suspended above this voltage.
103AT)
VT1_RISE_HC%
72.4
73.3
74.2
%
(616)
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TS pin voltage falling threshold.
Charge back to ICHG and VREG
below this voltage. (616)
VT1_FALL_HC%
VT3_FALL_HC%
VT3_RISE _HC%
As Percentage to REGN
71
72
73
45.25
46.55
%
%
%
TS pin voltage falling threshold.
Charge suspended below this voltage.
(616)
As Percentage to REGN (45°C w/
103AT)
44.25
45.55
44.75
46.05
TS pin voltage rising threshold.
Charge back to ICHG and VREG
above this voltage. (616)
As Percentage to REGN
BOOST MODE THERMISTOR COMPARATOR (HOT/COLD)
TS pin voltage rising threshold, boost
mode is suspended above this
voltage.
As Percentage to REGN (–19.5°C w/
103AT)
VBCOLD_RISE%
79.5
30.2
80
80.5
32.2
%
As Percentage to REGN (0°C w/
103AT)
VBCOLD_FALL%
VBHOT_FALL%
VBHOT_RISE%
TS pin voltage falling threshold
72
31.2
44
%
%
%
TS pin voltage threshold. boost mode As Percentage to REGN, (64°C w/
is suspended below this voltage.
103AT)
As Percentage to REGN, (45°C w/
103AT)
TS pin voltage rising threshold
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
HSFET cycle-by-cycle overcurrent
IHSFET_OCP
threshold
5.2
8.0
A
SWITCHING CONVERTER
FSW
PWM switching frequency
Maximum PWM Duty Cycle
Oscillator frequency
1.32
1.5
97
1.68 MHz
%
DMAX
BOOST MODE CONVERTER
Battery voltage exiting boost mode
VVBAT falling
VVBAT rising
2.6
2.9
2.8
3.0
2.9
V
V
VBATLOWV_OTG
Battery voltage entering boost mode
3.15
Boost mode voltage regulation
accuracy
VBST_ACC
IBST_ACC
IVBUS = 0A, BOOST_V = 5V
4.85
1.2
9
5
1.4
10
5.15
1.6
V
A
A
Boost mode current regulation
accuracy
Boost mode battery discharge current
clamp on BATFET Q4
ISYS_OCP_Q4
REGN LDO
VVBUS = 5V, IREGN = 20mA
VVBUS = 9V, IREGN = 20mA
VVBUS = 5V, VREGN = 3.8V
4.58
5.6
50
4.7
6
4.8
6.5
V
V
VREGN
REGN LDO output voltage
REGN LDO current limit
IREGN
mA
LOGIC INPUT PIN
VIH
Input high threshold level (/CE)
Input low threshold level (/CE)
High-level leakage current (/CE)
1.3
V
V
VIL
0.4
1
IIN_BIAS
Pull up rail 1.8V
µA
LOGIC OUTPUT PIN
VOL
Output low threshold level (STAT, /PG) Sink current = 5mA
High-level leakage current (STAT, /PG) Pull up rail 1.8V
0.4
1
V
IOUT_BIAS
µA
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8.6 Timing Requirements
MIN
NOM
MAX
UNIT
VBUS / VBAT POWER UP
tPOORSRC
Bad adapter detection duration
30
2
ms
s
tPOORSRC_RETRY
BATTERY CHARGER
tTERM_DGL
Bad adapter detection retry wait time
Deglitch time for charge termination
Deglitch time for recharge threshold
Typical top-off timer
30
30
30
10
ms
ms
min
hr
tRECHG_DGL
tTOP_OFF
tSAFETY
Charge safety timer accuracy
8
12
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8.7 Typical Characteristics
100
95
90
85
80
75
70
100
95
90
85
80
75
VBUS Voltage
5 V
65
60
9 V
12 V
0
0.2
0.4
0.6
0.8
Boost Output Current (A)
1
1.2
0
0.5
1
1.5
Charge Current (A)
2
2.5
3
D002
D001
VOTG = 5.0 V
VBAT = 3.8 V
fSW = 1.5 MHz
VBAT = 3.8 V
inductor DCR = 18 mΩ
Inductor DCR = 18 mΩ
图8-2. Efficiency vs. OTG Current
图8-1. Charge Efficiency vs. Charge Current
4.5
4.4
4.3
4.2
4.1
4
2.75
2.5
2.25
2
IINDPM = 1.8 A
IINDPM = 1.28 A
IINDPM = 0.52 A
VBATREG = 4.208 V
VBATREG = 4.352 V
1.75
1.5
1.25
1
0.75
0.5
0.25
0
-40
-25
-10
5
20
35
50
Junction Temperature (°C)
65
80
95
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
D001
D001
VVBUS = 5 V
图8-3. BATREG Charge Voltage vs. Junction Temperature
图8-4. Input Current Limit vs. Junction Temperature
2.6
486
ICHG = 1.8 A
ICHG = 1.2 A
ICHG = 0.68 A
RILIM = 265 W
RILIM = 374 W
RILIM = 910 W
2.4
484
482
480
478
476
474
472
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
-25
-10
5
20
35
50
Junction Temperature (°C)
65
80
95
-40 -25 -10
5
20
35
50
65
Junction Temperature (°C)
80
95 110
D001
D001
VVBUS = 5 V
VBAT = 3.8 V
VVBUS = 5 V
VBAT = 3.8 V
图8-6. Input Current Limit Setting Ratio vs. Junction
图8-5. Charge Current vs. Junction Temperature
Temperature
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8.7 Typical Characteristics (continued)
705
700
695
690
685
680
675
670
665
RICHG = 372 W
RICHG = 562 W
RICHG = 1100 W
660
-40 -25 -10
5
20
35
50
65
Junction Temperature (°C)
80
95 110
D001
VVBUS = 5 V
VBAT = 3.8 V
图8-7. Charge Current Setting Ratio vs. Junction Temperature
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9 Detailed Description
9.1 Overview
The BQ25616/616J device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-ion and Li-
polymer battery. It includes an input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate
drive.
9.2 Functional Block Diagram
VBUS
PMID
VIN
VVVAC_PRESENT
RBFET (Q1)
+
UVLO
SLEEP
ACOV
VVAC
Q1 Gate
Control
œ
IVBUS
VBAT + VSLEEP
ACDRV
VAC
+
REGN
BTST
EN_REGN
EN_HIZ
VVAC
REGN
LDO
œ
VVAC
+
VVAC_OV
œ
FBO
VVBUS
VBUS_OVP_BOOST
+
VBST_OVP
œ
IQ2
Q2_UCP_BOOST
Q3_OCP_BOOST
+
VOTG_HSZCP
VVBUS
œ
œ
+
+
œ
+
œ
œ
+
HSFET (Q2)
LSFET (Q3)
IQ3
VINDPM
SW
+
VOTG_BAT
IVBUS
CONVERTER
Control
œ
REGN
IINDPM
VBAT
+
BATOVP
UCP
104% × VREG
ILSFET_UCP
IQ3
IC TJ
TREG
PGND
œ
IQ2
VBAT
VREG
ICHG
Q2_OCP
+
œ
+
œ
+
+
IHSFET_OCP
VSYS
œ
œ
VSYS_MIN
VBTST - VSW
EN_HIZ
EN_CHARGE
EN_BOOST
+
REFRESH
VBTST_REFRESH
ICHG_REG
œ
SYS
ICHG
VREG
ICHG_REG
BATFET
(Q4)
Q4 Gate
Control
VPOORSRC
VVBUS
BAT
POORSRC
TSHUT
+
REF
DAC
Converter
Control State
Machine
œ
ILIM
ICHG
VSET
IC TJ
+
TSHUT
œ
D+
Input Source
Detection
USB
Adapter
DÅ
VREG -VRECHG
VBAT
+
RECHRG
OTG
œ
ICHG
+
TERMINATION
BATLOWV
ITERM
œ
CHARGE
CONTROL
STATE
VBATLOWV
STAT
PG
+
VBAT
MACHINE
œ
BQ25616(J)
VSHORT
+
BATSHORT
SUSPEND
VBAT
œ
Battery
Sensing
Thermistor
TS
(BQ25616, HOT/COLD)
(BQ25616J, JEITA)
CE
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9.3 Feature Description
9.3.1 Power-On-Reset (POR)
The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VVBUS rises above
VVBUS_UVLOZ or VBAT rises above VBAT_UVLOZ, the sleep comparator, battery depletion comparator, and BATFET
driver are active.
9.3.2 Device Power Up From Battery Without Input Source
If only the battery is present and the voltage is above depletion threshold (VBAT _DPLZ), the BATFET turns on and
connects the battery to the system. The REGN stays off to minimize the quiescent current. The low RDSON of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through the BATFET. When the system is overloaded or
shorted (IBAT > ISYS_OCP_Q4), the device turns off BATFET immediately until the input source plugs in again.
9.3.3 Power Up From Input Source
When an input source is plugged in, the device checks the input source voltage to turn on the REGN LDO and
all the bias circuits. It detects and sets the input current limit before the buck converter is started. The power-up
sequence from input source is as listed:
1. Power Up ACFET, see 节9.3.3.1 (optional)
2. Power Up REGN LDO, see 节9.3.3.2
3. Poor Source Qualification, see 节9.3.3.3
4. Input Source Type Detection is based on D+/D–to set default input current limit (IINDPM threshold), see 节
9.3.3.4
5. Input Voltage Limit Threshold Setting (VINDPM threshold), see 节9.3.3.5
6. Power Up Converter, see 节9.3.3.6
9.3.3.1 Power Up ACFET
The external ACFET provides an additional layer of voltage protection for the device. During input surge up to 30
V, the charger turns off ACFET and converter with 130-ns response time to disconnect VBUS from VAC. If users
don't need ACFET, they shall connect VAC to VBUS and keep ACDRV pin floating. The ACFET is enabled when
all the below conditions are valid.
The ACFET is enabled when all the below conditions are valid.
• VVAC_PRESENT < VVAC < VACOV
.
• After tDEB (15 ms typ) delay is completed
If one of the above conditions is not valid, ACFET keeps off. The battery powers the system If it is present.
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VACOV (rising)
VAC*
VVAC_PRESENT (rising)
tON_VBUS
90%
VVAC_PRESENT (rising) < VAC < VACOV (rising)
must be valid before ACDRV goes high.
tDEB
ACDRV
10%
90%
VBUS
10%
(*) Stimulus from application
Note: beginning of blue lines indicate the trigger, and the arrow end of the blue line indicates the action
图9-1. ACFET Startup Control
9.3.3.2 Power Up REGN LDO
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. It also provides the
bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN LDO is
enabled when all the below conditions are valid:
• VVBUS > VVBUS_UVLOZ
• In buck mode, ACFET turns on, VVBUS > VBAT + VSLEEPZ
• In boost mode, VVBUS < VBAT + VSLEEPZ
• After 220-ms delay is completed
During high impedance mode , REGN LDO turns off. The battery powers up the system.
9.3.3.3 Poor Source Qualification
After the REGN LDO powers up, the device starts to check current capability of the input source. The first step is
poor source detection.
• VBUS voltage above VPOORSRC when pulling IBADSRC (typical 30 mA)
If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.
9.3.3.4 Input Source Type Detection (IINDPM Threshold)
After poor source detection, the device runs input source detection through D+/D– lines . The D+/D– detection
follows the USB Battery Charging Specification 1.2 (BC1.2) to detect standard (SDP/CDP/DCP) and non-
standard adapters through USB D+/D–lines.
9.3.3.4.1 D+/D–Detection Sets Input Current Limit
The device contains a D+/D– based input source detection to set the input current limit when a 5-V adapter is
plugged-in. The D+/D– detection includes standard USB BC1.2 and non-standard adapters. When an input
source is plugged in, the device starts standard USB BC1.2 detection. The USB BC1.2 is capable of identifying
Standard Downstream Port (SDP), Charging Downstream Port (CDP) and Dedicated Charging Port (DCP). The
non-standard detection is used to distinguish vendor specific adapters (Apple and Samsung) based on their
unique dividers on the D+/D– pins. If an adapter is detected as DCP, the input current limit is set at 2.4-A. If an
adapter is detected as unknown, the input current limit is set by ILIM pin .
The D+/D– automatically runs when adapter plugs in. The D+/D– detection contains three steps, DCD (Data
Contact Detection), primary detection, and secondary detection.
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DCD (Data Contact Detection) uses a current source to detect when the D+/D– pins have made contact during
an attach event. The protocol for data contact detect is as follows:
• Detect VBUS present and VBUS_GD (pass poor source detection)
• Turn on D+ IDP_SRC and the D–pull-down resistor RDM_DWN for 13 ms
• If the USB connector is properly attached, the D+ line goes from HIGH to LOW, wait up to 0.5 sec. When the
DCD timer of 0.5 sec is expired, the non-standard adapter detection is applied to set the input current limit.
• Turn off IDP_SRC and disconnect RDM_DWN
The primary detection is used to distinguish between USB host (Standard Down Stream Port, or SDP) and
different type of charging ports (Charging Down Stream Port, or CDP, and Dedicated Charging Port, or DCP).
The protocol for primary detection is as follows:
• Turn on VDP_SRC on D+ and IDM_Sink on D–for 40 ms
• If portable device is attached to a USB host (SDP), the D–is below VREF_DAT. Otherwise, it is attached to
either CDP or DCP.
• Turn off VDP_SRC and IDM_Sink
The secondary detection is used to distinguish two types of charging ports (CDP and DCP). The protocol for
secondary detection is as follows:
• Turn on VDM_SRC on D- and IDP_Sink on D+ for 40 ms
• If portable device is attached to a Charging Downstream Port (CDP), the D+ is below VDAT_REF. Otherwise, it
is attached to DCP.
• Turn off VDM_SRC and IDP_Sink
Most of the time, a CDP requires the portable device (such as smart phone, tablet) to send back an enumeration
within 2.5 seconds of CDP plug-in. Otherwise, the port will power cycle back to SDP even the D+/D– detection
indicates CDP.
表9-1. Non-Standard Adapter Detection
NON-STANDARD
D+ THRESHOLD
INPUT CURRENT LIMIT (A)
D–THRESHOLD
ADAPTER
Divider 1
Divider 2
Divider 3
Divider 4
VD+ within VD+/D- _2p8
VD+ within VD+/D- _1p2
VD+ within VD+/D- _2p0
VD+ within VD+/D- _2p8
VD– within VD+/D- _2p0
VD– within VD+/D- _1p2
VD– within VD+/D- _2p8
VD– within VD+/D- _2p8
2.1
2
1
2.4
表9-2. Input Current Limit Setting from D+/D–Detection
INPUT CURRENT LIMIT (IINDPM)
D+/D–DETECTION
USB CDP
1.5 A
2.4 A
USB DCP
Divider 1
2.1 A
Divider 2
2.0 A
Divider 3
1.0 A
Divider 4
2.4 A
Unknown 5-V Adapter
Set by ILIM pin
9.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device has two modes to set the VINDPM threshold.
• Fixed VINDPM threshold. VINDPM is set at 4.3 V.
• VINDPM threshold tracks the battery voltage to optimize the converter headroom between input and output.
The actual input voltage limit is the higher of the VINDPM setting (4.3-V) and VBAT + 200 mV.
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9.3.3.6 Power Up Converter in Buck Mode
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. The
system voltage is powered from the converter instead of the battery. If battery charging is disabled, the BATFET
turns off. Otherwise, the BATFET stays on to charge the battery.
The device provides soft start when the system rail is ramping up. When the system rail is below VBAT_SHORT, the
input current is limited to 200 mA . The system load should be appropriately planned not to exceed the 200-mA
IINDPM limit. After the system rises above VBAT_SHORTZ, the device input current limit is the value set the by ILIM
pin .
As a battery charger, the device deploys a highly efficient 1.5-MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current, and temperature simplifying output filter design.
The converter supports PFM operation by default for fast transient response during system voltage regulation
and better light load efficiency.
9.3.4 Boost Mode Operation From Battery
The device supports boost converter operation to deliver power from the battery to other portable devices
through a USB port. The output voltage is regulated at 5 V and output current is up to 1.2 A with constant current
regulation.
Boost operation is enabled if the conditions below are valid:
1. OTG pin HIGH
2. VBUS less than VBAT + VSLEEP (in sleep mode) before converter starts.
3. Voltage at TS (thermistor) pin, as a percentage of VREGN, is within acceptable range (VBHOT_RISE% < VTS%
VBCOLD_FALL%
<
)
4. After 30-ms delay from boost mode enable .
5. Not in any fault such as ISYS_OCP_Q4, TSHUT, ACOV or VBUS OV.
The converter supports PFM operation at light load in Boost mode.
9.3.5 Standalone Charger
The BQ25616/616J is a standalone device without host control. Any change on CE, ICHG and ILIM pins will
cause a real time internal reference change. Charging is enabled or disabled via the CE pin. D+/D– and ILIM
pins control the input current limit settings. D+/D– detection and VSET pin setting only takes effect upon
adapter plug-in.
Charge current must be programmed to a value within a range of 300 mA to 3000 mA with a pull-down resistor
on the ICHG pin. The charge current is set as:
IICHG = KICHG/RICHG
(1)
Input current limit must be programmed to a value within a range of 500 mA to 3200 mA with a pull-down resistor
on the ILIM pin. The input current limit is set as:
IIINDPM = KILIM/RILIM
(2)
The battery regulation voltage is programmed with a pull-down resistor on the VSET pin as follows:
• RVSET > 50 kΩ(float pin): VREG = 4.20 V
• RVSET < 500 Ω(short pin): VREG = 4.35 V
• 5kΩ< RVSET < 25 kΩ: VREG = 4.10 V
表9-3. Standalone Device Configuration
BQ25616/616J
USB OTG
5 V/1.2 A
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表9-3. Standalone Device Configuration (continued)
BQ25616/616J
USB Detection
VINDPM
D+/D–
4.3 V and VBAT + 200 mV
4 V - 13.5 V
VBUS Operating Range
VREG
VSET pin (4.20 V, 4.35 V, or 4.10 V)
10 hr fast charge
2 hr
Safety Timer
Pre-charge Timer
IPRECHG
5% of ICHG
ITERM
5% of ICHG
JEITA 0-60°C (BQ25616J), Hot/Cold
0-45°C (BQ25616)
Charging Temperature Profile
OTG Temperature Profile
–20°C to +60°C
If a fault is detected, the STAT pin will blink at 1 Hz. STAT pin will stop blinking when the fault goes away. All
faults will be reset upon adapter re-connection. A boost mode fault will be cleared either by adapter re-
connection or toggling of the OTG pin.
9.3.6 Power Path Management
The device accommodates a wide range of input sources such as USB, wall adapter, or car charger. The device
provides automatic power path selection to supply the system (SYS) from the input source (VBUS), battery
(BAT), or both.
9.3.6.1 Narrow VDC Architecture
When the battery is below the minimum system voltage setting, the BATFET operates in linear mode (LDO
mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage
rises above the minimum system voltage, the BATFET is fully on and the voltage difference between the system
and battery is the VDS of the BATFET.
When battery charging is disabled and above the minimum system voltage setting or charging is terminated, the
system is always regulated at typically 50 mV above the battery voltage.
4.5
Minimum System Voltage
Charge Disabled
Charge Enabled
4.1
4.3
3.9
3.7
3.5
3.3
3.1
2.7
2.9
3.1
3.3
3.5
BAT (V)
3.7
3.9
4.1
4.3
D002
图9-2. System Voltage vs Battery Voltage
9.3.6.2 Dynamic Power Management
To meet the maximum current limit in the USB specification and avoid overloading the adapter, the device
features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage.
When input source is overloaded, either the current exceeds the input current limit (IINDPM) or the voltage falls
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below the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls
below the input current limit or the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement
mode where the BATFET turns on and the battery starts discharging so that the system is supported from both
the input source and battery.
图 9-3 shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.5-V minimum
system voltage setting.
Voltage
VBUS
9V
SYS
BAT
3.6V
3.4V
3.2V
3.18V
Current
4A
ICHG
3.2A
2.8A
ISYS
1.2A
1.0A
IIN
0.5A
-0.6A
DPM
DPM
Supplement
图9-3. DPM Response
9.3.6.3 Supplement Mode
When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation
from entering and exiting the supplement mode.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until
the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge
current. 图 9-4 shows the V-I curve of the BATFET gate regulation operation. The BATFET turns off to exit
supplement mode when the battery is below battery depletion threshold.
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4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55
V(BAT-SYS) (mV)
D001
Plot1
图9-4. BAFET V-I Curve
9.3.7 Battery Charging Management
The device charges a 1-cell Li-ion battery with up to 3.0-A charge current for a high capacity tablet battery. The
19.5-mΩBATFET improves charging efficiency and minimizes the voltage drop during discharging.
9.3.7.1 Autonomous Charging Cycle
When battery charging is enabled (CE pin is LOW), the device autonomously completes a charging cycle. The
device default charging parameters are listed in 表9-4.
表9-4. Charging Parameter Default Settings
DEFAULT MODE
Charging voltage
Charging current
Pre-charge current
Termination current
BQ25616/616J
VSET pin, 4.10 V/4.20 V/4.35 V
ICHG pin
5% of ICHG
5% of ICHG
JEITA (BQ25616J), Hot/Cold
(BQ25616)
Temperature profile
Safety timer
10 hours
A new charge cycle starts when the following conditions are valid:
• Converter starts
• Battery charging is enabled (CE is low)
• No thermistor fault on TS.
• No safety timer fault
The device automatically terminates the charging cycle when the charging current is below the termination
threshold, the battery voltage is above the recharge threshold, and the device is not in DPM mode or thermal
regulation. When a fully charged battery is discharged below recharge threshold, the device automatically starts
a new charging cycle. After the charge is done, a toggle of the CE pin initiates a new charging cycle. Adapter
removal and replug will also restart a charging cycle.
The STAT output indicates charging status: charging (LOW), charging complete or charge disable (HIGH), or
charging fault (blinking).
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9.3.7.2 Battery Charging Profile
The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage,
and top-off trickle charging. At the beginning of a charging cycle, the device checks the battery voltage and
regulates current and voltage accordingly.
表9-5. Charging Current Setting
VBAT
< 2.2 V
CHARGING CURRENT
DEFAULT SETTING
100 mA
IBAT_SHORT
2.2 V to 3 V
> 3 V
IPRECHG
5% of ICHG pin setting
ICHG pin setting
ICHG
Regulation Voltage
Charge Current
Battery Voltage
Charge Current
VBATLOWV (3 V)
VSHORTZ (2.2 V)
IPRECHG
ITERM
ISHORT
Fast Charge and Voltage Regulation
Trickle Charge
Pre-charge
Safety Timer
Expiration
Top-off Timer
图9-5. Battery Charging Profile
9.3.7.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above the recharge threshold, and the current
is below termination current. After the charging cycle has completed, the BATFET turns off. STAT is asserted
HIGH to indicate charging is done. The converter keeps running to power the system, and BATFET can turn on
again to engage 节9.3.6.3.
If the device is in IINDPM/VINDPM regulation, or thermal regulation, the actual charging current will be less than
the termination value. In this case, termination is temporarily disabled.
When termination occurs, the STAT pin goes HIGH.
The top-off timer is reset at one of the following conditions:
1. Charge disable to enable
2. Charger enters termination
9.3.7.4 Thermistor Qualification
The device provides a single thermistor input for battery temperature monitoring.
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9.3.7.4.1 JEITA Guideline Compliance During Charging Mode (BQ25616J)
To improve the safety of charging Li-ion batteries, the JEITA guideline was released on April 20, 2007. The
guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low
and high temperature ranges.
To initiate a charge cycle, the voltage on TS pin, as a percentage of VREGN, must be within the VT1_FALL% to
VT5_RISE% thresholds. If the TS voltage percentage exceeds the T1-T5 range, the controller suspends charging,
a TS fault is reported and waits until the battery temperature is within the T1-T5 range.
At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to 20% of ICHG. At warm
temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V.
JEITA_WARM_ISET
100% of ICHG
JEITA_COOL_VSET
VREG
JEITA_WARM_VSET
4.1V
JEITA_COOL_ISET
20% of ICHG
T1
0
T2
T3
T5
60
5
10 15 20
25
30 35
40
45 50
Battery Thermistor Temperature (°C)
图9-6. JEITA Profile (BQ25616J)
方程式3 through 方程式4 describe how to calculate resistor divider values on the TS pin.
REGN
RT1
TS
NTC
103AT
RT2
图9-7. TS Pin Resistor Network
%
(3)
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%
%
%
%
(4)
In the equations above, RNTC, T1 is the NTC thermistor resistance value at temperature T1 and RNTC, T5 is the
NTC thermistor resistance value at temperature T5. Selecting a 0°C to 60°C range for a Li-ion or Li-polymer
battery then:
• RNTC,T1 = 27.28 kΩ(0°C)
• RNTC,T5 = 3.02 kΩ(60°C)
• RT1 = 5.3 kΩ
• RT2 = 31.14 kΩ
9.3.7.4.2 Hot/Cold Temperature Window During Charging Mode (BQ25616)
The BQ25616 provides simple Hot/Cold window T1-T3 with VREG and ICHG set on the pins. When RT1 is 5.3 KΩ
and RT2 is 31.14 KΩ, T1 is 0°C and T3 is 45°C.
ICHG
VREG
T2
15 20 25 30 35 40 45 50
T3
T5
60
T1
0
5 10
Battery Thermistor Temperature (°C)
图9-8. Hot/Cold Profile (BQ25616)
9.3.7.4.3 Boost Mode Thermistor Monitor During Battery Discharge Mode
For battery protection during Boost mode, the device monitors battery temperature to be within the VBCOLD and
VBHOT thresholds. When RT1 is 5.3 kΩ and RT2 is 31.14 kΩ, TBCOLD default is -19.5°C and TBHOT default is
64°C. When the temperature is outside of the temperature thresholds, Boost mode is suspended.
9.3.7.5 Charging Safety Timer
The device has a built-in safety timer to prevent an extended charging cycle due to abnormal battery conditions.
The safety timer is 2 hours when the battery is below the VBATLOWV threshold and 10 hours when the battery is
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higher than the VBATLOWV threshold. When the safety timer expires, the STAT pin is blinking at 1 Hz to report a
safety timer expiration fault.
During IINDPM/VINDPM regulation, or thermal regulation, the safety timer counts at a half clock rate, because
the actual charge current is likely below the setting. For example, if the charger is in input current regulation
throughout the whole charging cycle, and the safety time is set to 10 hours, the safety timer will expire in 20
hours.
During faults of BAT_FAULT, NTC_FAULT that lead to charging suspend, the safety timer is suspended as well.
Once the fault goes away, the timer resumes. If the user stops the current charging cycle, and starts it again, the
timer gets reset (toggle of CE pin).
9.3.8 Status Outputs (PG, STAT)
9.3.8.1 Power Good Indicator (PG Pin)
The PG pin goes LOW to indicate a good input source when:
• VVBUS above VVBUS_UVLO
• VVBUS above battery (not in sleep)
• VVBUS below VACOV threshold
• VVBUS above VPOORSRC (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
• Completed 节9.3.3.4
9.3.8.2 Charging Status Indicator (STAT)
The device indicates the charging state on the open drain STAT pin. The STAT pin can drive an LED.
表9-6. STAT Pin State
CHARGING STATE
STAT INDICATOR
LOW
Charging in progress (including recharge)
Charging termination (top off timer may be running)
HIGH
Sleep mode, charge disable, Boost mode
HIGH
Charge suspend (input overvoltage, TS fault, safety timer fault, or system overvoltage)
Blinking at 1 Hz
9.3.9 Protections
9.3.9.1 Input Current Limit
The device's ILIM pin is to program maximum input current when D+/D– detection identifies an unknown
adaptor plugged in. The maximum input current is set by a resistor from ILIM pin to ground as:
KILIM
IINDPM
=
RILIM
(5)
9.3.9.2 Voltage and Current Monitoring in Buck Mode
9.3.9.2.1 Input Overvoltage Protection (ACOV)
This device integrates the functionality of an overvoltage protector. The device can be paired with an external N-
channel FET to block input voltages in excess of the VBUS rating. For correct operation, connect the cathode of
the body diode to the VAC node. Back-to-back body diodes between VAC and VBUS are not recommended and
will prevent correct operation. The input voltage is sensed via the VAC pin and the ACDRV pin is used to control
the external FET gate for protection. The default OVP threshold is 14.2 V. The ACOV circuit has a reaction time
of 130 ns (typical) to turn off the external ACFET. Note that turning off the external ACFET takes longer and
depends on its gate capacitance. In addition to turning off the external ACFET, an ACOV event immediately
stops converter switching whether in buck or Boost mode. The device automatically resumes normal operation
once the input voltage drops back below the OVP threshold. During ACOV, REGN LDO is on, and the device
does not enter HIZ mode.
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9.3.9.2.2 System Overvoltage Protection (SYSOVP)
The charger device clamps the system voltage during a load transient so that the components connected to the
system are not damaged due to high voltage. The VSYS_OVP threshold is about 300 mV above battery regulation
voltage when battery charging is terminated. Upon SYSOVP, the converter stops switching immediately to clamp
the overshoot. The charger pulls 30-mA ISYS_LOAD discharge current to bring down the system voltage.
9.3.9.3 Voltage and Current Monitoring in Boost Mode
9.3.9.3.1 Boost Mode Overvoltage Protection
When PMID voltage rises above the regulation target and exceeds VBST_OVP, the device stops switching
immediately and the device exits Boost mode after the Boost mode OVP lasts for 12 ms. Meanwhile, if VAC (and
VBUS when shorted to VAC) voltage exceeds VACOV, the device exits Boost mode as well.
9.3.9.4 Thermal Regulation and Thermal Shutdown
9.3.9.4.1 Thermal Protection in Buck Mode
Besides the battery temperature monitor on the TS pin, the device monitors the internal junction temperature TJ
to avoid overheating the chip and limits the IC junction temperature in buck mode. When the internal junction
temperature exceeds the thermal regulation limit (110°C), the device lowers down the charge current. During
thermal regulation, the actual charging current is usually below the programmed battery charging current.
Therefore, termination is disabled, the safety timer runs at half the clock rate.
Additionally, the device has thermal shutdown to turn off the converter and the BATFET when the IC surface
temperature exceeds TSHUT 150°C. The BATFET and converter are enabled to recover when IC temperature is
130°C.
9.3.9.4.2 Thermal Protection in Boost Mode
Besides the battery temperature monitor on the TS pin, the device monitors the internal junction temperature to
provide thermal shutdown during Boost mode. When the IC junction temperature exceeds TSHUT 150°C, Boost
mode is disabled . When the IC junction temperature is below 145°C, the host can re-enable Boost mode.
9.3.9.5 Battery Protection
9.3.9.5.1 Battery Overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above battery regulation voltage. When battery overvoltage
occurs, the charger device immediately stops switching.
9.3.9.5.2 Battery Overdischarge Protection
When the battery is discharged below VBAT_DPL_FALL, the BATFET latches off to protect the battery from
overdischarge. To recover from overdischarge latch-off, an input source plug-in is required at VAC/VBUS.
9.3.9.5.3 System Overcurrent Protection
When the system is shorted or significantly overloaded (IBAT > IBATOP) and the current exceeds BATFET
overcurrent limit, the BATFET latched off. The BATFET latch can be reset with VBUS plug-in.
9.4 Device Functional Modes
The BQ25616/616J is a standalone device and therefore does not have I2C functions.
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
A typical application consists of the device configured as a stand-alone power path management device and a
single cell battery charger for Li-ion and Li-polymer batteries used in a wide range of smart phones and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The
device also integrates a bootstrap diode for the high-side gate drive.
External ACFET is optional. When external OVP is not used, short the VBUS and VAC pins and allow the
ACDRV pin to float.
10.2 Typical Applications
10.2.1 BQ25616/616J Application without External OVP
VAC
INPUT
3.9 Vœ 14V
SYSTEM
3.5V-4.35V
1µH
SW
VBUS
ACDRV
PMID
Q1
1µF
Q2
10µF
BTST
47nF
Q3
REGN
4. 7µF
10µF
PGND
SYS
SYS
SYS
Q4
STAT
PG
BAT
10µF
D+
D-
REGN
USB
Host
TS
OTG
CE
+
ILIM
BQ25616: HOT/COLD
BQ25616J: JEITA
ICHG
Float: 4.2V
Short: 4.35V
10kꢀ: 4.1V
VSET
BQ25616(J)
图10-1. BQ25616/616J Application Diagram without External OVP
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10.2.1.1 Design Requirements
For this design example, use the parameters shown in the table below.
表10-1. Design Parameters
PARAMETER
VALUE
4-V to 13.5-V
2.4-A
VVBUS voltage range
Input current limit ( D+/D–Detection)
Fast charge current limit ( ICHG pin)
Minimum system voltage
ICHG pin
3.5-V
Battery regulation voltage ( VSET pin )
4.2-V
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Inductor Selection
The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor
saturation current higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
I
SAT ≥ICHG + (1/2) IRIPPLE
(6)
The inductor ripple current depends on the input voltage (VVBUS), the duty cycle (D = VBAT/VVBUS), the switching
frequency (fS) and the inductance (L).
VIN ´D ´ (1- D)
=
IRIPPLE
fs ´ L
(7)
The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually
inductor ripple is designed in the range between 20% and 40% maximum charging current as a trade-off
between inductor size and efficiency for a practical design.
10.2.1.2.2 Input Capacitor and Resistor
Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The
worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest
to 50% and can be estimated using 方程式8.
ICIN = ICHG ´ D ´ (1- D)
(8)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher capacitor is
preferred for 12-V input voltage. Capacitance of minimum 10 μF is suggested for typical of 3-A charging current.
During high current output over 700 mA in boost mode, a 10 kΩpull-down resistor on VBUS is recommended to
keep VBUS low in case Q1 RBFET leakage gets high.
10.2.1.2.3 Output Capacitor
Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.
方程式9 shows the output capacitor RMS current ICOUT calculation.
IRIPPLE
ICOUT
=
» 0.29 ´ IRIPPLE
2 ´
3
(9)
The output capacitor voltage ripple can be calculated as follows:
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æ
ç
è
ö
VOUT
8LCfs2
VOUT
V
DVO =
1-
÷
IN ø
(10)
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensation optimized for >10-μF ceramic output capacitance. The
preferred ceramic capacitor is 10-V rating, X7R or X5R.
10.2.1.3 Application Curves
VVBUS = 5 V
VVBAT = 3.2 V
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
图10-2. Power-Up with Charge Disabled
图10-3. Power-Up with Charge Enabled
VVBUS = 5 V
VVBAT = 3.2 V
VVBUS = 5 V to 17V
VVBAT = 3.2 V
图10-4. OVPFET Turn-on during Power-Up
图10-5. OVPFET Turn-off during Input OVP
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VVBUS = 5 V
VVBUS = 9 V
ISYS = 50 mA
ISYS = 50 mA
Charge Disabled
Charge Disabled
图10-6. PFM Switching in Buck Mode
图10-7. PFM Switching in Buck Mode
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.8 V
VVBUS = 12 V
ISYS = 50 mA
Charge Disabled
图10-9. PWM Switching in Buck Mode
图10-8. PFM Switching in Buck Mode
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VVBUS = 12 V
ICHG = 2 A
VVBAT = 3.8 V
VVBUS = 5 V
VVBAT = 3.2 V
ICHG = 2 A
图10-10. PWM Switching in Buck mode
图10-11. Charge Enable
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
VVBAT = 4 V
ILOAD= 50 mA
PFM Enabled
图10-12. Charge Disable
图10-13. OTG Switching
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VVBUS = 5 V
IINDPM = 1 A
ICHG = 1 A
VVBAT = 4 V
ISYS from 0 A to 2 A
VBAT = 3.7 V
ILOAD= 1 A
PFM Enabled
图10-14. OTG Switching
图10-15. System Load Transient
VVBUS = 5 V
IINDPM = 2 A
VVBUS = 5 V
IINDPM = 1 A
ICHG = 2 A
ISYS from 0 A to 4 A
VBAT = 3.7 V
ICHG = 1 A
ISYS from 0 A to 2 A
VBAT = 3.7 V
图10-16. System Load Transient
图10-17. System Load Transient
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VVBUS = 5 V
IINDPM = 1 A
ICHG = 2 A
VVBUS = 5 V
IINDPM = 2 A
ICHG = 2 A
ISYS from 0 A to 4 A
VBAT = 3.7 V
ISYS from 0 A to 2 A
VBAT = 3.7 V
图10-18. System Load Transient
图10-19. System Load Transient
VVBUS = 5 V
IINDPM = 2 A
ICHG = 2 A
VBAT = 3.8 V
CLOAD = 470 µF
ISYS from 0 A to 4 A
VBAT = 3.7 V
图10-21. OTG Start-Up
图10-20. System Load Transient
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10.2.2 BQ25616/616J Application with External OVP
VAC
INPUT
3.9 Vœ 14V
SYSTEM
3.5V-4.35V
1µH
SW
VBUS
Q1
1µF
ACFET
Q2
10µF
BTST
47nF
ACDRV
PMID
Q3
REGN
4. 7µF
10µF
PGND
SYS
SYS
SYS
Q4
STAT
PG
BAT
10µF
D+
D-
REGN
USB
Host
TS
OTG
CE
+
ILIM
BQ25616: HOT/COLD
BQ25616J: JEITA
ICHG
Float: 4.2V
Short: 4.35V
10kꢀ: 4.1V
VSET
BQ25616(J)
图10-22. BQ25616/616J Application Diagram with External OVP
10.2.2.1 Design Requirements
Refer to 节10.2.1.1 for design requirements.
10.2.2.2 Detailed Design Procedure
Refer to 节10.2.1.2 for detailed design procedure.
10.2.2.3 Application Curves
Refer to 节10.2.1.3 for application curves.
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11 Power Supply Recommendations
In order to provide an output voltage on SYS, the battery charger requires a power supply between 4 V and 13.5
V input with at least a 100-mA current rating connected to VBUS and a single-cell Li-ion battery with battery
voltage greater than VBAT_UVLOZ connected to BAT. The source current rating needs to be at least 3 A in order for
the buck converter of the charger to provide maximum output power to SYS.
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12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high frequency current path loop (see 图 12-1) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the
proper layout.
1. Place an input capacitor as close as possible to the PMID pin and GND pin connections and use the shortest
copper trace connection or GND plane. Add a 1-nF small size (such as 0402 or 0201) decoupling cap for the
high frequency noise filter and EMI improvement.
2. Place the inductor input pin as close as possible to SW pin. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put the output capacitor near to the inductor and the device. Ground connections need to be tied to the IC
ground with a short copper trace connection or GND plane.
4. Route the analog ground separately from power ground. Connect the analog ground and connect power
ground separately. Connect the analog ground and power ground together using the thermal pad as the
single ground connection point. Or use a 0-Ωresistor to tie the analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just beneath
the device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Place the decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
8. Ensure that the number and sizes of vias allow enough copper for a given current path.
See the BQ25618 BMS024 Evaluation Module User's Guide and BQ25619 BMS025 Evaluation Module EVM
User's Guide for the recommended component placement with trace and via locations. For the VQFN
information, refer to Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB
Attachment Application Report.
12.2 Layout Example
+
+
œ
图12-1. High Frequency Current Path
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图12-2. Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• BQ25619 BMS025 Evaluation Module User's Guide
• BQ25618 BMS024 Evaluation Module User's Guide
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25616JRTWR
BQ25616JRTWT
ACTIVE
WQFN
WQFN
RTW
24
24
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ
25616J
Samples
Samples
ACTIVE
RTW
NIPDAU
BQ
25616J
BQ25616RTWR
BQ25616RTWT
ACTIVE
ACTIVE
WQFN
WQFN
RTW
RTW
24
24
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ25616
Samples
Samples
BQ25616
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25616JRTWR
BQ25616JRTWT
BQ25616RTWR
BQ25616RTWT
WQFN
WQFN
WQFN
WQFN
RTW
RTW
RTW
RTW
24
24
24
24
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25616JRTWR
BQ25616JRTWT
BQ25616RTWR
BQ25616RTWT
WQFN
WQFN
WQFN
WQFN
RTW
RTW
RTW
RTW
24
24
24
24
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTW 24
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224801/A
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