BQ25720RSNR [TI]
具有电源路径和 USB-C® PD OTG 的 SMBus 1-4 节电池 NVDC 降压/升压电池充电控制器 | RSN | 32 | -40 to 125;型号: | BQ25720RSNR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有电源路径和 USB-C® PD OTG 的 SMBus 1-4 节电池 NVDC 降压/升压电池充电控制器 | RSN | 32 | -40 to 125 电池 控制器 光电二极管 |
文件: | 总106页 (文件大小:3100K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BQ25720
ZHCSO21 –MAY 2021
BQ25720 具有系统功率监测器和处理器热量监测器的SMBus 1 至4 节电池窄
VDC 降压/升压电池充电控制器
– ±2.5% 输入电流调节
– ±2% 输入/充电电流监测
1 特性
• 与BQ25710 引脚对引脚兼容
• 适用于USB-C 电力输送(PD) 接口平台的降压/升压
窄电压直流(NVDC) 充电器
• 安全
– 热关断
– 输入、系统和电池过压保护
– 输入、MOSFET 和电感器过流保护
• 封装:32 引脚,4.0mm × 4.0mm WQFN
– 输入范围为3.5V 至26V,可为1 至4 节电池充
电
– 充电电流高达16.2A/8.1A,分辨率为128mA/
64mA,基于5mΩ/10mΩ检测电阻
– 输入电流限制高达10A/6.35A,分辨率为
100mA/50mA,基于5mΩ/10mΩ检测电阻
– 支持USB 2.0、USB 3.0、USB 3.1 和USB 电
力传输(PD)
– 输入电流优化器(ICO),无需过载适配器即可获
取最大输入功率
– 符合USB-PD 规范的集成型快速角色交换
(FRS) 功能
– 可在降压、降压/升压和升压操作之间进无缝转
换
– 提供输入电流和电压调节(IINDPM 和
VINDPM)以防电源过载
2 应用
• 标准笔记本电脑、Chromebook
• 平板电脑(多媒体)、无线扬声器
• 超声波扫描仪、呼吸机
3 说明
BQ25720 是一款同步 NVDC 降压/升压电池充电控制
器,可通过 USB 适配器、高电压 USB-C 电力输送
(PD) 源和传统适配器等各种输入源为 1 至 4 节电池充
电。
器件信息
封装(1)
封装尺寸(标称值)
器件型号
BQ25720
WQFN (32) 4.00mm × 4.00mm
• TI 获得专利的开关频率抖动模式,可降低EMI 噪声
• TI 获得专利的直通模式(PTM),可提高系统功效并
实现99% 的电池快速充电。
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
VSYS
• 适用于Intel 平台且符合IMVP8/IMVP9 标准的系统
功能
Adapter
3.5V œ 24V
BATT
(1S-4S)
Q2
Q3
– 增强型Vmin 主动保护(VAP) 模式可在系统峰值
功率尖峰期间根据最新的Intel 规范通过输入电
容器为电池补电
Q1
Q4
HIDRV1
SW1BTST1BTST2SW2
LODRV1
HIDRV2
LODRV2
SYS
VBUS
ACN
ACP
BATDRV
SRP
– 综合PROCHOT 曲线
BQ25720
SRN
– 两级放电电流限制PROCHOT 曲线,可避免电
池电量耗尽
– 系统功率监测器
• 通过专用引脚监测输入和电池电流
• 集成型8 位ADC,可监控电压、电流和功率
• 在补充模式下实现电池MOSFET 理想二极管运
行,可在适配器满载时支持系统
• 通过电池给USB 端口加电(USB OTG)
Host
应用示意图
– 具有8mV 分辨率的3V 至24V OTG
– 输出电流限制高达12.7A/6.35A,分辨率为
100mA/50mA,基于5mΩ/10mΩ检测电阻
• 800kHz/1.2MHz 可编程开关频率,具有2.2µH/
1.0µH 电感器
• 可通过SMBus 主机控制接口实现灵活系统配置
• 高精度调节和监控
– ±0.5% 充电电压调节
– ±3% 充电电流调节
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
Table of Contents
9.5 Programming............................................................ 38
9.6 Register Map.............................................................41
10 Application and Implementation................................85
10.1 Application Information........................................... 85
10.2 Typical Application.................................................. 85
11 Power Supply Recommendations..............................95
12 Layout...........................................................................96
12.1 Layout Guidelines................................................... 96
12.2 Layout Example...................................................... 97
13 Device and Documentation Support..........................99
13.1 Device Support....................................................... 99
13.2 Documentation Support.......................................... 99
13.3 接收文档更新通知................................................... 99
13.4 支持资源..................................................................99
13.5 Trademarks.............................................................99
13.6 静电放电警告.......................................................... 99
13.7 术语表..................................................................... 99
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 8
8.1 Absolute Maximum Ratings........................................ 8
8.2 ESD Ratings............................................................... 8
8.3 Recommended Operating Conditions.........................8
8.4 Thermal Information....................................................9
8.5 Electrical Characteristics.............................................9
8.6 Timing Requirements................................................20
8.7 Typical Characteristics..............................................21
9 Detailed Description......................................................24
9.1 Overview...................................................................24
9.2 Functional Block Diagram.........................................25
9.3 Feature Description...................................................26
9.4 Device Functional Modes..........................................37
Information.................................................................. 100
4 Revision History
DATE
REVISION
NOTES
May 2021
*
Initial release.
Copyright © 2023 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
5 Description (continued)
The NVDC configuration allows the system to be regulated based on battery voltage, but not drop below system
minimum voltage. The system keeps operating even when the battery is completely discharged or removed.
When load power exceeds input source rating, the battery goes into supplement mode and prevents the system
from crashing.
During power up, the charger sets the converter to a buck, boost, or buck-boost configuration based on the input
source and battery conditions. The charger seamlessly transitions between the buck, boost, and buck-boost
operation modes without host control.
In the absence of an input source, the BQ25720 supports the USB On-the-Go (OTG) function from a 1- to 4-cell
battery to generate an adjustable 3-V to 24-V output on VBUS with 8-mV resolution. The OTG output voltage
transition slew rate can be configured to comply with the USB-PD 3.0 PPS specification.
When only a battery powers the system and no external load is connected to the USB OTG port, the BQ25720
implements the latest Intel Vmin Active Protection (VAP) feature, in which the device charges up the VBUS
voltage from the battery to store some energy in the input decoupling capacitors. During a system peak power
spike, the energy stored in the input capacitors supplements the system, to prevent the system voltage from
dropping below the minimum system voltage and causing a system crash.
The BQ25720 monitors adapter current, battery current, and system power. The flexibly programmed PROCHOT
output goes directly to the CPU for throttle back when needed.
The latest version of the USB-C PD specification includes Fast Role Swap (FRS) to ensure power role swapping
occurs in a timely fashion so that the device(s) connected to the dock can avoid experiencing momentary power
loss or glitching. This device integrates FRS in compliance with the PD specification.
TI patented switching frequency dithering pattern can significantly reduce EMI noise over the whole conductive
EMI frequency range (150 kHz to 30 MHz). Multiple dithering scale options are available to provide flexibility for
different applications to simplify EMI noise filter design.
The charger can be operated in the TI patented Pass Through Mode (PTM) to improve efficiency over the full
load range. In PTM, input power is directly passed through the charger to the system. Switching losses of the
MOSFETs and inductor core loss can be saved for high efficiency operation.
The BQ25720 is available in a 32-pin 4 mm × 4 mm WQFN package.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
6 Device Comparison Table
BQ25710
BQ25713
I2C
BQ25720
SMBus
BQ25723
I2C
BQ25730
I2C
BQ25731
I2C
Interface
SMBus
09h
Device Address
6Bh
09h
6Bh
6Bh
6Bh
Maximum Charge Current
Switching Frequency (Hz)
Cell Count
8.128 A
800 k/1.2 M
1s to 4s
8.128 A
800 k/1.2 M
1s to 4s
16.256 A
800 k/1.2 M
1s to 4s
16.256 A
800 k/1.2 M
1s to 4s
16.256 A
400 k/800 k
1s to 5s
16.256 A
400 k/800 k
1s to 5s
Input Current Sense Resistor
10 mΩ/20 mΩ 10 mΩ/20 mΩ 5 mΩ/10 mΩ
5 mΩ/10 mΩ
5 mΩ/10 mΩ
5 mΩ/10 mΩ
Latch/Non latch Latch/Non latch Latch/Non latch Latch/Non latch
Independent Comparator Latch
Non Latch
Non Latch
(default)
(default)
(default)
(default)
2.4 V ~ 8.0 V
(0.8-V step
size) Default:
2.4 V
2.4 V ~ 8.0 V
(0.8-V step
size) Default:
2.4 V
2.4 V ~ 8.0 V
(0.8-V step
size) Default:
2.4 V
1.6 V
VSYS_UVP
2.4 V
2.4 V
OTG Voltage Range
Frequency Dithering
BATFET Power Path
Pre-charge LDO Mode
3.0 V to 20.8 V 3.0 V to 20.8 V
3.0 V to 24 V
3.0 V to 24 V
3.0 V to 24 V
3.0 V to 24 V
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
4
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
7 Pin Configuration and Functions
VBUS
ACN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
HIDRV2
SW2
ACP
VSYS
CHRG_OK
OTG/VAP/FRS
ILIM_HIZ
VDDA
BATDRV
SRP
Thermal
Pad
SRN
CELL_BATPRESZ
COMP2
IADPT
图7-1. RSN Package 32-Pin WQFN Top View
表7-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NUMBER
Input current sense amplifier negative input. The leakage on ACP and ACN are matched. A
RC low-pass filter is required to be placed between the sense resistor and the ACN pin to
suppress the high frequency noise in the input current signal. Refer to 节10.2.2.1 for
ACP/ACN filter design.
ACN
ACP
2
PWR
PWR
O
Input current sense amplifier positive input. The leakage on ACP and ACN are matched. A
RC low-pass filter is required to be placed between the sense resistor and the ACP pin to
suppress the high frequency noise in the input current signal. Refer to 节10.2.2.1 for
ACP/ACN filter design.
3
P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the
BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to
regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on
during fast charge and works as an ideal-diode in supplement mode.
BATDRV
21
Buck mode high-side power MOSFET driver power supply. Connect a 0.047-µF capacitor
between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated.
BTST1
BTST2
30
25
PWR
PWR
Boost mode high-side power MOSFET driver power supply. Connect a 0.047-μF capacitor
between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated.
Battery cell selection pin for 1- to 4- cell battery setting. CELL_BATPRESZ pin is biased from
VDDA through a resistor divider. CELL_BATPRESZ pin also sets SYSOVP thresholds to 5 V
for 1-cell, 12 V for 2-cell and 19.5 V for 3-cell/4-cell. CELL_BATPRESZ pin is pulled below
VCELL_BATPRESZ_FALL to indicate battery removal. After battery is removed the charge voltage
register REG0x15h() goes back to default. No external cap is allowed at CELL_BATPRESZ
pin. The device exits LEARN mode and disables charge when CELL_BATPRESZ pin is
pulled low (upon battery removal).
CELL_BATPRESZ
18
I
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表7-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NUMBER
Open drain active high indicator to inform the system good power source is connected to the
charger input. Connect to the pullup rail via 10-kΩresistor. When VBUS rises above 3.5 V
and falls below 25.8 V, CHRG_OK is HIGH after 50-ms deglitch time. When VBUS falls
below 3.2 V or rises above 26.8 V, CHRG_OK is LOW. When one of SYSOVP, SYSUVP,
ACOC, TSHUT, BATOVP, BATOC or force converter off faults occurs, CHRG_OK is asserted
LOW.
CHRG_OK
4
O
Input of independent comparator. The independent comparator compares the voltage
sensed on CMPIN pin with internal reference, and its output is on CMPOUT pin. Internal
reference, output polarity and deglitch time is selectable by the SMBus host. With polarity
HIGH (CMP_POL = 1b), place a resistor between CMPIN and CMPOUT to program
hysteresis. With polarity LOW (CMP_POL = 0b), the internal hysteresis is 100 mV. If the
independent comparator is not in use, tie CMPIN to ground.
CMPIN
14
15
I
Open-drain output of independent comparator. Place a pullup resistor from CMPOUT to
pullup supply rail. Internal reference, output polarity and deglitch time are selectable by the
SMBus host. If the independent comparator is not in use, float CMPOUT pin.
CMPOUT
O
COMP2
COMP1
17
16
I
I
Buck boost converter compensation pin 2. Refer to 节9.3.13 for COMP2 pin RC network.
Buck boost converter compensation pin 1. Refer to 节9.3.13 for COMP1 pin RC network.
Active HIGH to enable OTG, VAP or FRS modes. 1) When OTG_VAP_MODE=1b and
EN_OTG=1b, pulling high this pin can enable OTG mode. 2) When OTG_VAP_MODE=1b
and EN_FRS=1b, pulling high this pin can enable FRS mode in forward operation. 3) When
OTG_VAP_MODE=0b, pulling high OTG/VAP/FRS pin is to enable VAP mode.
OTG/VAP/FRS
5
I
Buck mode high-side power MOSFET (Q1) driver. Connect to high-side n-channel MOSFET
gate.
HIDRV1
HIDRV2
31
24
O
O
Boost mode high-side power MOSFET(Q4) driver. Connect to high-side n-channel MOSFET
gate.
The adapter current monitoring output pin. VIADPT = 20 or 40 × (VACP –VACN) with ratio
selectable through IADPT_GAIN bit. This pin is also used to program the inductance used in
the application. Refer to 节9.3.12 for selecting resistor from the IADPT pin to ground . For a
2.2-µH inductance, the resistor is 137 kΩ. Place a 100-pF or less ceramic decoupling
capacitor from IADPT pin to ground. IADPT output voltage is clamped below 3.3 V.
IADPT
IBAT
8
9
O
O
The battery current monitoring output pin. VIBAT = 8 or 16 × (VSRP –VSRN) for charge
current, or VIBAT = 8 or 16 × (VSRN –VSRP) for discharge current, with ratio selectable
through IBAT_GAIN bit. Place a 100-pF or less ceramic decoupling capacitor from IBAT pin
to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.
Input current limit setting pin. Program ILIM_HIZ voltage by connecting a resistor divider
from VDDA rail to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40 × IDPM ×
Rac, in which IDPM is the target input current limit.
When EN_EXTILIM = 1b the input current limit used by the charger is the lower setting of
ILIM_HIZ pin and IIN_HOST register. When EN_EXTILIM = 0b input current limit is only
determined by IIN_HOST register.
When the pin voltage is below 0.4 V, the device enters high impedance (HIZ) mode with low
quiescent current. When the pin voltage is above 0.8 V, the device is out of HIZ mode. The
ILIM_HIZ pin voltage is continuous read and used for updating current limit setting (If
EN_EXTILIM=1b ), this allows dynamic change input current limit setting by adjusting this
pin voltage.
ILIM_HIZ
LODRV1
6
I
Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET
gate.
29
O
Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET
gate.
LODRV2
PGND
26
27
O
GND
Device power ground.
Active low open drain output indicator. It monitors adapter input current, battery discharge
current, and system voltage. After any event in the PROCHOT profile is triggered, a pulse is
asserted. The minimum pulse width is adjustable through PROCHOT_WIDTH bits.
PROCHOT
11
O
Copyright © 2023 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表7-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NUMBER
Current mode system power monitor. The output current is proportional to the total power
from the adapter and the battery. The gain is selectable through SMBus. Place a resistor
from PSYS to ground to generate output voltage. This pin can be floating if not in use. Its
output voltage is clamped at 3.3 V. Place a capacitor in parallel with the resistor for filtering.
PSYS
10
O
6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS
above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power
ground. REGN pin output is for power stage gate drive.
REGN
28
PWR
SMBus clock input. Connect to clock line from the host controller or smart battery. Connect a
10-kΩpullup resistor according to specifications.
SCL
SDA
13
12
I
SMBus open-drain data I/O. Connect to data line from the host controller or smart battery.
Connect a 10-kΩpullup resistor according to SMBus specifications.
I/O
Charge current sense amplifier negative input. SRN pin is for battery voltage sensing as
well. Connect a 0.1-μF filter cap cross battery charging sensing resistor and use 10-Ω
contact resistor between SRN pin and battery charging sensing resistor. The leakage current
on SRP and SRN are matched.
SRN
SRP
19
20
PWR
PWR
Charge current sense amplifier positive input. Connect a 0.1-μF filter cap cross battery
charging sensing resistor and use 10-Ωcontact resistor between SRP pin and battery
charging sensing resistor. The leakage current on SRP and SRN are matched.
Buck mode switching node. Connect to the source of the buck half bridge high side n-
channel MOSFET.
SW1
32
23
1
PWR
PWR
PWR
PWR
Boost mode switching node. Connect to the source of the boost half bridge high side n-
channel MOSFET.
SW2
Charger input voltage. An input low pass filter of 1 Ωand 0.47 µF (minimum) is
recommended.
VBUS
VDDA
Internal reference bias pin. Connect a 10-Ωresistor from REGN to VDDA and a 1-μF
ceramic capacitor from VDDA to power ground.
7
Charger system voltage sensing. The system voltage regulation maximum limit is
programmed in ChargeVoltage register plus 150 mV and regulation minimum limit is
programmed in VSYS_MIN register.
VSYS
22
PWR
Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on the
thermal pad plane connecting to power ground planes. It serves as a thermal pad to
dissipate the heat.
Thermal pad
–
–
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–2
MAX
32
32
38
7
UNIT
SRN, SRP, ACN, ACP, VBUS, VSYS
SW1, SW2
BTST1, BTST2, HIDRV1, HIDRV2, BATDRV
LODRV1, LODRV2 (25nS)
HIDRV1, HIDRV2 (25nS)
–0.3
–4
38
32
–4
Voltage
V
SW1, SW2 (25nS)
–4
SDA, SCL, REGN, PSYS, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ,
LODRV1, LODRV2, VDDA, COMP2, CMPIN, CMPOUT,OTG/VAP/
FRS,
7
–0.3
PROCHOT
5.5
3.6
7
–0.3
–0.3
–0.3
–0.5
–40
–55
IADPT, IBAT, COMP1
BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2
Differential
V
Voltage
SRP-SRN, ACP-ACN
0.5
150
150
Temperature
Temperature
Junction temperature range, TJ
Storage temperature, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
26
UNIT
ACN, ACP, VBUS
SRN, SRP, VSYS
0
19.2
26
SW1, SW2
–2
0
BTST1, BTST2, HIDRV1, HIDRV2, BATDRV
32
Voltage
V
SDA, SCL, REGN, PSYS, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ,
LODRV1, LODRV2, VDDA, COMP2, CMPIN, CMPOUT,OTG/VAP/FRS
0
6.5
PROCHOT
0
5.3
3.3
IADPT, IBAT, COMP1
0
0
BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2
SRP-SRN, ACP-ACN
6.5
Differential
Voltage
0.5
V
–0.5
0
BATDRV-VSYS
10.8
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
8
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
–20
–20
NOM
MAX
125
85
UNIT
Junction temperature range, TJ
Temperature
°C
Storage temperature, Tstg
8.4 Thermal Information
BQ25720
THERMAL METRIC(1)
RSN (WQFN)
UNIT
32 PINS
37.2
26.1
7.8
RθJA
Junction-to-ambient thermal resistance (JEDEC(1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
7.8
ΨJB
RθJC(bot)
2.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
Input voltage
operating range
TEST CONDITIONS
MIN
TYP
MAX UNIT
VINPUT_OP
3.5
26
V
MAX SYSTEM VOLTAGE REGULATION
System Voltage
Regulation, measured
on VSYS (charge
disabled)
VSYSMAX_RNG
1.024
19.2
V
V
VSRN
150 mV
+
REG0x15() = 0x41A0H (16.800 V)
REG0x15() = 0x3138H (12.600 V)
REG0x15() = 0x20D0H (8.400 V)
REG0x15() = 0x1068H (4.200 V)
2%
2%
–2%
–2%
–3%
–3%
1.00
VSRN
150 mV
+
V
V
V
System voltage
regulation accuracy
(charge disabled and
EN_OOA=0b)
VSYSMAX_ACC
VSRN
150 mV
+
3%
VSRN
150 mV
+
3%
MINIMUM SYSTEM VOLTAGE REGULATION
System Voltage
Regulation, measured
on VSYS
VSYS_MIN_RNG
19.2
V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
–2%
–2%
–3%
–3%
TYP
MAX UNIT
12.30
V
–2%
V
REG0x3E() = 0x7B00H
9.20
6.60
3.60
Minimum System
REG0x3E() = 0x5C00H
REG0x3E() = 0x4200H
REG0x3E() = 0x2400H
Voltage Regulation
Accuracy (VBAT
–2%
V
VSYS_MIN_REG_ACC
below REG0x3E()
setting, EN_OOA=0b)
–3%
V
–3%
CHARGE VOLTAGE REGULATION
Battery voltage
VBAT_RNG
regulation
1.024
19.2
V
V
16.8
12.6
8.4
REG0x15() = 0x41A0H
REG0x15() = 0x3138H
REG0x15() = 0x20D0H
REG0x15() = 0x1068H
0.5%
0.5%
0.6%
1.2%
–0.5%
–0.5%
–0.6%
–1.1%
V
V
V
Battery voltage
regulation accuracy
(charge enable) (0°C
to 85°C)
VBAT_REG_ACC
4.2
CHARGE CURRENT REGULATION IN FAST CHARGE
Charge current
VIREG_CHG_RNG
regulation differential
voltage range
0
81.28 mV
VIREG_CHG = VSRP –VSRN
4096
2048
1024
512
mA
2.0%
mA
REG0x14() = 0x1000H
REG0x14() = 0x0800H
REG0x14() = 0x0400H
REG0x14() = 0x0200H
–3.0%
–4.0%
–5.0%
–12.0%
Charge current
regulation accuracy
10-mΩsensing
resistor, VBAT above
0x3E() setting (0°C to
85°C)
3.0%
mA
ICHRG_REG_ACC
6.0%
mA
12.0%
CHARGE CURRENT REGULATION IN LDO MODE
CELL(≥2 S) VSRN < VSYS_MIN
384
384
2
mA
mA
A
Pre-charge current
clamp
ICLAMP
CELL 1 S, VSRN < 3 V
CELL 1 S, 3 V < VSRN < VSYS_MIN
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
10
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
REG0x14() = 0x0180H
384
mA
15.0%
25.0%
mA
≥2S
–15.0%
–25.0%
1S
Pre-charge current
regulation accuracy
with 10-mΩ
SRP/SRN series
resistor, VBAT below
VSYS_MIN(REG0x3
E()) setting (0°C to
85°C)
REG0x14() = 0x0100H
256
192
128
20.0%
35.0%
mA
≥2S
–20.0%
–35.0%
IPRECHRG_REG_ACC
1S
REG0x14() = 0x00C0H
25.0%
50.0%
mA
≥2S
–25.0%
–50.0%
1S
REG0x14() = 0x0080H
30.0%
≥2S
–30.0%
–13.5
SRP, SRN leakage
current mismatch
(0°C to 85°C)
ILEAK_SRP_SRN
10.0 µA
INPUT CURRENT REGULATION
Input current
regulation differential
voltage range with
10-mΩACP/ACN
series resistor
VIREG_DPM_RNG
0.5
64 mV
VIREG_DPM = VACP –VACN
REG0x3F() = 0x4E00H
REG0x3F() = 0x3A00H
REG0x3F() = 0x1C00H
REG0x3F() = 0x0800H
3800
2800
1300
300
3900
2900
1400
400
4000 mA
3000 mA
1500 mA
500 mA
Input current
regulation accuracy
(-40°C to 105°C) with
10-mΩACP/ACN
series resistor
IIIN_DPM_REG_ACC
ACP, ACN leakage
current mismatch
ILEAK_ACP_ACN
10 µA
–21
Voltage range for
input current
regulation (ILIM_HIZ
Pin)
VIREG_DPM_RNG_ILIM
1.15
4
V
Input Current
VILIM_HIZ = 2.6 V
VILIM_HIZ = 2.2 V
VILIM_HIZ = 1.6 V
3800
2800
1300
4000
3000
1500
4200 mA
3200 mA
1700 mA
Regulation Accuracy
on ILIM_HIZ pin
VILIM_HIZ = 1 V + 40 ×
IDPM × RAC, with 10-
mΩACP/ACN series
resistor
IIIN_DPM_REG_ACC_ILIM
VILIM_HIZ = 1.2 V
300
500
700 mA
ILIM_HIZ pin leakage
current
ILEAK_ILIM
1
µA
–1
INPUT VOLTAGE REGULATION
Input voltage
VDPM_RNG
Voltage on VBUS
3.2
19.52
V
regulation range
REG0x3D()=0x3C80H
18688
10880
4480
mV
2%
2.5%
5.0%
–3%
–4%
REG0x3D()=0x1E00H
REG0x3D()=0x0500H
mV
mV
Input voltage
VDPM_REG_ACC
regulation accuracy
–5.2%
OTG CURRENT REGULATION
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIOTG_REG = VACP –VACN
MIN
TYP
MAX UNIT
OTG output current
regulation differential
voltage range
VIOTG_REG_RNG
0
81.28 mV
OTG output current
regulation accuracy
with 50-mA LSB and
10-mΩACP/ACN
series resistor
REG0x3C() = 0x3C00H
REG0x3C() = 0x1E00H
2800
1300
3000
1500
3200 mA
1700 mA
IOTG_ACC
REG0x3C() = 0x0A00H
300
500
700 mA
OTG VOLTAGE REGULATION
OTG voltage
regulation range(OOA Voltage on VBUS
VOTG_REG_RNG
3
24.00
V
V
disabled)
REG0x3B()=0x2CEC
REG0x3B()=0x1770H
REG0x3B()=0x09C4H
23.00
12.00
5.00
2%
2%
3%
–2%
–2%
–3%
OTG voltage
regulation
accuracy(OOA
disabled)
V
V
VOTG_REG_ACC
REGN REGULATOR
REGN regulator
voltage (0 mA –60
mA)
VREGN_REG
VVBUS = 10 V
5.7
3.8
50
6
4.3
65
6.3
4.6
V
V
REGN voltage in drop
out mode
VDROPOUT
VVBUS = 5 V, ILOAD = 20 mA
VVBUS = 10 V, force VREGN =4 V
REGN current limit
when converter is
enabled
IREGN_LIM_Charging
mA
QUIESCENT CURRENT
VBAT = 18 V, REG0x12[15] = 1,REG0x30[14] = 0b,
in low-power mode, Disable PSYS
22
35
45 µA
60 µA
VBAT = 18 V, REG0x12[15] = 1, REG0x30[14] = 1b,
REG0x30[13:12] = 11b,REGN off, Disable PSYS,
Enable low power PROCHOT
System powered by
battery. BATFET on.
ISRN + ISRP + ISW2
IBTST2 + ISW1 + IBTST1
+ IACP + IACN + IVBUS
+ IVSYS
+
IBAT_BATFET_ON
VBAT = 18 V, REG0x12[15]= 0,REG0x30[13:12]=
11b, REGN on, Disable PSYS, In performance
mode
880
980
1170 µA
1270 µA
VBAT = 18 V, REG0x12[15] = 0, REG0x30[13:12] =
00b, REGN on, Enable PSYS, In performance
mode
Input current during
PFM in buck mode,
no load, IVBUS + IACP VIN = 20 V, VBAT = 12.6 V, 3s, REG0x12[10] = 0;
+ IACN + IVSYS + ISRP MOSFET Qg = 4 nC
+ ISRN + ISW1 + IBTST
IAC_SW_LIGHT_buck
2.2
2.7
mA
mA
+ ISW2 + IBTST2
Input current during
PFM in boost mode,
no load, IVBUS + IACP VIN = 5 V, VBAT = 8.4 V, 2s, REG0x12[10] = 0;
+ IACN + IVSYS + ISRP MOSFET Qg = 4 nC
+ ISRN + ISW1 + IBTST2
IAC_SW_LIGHT_boost
+ ISW2 + IBTST2
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
12
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
Input current during
PFM in buck boost
TEST CONDITIONS
MIN
TYP
MAX UNIT
mode, no load, IVBUS VIN = 12 V, VBAT = 12 V, REG0x12[10] = 0;
+ IACP + IACN + IVSYS MOSFET Qg = 4 nC
IAC_SW_LIGHT_buckboost
2.4
mA
+ ISRP + ISRN + ISW1
+
IBTST1 + ISW2 + IBTST2
VBAT = 8.4 V, VBUS = 5 V, 800 kHz switching
frequency, MOSFET Qg = 4nC
Quiescent current
during PFM in OTG
3
4.2
6.2
mA
mA
mA
mode IVBUS + IACP
IACN + IVSYS + ISRP
+
+
VBAT = 8.4 V, VBUS = 12 V, 800 kHz switching
frequency, MOSFET Qg = 4nC
IOTG_STANDBY
ISRN + ISW1 + IBTST2
ISW2 + IBTST2
+
VBAT = 8.4 V, VBUS = 20 V, 800 kHz switching
frequency, MOSFET Qg = 4nC
CURRENT SENSE AMPLIFIER
Input common mode
range
VACP_ACN_OP
Voltage on ACP/ACN
3.8
3.1
26
V
V
IADPT output clamp
voltage
VIADPT_CLAMP
IIADPT
3.2
3.3
1
IADPT output current
mA
V/V
V/V
V(IADPT) / V(ACP-ACN), REG0x12[4] = 0
V(IADPT) / V(ACP-ACN), REG0x12[4] = 1
V(ACP-ACN) = 40.96 mV
20
40
Input current sensing
gain
AIADPT
2%
3%
–2%
–3%
V(ACP-ACN) = 20.48 mV
Input current monitor
accuracy
VIADPT_ACC
V(ACP-ACN) =10.24 mV
6%
–6%
V(ACP-ACN) = 5.12 mV
10%
–10%
Maximum
CIADPT_MAX
capacitance at IADPT
Pin
100 pF
Battery common
mode range
VSRP_SRN_OP
Voltage on SRP/SRN
2.5
19.2
V
V
IBAT output clamp
voltage
VIBAT_CLAMP
IIBAT
3.05
3.2
3.3
1
IBAT output current
mA
V/V
Charge and
V(IBAT) / V(SRN-SRP), REG0x12[3] = 0,
V(IBAT) / V(SRN-SRP), REG0x12[3] = 1,
8
discharge current
sensing gain on IBAT
pin
AIBAT
16
V/V
V(SRN-SRP) = 40.96 mV
V(SRN-SRP) = 20.48 mV
V(SRN-SRP) =10.24 mV
V(SRN-SRP) = 5.12 mV
2%
4%
–2%
–4%
Charge and
discharge current
monitor accuracy on
IBAT pin
IIBAT_CHG_ACC
7%
–7%
15%
–15%
Maximum
CIBAT_MAX
capacitance at IBAT
Pin
100 pF
SYSTEM POWER SENSE AMPLIFIER
PSYS output voltage
range
VPSYS
0
0
3.3
V
IPSYS
PSYS output current
PSYS system gain
160 µA
µA/W
I(PSYS) / (P(IN) +P(BAT)), REG0x30[13:12] =
00b;REG0x30[9] = 1b
APSYS
1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I(PSYS) / P(IN), REG0x30[13:12]= 01b;REG0x30[9] =
1b
APSYS
PSYS system gain
1
µA/W
Adapter only with system power = 19.5 V / 45 W, TA
= 0 to 85°C
4%
3%
–4%
–3%
PSYS gain accuracy
(REG0x30[13:12] =
00b)
Battery only with system power = 11 V / 44 W, TA =
0 to 85°C
VPSYS_ACC
PSYS gain accuracy
(REG0x30[13:12] =
01b)
Adapter only with system power = 19.5 V / 45 W, TA
= 0 to 85°C
4%
–4%
VPSYS_CLAMP
PSYS clamp voltage
3
3.3
V
VMIN ACTIVE PROTECTION(VAP) PROCHOT COMPARATOR
VAP VSYS rising
threshold 1
VSYS_TH1Z
VSYS_TH1 rising
6.4
6.3
6.6
6.5
6.75
6.65
V
V
VAP VSYS falling
threshold 1
VSYS_TH1
VSYS_TH1 falling REG33<7:2>=100010b
VAP VSYS threshold
1 hysteresis
VSYS_TH1_HYST
100
mV
VSYS threshold 1
falling deglitch for
VAP shooting
tSYS_TH1_falling_DEG
4
us
VAP VSYS rising
threshold 2
VSYS_TH2Z
VSYS_TH2 rising
6.1
6.0
6.3
6.2
6.45
6.35
V
V
VAP VSYS falling
threshold 2
VSYS_TH2
VSYS_TH2 falling REG37<7:2>=011111b
VAP VSYS threshold
2 hysteresis
VSYS_TH2_HYST
100
mV
VSYS threshold 2
falling deglitch for
throttling
tSYS_TH2_falling_DEG
4
us
VAP mode VBUS
rising threshold
VBUS_VAP_THZ
VBUS_VAP_TH rising
3.15
3.0
3.35
3.2
150
4
3.50
3.35
V
V
VAP mode VBUS
falling threshold
VBUS_VAP_TH
VBUS_VAP_TH falling REG37<15:9>=0000000b
VAP mode VBUS
threshold hysteresis
VBUS_VAP_TH_HYST
tBUS_VAP_TH_falling_DEG
mV
us
VBUS falling deglitch
for throttling
VSYS UNDER VOLTAGE LOCKOUT COMPARATOR
VSYS undervoltage
rising threshold(≥1S)
VSYS_UVLOZ
VSYS rising
2.3
2.2
2.5
2.4
2.65
2.55
V
V
VSYS undervoltage
falling
VSYS_UVLO
VSYS falling REG36<15:13>=000b
threshold(≥1S)
VSYS undervoltage
hysteresis(≥1S)
VSYS_UVLO_HYST
100
mV
VBUS UNDER VOLTAGE LOCKOUT COMPARATOR
VBUS undervoltage
rising threshold
VVBUS_UVLOZ
VVBUS_UVLO
VBUS rising
VBUS falling
2.35
2.2
2.55
2.4
2.80
2.6
V
V
VBUS undervoltage
falling threshold
VBUS undervoltage
hysteresis
VVBUS_UVLO_HYST
150
mV
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
14
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBUS converter
VVBUS_CONVEN
enable rising
threshold
VBUS rising
VBUS falling
3.2
3.5
3.9
3.5
V
VBUS converter
enable falling
threshold
VVBUS_CONVENZ
2.9
3.2
V
VBUS converter
enable hysteresis
VVBUS_CONVEN_HYST
300
mV
BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR
VBAT undervoltage
rising threshold
VVBAT_UVLOZ
VSRN rising
VSRN falling
2.35
2.2
2.55
2.4
2.80
2.6
V
V
VBAT undervoltage
falling threshold
VVBAT_UVLO
VBAT undervoltage
hysteresis
VVBAT_UVLO_HYST
VVBAT_OTGEN
VVBAT_OTGENZ
VVBAT_OTGEN_HYST
150
3.55
2.4
mV
V
VBAT OTG enable
rising threshold
VSRN rising
VSRN falling
3.25
2.15
3.85
2.65
VBAT OTG enable
falling threshold
V
VBAT OTG enable
hysteresis
1150
mV
VBUS UNDER VOLTAGE COMPARATOR (OTG MODE)
VBUS undervoltage
falling threshold
VVBUS_OTG_UV
tVBUS_OTG_UV
As percentage of REG0x3B()
85%
7
VBUS time
undervoltage deglitch
ms
ms
VBUS OVER VOLTAGE COMPARATOR (OTG MODE)
VBUS overvoltage
VVBUS_OTG_OV
tVBUS_OTG_OV
As percentage of REG0x3B()
110%
10
rising threshold
VBUS Time
Overvoltage Deglitch
PRE-CHARGE to FAST CHARGE TRANSITION(For ≥2S)
LDO mode to fast
charge mode
threshold, VSRN
rising
VBAT_VSYS_MIN_RISE
as percentage of 0x3E()
98%
100%
102%
LDO mode to fast
charge mode
threshold, VSRN
falling
VBAT_VSYS_MIN_FALL
as percentage of 0x3E()
97.5%
2.5%
Fast charge mode to
LDO mode threshold as percentage of 0x3E()
hysteresis
VBAT_VSYS_MIN_HYST
BATTERY LOWV COMPARATOR (Pre-charge to Fast Charge Threshold for 1S)
BATLOWV falling
VBATLV_FALL
threshold
2.8
V
BATLOWV rising
VBATLV_RISE
threshold
3
V
VBATLV_RHYST
BATLOWV hysteresis
200
mV
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VBUS overvoltage
rising threshold
VACOV_RISE
VBUS rising
26.0
26.8
27.7
V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBUS overvoltage
falling threshold
VACOV_FALL
VBUS falling
25.0
25.8
26.7
V
V
VBUS overvoltage
hysteresis
VACOV_HYST
1.0
100
1
VBUS deglitch
overvoltage rising
tACOV_RISE_DEG
tACOV_FALL_DEG
VBUS converter rising to stop converter
VBUS converter falling to start converter
us
ms
VBUS deglitch
overvoltage falling
INPUT OVER CURRENT COMPARATOR (ACOC)
ACP to ACN rising
threshold, w.r.t. ILIM2
in REG0x33[15:11]
Voltage across input sense resistor rising,
Reg0x31[2]= 1
VACOC
180%
200%
220%
Measure between
ACP and ACN
VACOC_FLOOR
VACOC_CEILING
Set IIN_DPM to minimum
Set IIN_DPM to maximum
44
50
56 mV
Measure between
ACP and ACN
172
180
188 mV
tACOC_DEG_RISE
tACOC_RELAX
Rising deglitch time
Relax time
Deglitch time to trigger ACOC
250
250
us
Relax time before converter starts again
ms
SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)
1 s
5.8
11.7
19
6
12
6.1
12.2
20
V
V
V
V
System overvoltage
rising threshold to
turnoff converter
2 s
3 s
4 s
VSYSOVP_RISE
19.5
19.5
19
20
1 s
2 s
3 s
4 s
5.5
11.7
19.3
19.3
V
V
V
V
System overvoltage
falling threshold
VSYSOVP_FALL
Discharge current
when SYSOVP stop
switching was
triggered
ISYSOVP
on VSYS pin
20
mA
BAT OVER-VOLTAGE COMPARATOR (BATOVP)
Overvoltage rising
threshold as
percentage of
VBAT_REG in
REG0x15()
1 s, 4.2 V
102.5%
102.5%
100%
104%
104%
102%
102%
2%
106%
105%
104%
103%
VBATOVP_RISE
≥2 s
1 s
Overvoltage falling
threshold as
percentage of
VBAT_REG in
REG0x15()
VBATOVP_FALL
100%
≥2 s
1 s
Overvoltage
hysteresis as
percentage of
VBAT_REG in
REG0x15()
VBATOVP_HYST
2%
≥2 s
Discharge current
during BATOVP
IBATOVP
Discharge current through VSYS pin
40
mA
CONVERTER OVER-CURRENT COMPARATOR (Q2)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
16
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Converter Over-
Reg0x31[5]=1
Reg0x31[5]=0
150
mV
Current Limit across
Q2 MOSFET drain to
source voltage
VOCP_limit_Q2
210
mV
Reg0x31[5]=1
Reg0x31[5]=0
45
60
mV
mV
VOCP_limit_SYSSHORT_Q System Short or SRN
< 2.4 V
2
CONVERTER OVER-CURRENT COMPARATOR (ACX)
Converter Over-
Current Limit across
ACP-ACN input
current sensing
resistor
Reg0x31[4]=1; RSNS_RAC=0b
150
280
mV
mV
VOCP_limit_ACX
Reg0x31[4]=0;RSNS_RAC=0b
Reg0x31[4]=1
Reg0x31[4]=0
90
mV
mV
VOCP_limit_SYSSHORT_A System Short or SRN
< 2.4 V
CX
150
THERMAL SHUTDOWN COMPARATOR
Thermal shutdown
TSHUT_RISE
Temperature increasing
Temperature reducing
155
135
20
°C
°C
°C
us
rising temperature
Thermal shutdown
TSHUTF_FALL
falling temperature
Thermal shutdown
TSHUT_HYS
hysteresis
Thermal deglitch
tSHUT_RDEG
100
12
shutdown rising
Thermal deglitch
tSHUT_FHYS
ms
shutdown falling
ICRIT PROCHOT COMPARATOR
Input current rising
threshold for throttling
as 10% above ILIM2
(REG0x33[15:11])
INOM PROCHOT COMPARATOR
INOM rising threshold
IICRIT_PRO
Only when ILIM2 setting is higher than 2A
105%
105%
110%
117%
116%
as 10% above
IIN_DPM
(REG0x22[15:8])
IINOM_PRO
110%
8192
BATTERY DISCHARGE CURRENT LIMIT PROCHOT COMPARATOR(IDCHG)
mA
IDCHG threshold1 for
throttling CPU
Reg0x34h<15:10>=010000b, with 10mΩSRP/SRN
current sensing resistor
IDCHG_TH1
IDCHG_DEG1
IDCHG_TH2
tDCHG_DEG2
96%
96%
103%
IDCHG threshold1
deglitch time
Reg0x34h<9:8>=01b
1.25
sec
12288
mA
Reg0x34h<15:10>=010000b 36h<5:3>=001b,with
10mΩSRP/SRN current sensing resistor
IDCHG threshold2 for
throttling CPU
103%
IDCHG threshold2
deglitch time
Reg0x36h<7:6>=01b
1.6
ms
INDEPENDENT COMPARATOR
Reg0x30h<7>= 1, CMPIN falling
Reg0x30h<7>= 0, CMPIN falling
1.17
2.27
1.2
2.3
1.23
2.33
V
V
Independent
VINDEP_CMP
comparator threshold
Independent
comparator
hysteresis
VINDEP_CMP_HYS
CMPIN falling
100
mV
POWER MOSFET DRIVER
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PWM OSCILLATOR AND RAMP
PWM switching
frequency
FSW
FSW
Reg0x12[9] = 0
Reg0x12[9] = 1
1020
680
1200
800
1380 kHz
920 kHz
PWM switching
frequency
BATFET GATE DRIVER (BATDRV)
Gate drive voltage on
BATFET
VBATDRV_ON
8.5
10
30
11.5
V
Drain-source voltage
on BATFET during
ideal diode operation
VBATDRV_DIODE
mV
Measured by
RBATDRV_ON
sourcing 10 µA
current to BATDRV
3
4
6
kΩ
kΩ
Measured by sinking
10 µA current from
BATDRV
RBATDRV_OFF
1.2
2.1
PWM HIGH SIDE DRIVER (HIDRV Q1)
High-side driver
RDS_HI_ON_Q1
RDS_HI_OFF_Q1
VBTST1_REFRESH
(HSD) turnon
resistance
VBTST1 - VSW1 = 5 V
6
1.3
3.7
Ω
Ω
V
High-side driver
turnoff resistance
VBTST1 - VSW1 = 5 V
2.2
4.6
Bootstrap refresh
comparator falling
threshold voltage
VBTST1 - VSW1 when low-side refresh pulse is
requested
3.2
PWM HIGH SIDE DRIVER (HIDRV Q4)
High-side driver
RDS_HI_ON_Q4
RDS_HI_OFF_Q4
VBTST2_REFRESH
(HSD) turnon
resistance
VBTST2 - VSW2 = 5 V
6
1.5
3.7
Ω
Ω
V
High-side driver
turnoff resistance
VBTST2 - VSW2 = 5 V
2.4
4.6
Bootstrap refresh
comparator falling
threshold voltage
VBTST2 - VSW2 when low-side refresh pulse is
requested
3.3
PWM LOW SIDE DRIVER (LODRV Q2)
Low-side driver (LSD)
RDS_LO_ON_Q2
VBTST1 - VSW1 = 5.5 V
VBTST1 - VSW1 = 5.5 V
6
Ω
Ω
turnon resistance
Low-side driver
RDS_LO_OFF_Q2
1.7
2.6
4.6
turnoff resistance
PWM LOW SIDE DRIVER (LODRV Q3)
Low-side driver (LSD)
RDS_LO_ON_Q3
VBTST2 - VSW2 = 5.5 V
VBTST2 - VSW2 = 5.5 V
7.6
2.9
Ω
Ω
turnon resistance
Low-side driver
RDS_LO_OFF_Q3
turnoff resistance
INTERNAL SOFT START During Charge Enable
Charge current soft-
SSSTEP_SIZE
64
8
mA
us
start step size
Charge current soft-
SSSTEP_TIME
start duration time for
each step
INTEGRATED BTST DIODE (D1)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
18
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VF_D1
VR_D1
Forward bias voltage IF = 20 mA at 25°C
0.8
V
Reverse breakdown
voltage
IR = 2 µA at 25°C
20
V
INTEGRATED BTST DIODE (D2)
VF_D2
Forward bias voltage IF = 20 mA at 25°C
0.8
V
V
Reverse breakdown
IR = 2 µA at 25°C
voltage
VR_D2
20
INTERFACE
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold
VIN_ HI Input high threshold
SMBus
SMBus
0.8
V
V
2.1
LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)
Output saturation
voltage
VOUT_ LO
5 mA drain current
Voltage = 7 V
0.4
1
V
VOUT_ LEAK
Leakage current
µA
–1
LOGIC INPUT (OTG/VAP/FRS pin)
VIN_ LO_OTG Input low threshold
VIN_ HI_OTG Input high threshold
0.4
V
V
1.3
LOGIC OUTPUT OPEN DRAIN SDA
Output Saturation
Voltage
VOUT_ LO_SDA
VOUT_ LEAK_SDA
5 mA drain current
Voltage = 7 V
0.4
1
V
Leakage Current
µA
–1
–1
–1
LOGIC OUTPUT OPEN DRAIN CHRG_OK
Output Saturation
VOUT_ LO_CHRG_OK
5 mA drain current
Voltage = 7 V
0.4
1
V
Voltage
VOUT_ LEAK _CHRG_OK Leakage Current
µA
LOGIC OUTPUT OPEN DRAIN CMPOUT
Output Saturation
VOUT_ LO_CMPOUT
5 mA drain current
Voltage = 7 V
0.4
1
V
Voltage
VOUT_ LEAK _CMPOUT
Leakage Current
µA
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
Output saturation
VOUT_ LO_PROCHOT
300 mV
50 Ωpullup to 1.05 V / 5-mA
voltage
VOUT_ LEAK_PROCHOT Leakage current
Voltage = 5.5 V
1
µA
–1
ANALOG INPUT (ILIM_HIZ)
Voltage to get out of
HIZ mode
VHIZ_ LO
ILIM_HIZ pin rising
ILIM_HIZ pin falling
0.8
V
V
Voltage to enable HIZ
mode
VHIZ_ HIGH
0.4
ANALOG INPUT (CELL_BATPRESZ)
CELL_BATPRESZ pin voltage as percentage of
REGN = 6 V
VCELL_4S
VCELL_3S
VCELL_2S
VCELL_1S
4S setting
3S setting
2S setting
1S setting
68.4%
51.7%
35%
75%
55%
40%
25%
81.5%
65%
CELL_BATPRESZ pin voltage as percentage of
REGN = 6 V
CELL_BATPRESZ pin voltage as percentage of
REGN = 6 V
48.5%
31.6%
CELL_BATPRESZ pin voltage as percentage of
REGN = 6 V
18.4%
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CELL_BATPRESZ rising
CELL_BATPRESZ falling
MIN
TYP
MAX UNIT
VCELL_BATPRESZ_RISE Battery is present
VCELL_BATPRESZ_FALL Battery is removed
ANALOG INPUT (COMP1, COMP2)
18%
15%
ILEAK_COMP1
ILEAK_COMP2
COMP1 Leakage
COMP2 Leakage
120 nA
120 nA
–120
–120
8.6 Timing Requirements
MIN
NOM
MAX
UNIT
SMBus TIMING CHARACTERISTICS
tr
SCL/SDA rise time
SCL/SDA fall time
SCL pulse width high
SCL pulse width low
300
300
50
ns
ns
µs
µs
µs
µs
ns
ns
µs
µs
kHz
tf
tHIGH
tLOW
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
0.6
1.3
0.6
0.6
100
300
0.6
1.3
10
Setup time for START condition
Start condition hold time after which first clock pulse is generated
Data setup time
Data hold time
Set up time for STOP condition
Bus free time between START and STOP conditions
Clock frequency
fSCL
400
35
HOST COMMUNICATION FAILURE
tTIMEOUT
SMBus bus release timeout(1)
tBOOT
25
10
4
ms
ms
s
Deglitch for watchdog reset signal
Watchdog timeout period, REG0x12[14:13]=01
Watchdog timeout period, REG0x12[14:13]=10
Watchdog timeout period, REG0x12[14:13]=11
5.5
88
7
105
210
tWDI
70
140
s
175
s
(1) Devices participating in a transfer timeout when any clock low exceeds the 25-ms minimum timeout period. Devices that have detected
a timeout condition must reset the communication no later than the 35-ms maximum timeout period. Both a host and a target must
adhere to the maximum value specified because it incorporates the cumulative stretch limit for both a host (10 ms) and a target (25
ms).
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
20
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.7 Typical Characteristics
RAC = 5 mΩ, RSR = 5 mΩ, Inductance = 2.2 μH, CCM Frequency = 800 kHz
100
98
96
94
92
90
88
86
84
82
100
98
96
94
92
90
88
86
84
82
VOUT=3.7V
VOUT=7.4V
VOUT=11.1V
VOUT=14.8V
VOUT=3.7V
VOUT=7.4V
VOUT=11.1V
VOUT=14.8V
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
CCM 800 kHz VOUT = System voltage
图8-1. System Efficiency
Output Current(A)
CCM 800 kHz VOUT = System voltage
图8-2. System Efficiency
VIN = 5 V
VIN = 9 V
100
98
96
94
92
90
88
86
84
82
100
98
96
94
92
90
88
86
84
82
VOUT=3.7V
VOUT=7.4V
VOUT=11.1V
VOUT=14.8V
VOUT=3.7V
VOUT=7.4V
VOUT=11.1V
VOUT=14.8V
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
Output Current(A)
CCM 800 kHz VOUT = System voltage
图8-3. System Efficiency
Output Current(A)
CCM 800 kHz VOUT = System voltage
图8-4. System Efficiency
VIN = 15 V
VIN = 20 V
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
VOUT=4.2V
VOUT=8.4V
VOUT=12.6V
VOUT=16.8V
VOUT=4.2V
VOUT=8.4V
VOUT=12.6V
VOUT=16.8V
0
0.01
0.02
0.03
0.04
0.05
0
0.01
0.02
0.03
0.04
0.05
Output Current(A)
Output Current(A)
VIN = 5 V EN_OOA = 0b
VOUT = System voltage
VIN = 12 V EN_OOA = 0b
VOUT = System voltage
图8-5. Light Load System Efficiency
图8-6. Light Load System Efficiency
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.7 Typical Characteristics (continued)
90
85
80
75
70
65
60
98
96
94
92
90
88
86
84
82
80
VOUT=4.2V
VOTG=5V
VOTG=9V
VOTG=15V
VOTG=20V
VOUT=8.4V
VOUT=12.6V
VOUT=16.8V
55
50
0
0.01
0.02
0.03
0.04
0.05
0
1
2
3
4
5
6
7
8
9
10
Output Current(A)
Output Current(A)
VIN = 20 V EN_OOA = 0b
VOUT = System voltage
VBAT = 4 V
CCM 800 kHz
图8-7. Light Load System Efficiency
图8-8. OTG Efficiency with 1S Battery
98
96
94
92
90
88
86
84
82
80
98
96
94
92
90
88
86
84
82
80
VOTG=5V
VOTG=9V
VOTG=15V
VOTG=20V
VOTG=5V
VOTG=9V
VOTG=15V
VOTG=20V
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Output Current(A)
Output Current(A)
VBAT = 8 V
CCM 800 kHz
VBAT = 12 V
CCM 800 kHz
图8-9. OTG Efficiency with 2S Battery
图8-10. OTG Efficiency with 3S Battery
98
96
94
92
90
88
86
84
82
80
100
95
90
85
80
75
70
65
60
VOTG=5V
VOTG=9V
VOTG=15V
VOTG=20V
VBUS=20V
VBUS=15V
0
1
2
3
4
5
6
7
8
9
10
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current(A)
Output Current(A)
VBAT = 16 V
CCM 800 kHz
VBAT = 8.4 V
VOUT = VBUS
图8-11. OTG Efficiency with 4S Battery
图8-12. PTM Mode Ligh Load System Efficiency
Copyright © 2023 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
8.7 Typical Characteristics (continued)
100
99
98
97
96
95
94
93
92
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
VIN=5V
VIN=9V
VIN=15V
VIN=20V
VBUS=20V
VBUS=15V
91
90
0
1
2
3
4
5
6
7
8
9
10
3
5
7
9
11
13
15
17
19 20
Output Current(A)
Charge Voltage setting(V)
ICHG = 1024 mA CCM 800 kHz
图8-14. Battery Voltage Regulation Accuracy
VBAT = 8.4 V
VOUT = VBUS
图8-13. PTM Mode Heavy Load System Efficiency
2
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
-1
-1
VBAT=3.7V
VBAT=7.4V
VIN=5V
VIN=9V
-1.5
-2
VBAT=11.1V
VBAT=14.8V
VIN=15V
VIN=20V
-1.5
-2
3
5
7
9
11
13
15
17
19 20
3
5
7
9
11
13
15
17
19 20
VINDPM setting(V)
VSYS_MIN setting(V)
ICHG = 1024 mA
CCM 800 kHz
IBUS = 100 mA
VBAT = 0.5 V
CCM 800 kHz
EN_OOA = 0b
图8-15. Input Voltage(VINDPM) Regulation Accuracy
图8-16. Minimum System Voltage Regulation Accuracy
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9 Detailed Description
9.1 Overview
The BQ25720 is a narrow VDC buck-boost charger controller for portable electronics such as notebook,
detachable, ultrabook, tablet, and other mobile devices with rechargeable batteries. It provides seamless
transition between different converter operation modes (buck, boost, or buck-boost), fast transient response, and
high light load efficiency.
The BQ25720 supports a wide range of power sources, including USB-C PD ports, legacy USB ports, traditional
AC-DC adapters, and so forth. It takes input voltage from 3.5 V to 26 V and charges a battery of 1 to in series. In
the absence of an input source, the BQ25720 supports the USB On-the-Go (OTG) function from a cell battery to
generate an adjustable 3 V to 24 V at the USB port with 8-mV resolution.
When only the battery powers the system and no external load is connected to the USB OTG port, the BQ25720
provides the Vmin Active Protection (VAP) feature. In VAP operation, the BQ25720 first charges up the voltage
of the input decoupling capacitors at VBUS to store a certain amount of energy. During the system peak power
spike, the huge current drawn from the battery introduces a larger voltage drop across the impedance from the
battery to the system. The energy stored in the input capacitors will supplement the system, to prevent the
system voltage from dropping below the minimum system voltage and leading the system to a black screen. This
VAP is designed to absorb system power peaks during the periods of high demand to improve system turbo
performance, which is highly recommended by Intel for the platforms with a 1S~2S battery.
The BQ25720 features Dynamic Power Management (DPM) to limit input power and avoid AC adapter
overloading. During battery charging, as system power increases, charging current is reduced to maintain total
input current below adapter rating. If system power demand temporarily exceeds adapter rating, the BQ25720
supports the NVDC architecture to allow battery discharge energy to supplement system power.
The BQ25720 monitors adapter current, battery current, and system power. The flexibility of the programmable
PROCHOT output goes directly to the CPU for throttling back when needed.
The latest version of the USB-C PD specification includes Fast Role Swap (FRS) to ensure power role swapping
occurs in a timely fashion so that the device(s) connected to the dock never experience momentary power loss
or glitching. The device integrates FRS with compliance to the USB-C PD specification.
The TI patented switching frequency dithering pattern can significantly reduce EMI noise over the entire
conductive EMI frequency range (150 kHz to 30 MHz). Multiple dithering scale options are available to provide
flexibility for different applications to simplify EMI noise filter design.
In order to be compliant with Intel IMVP8 / IMVP9, the BQ25720 includes a PSYS function to monitor the total
platform power from the adapter and battery. Besides PSYS, it provides both an independent input current buffer
(IADPT) and a battery current buffer (IBAT) with highly accurate current sense amplifiers. If the platform power
exceeds the available power from the adapter and battery, a PROCHOT signal is asserted to the CPU so that
the CPU optimizes its performance to the power available to the system.
The SMBus host controls input current, charge current, and charge voltage registers with high resolution, high
accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
24
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.2 Functional Block Diagram
4
CHRG_OK
CHRG_OK_DRV
50ms Rising
Deglitch
Block Diagram
** programmable in register
EN_REGN
50ms Rising
Deglitch
3.5V
1
VBUS
VREF_CMP**
CMP_DEG**
14
15
CMPIN
ACOV
26.8V
CMPOUT
VREF_VINDPM or VREF_VOTG
COMP1
COMP2
16
17
VDDA
VSNS_VINDPM or VSYS_VOTG
EN_HIZ
ILIM_HIZ
VREF_ILIM
6
Decoder
VSYS
VREF_IIN_DPM, or VREF_IOTG
2
3
ACP
ACN
VSNS_IIN_DPM, or VSNS_IOTG
LDO Mode
Gate Control
BATDRV
21
20X/40X
VSYS-10V
20X/40X
VSNS_IOTG
30
31
32
7
BTST1
IADPT
IBAT
HIDRV1
Loop Selector
and
Error Ampli er
8
9
VSNS_IIN
VSNS_ICHG
SW1
VSNS_IDCHG
16X/8X
PWM
VDDA
EN_REGN
REGN
LDO
REGN
VREF_ICHG
VSNS_ICHG
28
EN_HIZ
EN_LEARN
EN_LDO
20
19
SRP
SRN
16X/8X
EN_CHRG
EN_OTG
VREF_VBAT
PWM
Driver
Logic
29
27
25
24
23
LODRV1
PGND
BTST2
HIDRV2
SW2
VSNS_VBAT
VREF_VSYS
22
VSYS
VSNS_VSYS
VSNS_VSYS
VSNS_VBAT
ACN
PSYS
(ACP-ACN)
SRN
VSNS_ICHG Over Current
10
VSNS_IDCHG
Over Voltage
(SRN-SRP)
VSNS_IIN_DPM
VSNS_VINDPM
26
18
LODRV2
Detect
EN_HIZ
SMBus
Interface
EN_LEARN
EN_LDO
EN_CHRG
EN_OTG
BATPRESZ
12
SDA
ChargeOp on0()
ChargeOp on1()
ChargeOp on2()
ChargeCurrent()
ChargeVoltage()
InputCurrent()
InputVoltage()
MinSysVoltage()
OTGVoltage()
Decoder
CELL_CONFIG
CELL_BATPRESZ
VREF_VSYS
13
5
SCL
VREF_VBAT
VREF_ICHG
Loop
Regula on
Reference
IADPT
IBAT
VREF_IIN_DPM
VREF_VINDPM
VREF_IOTG
OTG/VAP/FRS
Processor
Hot
11
PROCHOT
VSYS
VREF_VOTG
CHRG_OK
OTGCurrent()
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.3 Feature Description
9.3.1 Power-Up Sequence
The device powers up from the higher voltage of VBUS or VBAT through integrated power selector. The charger
starts POR (power on reset) when VBUS exceeds VVBUS_UVLOZ or VBAT exceeds VVBAT_UVLOZ. 5 ms after either
VBUS or VBAT becomes valid, the charger resets all the registers to the default state. Another 5 ms later, the
user registers become accessible to the host.
Power up sequence when the charger is powered up from VBUS:
• After VBUS above VVBUS_UVLOZ, enable 6-V LDO REGN pin and VDDA pin voltage increase accordingly.
CHRG_OK pin goes HIGH and the AC_STAT is configured to 1.
• After passing VBUS qualification, the REGN voltage is setup. VINDPM is detected in VBUS steady state
voltage and IIN_DPM is detected at ILIM_HIZ pin steady state voltage.
• Battery CELL configuration is read at CELL_BATPRESZ pin voltage and compared to VDDA to determine
cell configuration. Corresponding the default value of ChargeVoltage register (REG0x15()), ChargeCurrent
register (Reg0x14), VSYS_MIN register(Reg0x3E) and SYSOVP threshold are loaded.
• Converter powers up.
Power up sequence when the charger is powered up from VBAT:
• If only battery is present and the voltage is above VVBAT_UVLOZ , charger wakes up and the BATFET is turned
on and connecting the battery to system.
• By default, the charger is in low power mode (EN_LWPWR = 1b) with lowest quiescent current. The REGN
LDO stays off. The Quiescent current is minimized. PROCHOT is available through the independent
comparator by setting EN_PROCHOT_LPWR=1b.
• The adapter present comparator is activated, to monitor the VBUS voltage.
• SDA and SDL lines stand by waiting for host commands.
• Device can move to performance mode by configuring EN_LWPWR = 0b. The host can enable IBAT buffer
through setting EN_IBAT=1b to monitor discharge current. The PSYS, PROCHOT or the independent
comparator also can be enabled by the host.
• In performance mode, the REGN LDO is always available to provide an accurate reference and gate drive
voltage for the converter.
9.3.2 Vmin Active Protection (VAP) with Battery only
When operating in battery only mode, high system peak power can cause the VSYS to drop below the minimum
system voltage due to impedance of battery pack, charging sense resistor and BATFET. Device incorporates
VAP mode to help supplement the system during high peak power events by releasing energy previously stored
in the input capacitor. While the system is operating with normal power loads, the charger can be configured to
store energy in the input capacitors by charging them up to a programamble voltage level. During these high
system power spikes, the energy stored in the input capacitors will supplement the system, to prevent the
system voltage from dropping below the minimum system voltage. The VAP mode can help achieve much better
Turbo performance for Intel CPU under battery only condition. Please contact factory for more detail information
about VAP mode.
9.3.3 Two-Level Battery Discharge Current Limit
To prevent the triggering of battery overcurrent protection and avoid battery wear-out, two battery current limit
levels (IDCHG_TH1 and IDCHG_TH2) PROCHOT profiles are recommended to be enabled. Define
IDCHG_TH1 through REG0x34h[15:10], IDCHG_TH2 is set through REG0x36[5:3] for fixed percentage of
IDCHG_TH1. There are dedicated de-glitch time setting registers(IDCHG_DEG1 and IDCHG_DEG2) for both
IDCHG_TH1 and IDCHG_TH2.
• When battery discharge current is continuously higher than IDCHG_TH1 for more than IDCHG_DEG1 de-
glitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH1,
then the time counter resets automatically. STAT_IDCHG1 bit will be set to 1 after PROCHOT is triggered.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
26
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
Set PP_IDCHG1=1b to enable IDCHG_TH1 for triggering PROCHOT.
• When battery discharge current is continuously higher than IDCHG_TH2 for more than IDCHG_DEG2 de-
glitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH2,
then the time counter resets automatically. STAT_IDCHG2 bit will be set to 1 after PROCHOT is triggered.
Set PP_IDCHG2=1b to enable IDCHG_TH2 for triggering PROCHOT.
IDCHG_TH2
IDCHG_TH1
0A
/PROCHOT
IDCHG_DEG1
IDCHG_DEG1
IDCHG_DEG2
IDCHG_DEG2
图9-1. Two-Level Battery Discharging Current Trigger PROCHOT Diagram
9.3.4 Fast Role Swap Feature
Fast Role Swap (FRS) means charger quickly swaps from power sink role to power source role to provide an
OTG output voltage to accessories when the original power source is disconnected. This feature is defined to
transfer the charger from forward mode to OTG mode quickly without dropping VBUS voltage per USB-C PD
specification requirement.Please contact factory for more detail information about FRS mode.
9.3.5 CHRG_OK Indicator
CHRG_OK is an active HIGH open drain indicator. It indicates the charger is in normal operation when the
following conditions are valid:
• VBUS is above VVBUS_CONVEN
• VBUS is below VACOV_FALL
• No faults triggered such as: SYSOVP/SYSUVP/ACOC/TSHUT/BATOVP/BATOC/force converter off.
9.3.6 Input and Charge Current Sensing
The charger supports 10 mΩ and 5 mΩ for both input current sensing and charge current sensing. By default,
10 mΩ is enabled by POR setting RSNS_RAC=0b and RSNS_RSR=0b, if 5 mΩ sensing is used please
configure RSNS_RAC=1b and RSNS_RSR=1b. Lower current sensing resistor can help improve overall charge
efficiency especially under heavy load. At same time PSYS,IADPT,IBAT pin accuracy and IINDPM/ICHG/IOTG
regulation accuracy get worse due to effective signal reduction in comparison to error signal components.
When RSNS_RAC=RSNS_RSR=0b and 10 mΩ is used for both input and charge current sensing, the pre-
charge current clamp is 384 mA (2 A for 1S if VSYS_MIN>VBAT>3 V ), the maximum IIN_HOST setting is
clamped at 6.35 A, and the maximum charge current is clamped at 8.128 A.
When RSNS_RAC=RSNS_RSR=1b and 5 mΩ is used for both input and charge current sensing, the charger
will internally compensate pre-charge current clamp to be 384 mA (2 A for 1S if VSYS_MIN>VBAT>3 V ) under
5-mΩ current sensing which keeps consistent between 10 mΩ and 5 mΩ. Under 5-mΩ current sensing
application charge current range is doubled to 16.256 A. Based on EN_FAST_5MOHM register bit status and
IADPT pin resistor the maximum input current can be configured referring to 表9-1:
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
For defined current sense resistors (10 mΩ/5 mΩ), PSYS function is still valid when unsymmetrical input current
sense and charge current sense resistors are used. But RSNS_RAC and RSNS_RSR bit status have to be
consistent with practical resistors used in the system.
表9-1. Maximum Input Current Limit Configuration Table
INDUCTANCE (IADPT Pin
Resistance)
MAXIMUM INPUT CURRENT LIMIT
(IINDPM)
EN_FAST_5MOHM
RSR_RAC BIT
Xb
1b
0b
Xb
Xb
RSNS_RAC=0b
RSNS_RAC=1b
RSNS_RAC=1b
RSNS_RAC=0b
RSNS_RAC=1b
6.35 A
6.35 A
10 A
1.0 uH(90.9 kΩ)
1.5 uH(121 kΩ)
2.2 uH(137 kΩ)
6.35 A
10 A
3.3 uH(169 kΩ)
9.3.7 Input Voltage and Current Limit Setup
The actual input current limit being adopted by the device is the lower setting of IIN_DPM and ILIM_HIZ pin.
Register IIN_DPM input current limit setting will reset for below scenarios:
• When adapter is removed (CHRG_OK is not valid). Note when adapter is removed IIN_HOST will be reset
one time to 3.25 A, under battery only host is still able to overwrite IIN_HOST register with a new value. If the
adapter plug back in and CHRG_OK is pulled up, IIN_HOST will not be reset again.
• When input current optimization (ICO) is executed (EN_ICO_MODE=1b), the charger will automatically detect
the optimized input current limit based on adapter output characteristic. The final IIN_DPM register setting
could be different from IIN_HOST after ICO.
The voltage regulation loop of the charger regulates the input voltage to prevent the input adapter collapsing.
The VINDPM threshold should be configured based on no load input voltage level.Charger initiates a VBUS
voltage measurement without any load (VBUS at no load) right before the converter is enabled. The default
VINDPM threshold is VBUS at no load – 1.28 V. Host can adjust VINDPM threshold after device POR through
InputVoltage register(0x3D[]), range from 3.2V to 19.52V with LSB 64mV.
After input current and voltage limits are set, the charger device is ready to power up. The host can always
program the input current and voltage limit after the charger being powered up based on the input source type.
9.3.8 Battery Cell Configuration
CELL_BATPRESZ pin is biased with a resistor divider from VDDA to GND. After REGN LDO is activated (VDDA
rise up), the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. No external
cap is allowed at CELL_BATPRESZ pin. When CELL_BATPRESZ pin is pulled down to GND (because of
battery removal) at the beginning of startup process, VSYS_MIN = 3.6 V and SYS_OVP = 25 V and Maximum
charge voltage (REG0x15) follow 1 cell default setting 4.2 V. . Refer to 表 9-2 for CELL_BATPRESZ pin
configuration typical voltage for swept cell count.
表9-2. Battery Cell Configuration
PIN VOLTAGE w.r.t.
VDDA
CHARGEVOLTAGE
(REG0x15h)
VSYS/VBAT
ADC OFFSET
CELL COUNT
SYSOVP
VSYS_MIN
4S
75%
55%
40%
25%
0%
16.800 V
12.600 V
8.400 V
4.200 V
4.200 V
19.5 V
19.5 V
12 V
12.3 V
9.2 V
6.6 V
3.6 V
3.6 V
2.88 V
2.88 V
2.88 V
2.88 V
2.88 V
3S
2S
1S
6 V
Battery removal
25 V
9.3.9 Device HIZ State
When input source is present, the charger can enter HIZ mode (converter shuts off) when ILIM_HIZ pin voltage
is below 0.4 V or EN_HIZ is set to 1b. The charger is in the low quiescent current mode with REGN LDO
Copyright © 2023 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
enabled, ADC circuits are disactivated to reduce quiescent current. In order to exit HIZ mode, ILIM_HIZ pin
voltage has to be higher than 0.8 V and EN_HIZ bit has to be set to 0b.
9.3.10 USB On-The-Go (OTG)
The device supports USB OTG operation to deliver power from the battery to other portable devices through
USB port. The OTG mode output voltage is set in OTGVoltage register REG0x3B() with 8-mV LSB range from
3.0 V to 24 V. The OTG mode output current is set in OTGCurrent register REG0x3C with 50-mA LSB range
from 0 A to 6.35 A under 10-mΩ input current sensing. Both OTG voltage and OTG current are qualified for
USB-C™ programed power supply (PPS) specification in terms of resolution and accuracy. The OTG mode can
be enabled following below steps:
• Set target OTG current limit in OTGCurrent register, VBUS is below VVBUS_CONVENZ
• Set OTG_VAP_MODE = 1b and EN_OTG = 1b.
.
• OTG/VAP/FRS pin is pulled high.
• 15 ms after the above conditions are valid, converter starts and VBUS ramps up to target voltage. CHRG_OK
pin goes HIGH if OTG_ON_CHRGOK= 1b.
OTG/VAP/FRS pin is used as multi-function to enable OTG, VAP and FRS mode.
9.3.11 Converter Operation
The charger operates in buck, buck-boost and boost mode under different VBUS and VSYS combination. The
buck-boost can operate seamlessly across the three operation modes. The 4 main switches operating status
under continuous conduction mode (CCM) are listed below for reference.
表9-3. MOSFET Operation
MODE
Q1
BUCK
Switching
Switching
OFF
BUCK-BOOST
BOOST
ON
Switching
Q2
Switching
OFF
Q3
Switching
Switching
Switching
Q4
ON
Switching
9.3.12 Inductance Detection Through IADPT Pin
The charger reads the inductance value through the resistance tied to IADPT pin before the converter starts up.
The resistances recommended for 1-μH (1200 kHz), 2.2-μH (800 kHz), and 3.3-μH (800 kHz) inductance are
90.9 kΩ, 137 kΩ, 169 kΩ, respectively. A surface mount chip resistor with ±2% or better tolerance must to be
used for an accurate inductance detection. In order to detect the correct IADPT pin pull down resistance and get
rid of disturbance from external circuit, before converter startup all the additional sensing circuit connecting to
IADPT pin should be high impedance.
表9-4. Inductor Detection through IADPT Resistance
INDUCTOR IN USE
RESISTOR ON IADPT PIN
1 µH (recommended for 1200 kHz)
1.5 µH (recommended for 800 kHz)
2.2 µH (recommended for 800 kHz)
3.3 µH (recommended for 800 kHz)
90.9 kΩ
121 kΩ
137 kΩor 140 kΩ
169 kΩ
9.3.13 Converter Compensation
The charger employs two compensation pins COMP1 and COMP2 for converter compensation purpose,
appropriate RC network is needed to guarantee converter steady state and transient operation. Under different
operation frequency corresponding RC network value needs to be configured respectively as shown in below
table. The definition of these RC components can be referred to 图 9-2. It is not recommended to change the
compensation network value due to the complexity of various operation modes.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
COMP2 C22
表9-5. Compensation Configuration
COMPONENT
VALUE
INDUCTOR
COMP1 R1
COMP1 C11
COMP1 C12
COMP2 R2
COMP2 C21
800 kHz
800 kHz
800 kHz
1200 kHz
3.3 nF
3.3 nF
3.3 nF
3.3 nF
33 pF
33 pF
33 pF
33 pF
1200 pF
1200 pF
1200 pF
1200 pF
15 pF
15 pF
15 pF
15 pF
3.3 μH
2.2 μH
1.5 μH
1.0 μH
16.9 kΩ
16.9 kΩ
16.9 kΩ
16.9 kΩ
15 kΩ
10 kΩ
6.8 kΩ
5 kΩ
COMP1
COMP2
R1
R2
C12
C22
C11
C21
图9-2. Compensation RC Network
9.3.14 Continuous Conduction Mode (CCM)
With sufficient charge or system current, the inductor current does not cross 0 A, which is defined as CCM. The
controller starts a new cycle with ramp coming up from 200 mV. As long as the error amplifier output voltage is
above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds error
amplifier output voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp
gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during
transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the
body-diode of the low-side power MOSFET conducts the inductor current.
During CCM, the inductor current always flows. Having the LSFET turn-on when the HSFET is off keeps the
power dissipation low and allows safe charging at high currents.
9.3.15 Pulse Frequency Modulation (PFM)
In order to improve converter light-load efficiency, BQ25720 switches to PFM operation at light load. The
effective switching frequency will decrease accordingly when system load decreases. The minimum frequency
can be limited to 25 kHz when the OOA feature is enabled (EN_OOA=1b) to avoid audible noise.
9.3.16 Switching Frequency and Dithering Feature
Normally, the IC switches in fixed frequency which can be adjusted through PWM_FREQ register bit. The
Charger also support frequency dithering function to improve EMI performance. This function is disabled by
default with setting EN_DITHER=00b. It can be enabled by setting EN_DITHER=01/10/11b, the switching
frequency is not fixed when dithering is enabled. It varies within determined range by EN_DITHER setting,
01/10/11b is corresponding to ±2%/4%/6% switching frequency. Please contact factory for more detail
information.
9.3.17 Current and Power Monitor
9.3.17.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
A high-accuracy current sense amplifier (CSA) is used to monitor the input current during forward charging, or
output current during OTG (IADPT) and the charge/discharge current (IBAT). IADPT voltage is 20× or 40× the
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
30
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
differential voltage across ACP and ACN. IBAT voltage is 8×/16× of the differential across SRP and SRN. After
input voltage or battery voltage is above UVLO, IADPT output becomes valid. To lower the voltage on current
monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be
achieved.
• VIADPT = 20 or 40 × (VACP –VACN) during forward mode, or 20 or 40 × (VACN –VACP) during reverse OTG
mode.
• VIBAT = 8 or 16 × (VSRP –VSRN) during forward charging mode.
• VIBAT = 8 or 16 × (VSRN –VSRP) during forward supplement mode, reverse OTG mode and battery only
discharge scenario.
A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An
additional RC filter is optional. Note that RC filtering has additional response delay. The CSA output voltage is
clamped at 3.3 V.
9.3.17.2 High-Accuracy Power Sense Amplifier (PSYS)
The charger monitors total system power. During forward mode, the input adapter powers the system. During
reverse OTG mode and battery only discharge scenario, the battery powers the system and VBUS output. The
ratio of PSYS pin output current and total system power, KPSYS, can be programmed in PSYS_RATIO register bit
with default 1 μA/W. The input and charge sense resistors (RAC and RSR) are selected in RSNS_RAC bit and
RSNS_RSR bit. By default, PSYS_CONFIG=00b and PSYS voltage can be calculated with 方程式 1, where
IIN>0 when the charger is in forward charging and IIN<0 when charger is in OTG operation; where IBAT>0 when
the battery is in charging and IBAT<0 when battery is discharging.
VPSYS =RPSYS·KPSYS(VACP·IIN+VSYS·IBAT
)
(1)
RAC and RSR values are not limited to symmetrical both 5 mΩ or both 10 mΩ. For defined current sense
resistors (10 mΩ/5 mΩ), PSYS function is still valid when RAC=5 mΩ(RSNS_RAC=1b) and RSR=10
mΩ(RSNS_RAC=0b), vice versa. As long as RSNS_RAC and RSNS_RSR bit status are consistent with
practical resistors used in the system.
Charger can block IBAT contribution to above equation by setting PSYS_CONFIG =01b in forward mode and
block IBUS contribution to above equation by setting PSYS_OTG_IDCHG=1b in OTG mode.
To minimize the quiescent current, the PSYS function is disabled by default PSYS_CONFIG = 11b.
表9-6. PSYS Configuration Table
OTG
MODE PSYS
PSYS_OTG_IDCHG
BITS
FORWARD MODE PSYS
CONFIGURATION
CASE #
PSYS_CONFIG BITS
CONFIGURATION
1
00b
00b
01b
11b
10b
0b
1b
Xb
Xb
Xb
PSYS = PBUS+PBAT
PSYS = PBUS+PBAT
PSYS = PBUS
PSYS = PBUS + PBAT
PSYS =PBAT
2
3
PSYS = 0
4
PSYS = 0 (Disabled)
PSYS = 0 (Reserved)
PSYS = 0 (Disabled)
PSYS = 0 (Reserved)
5 (Reserved)
9.3.18 Input Source Dynamic Power Management
The charger supports Dynamic Power Management (DPM). Normally, the input power source provides power for
the system load and/or charging the battery. When the input current exceeds the input current setting (IIN_DPM),
or the input voltage falls below the input voltage setting (VINDPM), the charger decreases the charge current to
provide priority to the system load. As the system current rises, the available charge current drops accordingly
towards zero. If the system load keeps increasing after the charge current drops down to zero, the system
voltage starts to drop. As the system voltage drops below the battery voltage, the battery will discharge to
supplement the heavy system load.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.3.19 Input Current Optimizer (ICO)
For a recognized input adapter, IINDPM can be configured precisely to prevent adapter collapasing. When a
third party unknown adapter is used, then input voltage regulation (VINDPM) feature can be leveraged to
prevent input crash. With the increasing of input current, voltage drops along the input cable also increases and
voltage measured it charger input port decreases accordingly. VINDPM feature can limit input power from
adapter by regulating VBUS at certain value configured at InputVoltage register(0x3Dh[]). However, the adapter
may still overheat when it is kept running at its voltage limit for a long period of time. Therefore, it is preferred to
operate the third party adapter slightly under its current rating. The Input Current Optimizer (ICO) feature can
automatically maximize the power of unknown input adapter without continuously working under VINDPM. Note
the ICO feature can only be employed when the adapter input current limit is at least 500 mA. Please contact
factory for more detail information about ICO feature.
9.3.20 Two-Level Adapter Current Limit (Peak Power Mode)
Usually adapter can supply current higher than DC rating for a few milliseconds to tens of milliseconds. The
charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability and
minimize battery discharge during system load transient. The level 1 current limit, or ILIM1, is the same as
adapter DC current, set in IIN_DPM register. The level 2 overloading current, or ILIM2, is set in ILIM2_VTH, as a
percentage of ILIM1
.
When the charger detects input current surge and battery discharge due to load transient (both the adapter and
battery support the system together), or when the charger detects the system voltage starts to drop below
VSYS_MIN setting due to load transient (only the adapter supports the system), the charger will first apply ILIM2
for TOVLD (PKPWR_TOVLD_DEG register bits), and then ILIM1 for up to TMAX – TOVLD time. TMAX is
programmed in PKPWR_TMAX register bits. After TMAX, if the load is still high, another peak power cycle starts.
Charging is disabled during TMAX and TOVLD already expires; once TMAX, expires, a new cycle starts and
resumes charging automatically.
To prepare entering peak power follow below steps:
• Set EN_IIN_DPM=1b to enable input current dynamic power management.
• Set EN_EXTILIM=0b to disable external current limit.
• Set register IIN_HOST based on adapter output current rating as the level 1 current limit(ILIM1
)
• Set register bits ILIM2_VTH according to the adapter overload capability as the level 2 current limit(ILIM2) .
• Set register bits PKPWR_TOVLD_DEG as ILIM2 effective duration time for each peak power mode operation
cycle based on adapter capability.
• Set register bits PKPWR_TMAX as each peak power mode operation cycling time based on adapter
capability.
Depends on the battery existence and charge status peak power mode can be finally enabled with two different
approaches:
• When battery is depleted in which VBAT is lower than VSYS_MIN setting or battery is removed, host need to
set EN_PKPWR_VSYS=1b to enable peak power mode triggered by system voltage undershoot. The under-
shoot threshold is the VSYS_MIN register setting which is the system regulation point before load transient
happens. Typical application waveform refer to 图10-21.
• When battery is not depleted in which VBAT is higher than VSYS_MIN setting, host need to set
EN_PKPWR_IIN_DPM=1b to enable peak power mode triggered by input current overshoot. The overshoot
threshold is IIN_DPM register which is same as the level 1 current limit (ILIM1). Typical application waveform
refer to 图10-22.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
32
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
ICRIT_DEG
ICRIT
ILIM2
ILIM1
TOVLD
TOVLD
TMAX
IBUS
ISYS
IBAT
0A
Ba ery Discharge
PROCHOT_WIDTH
PROCHOT
图9-3. Two-Level Adapter Current Limit Timing Diagram
9.3.21 Processor Hot Indication
When CPU is running turbo mode, the system peak power may exceed available power from adapter and
battery together. The adapter current and battery discharge peak current, or system voltage drop is an indication
that system power is too high. The charger processor hot function monitors these events, and PROCHOT pulse
is asserted if the system power is too high. Once CPU receives PROCHOT pulse from charger, it slows down to
reduce system power. The events monitored by the processor hot function includes:
• ICRIT: adapter peak current, as 110% of ILIM2
• INOM: adapter average current (110% of IIN_DPM)
• IDCHG1: battery discharge current level 1
• IDCHG2: battery discharge current level 2, note IDCHG2 threshold is always larger than IDCHG1 threshold
determined by IDCHG_TH2 register setting.
• VBUS_VAP: VBUS threshold to trigger PROCHOT in VAP mode 2 and 3.
• VSYS: system voltage on VSYS pin
• Adapter Removal: upon adapter removal (VBUS is lower than ACOK_TH=3.2 V same as VVBUS_CONVENZ
threshold)
• Battery Removal: upon battery removal (CELL_BATPRESZ pin goes LOW)
• CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)
• VINDPM: VBUS lower than 83%/91%/100% of VINDPM setting. The effective threshold PROCHOT_VINDPM
is determined by combination of register PROCHOT_VINDPM_80_90 bit and LOWER_PROCHOT_VINDPM
bit:
– PROCHOT_VINDPM=VINDPM register setting: LOWER_PROCHOT_VINDPM=0b;
– PROCHOT_VINDPM=83% VINDPM register setting:
LOWER_PROCHOT_VINDPM=1b;PROCHOT_VINDPM_80_90=0b;
– PROCHOT_VINDPM=91% VINDPM register setting:
LOWER_PROCHOT_VINDPM=1b;PROCHOT_VINDPM_80_90=1b;
• EXIT_VAP: Every time when the charger exits VAP mode.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
The threshold of ICRIT, IDCHG1,IDCHG2,VSYS or VINDPM, and the deglitch time of ICRIT, INOM, IDCHG1,
IDCHG2, or CMPOUT are programmable through SMBus register bits. Except the PROCHOT_EXIT_VAP is
always enabled, the other triggering events can be individually enabled in ProchotOption1[7:0], PP_IDCHG2 and
PP_VBUS_VAP. When any enabled event in PROCHOT profile is triggered, PROCHOT is asserted low for a
single pulse with minimal width programmable in PROCHOT_WIDTH register bits. At the end of the single
pulse, if the PROCHOT event is still active, the pulse gets extended until the event is removed.
If the PROCHOT pulse extension mode is enabled by setting EN_PROCHOT_EXT= 1b, the PROCHOT pin will
be kept low until host writes PROCHOT_CLEAR= 0b, even if the triggering event has been removed.
If the PROCHOT_VINDPM or PROCHOT_EXIT_VAP is triggered, PROCHOT pin will always stay low until the
host clears it, no matter the PROCHOT is in one pulse mode or in extended mode. In order to clear
PROCHOT_VINDPM, host needs to write 0 to STAT_VINDPM. In order to clear PROCHOT_EXIT_VAP, host
needs to write 0 to STAT_EXIT_VAP.
PP_ICRIT
IADPT
+
ICRIT
Adjustable
Deglitch
Low Pass
Filter
PP_INOM
+
EXIT_VAP
(triggered by IN_VAP
falling edge)
INOM
1.05V
PP_IDCHG2
IDCHG2
IDCHG1
+
IDCHG_VTH2
PP_IDCHG1
PROCHOT
+
IDCHG_VTH1
VSYS_VTH2
10ms
Debounce
PP_VSYS
+
VSYS
VBUS
10ms
Fixed
Deglitch
4us
PP_VINDPM
A*VINDPM
+
Fixed
Deglitch
4us
PP_VBUS_VAP
PP_ACOK
VBUS_VAP_TH
+
VVBUS_CONVENZ
PP_CMP
PP_BATPRES
CELL_BATPRESZ
(one shot on pin falling edge)
VBUS
(one shot on pin falling edge)
CMPOUT
图9-4. PROCHOT Profile
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
34
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.3.21.1 PROCHOT During Low Power Mode
During low power mode (EN_LWPWR = 1), the charger offers a low power PROCHOT function with very low
quiescent current consumption (~35 μA), which uses the independent comparator to monitor the system
voltage, and assert PROCHOT to CPU if the system power is too high and resulting system voltage is lower than
specific threshold.
Below lists the register setting to enable PROCHOT monitoring system voltage in low power mode.
• EN_LWPWR = 1b to enable charger low power mode.
• REG0x34[7:0] = 00h
• REG0x30[6:4] = 000b
• Independent comparator threshold is always 1.2 V
• When EN_PROCHOT_LPWR = 1b, charger monitors system voltage. Connect CMPIN to voltage
proportional to system voltage. PROCHOT triggers from HIGH to LOW when CMPIN voltage rises above 1.2
V.
PROCHOT
1.2 V
Independent
Comparator
CMPIN
Voltage îVSYS
图9-5. PROCHOT Low Power Mode Implementation
9.3.21.2 PROCHOT Status
REG0x21[8:0] report which event in the profile triggers PROCHOT if the corresponding bit is set to 1. The status
bit can be reset back to 0 after it is read by the host, when the current PROCHOT event is not active any more.
Assume there are two PROCHOT events, event A and event B. Event A triggers PROCHOT first, but event B is
also active. Both status bits will be HIGH. At the end of the 10-ms PROCHOT pulse, if any of the PROCHOT
event is still active (either A or B), the PROCHOT pulse is extended.
9.3.22 Device Protection
9.3.22.1 Watchdog Timer
The charger includes a watchdog timer to terminate charging if the charger does not receive a write
ChargeVoltage() or write ChargeCurrent() command within 175s (default value and adjustable via
WDTMR_ADJ). When watchdog timeout occurs, all register values are kept unchanged except ChargeCurrent()
resets to 0 A . Write ChargeVoltage() or write ChargeCurrent() commands must be resent to reset watchdog
timer. Writing WDTMR_ADJ = 00b to disable watchdog timer or update new watchdog timer values can also
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
reset watchdog timer. New non-zero charge current value has to be written to ChargeCurrent() register to
resume charging after watchdog timer expires.
9.3.22.2 Input Overvoltage Protection (ACOV)
The charger has fixed ACOV voltage threshold with hysteresis. When VBUS pin voltage is higher than
VACOV_RISE for more than 100 μs, it is considered as adapter overvoltage. CHRG_OK pin will be pulled low by
the charger, and the converter will be disabled. As system falls below battery voltage, BATFET will be turned on.
When VBUS pin voltage falls below VACOV_FALL for more than 1 ms, it is considered as adapter voltage returns
back to normal voltage. CHRG_OK pin is pulled high by external pull-up resistor. The converter resumes if
enable conditions are valid.
9.3.22.3 Input Overcurrent Protection (ACOC)
If the input current exceeds the 1.33× or 2× of ILIM2_VTH set point ACOC_TH (adjustable through ACOC_VTH),
after 250-μs rising edge de-glitch time converter stops switching because of input overcurrent protection
(ACOC). ACOC is a non-latch fault, if input current falls below set point, after 250-ms falling edge de-glitch time
converter starts switching again. ACOC is disabled by default and need to be enabled by configuring
EN_ACOC=1b. When ACOC is triggered, its corresponding status bit Fault ACOC will be set and it can be
cleared by host read.
9.3.22.4 System Overvoltage Protection (SYSOVP)
When the converter starts up, the BQ25720 reads CELL_BATPRESZ pin configuration and sets ChargeVoltage()
and SYSOVP threshold (1s – 6 V, 2s – 12 V, 3s/4s – 19.5 V ). Before ChargeVoltage() is written by the host,
the battery configuration will change with CELL pin voltage. When SYSOVP happens, the device latches off the
converter. Fault SYSOVP status bit is set to 1. The user can clear latch-off by either writing 0 to the Fault
SYSOVP status bit or removing and plugging in the adapter again. After latch-off is cleared, the converter starts
again.
9.3.22.5 Battery Overvoltage Protection (BATOVP)
Battery overvoltage may happen when user plugs in a wrong battery or a wrong regulation voltage is written into
ChargeVoltage() register. The BATOVP rising threshold is 104% of regulation voltage set in ChargeVoltage()
register, and falling threshold is 102% of regulation voltage set in ChargeVoltage() register. When BATOVP rising
condition is triggered: if charge is enabled (charge current is not 0A) converter should shut down with both HS
MOSFET and LS MOSFET turned off; if charge is disabled the converter should keep operating without
disturbance until battery rise up system voltage to be high enough trigger SYSOVP. There is no user status bit to
monitor. Note VBAT voltage used for BATOVP detection is based on SRN pin measurement. When BATOVP is
triggered with charge enabled, 40-mA discharge current is added on VSYS pin will help discharge battery
voltage.
9.3.22.6 Battery Discharge Overcurrent Protection (BATOC)
The charger monitors the battery discharge current to provide the battery overcurrent protection (BATOC)
through voltage across SRN and SRP. BATOC can be enabled by configuring EN_BATOC=1b. BATOC threshold
is selected either 133% of IDCHG_TH2 or 200% IDCHG_TH2 through BATOC_VTH bit. The threshold is also
clamped between 100 mV and 360 mV SRN-SRP cross voltage.
When discharge current is higher than the threshold after 250-μs deglitch time, BATOC fault is triggered, status
bit Fault BATOC is set accordingly. Converter shuts down when BATOC is asserted to disable OTG operation
and reduce discharge current. BATFET status is not impacted if need to supplement power to system.
BATOC is not a latch fault, therefore after BATOC fault is removed, with 250-ms relax time, converter resume
switching automatically. But status bit Fault BATOC is only cleared by host read.
9.3.22.7 Battery Short Protection (BATSP)
For multicell operation, if BAT voltage falls below VSYS_MIN during charging, the maximum charger current is
limited to 384 mA. For single-cell operation, if BAT voltage falls below 3.0 V during charging, the maximum
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
36
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
charge current is limited to 384 mA; if BAT voltage is between 3.0 V and VSYS_MIN then maximum charge
current is limited to 2 A. Note VBAT voltage used for battery short detection is based on SRN pin measurement.
9.3.22.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
The charger VSYS_UVP is enabled by POR ( VSYS_UVP_ENZ=0b) and can be disabled by writing
VSYS_UVP_ENZ=1b. This protection is mainly defined to protect converter from system short circuit under both
startup and steady state process. VSYS pin is used to monitor the system voltage, when VSYS is lower than 2.4
V (configurable through VSYS_UVP register bits), there is 2-ms deglitch time, the IIN_DPM is clamped to 0.5 A
by the charger itself.
If hiccup mode is enabled with VSYS_UVP_NO_HICCUP = 0b, after 2-ms deglitch time, the charger should shut
down for 500 ms.The charger will restart for 10 ms if VSYS is still lower than 2.4 V, the charger should shut
down again. This hiccup mode will be tried continuously, if the charger restart failed for 7 times in 90 second, the
charger will be latched off. Fault VSYS_UVP bit will be set to 1 to report a system short fault. The charger only
can be enabled again by writing Fault VSYS_UVP bit to 0b.
If hiccup mode is disabled VSYS_UVP_NO_HICCUP = 1b. After 2-ms deglitch time, the charger should shut
down and latched off. Fault VSYS_UVP bit will be set to 1 to report a system short fault. The charger only can be
enabled again once the host writes Fault VSYS_UVP bit to 0b.
9.3.22.9 Thermal Shutdown (TSHUT)
The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junction temperatures low. As added level of protection, the charger converter turns off for self-
protection whenever the junction temperature reaches the 155°C. The charger stays off until the junction
temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16 mA and
stays on. When the temperature falls below 135°C, charge can be resumed with soft start.
When thermal shut down is triggered, TSHUT status bit will be triggered. This status bit keep triggered until host
read to clear it. If TSHUT is still present during host read, then this bit will try to be cleared when host read but
finally keep triggered because TSHUT still exists.
9.4 Device Functional Modes
9.4.1 Forward Mode
When input source is connected to VBUS, BQ25720 is in forward mode to regulate system and charge battery.
9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
The device employs Narrow VDC architecture (NVDC) with BATFET separating the system from the battery. The
minimum system voltage is set by VSYS_MIN register REG0x3E(). Even with a depleted battery, the system is
regulated above the minimum system voltage.
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is regulated at VSYS_MIN register value. As the battery voltage rises above the minimum
system voltage, system voltage is regulated 150 mV above battery voltage when BATFET is turned off (no
charging or no supplement current). When in charging or in supplement mode, the voltage difference between
the system and battery is the VDS of the BATFET and the BATFET is fully on.
9.4.1.2 Battery Charging
The BQ25720 charges 1- to 4-cell battery in constant current (CC), and constant voltage (CV) mode. Based on
CELL_BATPREZ pin setting, the charger sets default battery voltage 4.2 V/cell to ChargeVoltage(). According to
battery capacity, the host programs appropriate charge current to ChargeCurrent() register. When battery is full
or battery is not in good condition to charge, host terminates charge by setting CHRG_INHIBIT bit to 1b, or
setting ChargeCurrent() to zero.
9.4.2 USB On-The-Go
The BQ25720 supports USB OTG functionality to deliver power from the battery to other portable devices
through USB port (reverse mode). The OTG output voltage is compliant with USB-C PD specification, including 5
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
V, 9 V, 15 V, and 20 V. The output current regulation is compliant with USB-C PD specification, including 500
mA, 1.5 A, 3 A and 5 A, and so forth.
Similar to forward operation, the device switches from PWM operation to PFM operation at light load to improve
efficiency.
9.4.3 Pass Through Mode (PTM)-Patented Technology
The charger can be operated in the pass through mode (PTM) to improve efficiency. In PTM, the Buck and Boost
high-side FETs (Q1 and Q4) are both turned on, while the Buck and Boost low-side FETs are both turned off.
The input power is directly passed through the charger to the system. The switching losses of MOSFETs and the
inductor core loss are saved. The charger quiescent current under PTM mode is also minimized to further
increase light load efficiency. Charger will be transition from normal Buck-Boost operation to PTM operation by
setting EN_PTM = 1b; and will transition out of PTM mode with host control by setting EN_PTM =0b. Please
contact factory for more detail information about PTM mode.
9.5 Programming
The charger supports battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in 节9.5.1.1. The SMBus address is 12h . The ManufacturerID and DeviceID registers are assigned
to identify the charger device. The ManufacturerID register command always returns 40h.
9.5.1 SMBus Interface
The BQ25720 device operates as a target, receives control inputs from the embedded controller host through
the SMBus interface. The BQ25720 device uses a simplified subset of the commands documented in System
Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The device uses the
SMBus read-word and write-word protocols (shown in 表 9-7 and 表 9-8) to communicate with the smart battery.
The device performs only as a SMBus target device with address 0b0001001_X (0x12H Write/0x13H Read) and
does not initiate communication on the bus. In addition, the device has two identification registers, a 16-bit
device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).
SMBus communication starts when VBUS is above VVBUS_UVLO or VBAT is above VVBAT_UVLO
.
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pull-up resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the host signals a start condition, which is a high-to-low transition on SDA, while
SCL is high. When the host has finished communicating, the host issues a stop condition, which is a low-to-high
transition on SDA, while SCL is high. The bus is then free for another transmission. 图 9-6 and 图 9-7 show the
timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are
transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the
start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock
cycles are required to transfer each byte in or out of the device because either the host or the target
acknowledges the receipt of the correct byte during the ninth clock cycle. The BQ25720 supports the charger
commands listed in 表9-7.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
38
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.5.1.1 SMBus Write-Word and Read-Word Protocols
表9-7. Write-Word Format
S
SLAVE
W
ACK COMMAND
ACK LOW DATA
ACK
HIGH DATA
BYTE(1)
ACK
P
(1) (2)
(1) (3)
(4) (5)
(4) (5)
(4) (5)
(4) (5)
(1) (6)
ADDRESS(1)
BYTE(1)
BYTE(1)
7 bits
1b
0
1b
0
8 bits
1b
0
8 bits
1b
8 bits
1b
MSB LSB
MSB LSB
MSB LSB
0
MSB LSB
0
(1) Master to slave
(2) S = Start condition or repeated start condition
(3) W = Write bit (logic low)
(4) Slave to master (shaded gray)
(5) ACK = Acknowledge (logic low)
(6) P = Stop condition
表9-8. Read-Word Format
S(1) SLAVE
W
ACK COMMAND ACK S(1) SLAVE
R(1) ACK LOW DATA ACK HIGH DATA
NACK P
(2)
(1) (3) (4) (5)
(4) (5) (2)
(6)
(4) (5)
(1) (5)
(1) (7)
(1) (8)
ADDRESS(1)
BYTE(1)
8 bits
MSB LSB
ADDRESS(1)
BYTE(4)
BYTE(4)
8 bits
MSB LSB
7 bits
1b
0
1b
0
1b
0
7 bits
1b
1b
0
8 bits
1b
0
1b
1
MSB LSB
MSB LSB
1
MSB LSB
(1) Master to slave
(2) S = Start condition or repeated start condition
(3) W = Write bit (logic low)
(4) Slave to master (shaded gray)
(5) ACK = Acknowledge (logic low)
(6) R = Read bit (logic high)
(7) NACK = Not acknowledge (logic high)
(8) P = Stop condition
9.5.1.2 Timing Diagrams
SCL
SDA
A = Start condition
H = LSB of data clocked into target
I = Target pulls SDA line low
B = MSB of address clocked into target
C = LSB of address clocked into target
D = R/W bit clocked into target
E = Target pulls SDA line low
J = Acknowledge clocked into host
K = Acknowledge clock pulse
L = Stop condition, data executed by target
M = New start condition
F = ACKNOWLEDGE bit clocked into host
G = MSB of data clocked into target
图9-6. SMBus Write Timing
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
SCL
SDA
A = Start condition
G = MSB of data clocked into host
H = LSB of data clocked into host
I = Acknowledge clock pulse
J = Stop condition
B = MSB of address clocked into target
C = LSB of address clocked into target
D = R/W bit clocked into target
E = Target pulls SDA line low
K = New start condition
F = ACKNOWLEDGE bit clocked into host
图9-7. SMBus Read Timing
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
40
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6 Register Map
表9-9. Charger Command Summary
SMBus
ADDR
REGISTER NAME
TYPE
R/W
DESCRIPTION
LINKS
12h
14h
ChargeOption0()
ChargeCurrent()
Charge Option 0
Go
Go
R/W
7-bit charge current setting
LSB 64 mA, Range 0 mA - 8128 mA
15h
ChargeVoltage()
R/W
12-bit charge voltage setting
Go
LSB 8 mV, Default: 1S-4200mV, 2S-8400mV,
3S-12600mV, 4S-16800mV,
20h
21h
22h
23h
ChargerStatus()
ProchotStatus()
IIN_DPM()
R with R/W Charger Status
bits
Go
Go
Go
Go
R with R/W Prochot Status
bits
R
7-bit input current limit in use
LSB: 50 mA, Range: 50 mA - 6350 mA
ADCVBUS/PSYS()
R
8-bit digital output of input voltage,
VBUS: Full range: 0 V - 24.48 V, LSB 96 mV
8-bit digital output of system power
PSYS: Full range: 3.06 V, LSB: 12 mV
24h
25h
26h
ADCIBAT()
R
R
R
7-bit digital output of battery charge current,
7-bit digital output of battery discharge current
ICHG: Full range 8.128 A, LSB 64 mA
Go
Go
IDCHG: Full range: 32.512 A, LSB: 256 mA
ADCIINCMPIN()
ADCVSYSVBAT()
8-bit digital output of input current,
8-bit digital output of CMPIN voltage
POR State - IIN: Full range: 12.75 A, LSB 50 mA
CMPIN: Full range 3.06 V, LSB: 12 mV
8-bit digital output of system voltage,
8-bit digital output of battery voltage
VSYS: Full range: 2.88 V - 19.2 V, LSB: 64 mV
(1S-4S)
Go
VBAT: Full range : 2.88 V - 19.2 V, LSB 64 mV
(1S-4S)
30h
31h
32h
33h
34h
35h
36h
37h
3Bh
ChargeOption1()
ChargeOption2()
ChargeOption3()
ProchotOption0()
ProchotOption1()
ADCOption()
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Charge Option 1
Charge Option 2
Charge Option 3
PROCHOT Option 0
PROCHOT Option 1
ADC Option
Go
Go
Go
Go
Go
Go
Go
Go
Go
ChargeOption4()
Vmin Active Protection()
OTGVoltage()
Charge Option 4
Vmin Active Protection
12-bit OTG voltage setting
LSB 8 mV, Range: 3000 mV –24000 mV
3Ch
3Dh
3Eh
OTGCurrent()
InputVoltage()
VSYS_MIN()
R/W
R/W
R/W
7-bit OTG output current setting
LSB 50 mA, Range: 0 A –6350 mA
Go
Go
Go
8-bit input voltage setting
LSB 64 mV, Range: 3200 mV –19520 mV
8-Bit minimum system voltage setting
LSB: 100 mV, Range: 1000 mV - 23000 mV
Default: 1S-3.6V, 2S-6.6V, 3S-9.2V, 4S-12.3V,
3Fh
FEh
IIN_HOST()
R/W
R
7-bit Input current limit set by host
LSB: 50 mA, Range: 50 mA - 6350 mA
Go
Go
ManufacturerID()
Manufacturer ID - 0x0040H
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
LINKS
表9-9. Charger Command Summary (continued)
SMBus
ADDR
REGISTER NAME
TYPE
DESCRIPTION
FFh
DeviceID()
R
Device ID
Go
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
42
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.1 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
图9-8. ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
15
14
13
12
11
10
9
8
EN_LWPWR
WDTMR_ADJ
R/W
IIN_DPM_AUT OTG_ON_CH
EN_OOA
PWM_FREQ
DIS_STRGRV
O_DISABLE
R/W
RGOK
R/W
R/W
7
R/W
R/W
1
R/W
0
6
5
4
3
2
EN_CMP_LAT VSYS_UVP_E
EN_LEARN
IADPT_GAIN
IBAT_GAIN
EN_LDO
EN_IIN_DPM CHRG_INHIBIT
CH
NZ
R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-10. ChargeOption0 Register (SMBus address = 12h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
EN_LWPWR
R/W
1b
Low Power Mode Enable, under low power mode lowest quiescent current is
achieved when only battery exist. It is not recommended to enable low power
mode when adapter present.
0b: Disable Low Power Mode. Device in performance mode with battery only.
The PROCHOT, current/power monitor buffer and comparator follow register
setting.
1b: Enable Low Power Mode. Device in low power mode with battery only for
lowest quiescent current. The REGN is off. The PROCHOT, discharge current
monitor buffer, power monitor buffer and independent comparator are
disabled. ADC is not available in Low Power Mode. Independent comparator
and its low power mode PROCHOT profile can be enabled by setting
EN_PROCHOT_LPWR bit to 1b. <default at POR>
14-13
WDTMR_ADJ
R/W
11b
WATCHDOG Timer Adjust
Set maximum delay between consecutive SMBus write of charge voltage or
charge current command.
If device does not receive a write on the REG0x15() or the REG0x14() within
the watchdog time period, the charger will be suspended by setting the
REG0x14() to 0 mA .
After expiration, the timer will resume upon the write of REG0x14(),
REG0x15() or REG0x12[14:13].
00b: Disable Watchdog Timer
01b: Enabled, 5 sec
10b: Enabled, 88 sec
11b: Enable Watchdog Timer, 175 sec <default at POR>
12
IIN_DPM_AUTO_DISAB R/W
LE
0b
IIN_DPM Auto Disable
When CELL_BATPRESZ pin is LOW, the charger automatically disables the
IIN_DPM function by setting EN_IIN_DPM (REG0x12[1]) to 0. The host can
enable IIN_DPM function later by writing EN_IIN_DPM bit (REG0x12[1]) to 1.
0b: Disable this function. IIN_DPM is not disabled when CELL_BATPRESZ
goes LOW. <default at POR>
1b: Enable this function. IIN_DPM is disabled when CELL_BATPRESZ goes
LOW.
11
OTG_ON_CHRGOK
R/W
0b
Add OTG to CHRG_OK
Drive CHRG_OK to HIGH when the device is in OTG mode.
0b: Disable <default at POR>
1b: Enable
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-10. ChargeOption0 Register (SMBus address = 12h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
10
EN_OOA
R/W
1b
Out-of-Audio Enable
In both forward mode and OTG mode, switching frequency reduces with
diminishing load, under extreme light load condition the switching frequency
could be lower than 25kHz which is already in audible frequency range. By
configuring EN_OOA=1b, the minimum PFM burst frequency is clamped at
around 25kHz to avoid any audible noise.
0b: No limit of PFM burst frequency
1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise
<default at POR>
9
8
PWM_FREQ
R/W
R/W
1b
1b
Switching Frequency Selection: Recommend 1200kHz with 1uH, 800 kHz with
2.2 µH.
0b: 1200kHz
1b: 800kHz<default at POR>
DIS_STRGRV
Switching HS MOSFET turn on gate drive strength.
0b: Enable HS MOSFET strong turn on gate drive strength
1b: Disable HS MOSFET strong turn on gate drive strength <default at POR>
表9-11. ChargeOption0 Register (SMBus address = 12h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
EN_CMP_LATCH
R/W
0b
The EN_CMP_LATCH bit, will latch the independent comparator output after it
is triggered at low state. If enabled in PROCHOT profile REG34H[6]=1 ,
STAT_COMP bit REG0x21[6] keep 1b after triggered until read by host and
clear
0b: Independent comparator output will not latch when it is low<default at
POR>
1b: Independent comparator output will latch when it is low, host can clear
CMPOUT pin by toggling this REG0x12[7] bit.
6
5
VSYS_UVP_ENZ
EN_LEARN
R/W
R/W
0b
0b
To disable system under voltage protection.
0b: VSYS under voltage protection is enabled <default at POR>
1b: VSYS under voltage protection is disabled
LEARN mode allows the battery to discharge and converter to shut off while
the adapter is present . It calibrates the battery gas gauge over a complete
discharge/charge cycle. When the host determines the battery voltage is
below battery depletion threshold, the host switch the system back to adapter
input by writing this bit back to 0b.
0b: Disable LEARN Mode <default at POR>
1b: Enable LEARN Mode
4
3
IADPT_GAIN
IBAT_GAIN
R/W
R/W
0b
1b
IADPT Amplifier Ratio
The ratio of voltage on IADPT and voltage across ACP and ACN.
0b: 20× <default at POR>
1b: 40×
IBAT Amplifier Ratio
The ratio of voltage on IBAT and voltage across SRP and SRN
0b: 8×
1b: 16× <default at POR>
Copyright © 2023 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-11. ChargeOption0 Register (SMBus address = 12h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
2
EN_LDO
R/W
1b
LDO Mode Enable
When battery voltage is below minimum system voltage (REG0x3E()), the
charger is in pre-charge with LDO mode enabled.
0b: Disable LDO mode, BATFET fully ON. Precharge current is set by battery
pack internal resistor. The system is regulated by the MaxChargeVoltage
register.
1b: Enable LDO mode, Precharge current is set by the ChargeCurrent register
and clamped below 384 mA (2 cell –4 cell, 1cell VBAT<3.0V) or 2A (1cell
3.0V<VBAT<3.6V). The system is regulated by the VSYS_MIN register.
<default at POR>
1
0
EN_IIN_DPM
R/W
R/W
1b
0b
IIN_DPM Enable
Host writes this bit to enable IIN_DPM regulation loop. When the IIN_DPM is
disabled by the charger (refer to IIN_DPM_AUTO_DISABLE), this bit goes
LOW.
0b: IIN_DPM disabled
1b: IIN_DPM enabled <default at POR>
CHRG_INHIBIT
Charge Inhibit
When this bit is 0, battery charging will start with valid values in the
ChargeVoltage() register and the ChargeCurrent register.
0b: Enable Charge <default at POR>
1b: Inhibit Charge
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.2 ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
To set the charge current, write a 16-bit ChargeCurrent() command (REG0x14h()) using the data format listed in
图9-9, 表9-12, and 表9-13.
With 10-mΩ sense resistor, the charger provides charge current range of 0 A to 8.128 A, with a 64-mA step
resolution.
Upon POR, ChargeCurrent() is 0 A. Below scenarios will also reset Charge current to zero:
• CELL_BATPRESZ going LOW (battery removal).
• STAT_AC is not valid (adapter removal).
• RESET_REG is asserted and reset all registers.
• Charge voltage is written to be 0 V.
• Watch dog event is triggered.
Charge current is not reset in force converter latch off fault (REG0x20[2]), and ACOC/TSHUT/SYSOVP/ACOV/
VSYS_UVP/BATOVP/BATOC faults.
The SRP and SRN pins are used to sense voltage drop across RSR with default value of 10 mΩ. However, the
host can always set current sensing to 5 mΩ referring to 节 9.3.6. For a smaller sense resistor, a smaller sense
voltage is given, and a lower regulation accuracy; but at the benefit of lower conduction loss.
图9-9. ChargeCurrent Register With 10-mΩSense Resistor (SMBus address = 14h) [reset = 0000h]
15
14
13
12
11
10
9
8
Reserved
Charge Current, Charge Current, Charge Current, Charge Current, Charge Current,
bit 6
R/W
4
bit 5
R/W
3
bit 4
R/W
bit 3
R/W
1
bit 2
R/W
0
R/W
6
7
5
2
Charge Current, Charge Current,
Reserved
Reserved
bit 1
bit 0
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-12. Charge Current Register With 10-mΩSense Resistor (SMBus address = 14h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-13
Reserved
R/W
R/W
000b
0b
Not used. 1 = invalid write.
12
11
10
9
Charge Current, bit 6
0 = Adds 0 mA of charger current.
1 = Adds 4096 mA of charger current.
Charge Current, bit 5
Charge Current, bit 4
Charge Current, bit 3
Charge Current, bit 2
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0 = Adds 0 mA of charger current.
1 = Adds 2048 mA of charger current.
0 = Adds 0 mA of charger current.
1 = Adds 1024 mA of charger current.
0 = Adds 0 mA of charger current.
1 = Adds 512 mA of charger current.
8
0 = Adds 0 mA of charger current.
1 = Adds 256 mA of charger current.
Copyright © 2023 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-13. Charge Current Register With 10-mΩSense Resistor (SMBus address = 14h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
Charge Current, bit 1
R/W
0b
0 = Adds 0 mA of charger current.
1 = Adds 128 mA of charger current.
6
Charge Current, bit 0
Reserved
R/W
R/W
0b
0 = Adds 0 mA of charger current.
1 = Adds 64 mA of charger current.
5-0
000000b
Not used. Value Ignored.
9.6.2.1 Battery Pre-Charge Current Clamp
During pre-charge, BATFET works in linear mode (LDO mode) (default EN_LDO= 1b). For 2-4 cell battery, the
system is regulated at VSYS_MIN register and the pre-charge current is clamped at 384 mA. For 1 cell battery,
the pre-charge to fast charge threshold is 3 V, and the pre-charge current is clamped at 384 mA. However, the
BATFET stays in LDO mode operation untill battery voltage is above minimum system voltage (~3.6 V). During
battery voltage from 3 V to 3.6 V, the fast charge current is clamped at 2 A.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.3 ChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin
setting]
To set the output charge voltage, write a 16-bit ChargeVoltage register command (REG0x15()) using the data
format listed in 图9-10, 表9-14, and 表9-15. The charger provides charge voltage range from 1.024 V to 19.200
V, with 8-mV step resolution. Any write below 1.024 V or above19.200 V is ignored
Upon POR, REG0x15() is by default set as 4200 mV for 1 s, 8400 mV for 2 s, 12600 mV for 3 s or 16800 mV for
4 s. After CHRG_OK goes high, the charge will start when the host writes the charging current to REG0x14(),
the default charging voltage is used if REG0x15() is not programmed. If the battery is different from 4.2 V/cell,
the host has to write to REG0x15() before REG0x14() for correct battery voltage setting. Writing REG0x15() to 0
should keep REG0x15() value unchanged, and force REG0x14() to zero to disable charge.
The SRN pin senses the battery voltage for voltage regulation and should be connected as close to the battery
as possible.
图9-10. ChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin
setting]
15
14
13
12
11
10
9
8
Reserved
Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage,
bit 11
R/W
6
bit 10
R/W
5
bit 9
R/W
4
bit 8
R/W
3
bit 7
R/W
2
bit 6
R/W
bit 5
R/W
0
R/W
7
1
Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage,
Reserved
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-14. ChargeVoltage Register (SMBus address = 15h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
14
Reserved
R/W
R/W
0b
0b
Not used. 1 = invalid write.
Charge Voltage, bit 11
0 = Adds 0 mV of charger voltage.
1 = Adds 16384 mV of charger voltage.
13
12
11
10
9
Charge Voltage, bit 10
Charge Voltage, bit 9
Charge Voltage, bit 8
Charge Voltage, bit 7
Charge Voltage, bit 6
Charge Voltage, bit 5
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0 = Adds 0 mV of charger voltage.
1 = Adds 8192 mV of charger voltage
0 = Adds 0 mV of charger voltage.
1 = Adds 4096 mV of charger voltage.
0 = Adds 0 mV of charger voltage.
1 = Adds 2048 mV of charger voltage.
0 = Adds 0 mV of charger voltage.
1 = Adds 1024 mV of charger voltage.
0 = Adds 0 mV of charger voltage.
1 = Adds 512 mV of charger voltage.
8
0 = Adds 0 mV of charger voltage.
1 = Adds 256 mV of charger voltage.
表9-15. ChargeVoltage Register (SMBus address = 15h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
Charge Voltage, bit 4
R/W
0b
0 = Adds 0 mV of charger voltage.
1 = Adds 128 mV of charger voltage.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
48
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-15. ChargeVoltage Register (SMBus address = 15h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
6
Charge Voltage, bit 3
R/W
0b
0 = Adds 0 mV of charger voltage.
1 = Adds 64 mV of charger voltage.
5
Charge Voltage, bit 2
Charge Voltage, bit 1
Charge Voltage, bit 0
Reserved
R/W
R/W
R/W
R/W
0b
0 = Adds 0 mV of charger voltage.
1 = Adds 32 mV of charger voltage.
4
0b
0 = Adds 0 mV of charger voltage.
1 = Adds 16 mV of charger voltage.
3
0b
0 = Adds 0 mV of charger voltage.
1 = Adds 8 mV of charger voltage.
2-0
000b
Not used. Value Ignored.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.4 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
图9-11. ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
15
14
13
12
11
10
9
8
STAT_AC
ICO_DONE
IN_VAP
IN_VINDPM
IN_IIN_DPM
IN_FCHRG
IN_PCHRG
IN_OTG
R
R
R
R
4
R
3
R
2
R
1
R
0
7
6
5
Fault ACOV
Fault BATOC
Fault ACOC
FAULT
SYSOVP
Fault VSYS
_UVP
Fault
Force_Converte
r_Off
Fault_OTG
_OVP
Fault_OTG
_UVP
R
R
R
R/W
R/W
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-16. ChargerStatus Register (SMBus address = 20h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
STAT_AC
R
0b
Input source status. STAT_AC is valid as long as VBUS go within
3.5V ~26V range. It is different from CHRG_OK bit, When
CHRG_OK is valid, STAT_AC must be valid, but if STAT_AC is valid,
it is not necessary CHRG_OK is valid. There are Force converter off,
ACOC, TSHUT , SYSOVP, VSYS_UVP, BATOVP can pull low
CHRG_OK.
0b: Input not present
1b: Input is present
14
13
ICO_DONE
IN_VAP
R
R
0b
0b
After the ICO routine is successfully executed, the bit goes 1.
0b: ICO is not complete
1b: ICO is complete
0b: Charger is not operated in VAP mode
1b: Charger is operated in VAP mode
Digital status bit indicates VAP has enabled(1) or disabled(0). The
enable of VAP mode only follows the host command, which is not
blocked by any status of /PROCHOT. The exit of VAP mode also
follows the host command, except that any faults will exit VAP mode
automatically. STAT_EXIT_VAP (REG0x21[8]) becomes 1 which will
pull low /PROCHOT until host clear.
The host can enable VAP by setting OTG/VAP/FRS pin high and
0x32[5]=0, disable VAP by setting either OTG/VAP/FRS pin low or
0x32[5]=1. Any faults in VAP When IN_VAP bit goes 0->1, charger
should disable VINDPM, IIN_DPM, ICRIT, ILIM pin, disable
PP_ACOK if it is enabled, enable PP_VSYS if it is disabled. When
IN_VAP bit goes 1->0, charger should enable VINDPM, IIN_DPM,
ICRIT, ILIM pin function.
12
IN_VINDPM
R
0b
0b: Charger is not in VINDPM during forward mode, or voltage
regulation during OTG mode
1b: Charger is in VINDPM during forward mode, or voltage
regulation during OTG mode
11
10
IN_IIN_DPM
IN_FCHRG
R
R
0b
0b
0b: Charger is not in IIN_DPM during forward mode.
1b: Charger is not in IIN_DPM during forward mode.
0b: Charger is not in fast charge
1b: Charger is in fast charger
Copyright © 2023 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-16. ChargerStatus Register (SMBus address = 20h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
9
IN_PCHRG
R
0b
0b: Charger is not in pre-charge
1b: Charger is in pre-charge
8
IN_OTG
R
0b
0b: Charger is not in OTG
1b: Charge is in OTG
表9-17. ChargerStatus Register (SMBus address = 20h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
Fault ACOV
R
0b
The status are latched if triggered until a read from host.
0b: No fault
1b: ACOV
6
Fault BATOC
R
0b
The status is latched if triggered until a read from host. Fault
indicator for BATOC only during normal operation. However in PTM
mode when EN_BATOC=1b, this status bit is fault indicator for both
BATOVP and BATOC; when EN_BATOC=0b, this status bit is not
effective.
0b: No fault
1b: BATOC is triggered
5
4
Fault ACOC
R
0b
0b
The status is latched if triggered until a read from host.
0b: No fault
1b: ACOC
Fault SYSOVP
R/W
SYSOVP Status and Clear. SYSOVP fault is latched until a clear
from host by writing this bit to 0.
When the SYSOVP occurs, this bit is HIGH. During the SYSOVP, the
converter is disabled.
After the SYSOVP is removed, the user must write a 0 to this bit or
unplug the adapter to clear the SYSOVP condition to enable the
converter again.
0b: Not in SYSOVP <default at POR>
1b: In SYSOVP. When SYSOVP is removed, write 0 to clear the
SYSOVP latch.
3
2
Fault VSYS_UVP
R/W
0b
0b
VSYS_UVP fault status and clear. VSYS_UVP fault is latched until a
clear from host by writing this bit to 0.
0b: No fault <default at POR>
1b: When system voltage is lower than VSYS_UVP, then 7 times
restart tries are failed.
Fault Force_Converter_Off
R
The status is latched if triggered until a read from host.
0b: No fault
1b: Force converter off triggered (when FORCE_CONV_OFF
(REG0x30[3]=1b)
1
0
Fault_OTG_OVP
Fault_OTG_UVP
R
R
0b
0b
The status is latched if triggered until a read from host.
0b: No fault
1b: OTG OVP fault is triggered
The status is latched if triggered until a read from host.
0b: No fault
1b: OTG UVP fault is triggered
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.5 ProchotStatus Register (SMBus address = 21h) [reset = B800h]
All the status bits in REG0x21[15,10,6:0] will be cleared after host read.
图9-12. ProchotStatus Register (SMBus address = 21h) [reset = B800h]
15
14
13
12
11
10
9
8
Reserved
EN_PROCHOT
_EXT
PROCHOT_WIDTH
PROCHOT_CL
EAR
TSHUT
STAT_VAP_FAI STAT_EXIT_VA
L
R/W
1
P
R/W
0
R
7
R/W
6
R/W
R/W
R
5
4
3
2
STAT_VINDPM STAT_COMP
STAT_ICRIT
STAT_INOM
STAT_IDCHG1
STAT_VSYS
STAT_BAT_Re STAT_ADPT_R
moval
emoval
R/W
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-18. ProchotStatus Register (SMBus address = 21h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
14
Reserved
R
1b
0b
Reserved
EN_PROCHOT _EXT
R/W
PROCHOT Pulse Extension Enable. When pulse extension is
enabled, keep the PROCHOT pin voltage LOW until host writes
REG0x21[11] = 0.
0b: Disable pulse extension <default at POR>
1b: Enable pulse extension
13-12
PROCHOT _WIDTH
PROCHOT _CLEAR
R/W
R/W
11b
PROCHOT Pulse Width Minimum PROCHOT pulse width when
REG0x21[14] = 0
00b: 100 us
01b: 1 ms
10b: 5 ms
11b: 10 ms <default at POR>
11
1b
PROCHOT Pulse Clear.
Clear PROCHOT pulse when 0x21[14] = 1.
0b: Clear PROCHOT pulse and drive PROCHOT pin HIGH
1b: Idle <default at POR>
10
9
TSHUT
R
0b
0b
TSHUT trigger:
0b: TSHUT is not triggered
1b: TSHUT is triggered
STAT_VAP_FAIL
R/W
This status bit reports a failure to load VBUS 7 consecutive times
in VAP mode, which indicates the battery voltage might be not
high enough to enter VAP mode, or the VAP loading current
settings are too high.
0b: Not is VAP failure <default at POR>
1b: In VAP failure, the charger exits VAP mode, and latches off
until the host writes this bit to 0.
8
STAT_EXIT_VAP
R/W
0b
When the charger is operated in VAP mode, it can exit VAP by
either being disabled through host, or there are ACOV/ACOC/
SYSOVP/BATOVP/VSYS_UVP faults.
0b: PROCHOT_EXIT_VAP is not active <default at POR>
1b: PROCHOT_EXIT_VAP is active, PROCHOT pin is low until
host writes this status bit to 0.
Copyright © 2023 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
SMBus
表9-19. ProchotStatus Register (SMBus address = 21h) Field Descriptions
FIELD
TYPE
RESET
DESCRIPTION
BIT
7
STAT_VINDPM
R/W
0b
PROCHOT Profile VINDPM status bit
0b: Not triggered
1b: Triggered,PROCHOT pin is low until host writes this status bit
to 0 when PP_VINDPM = 1b
6
5
4
3
2
1
0
STAT_COMP
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
PROCHOT Profile CMPOUT status bit. The status is latched until
a read from host.
0b: Not triggered
1b: Triggered
STAT_ICRIT
PROCHOT Profile ICRIT status bit. The status is latched until a
read from host.
0b: Not triggered
1b: Triggered
STAT_INOM
PROCHOT Profile INOM status bit. The status is latched until a
read from host.
0b: Not triggered
1b: Triggered
STAT_IDCHG1
STAT_VSYS
PROCHOT Profile IDCHG1 status bit. The status is latched until a
read from host.
0b: Not triggered
1b: Triggered
PROCHOT Profile VSYS status bit. The status is latched until a
read from host.
0b: Not triggered
1b: Triggered
STAT_Battery_Removal
STAT_Adapter_Removal
PROCHOT Profile Battery Removal status bit. The status is
latched until a read from host.
0b: Not triggered
1b: Triggered
PROCHOT Profile Adapter Removal status bit. The status is
latched until a read from host.
0b: Not triggered
1b: Triggered
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.6 IIN_DPM Register With 10-mΩSense Resistor (SMBus address = 22h) [reset = 4100h]
IIN_DPM register reflects the actual input current limit programmed in the register, either from IIN_HOST register
or from ICO.
After ICO, the current limit used by DPM regulation may differ from the IIN_HOST register settings. The actual
DPM limit is reported in IIN_DPM register.
To read the nominal or typical input current limit:
• When using a 10-mΩsense resistor(RSNS_RAC=0b). There is 50mA offset at code 0. Note this offset is
only applied to code 0, not applied to other codes.
• When using a 5-mΩsense resistor(RSNS_RAC=1b). There is 100mA offset at code 0. Note this offset is
only applied to code 0, not applied to other codes.
To read the maximum input current limit, need to add 100mA/200mA offset based on above nominal input
current limit reading approach:
• When using a 10-mΩsense resistor(RSNS_RAC=0b). There is 150mA offset at code 0 and this 150mA
offset is only applied to code 0, 100mA offset should be added for all other non-zero codes.
• When using a 5-mΩsense resistor(RSNS_RAC=1b). There is 300mA offset at code 0 and this 300mA offset
is only applied to code 0, 200mA offset should be added for all other non-zero codes
图9-13. IIN_DPM Register With 10-mΩSense Resistor (SMBus address = 22h) [reset = 4100h]
15
14
13
12
11
10
9
8
Reserved
Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in
DPM, bit 6
DPM, bit 5
DPM, bit 4
DPM, bit 3
DPM, bit 2
DPM, bit 1
DPM, bit 0
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-20. IIN_DPM Register With 10-mΩSense Resistor (SMBus address = 22h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
14
Reserved
R
R
0b
0b
Not used. 1 = invalid write.
Input Current in DPM, bit 6
0 = Adds 0 mA of input current.
1 = Adds 3200 mA of input current.
13
12
11
10
9
Input Current in DPM, bit 5
Input Current in DPM, bit 4
Input Current in DPM, bit 3
Input Current in DPM, bit 2
Input Current in DPM, bit 1
Input Current in DPM, bit 0
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0 = Adds 0 mA of input current.
1 = Adds 1600 mA of input current.
0 = Adds 0 mA of input current.
1 = Adds 800mA of input current
0 = Adds 0 mA of input current.
1 = Adds 400 mA of input current.
0 = Adds 0 mA of input current.
1 = Adds 200 mA of input current.
0 = Adds 0 mA of input current.
1 = Adds 100 mA of input current.
8
0 = Adds 0 mA of input current.
1 = Adds 50 mA of input current.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
54
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-21. IIN_DPM Register With 10-mΩSense Resistor (SMBus address = 22h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-0
Reserved
R
00000000b
Not used. Value Ignored.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.7 ADCVBUS/PSYS Register (SMBus address = 23h)
• VBUS: Full range: 0 mV to 24480 mV, LSB: 96 mV
• PSYS: Full range: 3.06 V, LSB: 12 mV(ADC_FULLSCALE=1b)
• PSYS: Full range: 2.04 V, LSB: 8 mV(ADC_FULLSCALE=0b)
图9-14. ADCVBUS/PSYS Register (SMBus address = 23h)
15
R
7
14
R
6
13
R
5
12
R
4
11
R
3
10
R
2
9
R
1
8
R
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-22. ADCVBUS/PSYS Register (SMBus address = 23h) Field Descriptions
BIT
15-8
7-0
FIELD
TYPE
RESET
DESCRIPTION
R
R
8-bit Digital Output of Input Voltage
8-bit Digital Output of System Power
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
56
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.8 ADCIBAT Register (SMBus address = 24h)
• ICHG: Full range when using a 10-mΩsense resistor(RSNS_RSR=0b):8.128 A, LSB: 64 mA.
• ICHG: Full range when using a 5-mΩsense resistor(RSNS_RSR=1b):16.256A,LSB: 128mA.
• IDCHG: Full range when using a 10-mΩsense resistor(RSNS_RSR=0b):32.512 A, LSB: 256 mA. Note when
discharge current is higher than 32.512A, the ADC will report 32.512A
• IDCHG: Full range when using a 5-mΩsense resistor(RSNS_RSR=1b):65.024A,LSB: 512mA. Note when
discharge current is higher than 65.024A, the ADC will report 65.024A
图9-15. ADCIBAT Register (SMBus address = 24h)
15
Reserved
7
14
R
6
13
R
5
12
R
4
11
R
3
10
R
2
9
R
1
8
R
0
Reserved
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-23. ADCIBAT Register (SMBus address = 24h) Field Descriptions
BIT
15
FIELD
TYPE
RESET
DESCRIPTION
Reserved
R
R
R
R
Not used. Value ignored.
14-8
7
7-bit Digital Output of Battery Charge Current
Not used. Value ignored.
Reserved
6-0
7-bit Digital Output of Battery Discharge Current
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.9 ADCIINCMPIN Register (SMBus address = 25h)
• IIN Full range: When using a 10-mΩsense resistor(RSNS_RAC=0b): 12.75 A, LSB: 50 mA.
• IIN Full range: When using a 5-mΩsense resistor(RSNS_RAC=1b): 25.5A, LSB:100mA.
• CMPIN Full range: 3.06 V, LSB: 12 mV (ADC_FULLSCALE=1b)
• CMPIN Full range: 2.04 V, LSB: 8 mV (ADC_FULLSCALE=0b)
图9-16. ADCIINCMPIN Register (SMBus address = 25h)
15
R
7
14
R
6
13
R
5
12
R
4
11
R
3
10
R
2
9
R
1
8
R
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-24. ADCIINCMPIN Register (SMBus address = 25h)Field Descriptions
BIT
15-8
7-0
FIELD
TYPE
RESET
DESCRIPTION
R
R
8-bit Digital Output of Input Current
8-bit Digital Output of CMPIN voltage
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
58
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.10 ADCVSYSVBAT Register (SMBus address = 26h)
• VSYS: Full range: 2.88 V to 19.2 V, LSB: 64 mV (1S-4S)
• VBAT: Full range: 2.88 V to 19.2 V, LSB: 64 mV (1S-4S)
图9-17. ADCVSYSVBAT Register (SMBus address = 26h)
15
R
7
14
R
6
13
R
5
12
R
4
11
R
3
10
R
2
9
R
1
8
R
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-25. ADCVSYSVBAT Register (SMBus address = 26h) Field Descriptions
BIT
15-8
7-0
FIELD
TYPE
RESET
DESCRIPTION
R
R
8-bit Digital Output of System Voltage
8-bit Digital Output of Battery Voltage
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.11 ChargeOption1 Register (SMBus address = 30h) [reset = 3300h]
图9-18. ChargeOption1 Register (SMBus address = 30h) [reset = 3300h]
15
14
13
12
11
10
9
8
EN_IBAT
EN_PROCHOT
_LPWR
PSYS_CONFIG
RSNS_RAC
RSNS_RSR
PSYS_RATIO EN_FAST_5MO
HM
R/W
R/W
R/W
R/W
3
R/W
R/W
1
R/W
0
7
6
5
4
2
CMP_REF
CMP_POL
CMP_DEG
R/W
FORCE_CON
V_OFF
EN_PTM
EN_SHIP_DCH
G
AUTO_WAKEU
P_EN
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-26. ChargeOption1 Register (SMBus address = 30h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET DESCRIPTION
15
14
EN_IBAT
R/W
0b
IBAT Enable
Enable the IBAT output buffer. In low power mode (REG0x12[15] = 1), IBAT
buffer is always disabled regardless of this bit value.
0b Turn off IBAT buffer to minimize Iq <default at POR>
1b: Turn on IBAT buffer
EN_PROCHOT_LPWR
R/W
R/W
0b
Enable PROCHOT during battery only low power mode
With battery only, enable VSYS in PROCHOT with low power consumption. Do
not enable this function with adapter present. Refer to 节9.3.21.1 for more
details.
0b: Disable Independent Comparator low power PROCHOT <default at POR>
1b: Enable Independent Comparator low power PROCHOT
13-12 PSYS_CONFIG
11b
PSYS Enable and Definition Register
Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low
power mode (REG0x12[15] = 1), PSYS sensing and buffer are always disabled
regardless of this bit value.
00b: PSYS=PBUS+PBAT
01b: PSYS=PBUS
10b: Reserved
11b: Turn off PSYS buffer to minimize Iq<default at POR>
11
10
9
RSNS_RAC
RSNS_RSR
PSYS_RATIO
R/W
R/W
R/W
0b
0b
1b
Input sense resistor RAC
0b: 10 mΩ<default at POR>
1b: 5 mΩ
Charge sense resistor RSR
0b: 10 mΩ<default at POR>
1b: 5 mΩ
PSYS Gain
Ratio of PSYS output current vs total system power
0b: 0.25 µA/W
1b: 1 µA/W <default at POR>
Copyright © 2023 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-26. ChargeOption1 Register (SMBus address = 30h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET DESCRIPTION
1b
8
EN_FAST_5MOHM
R/W
Enable fast compensation to increase bandwidth under 5mΩRAC
(RSNS_RAC=1b) for input current up to 6.4A application (The fast
compensation will only work when IADPT pin is configured less than 160kΩ)
0b: Turn off bandwidth promotion under RSNS_RAC=1b
(Note when this bit configured as 0b, IIN_HOST DAC can be extended up to
10A, writing IIN_HOST value higher than 10A will be neglected, the ICHG
regulation loop will be slower to guarantee stability under 6.4A~10A input current
range)
1b: Turn on bandwidth promotion under RSNS_RAC=1b <default at POR>
(Note when this bit configured as 1b, IIN_HOST DAC is clamped at 6.4A, writing
IIN_HOST value higher than 6.4A will be neglected, the ICHG regulation loop
will be faster within 6.4A input current range)
表9-27. ChargeOption1 Register (SMBus address = 30h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET DESCRIPTION
7
CMP_REF
R/W
0b
0b
Independent Comparator internal Reference
0b: 2.3 V <default at POR>
1b: 1.2 V
6
CMP_POL
CMP_DEG
R/W
R/W
Independent Comparator output Polarity
0b: When CMPIN is above internal threshold, CMPOUT is LOW (internal
hysteresis) <default at POR>
1b: When CMPIN is below internal threshold, CMPOUT is LOW (external
hysteresis)
5-4
00b
Independent comparator deglitch time, only applied to the falling edge of
CMPOUT (HIGH →LOW).
00b: Independent comparator is enabled with output deglitch time 5 µs <default
at POR>
01b: Independent comparator is enabled with output deglitch time of 2 ms
10b: Independent comparator is enabled with output deglitch time of 20 ms
11b: Independent comparator is enabled with output deglitch time of 5 sec
3
FORCE_CONV_OFF
R/W
0b
Force Converter Off function
When independent comparator triggers, (CMPOUT pin pulled down) charger
latches off into HIZ mode, at the same time, CHRG_OK signal goes LOW to
notify the system. Charge current is also set to zero internally, but charge current
register setting keeps the same. To get out of HIZ, firstly the CMPOUT should be
released to high and secondly FORCE_CONV_OFF bit should be cleared(=0b).
0b: Disable this function <default at POR>
1b: Enable this function
2
EN_PTM
R/W
0b
PTM enable register bit, it will automatically reset to zero
0b: disable PTM. <default at POR>
1b: enable PTM.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-27. ChargeOption1 Register (SMBus address = 30h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET DESCRIPTION
0b
1
EN_SHIP_DCHG
R/W
Discharge SRN for Shipping Mode. Used to discharge VBAT pin capacitor
voltage which is necessary for battery gauge device shipping mode.
When this bit is 1, discharge SRN pin down in 140 ms with around 10mA current
flowing through both SRN and SRP pin, totally 20mA. When 140 ms is over, this
bit is reset to 0 automatically. If this bit is written to 0b by host before 140ms
expires, VSYS should stop discharging immediately. After SRN is discharged to
0V the discharge current will shut off automatically in order to get rid of any
negative voltage on SRN pin. Note if after 140ms SRN voltage is still not low
enough for battery gauge device entering ship mode, the host may need to write
this bit to 1b again to start a new 140ms discharge cycle.
0b: Disable shipping mode <default at POR>
1b: Enable shipping mode
0
AUTO_WAKEUP_EN
R/W
0b
Auto Wakeup Enable
When this bit is HIGH, if the battery is below VSYS_MIN , the device should
automatically enable 128 mA charging current for 30 mins. When the battery is
charged up above minimum system voltage, charge will terminate and the bit is
reset to LOW. The charger will also exit auto wake up if host write a new charge
current value to charge current register Reg0x14().
0b: Disable <default at POR>
1b: Enable
Copyright © 2023 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.12 ChargeOption2 Register (SMBus address = 31h) [reset = 00B7]
图9-19. ChargeOption2 Register (SMBus address = 31h) [reset = 00B7]
15
14
13
12
11
10
9
8
PKPWR_TOVLD_DEG
R/W
EN_PKPWR_II EN_PKPWR_V PKPWR_OVLD PKPWR_RELA
PKPWR_TMAX[1:0]
R/W
N_DPM
R/W
SYS
R/W
_STAT
R/W
X_STAT
R/W
7
6
5
4
3
2
1
0
EN_EXTILIM
EN_ICHG_IDC
HG
Q2_OCP
ACX_OCP
EN_ACOC
ACOC_VTH
EN_BATOC
BATOC_VTH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-28. ChargeOption2 Register (SMBus address = 31h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-14 PKPWR_TOVLD_DEG
R/W
00b
Input Overload time in Peak Power Mode
00b: 1 ms <default at POR>
01b: 2 ms
10b: 5 ms
11b: 10 ms
13
12
EN_PKPWR_IIN_DPM
R/W
R/W
0b
0b
Enable Peak Power Mode triggered by input current overshoot
If REG0x31[13:12] are 00b, peak power mode is disabled. Upon adapter
removal, the bits are reset to 00b.
0b: Disable peak power mode triggered by input current overshoot
<default at POR>
1b: Enable peak power mode triggered by input current overshoot.
EN_PKPWR_VSYS
Enable Peak Power Mode triggered by system voltage under-shoot
If REG0x31[13:12] are 00b, peak power mode is disabled. Upon adapter
removal, the bits are reset to 00b.
0b: Disable peak power mode triggered by system voltage under-shoot
<default at POR>
1b: Enable peak power mode triggered by system voltage under-shoot.
11
10
STAT_PKPWR_OVLD
STAT_PKPWR_RELAX
PKPWR_TMAX[1:0]
R/W
R/W
R/W
0b
Indicator that the device is in overloading cycle. Write 0 to get out of
overloading cycle.
0b: Not in peak power mode. <default at POR>
1b: In peak power mode.
0b
Indicator that the device is in relaxation cycle. Write 0 to get out of
relaxation cycle.
0b: Not in relaxation cycle. <default at POR>
1b: In relaxation mode.
9-8
00b
Peak power mode overload and relax cycle time.
00b: 20 ms <default at POR>
01b: 40 ms
10b: 80 ms
11b: 1 sec
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-29. ChargeOption2 Register (SMBus address = 31h) Field Descriptions
SMBus
FIELD
BIT
TYPE
RESET
DESCRIPTION
7
EN_EXTILIM
R/W
1b
Enable ILIM_HIZ pin to set input current limit
0b: Input current limit is set by IIN_DPM register..
1b: Input current limit is set by the lower value of ILIM_HIZ pin and
IIN_DPM register.. <default at POR>
6
5
EN_ICHG_IDCHG
Q2_OCP
R/W
R/W
0b
1b
0b: IBAT pin as discharge current. <default at POR>
1b: IBAT pin as charge current.
Q2 OCP threshold by sensing Q2 VDS
0b: 210 mV
1b: 150 mV <default at POR>
4
ACX_OCP
R/W
1b
Fixed Input current OCP threshold by sensing ACP-ACN, converter is
disabled immediately when triggered non latch protection resume
switching automatically after ACX comparator release.
0b: 280 mV(RSNS_RAC=0b)/200mV(RSNS_RAC=1b)
1b: 150 mV(RSNS_RAC=0b)/100mV(RSNS_RAC=1b) <default at
POR>
3
EN_ACOC
R/W
0b
ACOC Enable
Configurable Input overcurrent (ACOC) protection by sensing the
voltage across ACP and ACN. Upon ACOC (after 250-μs blank-out
time), converter is disabled. Non latch fault, after 250ms falling edge de-
glitch time converter starts switching automatically.
0b: Disable ACOC <default at POR>
1b: ACOC threshold 133% or 200% ILIM2
2
1
ACOC_VTH
EN_BATOC
R/W
R/W
1b
1b
ACOC Limit
Set MOSFET OCP threshold as percentage of IIN_DPM with current
sensed from RAC.
0b: 133% of ILIM2
1b: 200% of ILIM2 <default at POR>
BATOC
Battery discharge overcurrent (BATOC) protection by sensing the
voltage across SRN and SRP. Upon BATOC, converter is disabled.
0b: Disable BATOC
1b: Enable BATOC threshold 133% or 200% PROCHOT IDCHG_TH2
<default at POR>
0
BATOC_VTH
R/W
1b
Set battery discharge overcurrent threshold as percentage of
PROCHOT battery discharge current limit. Note when SRN and SRP
common voltage is low for 1S application, the BATOC threshold could
be derating.
0b: 133% of PROCHOT IDCHG_TH2
1b: 200% of PROCHOT IDCHG _TH2<default at POR>
Copyright © 2023 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.13 ChargeOption3 Register (SMBus address = 32h) [reset = 0434h]
图9-20. ChargeOption3 Register (SMBus address = 32h) [reset = 0434h]
15
14
13
12
11
10
9
8
EN_HIZ
RESET_REG RESET_VINDP
M
EN_OTG
EN_ICO_MOD EN_PORT_CT EN_VSYS_MIN EN_OTG_BIGC
E
RL
_SOFT_SR
AP
R/W
7
R/W
6
R/W
5
R/W
4
R/W
R/W
R/W
R/W
3
2
1
0
BATFET_ENZ EN_VBUS_VAP OTG_VAP_MO
DE
IL_AVG
R/W
CMP_EN
BATFETOFF_H PSYS_OTG_ID
IZ
CHG
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-30. ChargeOption3 Register (SMBus address = 32h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
14
13
EN_HIZ
R/W
0b
Device HIZ Mode Enable
When the charger is in HIZ mode, the device draws minimal quiescent
current. With VBUS above UVLO. REGN LDO stays on, and system
powers from battery.
0b: Device not in HIZ mode <default at POR>
1b: Device in HIZ mode
RESET_REG
R/W
R/W
0b
0b
Reset Registers
All the registers are reset to POR default setting except the VINDPM
register.
0b: Idle <default at POR>
1b: Reset all the registers to default values. After reset, this bit goes back
to 0.
RESET_VINDPM
Reset VINDPM Threshold
0b: Idle
1b: Converter is disabled to measure VINDPM threshold. After VINDPM
measurement is done, this bit goes back to 0 and converter starts. (When
battery voltage is lower than VSYS_MIN this function is not
recommended due to potential risk to crash system during VINDPM
measurement .)
12
EN_OTG
R/W
0b
OTG Mode Enable
Enable device in OTG mode when OTG/VAP/FRS pin is HIGH.
0b: Disable OTG <default at POR>
1b: Enable OTG mode to supply VBUS from battery.
11
10
9
EN_ICO_MODE
R/W
R/W
R/W
0b
1b
0b
Enable ICO Algorithm
0b: Disable ICO algorithm. <default at POR>
1b: Enable ICO algorithm.
EN_PORT_CTRL
Enable BATFET control
0b: Disable BATFET control pin by HIZ BATDRV pin
1b: Enable BATFET control pin by activate BATDRV pin
EN_VSYS_MIN_SOFT_SR
Enable VSYS_MIN soft slew rate transition
0b: Disable VSYS_MIN soft slew rate transition <default at POR>
1b:Enable VSYS_MIN soft slew rate transition (1LSB/8us=12.5mV/us)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-30. ChargeOption3 Register (SMBus address = 32h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
8
EN_OTG_BIGCAP
R/W
0b
Enable OTG compensation for VBUS effective capacitance larger than
33uF
0b: Disable OTG large VBUS capacitance compensation(Recommended
for VBUS effective capacitance smaller than 33uF) <default at POR>
1b: Enable OTG large VBUS capacitance compensation(Recommended
for VBUS effective capacitance larger than 33uF)
表9-31. ChargeOption3 Register (SMBus address = 32h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
BATFET_ENZ
R/W
0b
Turn off BATFET under battery only mode. If charger is not in battery only
mode this bit is not allowed to be written to 1. Under battery only OTG
mode, this bit is forced to be 0b.
0b: Not force turn off BATFET <default at POR>
1b: Force turn off BATFET
6
5
EN_VBUS_VAP
R/W
R/W
0b
1b
Enable the VBUS VAP for VAP operation mode 2&3
0b: Disabled <default at POR>
1b: Enabled
OTG_VAP_MODE
The selection of the external OTG/VAP/FRS pin control. Don't
recommend to change pin control after OTG/VAP/FRS pin is pulled high.
0b: the external OTG/VAP/FRS pin controls the EN/DIS VAP mode
1b: the external OTG/VAP/FRS pin controls the EN/DIS OTG mode
<default at POR>
4-3
IL_AVG
R/W
10b
Converter inductor average current clamp. It is recommended to choose
the smallest option which is higher than maximum possible converter
average inductor current.
00b: 6A
01b: 10A
10b: 15A <default at POR>
11b: Disabled
2
1
0
CMP_EN
R/W
R/W
R/W
1b
0b
0b
Enable Independent Comparator with effective low.
0b: Disabled
1b: Enabled <default at POR>
BATFETOFF_HIZ
PSYS_OTG_IDCHG
Control BATFET on/off during charger HIZ mode.
0b: BATFET on during charger HIZ mode <default at POR>
1b: BATFET off during charger HIZ mode
PSYS function during OTG mode.
0b: PSYS as battery discharge power minus OTG output power <default
at POR>
1b: PSYS as battery discharge power only
Copyright © 2023 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.14 ProchotOption0 Register (SMBus address = 33h) [reset = 4A81h(2S~) 4A09(1S)]
To set VSYS_TH1 threshold to trigger discharging VBUS in VAP mode, write a 6-bit Vmin Active Protection
register command (REG0x33<7:2>()) using the data format listed in 图 9-21, 表 9-32, and 表 9-33. The charger
Measure on VSYS with fixed 5-µs deglitch time. Trigger when SYS pin voltage is below the thresholds. The
threshold range from 3.2V(000000b) to 9.5V(111111b) for 2s~ and 3.2V(000000b) to 3.9V(000111b)for 1S, with
100-mV step resolution. There is a fixed DC offset which is 3.2V. Under 1S application writing beyond 3.9V will
be ignored. For example 000111b and xxx111b result in same VSYS_TH1 setting 3.9V. Upon POR, the
VSYS_TH1 threshold to trigger VBUS discharge in VAP mode is 3.4V(000010b) for 1S and 6.400V(100000b) for
2s~
图9-21. ProchotOption0 Register (SMBus address = 33h) [reset = 4A81h(2S~) 4A09(1S)]
15
14
13
12
11
10
9
8
ILIM2_VTH
ICRIT_DEG
R/W
PROCHOT_VI
NDPM_80_90
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
0
2
1
VSYS_TH1
INOM_DEG LOWER_PRO
CHOT_VINDP
M
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-32. ProchotOption0 Register (SMBus address = 33h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-11 ILIM2_VTH
R/W
01001b
ILIM2 Threshold
5 bits, percentage of IIN_DPM in 0x22H. Measure current between ACP and
ACN.
Trigger when the current is above this threshold:
00001b - 11001b: 110% - 230%, step 5%
11010b - 11110b: 250% - 450%, step 50%
11111b: Out of Range (Ignored)
Default 150%, or 01001
10-9
ICRIT_DEG
R/W
01b
ICRIT Deglitch time
ICRIT threshold is set to be 110% ofILIM2
.
Typical ICRIT deglitch time to trigger PROCHOT.
00b: 15 µs
01b: 100 µs <default at POR>
10b: 400 µs
11b: 800 µs
8
PROCHOT_VINDPM_ R/W
80_90
0b
Lower threshold of the PROCHOT_VINDPM comparator
When REG0x33[0]=1, the threshold of the PROCHOT_VINDPM comparator is
determined by this bit setting.
0b: 83% of VinDPM threshold <default at POR>.
1b: 91% of VinDPM threshold
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-33. ProchotOption0 Register (SMBus address = 33h) Field Descriptions
SMBus
FIELD
BIT
TYPE
RESET
DESCRIPTION
7-2
VSYS_TH1
R/W
100000b( VSYS Threshold to trigger discharging VBUS in VAP mode.
2S~) Measure on VSYS with fixed 5-µs deglitch time. Trigger when SYS pin voltage is
000010b( below the thresholds. There is a fixed DC offset which is 3.2V.
1S)
2S - battery(Default: 6.4V)
000000b- 111111b: 3.2V - 9.5V with 100mV step size.
1S battery(Default: 3.4V)
XXX000b - XXX111b: 3.2 V - 3.9V with 100mV step size.
1
0
INOM_DEG
R/W
0b
INOM Deglitch Time
INOM is always 10% above IIN_DPM register setting. Measure current between
ACP and ACN.
Trigger when the current is above this threshold.
0b: 1 ms(max) <default at POR>
1b: 60 ms(max)
LOWER_PROCHOT_ R/W
VINDPM
1b
Enable the lower threshold of the PROCHOT_VINDPM comparator
0b: the threshold of the PROCHOT_VINDPM comparator follows the same
VINDPM REG0x3D() setting.
1b: the threshold of the PROCHOT_VINDPM comparator is lower and determined
by PROCHOT_VINDPM_80_90 bit setting. <default at POR>
Copyright © 2023 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.15 ProchotOption1 Register (SMBus address = 34h) [reset = 41A0h]
图9-22. ProchotOption1 Register (SMBus address = 34h) [reset = 41A0h]
15
14
13
12
11
10
9
8
IDCHG_TH1
IDCHG_DEG1
R/W
R/W
R/W
5
R/W
R/W
R/W
R/W
R/W
7
6
4
3
2
1
0
PP_VINDPM
R/W
PP_COMP
R/W
PP_ICRIT
R/W
PP_INOM
R/W
PP_IDCHG1
R/W
PP_VSYS
R/W
PP_BATPRES
R/W
PP_ACOK
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
When the REG0x34h[7:0] are set to be disabled, the PROCHOT event associated with that bit will not be
reported in the PROCHOT status register REG0x21h[7:0] any more, and the PROCHOT pin will not be pulled
low any more if the event happens.
表9-34. ProchotOption1 Register (SMBus address = 34h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET DESCRIPTION
15-10 IDCHG_TH1
R/W
010000b
IDCHG level 1 Threshold
6 bit, range, range 0 A to 32256 mA, step 512 mA.
Measure current between SRN and SRP.
Trigger when the discharge current is above the threshold.
If the value is programmed to 000000b PROCHOT is always triggered.
Default: 8192 mA or 010000b
9-8
IDCHG_DEG1
R/W
00b
IDCHG level 1 Deglitch Time
00b: 78ms
01b: 1.25s<default at POR>
10b: 5s
11b: 20s
表9-35. ProchotOption1 Register (SMBus address = 34h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET DESCRIPTION
7
PP_VINDPM
R/W
1b
VINDPM PROCHOT Profile
When all the REG0x34[7:0] bits are 0, PROCHOT function is disabled.
0b: disable
1b: enable<default at POR>
6
PP_COMP
R/W
0b
Independent comparator PROCHOT Profile
When not in low power mode(Battery only), use this bit to control independent
comparator PROCHOT profiles.
When in low power mode(Battery only), this bit will lose controllability to
independent comparator PROCHOT profiles. Need to use
EN_PROCHOT_LPWR to enable independent comparator and its PROCHOT
profile.
0b: disable <default at POR>
1b: enable
5
PP_ICRIT
R/W
1b
ICRIT PROCHOT Profile
0b: disable
1b: enable <default at POR>
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-35. ProchotOption1 Register (SMBus address = 34h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET DESCRIPTION
4
3
2
1
PP_INOM
R/W
0b
0b
0b
0b
INOM PROCHOT Profile
0b: disable <default at POR>
1b: enable
PP_IDCHG1
PP_VSYS
R/W
R/W
R/W
IDCHG1 PROCHOT Profile
0b: disable <default at POR>
1b: enable
VSYS PROCHOT Profile
0b: disable <default at POR>
1b: enable
PP_BATPRES
Battery removal PROCHOT Profile
0b: disable <default at POR>
1b: enable (one-shot falling edge triggered)
If BATPRES is enabled in PROCHOT after the battery is removed, it will
immediately send out one-shot PROCHOT pulse.
0
PP_ACOK
R/W
0b
Adapter removal PROCHOT Profile
0b: disable <default at POR>
1b: enable
ChargeOption0[15] = 0 to assert PROCHOT pulse after adapter removal.
If PP_ACOK is enabled in PROCHOT after the adapter is removed, it will be
pulled low.
Copyright © 2023 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.16 ADCOption Register (SMBus address = 35h) [reset = 2000h]
图9-23. ADCOption Register (SMBus address = 35h) [reset = 2000h]
15
14
13
12
11
10
9
8
ADC_CONV
ADC_START ADC_FULLSCA PTM_EXIT_LIG
Reserved
LE
HT_LOAD
R/W
R/W
7
R/W
6
R/W
R/W
3
R/W
2
R/W
1
R/W
0
5
4
EN_ADC_CMPI EN_ADC_VBU EN_ADC_PSY
EN_ADC_IIN EN_ADC_IDCH EN_ADC_ICHG EN_ADC_VSY EN_ADC_VBAT
N
S
S
G
S
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC
is disabled in low power mode. Before enabling ADC, low power mode should be disabled first.
表9-36. ADCOption Register (SMBus address = 35h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
ADC_CONV
R/W
0b
Typical each ADC channel conversion time is 25 ms maximum. Total ADC
conversion time is the product of 25ms and enabled channel counts.
0b: One-shot update. Do one set of conversion updates to registers
REG0x23(), REG0x24(), REG0x25(), and REG0x26() after ADC_START =
1.
1b: Continuous update. Do a set of conversion updates to registers
REG0x23(), REG0x24(), REG0x25(), and REG0x26() every 1 sec.
14
13
ADC_START
R/W
R/W
0b
1b
0b: No ADC conversion
1b: Start ADC conversion. After the one-shot update is complete, this bit
automatically resets to zero
ADC_FULLSCALE
ADC input voltage range adjustment for PSYS and CMPIN ADC Channels.
2.04V full scale holds 8mV/LSB resolution and 3.06V full scale holds
12mV/LSB resolution
0b: 2.04 V
1b: 3.06 V <default at POR>(Not accurate for REGN<6V application (VBUS
& VSYS< 6V)
)
12
PTM_EXIT_LIGHT_LOAD R/W
0b
PTM Mode Auto Exit Enable
When this bit is HIGH, under PTM mode operation when input current is
lower than 150mA(10mΩinput sensing resistor)/300mA(5mΩinput sensing
resistor) for more than 500us, charger should temporary exit PTM mode and
return to buck-boost mode operation. When input current increase back to
be higher than 200mA(10mΩinput sensing resistor)/400mA(5mΩinput
sensing resistor) for more than 500us, the charger should automatically
return to PTM operation.
0b: Disable <default at POR>
1b: Enable
11-8
Reserved
R/W
0000b
Reserved
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-37. ADCOption Register (SMBus address = 35h) Field Descriptions
SMBus
FIELD
BIT
TYPE
RESET
DESCRIPTION
7
6
5
4
3
2
1
0
EN_ADC_CMPIN
R/W
0b
0b: Disable <default at POR>
1b: Enable
EN_ADC_VBUS
EN_ADC_PSYS
EN_ADC_IIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
0b: Disable <default at POR>
1b: Enable
0b: Disable <default at POR>
1b: Enable
0b: Disable <default at POR>
1b: Enable
EN_ADC_IDCHG
EN_ADC_ICHG
EN_ADC_VSYS
EN_ADC_VBAT
0b: Disable <default at POR>
1b: Enable
0b: Disable <default at POR>
1b: Enable
0b: Disable <default at POR>
1b: Enable
0b: Disable <default at POR>
1b: Enable
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
72
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.17 ChargeOption4 Register (SMBus address = 36h) [reset = 0048h]
图9-24. ChargeOption4 Register (SMBus address = 36h) [reset = 0048h]
15
7
14
13
12
11
10
9
8
VSYS_UVP
EN_Dither
R/W
VSYS_UVP_N PP_VBUS_VAP STAT_VBUS_V
O_HICCUP
AP
R/W
6
R/W
R/W
R
5
4
3
2
1
0
STAT_PTM
R
IDCHG_DEG2
R/W
IDCHG_TH2
R/W
PP_IDCHG2
R/W
STAT_IDCHG2
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-38. ChargeOption4 Register (SMBus address = 36h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-13 VSYS_UVP
R/W
000b
VSYS Under Voltage Lock Out After UVP is triggered the charger enters
hiccup mode, and then the charger is latched off if the restart fails 7 times
in 90s The hiccup mode during the UVP can be disabled by setting
0x37[10]=1.
VSYS_UVP
000b
1s~ 4s
VSYS_UVP
100b
1s~ 4s
5.6V
2.4V(Default)
3.2V
4.0V
4.8V
6.4V
7.2V
8.0V
001b
010b
011b
101b
110b
111b
12-11 EN_DITHER
R/W
00b
Frequency Dither configuration
00b: Disable Dithering<default at POR>
01b: Dither 1X (±2% Fs dithering range)
10b: Dither 2X (±4% Fs dithering range)
11b: Dither 3X (±6% Fs dithering range)
10
9
VSYS_UVP_NO_HICCUP
R/W
R/W
R
0b
0b
0b
Disable VSYS_UVP Hiccup mode operation:
0b: Enable VSYS_UVP Hiccup mode <default at POR>
1b: Disable VSYS_UVP Hiccup mode
PP_VBUS_VAP
VBUS_VAP PROCHOT Profile
0b: disable <default at POR>
0b: enable
8
STAT_VBUS_VAP
PROCHOT profile VBUS_VAP status bit. The status is latched until a read
from host.
0b: Not triggered <default at POR>
1b: Triggered
表9-39. ChargeOption4 Register (SMBus address = 36h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-6
IDCHG_DEG2
R/W
01b
Battery discharge current limit 2 deglitch time(minimum value)
00b: 100us
01b: 1.6ms<default at POR>
10b: 6ms
11b: 12ms
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-39. ChargeOption4 Register (SMBus address = 36h) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
5-3
IDCHG_TH2
R/W
001b
Battery discharge current limit2 based on percentage of IDCHG_TH1.
Note IDCHG_TH2 setting higher than 32256mA should lose accuracy
derating between target value and 32256mA. (Recommend not to set
higher than 20A for 1S OTG boost operation)
000b: 125% IDCHG_TH1
001b: 150% IDCHG_TH1<default at POR>
010b: 175% IDCHG_TH1
011b: 200% IDCHG_TH1
100b: 250% IDCHG_TH1
101b: 300% IDCHG_TH1
110b: 350% IDCHG_TH1
111b: 400% IDCHG_TH1
2
1
0
PP_IDCHG2
STAT_IDCHG2
STAT_PTM
R/W
R
0b
0b
0b
IDCHG2 PROCHOT Profile
0b: disable <default at POR>
1b: enable
The status is latched until a read from host.
0b: Not triggered<default at POR>
1b: Triggered
R
PTM operation status bit monitor
0b: Not in PTM Operation<default at POR>
1b: In PTM Operation
Copyright © 2023 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.18 Vmin Active Protection Register (SMBus address = 37h) [reset = 006Ch(2s~4s)/0004h(1s)]
To set the VAP VBUS PROCHOT trigger threshold, write a 7-bit Vmin Active Protection register command
(REG0x[15:9])) using the data format listed in 图 9-25 and 表 9-40. The charger provides VAP mode VBUS
PROCHOT trigger threshold range from 3.2V(0000000b) to 15.9 V(1111111b), with 100-mV step resolution.
There is a fixed offset of 3.2V. Upon POR, the VBUS PROCHOT trigger threshold is 3.2 V(0000000b).
To set VSYS_TH2 Threshold to assert STAT_VSYS, write a 6-bit Vmin Active Protection register command
(REG0x[7:2])) using the data format listed in 图9-25 and 表9-41. The charger Measure on VSYS with fixed 5-µs
deglitch time. Trigger when SYS pin voltage is below the thresholds. The threshold range from 3.2V(000000b) to
9.5V(111111b) for 2s~ and 3.2V(000000b) to 3.9V(000111b)for 1S, with 100-mV step resolution. There is a fixed
DC offset which is 3.2V. Under 1S application writing beyond 3.9V will be ignored. For example xxx111b and
000111b result in same VSYS_TH2 setting 3.9V. Upon POR, the VSYS PROCHOT trigger threshold is
3.2V(000000b) for 1S and 5.9V(011011b) for 2s~ .
图9-25. Vmin Active Protection Register (SMBus address = 37h) [reset = 0070h/0004h]
15
14
13
12
11
10
9
8
VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_T VBUS_VAP_TH VBUS_VAP_TH
Reserved
Bit6
7
Bit5
Bit4
Bit3
H Bit2
Bit1
Bit0
R/W
R/W
6
5
4
3
2
1
0
VSYS_TH2 Bit6 VSYS_TH2 Bit5 VSYS_TH2 Bit4 VSYS_TH2 Bit3 VSYS_TH2
Bit2
VSYS_TH2 Bit1 EN_TH2_FOLL
OW_TH1
EN_FRS
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-40. Vmin Active Protection Register (SMBus address = 37h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
14
13
VBUS_VAP_TH, Bit6
R/W
0b
0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
1 = Adds 6400 mV of VAP Mode VBUS PROCHOT trigger voltage
threshold
VBUS_VAP_TH, Bit5
VBUS_VAP_TH, Bit4
R/W
R/W
0b
0b
0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
1 = Adds 3200 mV of VAP Mode VBUS PROCHOT trigger voltage
threshold
0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
1 = Adds 1600 mV of VAP Mode VBUS PROCHOT trigger voltage
threshold
12
11
10
9
VBUS_VAP_TH, Bit3
VBUS_VAP_TH, Bit2
VBUS_VAP_TH, Bit1
VBUS_VAP_TH, Bit0
Reserve
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
1 = Adds 800 mV of VAP mode VBUS PROCHOT trigger voltage threshold
0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold
1 = Adds 400 mV of VAP mode VBUS PROCHOT trigger voltage threshold
0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold
1 = Adds 200 mV of VAP mode VBUS PROCHOT trigger voltage threshold
0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold
1 = Adds 100 mV of VAP mode VBUS PROCHOT trigger voltage threshold
8
Reserve
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
75
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-41. Vmin Active Protection Register (SMBus address = 37h) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
6
5
4
3
2
1
VSYS_TH2, Bit5
R/W
0b
0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1 = Adds 3200 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
VSYS_TH2, Bit4
VSYS_TH2, Bit3
VSYS_TH2, Bit2
VSYS_TH2, Bit1
VSYS_TH2, Bit0
R/W
R/W
R/W
R/W
R/W
1b(2S~) 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
0b(1S)
1 = Adds 1600 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
1b(2S~) 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
0b(1S)
1 = Adds 800 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
0b
0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1 = Adds 400 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
0b(1S)
1b(2S~)
0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1 = Adds 200 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
1b
0b
0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1 = Adds 100 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
EN_VSYSTH2_FOLLOW_VS R/W
YSTH1
Enable internal VSYS_TH2 follow VSYS_TH1 setting neglecting register
REG37[7:2] setting
0b: disable <default at POR>
1b: enable
0
EN_FRS
R/W
0b
Fast Role Swap feature enable (note not recommend to change EN_FRS
during OTG operation, the FRS bit from 0 to 1 change will disable power
stage for about 50us (Fs=800kHz). HIZ mode holds higher priority, If
EN_HIZ=1b, this EN_FRS bit should be forced to 0b.
0b: disable <default at POR>
1b: enable
Copyright © 2023 Texas Instruments Incorporated
76
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.19 OTGVoltage Register (SMBus address = 3Bh) [reset = 09C4h]
To set the OTG output voltage limit, write to REG0x3B() using the data format listed in 图 9-26, 表 9-42, and 表
9-43.
The DAC is clamped in digital core at minimal 3V and maximum 24.0V during normal OTG operation. Any
register writing lower than the minimal or higher than the maximum will be ignored.
图9-26. OTGVoltage Register (SMBus address = 3Bh) [reset = 09C4h]
15
14
13
12
11
10
9
8
Reserved
R/W
OTG Voltage,
bit 11
OTG Voltage,
bit 10
OTG Voltage,
bit 9
OTG Voltage,
bit 8
OTG Voltage,
bit 7
OTG Voltage,
bit 6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
7
6
OTG Voltage,
bit 5
OTG Voltage,
bit 4
OTG Voltage,
bit 3
OTG Voltage,
bit 2
OTG Voltage,
bit 1
OTG Voltage,
bit 0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-42. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-14
13
Reserved
R/W
R/W
00b
0b
Not used. 1 = invalid write.
OTG Voltage, bit 11
0 = Adds 0 mV of OTG voltage.
1 = Adds 16384 mV of OTG voltage.
12
11
10
9
OTG Voltage, bit 10
OTG Voltage, bit 9
OTG Voltage, bit 8
OTG Voltage, bit 7
OTG Voltage, bit 6
R/W
R/W
R/W
R/W
R/W
0b
1b
0b
0b
1b
0 = Adds 0 mV of OTG voltage.
1 = Adds 8192 mV of OTG voltage.
0 = Adds 0 mV of OTG voltage.
1 = Adds 4096 mV of OTG voltage.
0 = Adds 0 mV of OTG voltage.
1 = Adds 2048 mV of OTG voltage.
0 = Adds 0 mV of OTG voltage.
1 = Adds 1024 mV of OTG voltage.
8
0 = Adds 0 mV of OTG voltage.
1 = Adds 512 mV of OTG voltage.
表9-43. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
6
5
4
3
OTG Voltage, bit 5
R/W
1b
0 = Adds 0 mV of OTG voltage.
1 = Adds 256 mV of OTG voltage.
OTG Voltage, bit 4
OTG Voltage, bit 3
OTG Voltage, bit 2
OTG Voltage, bit 1
R/W
R/W
R/W
R/W
1b
0b
0b
0b
0 = Adds 0 mV of OTG voltage.
1 = Adds 128 mV of OTG voltage.
0 = Adds 0 mV of OTG voltage.
1 = Adds 64 mV of OTG voltage.
0 = Adds 0 mV of OTG voltage.
1 = Adds 32 mV of OTG voltage.
0 = Adds 0 mV of OTG voltage.
1 = Adds 16 mV of OTG voltage.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
77
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-43. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions (continued)
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
2
OTG Voltage, bit 0
R/W
1b
0 = Adds 0 mV of OTG voltage.
1 = Adds 8 mV of OTG voltage.
1-0
Reserved
R/W
00b
Not used. Value Ignored.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
78
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.20 OTGCurrent Register (SMBus address = 3Ch) [reset = 3C00h]
To set the OTG output current limit, write to REG0x3C() using the data format listed in 图 9-27, 表 9-44, and 表
9-45.
图9-27. OTGCurrent Register (SMBus address = 3Ch) [reset = 3C00h]
15
14
13
12
11
10
9
8
Reserved
OTG Current
OTG Current
OTG Current
OTG Current
OTG Current
OTG Current
OTG Current
set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit
6
5
4
3
2
1
0
R/W
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
5
4
3
2
1
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-44. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
14
Reserved
R/W
R/W
0b
0b
Not used. 1 = invalid write.
OTG Current set by host, bit 6
0 = Adds 0 mA of OTG current.
1 = Adds 3200 mA of OTG current.
13
12
11
10
9
OTG Current set by host, bit 5
OTG Current set by host, bit 4
OTG Current set by host, bit 3
OTG Current set by host, bit 2
OTG Current set by host, bit 1
OTG Current set by host, bit 0
R/W
R/W
R/W
R/W
R/W
R/W
1b
1b
1b
1b
0b
0b
0 = Adds 0 mA of OTG current.
1 = Adds 1600mA of OTG current.
0 = Adds 0 mA of OTG current.
1 = Adds 800 mA of OTG current.
0 = Adds 0 mA of OTG current.
1 = Adds 400 mA of OTG current.
0 = Adds 0 mA of OTG current.
1 = Adds 200 mA of OTG current.
0 = Adds 0 mA of OTG current.
1 = Adds 100 mA of OTG current.
8
0 = Adds 0 mA of OTG current.
1 = Adds 50 mA of OTG current.
表9-45. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-0
Reserved
R/W
00000000b
Not used. Value Ignored.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
79
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.21 InputVoltage (VINDPM) Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
To set the input voltage limit, write a 16-bit InputVoltage register command (REG0x()) using the data format listed
in 图9-28, 表9-46, and 表9-47.
If the input voltage drops more than the InputVoltage register allows, the device enters VINDPM and reduces the
charge current. The default setting is 1.28 V below the no-load VBUS voltage. There is fixed offset voltage 3.2V
for all codes.
图9-28. InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
15
14
13
12
11
10
9
8
Reserved
R/W
Input Voltage,
bit 7
Input Voltage,
bit 6
Input Voltage,
bit 5
Input Voltage,
bit 4
Input Voltage,
bit 3
Input Voltage,
bit 2
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
7
6
Input Voltage,
bit 1
Input Voltage,
bit 0
Reserved
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-46. InputVoltage Register (SMBus address = 3Dh) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-14
13
Reserved
R/W
R/W
00b
0b
Not used. 1 = invalid write.
Input Voltage, bit 7
0 = Adds 0 mV of input voltage.
1 = Adds 8192 mV of input voltage.
12
11
10
9
Input Voltage, bit 6
Input Voltage, bit 5
Input Voltage, bit 4
Input Voltage, bit 3
Input Voltage, bit 2
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0 = Adds 0 mV of input voltage.
1 = Adds 4096mV of input voltage.
0 = Adds 0 mV of input voltage.
1 = Adds 2048 mV of input voltage.
0 = Adds 0 mV of input voltage.
1 = Adds 1024 mV of input voltage.
0 = Adds 0 mV of input voltage.
1 = Adds 512 mV of input voltage.
8
0 = Adds 0 mV of input voltage.
1 = Adds 256 mV of input voltage.
表9-47. InputVoltage Register (SMBus address = 3Dh) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
Input Voltage, bit 1
R/W
0b
0 = Adds 0 mV of input voltage.
1 = Adds 128 mV of input voltage.
6
Input Voltage, bit 0
Reserved
R/W
R/W
0b
0 = Adds 0 mV of input voltage.
1 = Adds 64 mV of input voltage
5-0
000000b
Not used. Value Ignored.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
80
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.22 VSYS_MIN Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
To set the minimum system voltage, write a 16-bit VSYS_MIN register command (REG0x3E()) using the data
format listed in 图9-29, 表9-48, and 表9-49. The charger provides minimum system voltage range from 1.0V to
19.2 V, with 100-mV step resolution. Any write below 1.0V or above 19.2 V is ignored. Upon POR, the
VSYS_MIN register is 3.6 V for 1 S, 6.6V for 2 S and 9.2 V for 3 S, and 12.3 V for 4 S. Writing VSYS_MIN to 0
will set it to the default value based on CELL_BATPRESZ pin.
图9-29. VSYS_MIN Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
15
14
13
12
11
10
9
8
VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit
7
R/W
7
6
R/W
6
5
R/W
5
4
R/W
4
3
R/W
3
2
R/W
2
1
R/W
1
0
R/W
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-48. VSYS_MIN Register (SMBus address = 3Eh) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
14
13
12
11
10
9
Min System Voltage, bit 7
R/W
0b
0 = Adds 0 mV of system voltage.
1 = Adds 12800 mV of system voltage.
Min System Voltage, bit 6
Min System Voltage, bit 5
Min System Voltage, bit 4
Min System Voltage, bit 3
Min System Voltage, bit 2
Min System Voltage, bit 1
Min System Voltage, bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
0 = Adds 0 mV of system voltage.
1 = Adds 6400mV of system voltage.
0 = Adds 0 mV of system voltage.
1 = Adds 3200 mV of system voltage.
0 = Adds 0 mV of system voltage.
1 = Adds 1600 mV of system voltage.
0 = Adds 0 mV of system voltage.
1 = Adds 800 mV of system voltage.
0 = Adds 0 mV of system voltage.
1 = Adds 400 mV of system voltage.
0 = Adds 0 mV of system voltage.
1 = Adds 200 mV of system voltage.
8
0 = Adds 0 mV of system voltage.
1 = Adds 100 mV of system voltage.
表9-49. VSYS_MIN Register (SMBus address = 3Eh) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-0
Reserved
R/W
00000000
b
Not used. Value Ignored.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.23 IIN_HOST Register (SMBus address = 3Fh) [reset = 4100h]
To set the nominal input current limit based on the adapter rated current. Write a 7-bit IIN_HOST register
command using the data format listed in 图9-30, and 表9-50.
When using a 10-mΩ sense resistor (RSNS_RAC=0b), the charger provides a nominal input-current limit range
of 50 mA to 6350 mA, with 50-mA resolution. The upper boundary is implemented through DAC clamp, writing
value higher than limitation will be neglected. The lower boundary is implemented through 50mA offset at code
0. Note this offset is only applied to code 0, not applied to other codes. The default nominal input current limit is
3.25 A. Upon adapter removal, the input current limit is reset to the default value of 3.25 A.
When using a 5-mΩ sense resistor (RSNS_RAC=1b) referring to 节 9.3.6, the input-current limit range can be
found under certain IADPT pin, EN_FAST_5MOHM bit status. The lower boundary is implemented through 100-
mA offset at code 0. Note this offset is only applied to code 0, not applied to other codes. The default current
limit is 3.2 A. Due to the USB current setting requirement, the register setting specifies the maximum current
instead of the typical current. Upon adapter removal, the nominal input current limit is reset to the default value
of 3.2 A.
To set the maximum input current limit based on adapter rated current. Additional 100mA(10-mΩ sense
resistor)/200mA(5-mΩ sense resistor) offset should be added based on above nominal input current limit to
obtain the maximum input current limit.
The ACP and ACN pins are used to sense RAC with the default value of 10 mΩ.
Instead of using the internal IIN_DPM loop, the user can build up an external input current regulation loop and
have the control signal on the ILIM_HIZ pin.
In order to disable ILIM_HIZ pin, the host can write to 0x31[7] to disable ILIM_HIZ pin, or pull ILIM_HIZ pin
above 4.0 V.
图9-30. IIN_HOST Register With 10-mΩSense Resistor (SMBus address = 3Fh) [reset = 4100h]
15
14
13
12
11
10
9
8
Reserved
Input Current
Input Current
Input Current
Input Current
Input Current
Input Current
Input Current
set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit
6
R/W
6
5
R/W
5
4
R/W
4
3
R/W
3
2
R/W
2
1
R/W
1
0
R/W
0
R/W
7
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-50. IIN_HOST Register With 10-mΩSense Resistor (SMBus address = 3Fh) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
14
Reserved
R/W
R/W
0b
1b
Not used. 1 = invalid write.
Input Current set by host, bit 6
0 = Adds 0 mA of input current.
1 = Adds 3200 mA of input current.
13
12
11
Input Current set by host, bit 5
Input Current set by host, bit 4
Input Current set by host, bit 3
R/W
R/W
R/W
0b
0b
0b
0 = Adds 0 mA of input current.
1 = Adds 1600 mA of input current.
0 = Adds 0 mA of input current.
1 = Adds 800 mA of input current.
0 = Adds 0 mA of input current.
1 = Adds 400 mA of input current.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
82
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表9-50. IIN_HOST Register With 10-mΩSense Resistor (SMBus address = 3Fh) Field Descriptions
(continued)
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
10
Input Current set by host, bit 2
R/W
R/W
R/W
0b
0 = Adds 0 mA of input current.
1 = Adds 200 mA of input current.
9
Input Current set by host, bit 1
Input Current set by host, bit 0
0b
1b
0 = Adds 0 mA of input current.
1 = Adds 100 mA of input current.
8
0 = Adds 0 mA of input current.
1 = Adds 50 mA of input current.
表9-51. IIN_HOST Register With 10-mΩSense Resistor (SMBus address = 3Fh) Field Descriptions
SMBus
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-0
Reserved
R
00000000
b
Not used. Value Ignored.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
83
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
9.6.24 ID Registers
9.6.24.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
图9-31. ManufactureID Register (SMBus address = FEh) [reset = 0040h]
7-0
Manufacturer ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-52. ManufactureID Register Field Descriptions
SMBus
FIELD
TYPE
RESET
DESCRIPTION (READ ONLY)
BIT
15-8
7-0
Reserved
R
R
00h
40h
Reserved
40h
MANUFACTURE_ID
9.6.24.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 00E1h]
图9-32. Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 00E1h]
7-0
DEVICE_ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-53. Device ID (DeviceAddress) Register Field Descriptions
SMBus
FIELD
TYPE
RESET
DESCRIPTION (READ ONLY)
BIT
15-8
7-0
Reserved
R
R
00h
Reserved
DEVICE_ID
BQ25720: 11 10 0001b (E1h)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
84
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Application Information
The BQ2572xEVM evaluation module (EVM) is a complete charger module for evaluating the BQ25720. The
application curves were taken using the BQ2572xEVM.
At the VBUS input with a 2.2-μH or smaller inductor, a minimum 4 μF effective (4 × 10-μF MLCC) is
suggested for a 45-W to 65-W adapter, and two more 10-μF MLCC capacitors are needed when power reaches
90 W. Note when VAP feature is employed, 1 × 33-μF POSCAP is recommended to be added to improve VAP
feature performance and finally system CPU performance.
At the charger VSYS output terminal, a minimum 7 μF effective (7 × 10-μF 0805 package MLCC) is suggested
for a 45-W to 65-W adapter, and two more 10-μF MLCC capacitors are needed when power reaches 90 W.
Overall 50-μF effective distributed capacitance on VSYS net is necessary (POSCAP is preferred), these
capacitors do not have to be placed at the charger VSYS output terminal, all capacitors connected to VSYS net
can be counted including the input capacitor of the next stage converters.
10.2 Typical Application
VSYS
2.2uH
RAC=5m ꢀ10m
RSR=5m ꢀ10m
VBUS
ꢁ ꢁ
BATT
(1-4S)
Q2
Q3
Q1
Q4
1nF
10nF
33nF
47nF
47nF
1uF
6x10uF
7x10uF
2x10uF
0.1uF
10
1.0uF
1x33uF
(Optional)
! ""
! ""
HIDRV1
HIDRV2
10
SYS
BATDRV
SRP
33nF
ACN
ACP
10
SRN
VDDA
ILIM_HIZ
REGN
380k
220k
REGN
1
1uF
2.2–3.3uF
VDDA
PGND
BQ25720
350k
VBUS
CELL_BATPRES
470nF
250k
3.3nF 16.9k
33pF
COMP1
COMP2
IADPT
IBAT
15pF
PSYS
100pF
100pF
137k
1200pF
10k
50
30k
PROCHOT
1.05V
To CPU
10k
10k
10k
3.3V or 1.8V
10k
Host
(SMBus)
图10-1. Application Diagram of BQ25720
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
85
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
10.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
3.5 V < Adapter Voltage < 26V
3.2 A for 65-W adapter
8400 mV for 2s battery
3072 mA for 2s battery
6600 mV for 2s battery
Input Voltage(2)
Input Current Limit (2)
Battery Charge Voltage(1)
Battery Charge Current(1)
Minimum System Voltage(1)
(1) Refer to battery specification for settings.
(2) Refer to adapter specification for settings for Input Voltage and Input Current Limit.
10.2.2 Detailed Design Procedure
The parameters are configurable using the evaluation software. The simplified application circuit (see 图10-1, as
the application diagram) shows the minimum component requirements. Inductor, capacitor, and MOSFET
selection are explained in the rest of this section. Refer to the EVM user's guide for the complete application
schematic.
10.2.2.1 ACP-ACN Input Filter
The BQ25720 has average current mode control. The input current sensing through ACP/ACN is critical to
recover inductor current ripple. Parasitic inductance on board will generate high frequency ringing on ACP-ACN
which overwhelms converter sensed inductor current information. It is also difficult to manage parasitic
inductance created based on different PCB layout. Larger parasitic inductance will generate larger sense current
ringing which could cause the average current control loop to go into oscillation. Therefore ACP-ACN sensing
information need to be conditioned.
For real system board condition, we suggest using below circuit design to get best result and filter noise induced
from different PCB parasitic factor. With time constant of filter from 47 ns to 200 ns, the filter is effective and the
delay of on the sensed signal is small, therefore there is no concern for average current mode control.
RAC
Q1
6x10uF
(0805)
RACN
4.99ohm
RACP
4.99ohm
10nF(0402) 1nF(0402)
CDIFF
Open
CACN
33nF
CACP
33nF
ACP
ACN
HIDRV1
图10-2. ACN-ACP Input Filter
10.2.2.2 Inductor Selection
The BQ25720 has two selectable fixed switching frequency. Higher switching frequency allows the use of
smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current
(ICHG) plus half the ripple current (IRIPPLE):
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
86
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
ISAT ³ ICHG + (1/2) IRIPPLE
(2)
The inductor ripple current in buck operation depends on input voltage (VIN), duty cycle (DBUCK = VOUT/VIN),
switching frequency (fS) and inductance (L):
IRIPPLE_BUCK = VIN × DBUCK× (1-DBUCK) / (fS × L)
During boost operation, the duty cycle is:
(3)
DBOOST = 1 –(VIN/VBAT
)
and the ripple current is:
IRIPPLE_BOOST = (VIN × DBOOST) / (fS × L)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9 V to 12.6 V for 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives
the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12 V to
16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20 –40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
10.2.2.3 Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current (plus system current there is any system load) when duty cycle
is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS
current occurs where the duty cycle is closest to 50% and can be estimated by 方程式4:
ICIN = ICHG
´
D × (1 - D)
(4)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed in front of RAC current sensing and as close as possible to the power stage half bridge MOSFETs.
Capacitance after RAC before power stage half bridge should be limited to 10 nF + 1 nF referring to 图 10-2
diagram. Because too large capacitance after RAC could filter out RAC current sensing ripple information. Voltage
rating of the capacitor must be higher than normal input voltage level, 25-V rating or higher capacitor is preferred
for 19-V to 20-V input voltage. The minimum input effective capacitance recommendation based on refers to 表
10-1.
Ceramic capacitors (MLCC) show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias
voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a
significant capacitance drop, especially for high input voltages and small capacitor packages. See the
manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary to
choose a higher voltage rating or nominal capacitance value in order to get the required effective capacitance
value at the operating point. Considering the 25 V 0603 package MLCC capacitance derating under 19-V to 20-
V input voltage, the recommended practical capacitors configuration can also be found in 表 10-1. Tantalum
capacitors (POSCAP) can avoid dc-bias effect and temperature variation effect which is recommended for 90 W
to 130 W higher power application.
表10-1. Minimum Input Capacitance Requirement
INPUT CAPACITORS vs TOTAL INPUT
65 W
90 W
130 W
POWER
Minimum effective input capacitance
4 μF
6 μF
13 μF
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
87
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表10-1. Minimum Input Capacitance Requirement (continued)
INPUT CAPACITORS vs TOTAL INPUT
POWER
65 W
90 W
130 W
Minimum practical input capacitors
configuration
4*10 μF (0603 25 V MLCC) 6*10 μF (0603 25 V MLCC) 3*10 μF (0603 25 V MLCC)
1* 10 μF (25 V to 35 V
POSCAP)
10.2.2.4 Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. To get
good loop stability, the resonant frequency of the output inductor and output capacitor should be designed
between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25-V X7R or X5R for output capacitor. Minimum
7 pcs of 10-μF 0603 package capacitor is suggested to be placed as close as possible to Q3&Q4 half bridge
(between Q4 drain and Q3 source terminal). Total minimum output effective capacitance along VSYS distribution
line is 50 μF refers to 表10-2. Recommend to place minimum 20-μF MLCC capacitors after the charge current
sense resistor for best stability.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage
is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a
significant capacitance drop, especially for high output voltages and small capacitor packages. See the
manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary to
choose a higher voltage rating or nominal capacitance value in order to get the required capacitance value at the
operating point. Considering the 25-V 0603 package MLCC capacitance derating under 21-V to 23-V output
voltage, the recommended practical capacitors configuration at VSYS output terminal can also be found in 表
10-2. Tantalum capacitors (POSCAP) can avoid dc-bias effect and temperature variation effect which are
recommend to be used along VSYS output distribution line to meet total minimum effective output capacitance
requirement.
表10-2. Minimum Output Capacitance Requirement
OUTPUT CAPACITORS vs TOTAL INPUT
65 W
90 W
130 W
POWER
Minimum Effective Output Capacitance
50 μF
50 μF
50 μF
Minimum output capacitors at charger VSYS
output terminal
7*10 μF (0603 25 V MLCC) 9*10 μF (0603 25 V MLCC) 9*10 μF (0603 25 V MLCC)
Additional output capacitors along VSYS
distribution line
2*22 μF (25 V~35 V
POSCAP)
2*22 μF (25 V~35 V
POSCAP)
2*22 μF (25 V~35 V
POSCAP)
10.2.2.5 Power MOSFETs Selection
Four external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
integrated into the IC with 6 V of gate drive voltage. 30 V or higher voltage rating MOSFETs are preferred for 19-
V to 20-V input voltage.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,
RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.
FOMtop = RDS(on) · QGD; FOMbottom = RDS(on) · QG
(5)
The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. Taking buck mode operation as an
example the power loss is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-
resistance (RDS(ON)_top), input voltage (VIN), switching frequency (fS), turn-on time (ton) and turn-off time (toff):
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
88
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
Ptop =Pcon_top+Psw_top
Pcon_top =D · IL_RMS 2 · RDS(on)_top
IL_RMS 2=IL_DC 2+Iripple 2/12
(6)
(7)
(8)
;
• IL_DC is the average inductor DC current under buck mode;
• Iripple is the inductor current ripple peak-to-peak value;
Psw_top =PIV_top+PQoss_top+PGate_top
;
(9)
The first item Pcon_top represents the conduction loss which is straight forward. The second term Psw_top
represents the multiple switching loss items in top MOSFET including voltage and current overlap losses
(PIV_top), MOSFET parasitic output capacitance loss (PQoss_top) and gate drive loss (PGate_top). To calculate
voltage and current overlap losses (PIV_top):
PIV_top =0.5x VIN · Ivalley · ton· fS+0.5x VIN · Ipeak · toff · fS
Ivalley =IL_DC- 0.5 · Iripple (inductor current valley value);
Ipeak =IL_DC+ 0.5 · Iripple (inductor current peak value);
(10)
(11)
(12)
• ton is the MOSFET turn-on time that VDS falling time from VIN to almost zero (MOSFET turn on conduction
voltage);
• toff is the MOSFET turn-off time that IDS falling time from Ipeak to zero;
The MOSFET turn-on and turn-off times are given by:
QSW
QSW
ton
=
, toff =
Ion
Ioff
(13)
where Qsw is the switching charge, Ion is the turn-on gate driving current, and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):
Qsw =QGD+QGS
(14)
Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron), and turn-off gate resistance (Roff) of the gate driver:
VREGN - Vplt
Vplt
Ion
=
, Ioff =
Ron
Roff
(15)
(16)
To calculate top MOSFET parasitic output capacitance loss (PQoss_top):
PQoss_top =0.5 · VIN· Qoss · fS
• Qoss is the MOSFET parasitic output charge which can be found in MOSFET datasheet;
To calculate top MOSFET gate drive loss (PGate_top):
PGate_top =VIN· QGate_top · fS
(17)
• QGate_top is the top MOSFET gate charge which can be found in MOSFET datasheet;
• Note here VIN is used instead of real gate drive voltage 6 V because, the gate drive 6 V is generated based
on LDO from VIN under buck mode, the total gate drive related loss are all considered when VIN is used for
gate drive loss calculation .
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
89
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
The bottom-side MOSFET loss also includes conduction loss and switching loss:
Pbottom =Pcon_bottom+Psw_bottom
(18)
(19)
(20)
Pcon_bottom =(1 - D) · IL_RMS 2 · RDS(on)_bottom
;
Psw_bottom =PRR_bottom+PDead_bottom+PGate_bottom
;
The first item Pcon_bottom represents the conduction loss which is straight forward. The second term Psw_bottom
represents the multiple switching loss items in bottom MOSFET including reverse recovery losses (PRR_bottom),
Dead time body diode conduction loss (PDead_bottom) and gate drive loss (PGate_bottom). The detail calculation can
be found below:
PRR_bottom=VIN · Qrr · fS
(21)
• Qrr is the bottom MOSFET reverse recovery charge which can be found in MOSFET data sheet;
PDead_bottom=VF · Ivalley · fS · tdead_rise+VF · Ipeak · fS · tdead_fall
(22)
• VF is the body diode forward conduction voltage drop;
• tdead_rise is the SW rising edge deadtime between top and bottom MOSFETs which is around 40 ns;
• tdead_fall is the SW falling edge deadtime between top and bottom MOSFETs which is around 30 ns;
PGate_bottom can follow the same method as top MOSFET gate drive loss calculation approach refer to 方程式17.
P-channel MOSFETs is used for battery charging BATFET. The gate drivers are internally integrated into the IC
with 10 V of gate drive voltage. 20 V or higher voltage rating MOSFETs are preferred for 1- to 4-cell battery
application, the Ciss of P-channel MOSFET should be chosen less than 5 nF.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
90
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
10.2.3 Application Curves
CH1: VBUS
CH2: VDDA
CH1: VBUS
CH2: VDDA
CH3: CHRG_OK
CH3: CHRG_OK
CH4: VSYS
CH4: VSYS
2-cell without battery
2-cell without battery
图10-3. Power Up From 20 V
图10-4. Power Up From 5 V
CH1: VBUS
CH1: VBUS
CH2: SW1
CH2: SW1
CH3: SW2
CH3: SW2
CH4: VSYS with 9Vos
CH4: IL
3-cell VBAT = 10 V
VBUS 5 V to 20 V
图10-5. Power Off From 12 V
图10-6. Line Regulation
CH2: SW1
CH1: HIDRV1
CH2: SW1
CH3: LODRV1
CH3: SW2
CH1: IL
CH4: IL
VBUS = 20 V, VSYS = 10 V, ISYS = 200 mA
VBUS = 20 V, VSYS = 10 V, ISYS = 2 A
图10-7. PFM Operation
图10-8. PWM Operation
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
91
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
CH2: SW2
CH2: SW1
CH3: SW2
CH1: HIDRV2
CH3: LODRV2
CH4: IL
CH4: IL
VBUS = 5 V, VBAT = 10 V
VBUS = 12 V, VBAT = 12 V
图10-9. Switching During Boost Mode
图10-10. Switching During Buck Boost Mode
CH1: VSYS
CH2: IIN
CH1: VSYS
CH2: IIN
CH3: ISYS
CH3: ISYS
VBUS = 9 V/3.25 A, 3-cell, VSYS = 9 V, Without battery
VBUS = 12 V/3.25 A, 3-cell, VSYS = 9 V, Without battery
图10-12. System Regulation in Buck Boost Mode
图10-11. System Regulation in Buck Mode
CH1: VSYS
CH2: IIN
CH2: IIN
CH3: ISYS
CH4: IBAT
CH3: ISYS
VBUS = 5 V/3.25 A, 3-cell, VSYS = 9 V, Without battery
VBUS = 20 V/3.25 A, VBAT = 7.5 V
图10-13. System Regulation in Boost Mode
图10-14. Input Current Regulation in Buck Mode
Copyright © 2023 Texas Instruments Incorporated
92
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
CH2:IIN
CH1: EN_OTG
CH2: VBUS
CH3:ISYS
CH4:IBAT
VBUS = 5 V/3.25 A, VBAT = 7.5 V
VBUS = 5 V
图10-15. Input Current in Boost Mode
图10-16. OTG Power Up from 8-V Battery
CH1: SCL
CH1: SCL
CH2: VBUS
CH2: VBUS
CH3: SW2
CH3: SW2
VBAT = 10 V, VBUS 5 V to 20 V, IOTG = 500 mA
图10-18. OTG Power Off
图10-17. OTG Voltage Ramp Up
CH2: VBUS
CH1:VBUS
CH2:FRS Pin
CH4:ISYS
CH3:IBUS
CH3: IVBUS
VBAT = 10 V, VBUS = 20 V
VBUS = 20 V, VOTG = 5 V, ISYS = 5 A,VBAT = 14.8 V
图10-19. OTG Load Transient
图10-20. FRS Transition Waveform
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
93
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
VBUS = 20 V
TMAX = 20 ms
IIN_DPM = 2 A
TOVLD = 10 ms
ILIM2_VTH = 200%
VSYS_MIN = 12.3
V
VBUS = 20 V
TMAX = 20 ms
ISYS = 1 to 6 A
IIN_DPM = 2 A
TOVLD = 10 ms
ICHG = 0 A
ILIM2_VTH = 200%
VBAT = 12.8 V
ISYS = 1 to 6 A
ICHG = 0 A
图10-22. Peak Power Mode IBUS Trigger
图10-21. Peak Power Mode VSYS Trigger
Copyright © 2023 Texas Instruments Incorporated
94
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
11 Power Supply Recommendations
The valid adapter range is from 3.5 V (VVBUS_CONVEN) to 26 V with at least 500-mA current rating. When
CHRG_OK goes HIGH, the system is powered from adapter through the charger. When adapter is removed, the
system is connected to battery through BATFET. Typically the battery depletion threshold should be greater than
the VSYS_MIN so that the battery capacity can be fully utilized for maximum battery run time.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
95
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
Proper layout of the components to minimize high frequency current path loop (see 节 12.2) is important to
prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout
priority list for proper layout.
表12-1. PCB Layout Guidelines
RULES COMPONENTS
FUNCTION
IMPACT
GUIDELINES
1
PCB layer stack up Thermal, efficiency, Multi- layer PCB is suggested. Allocate at least one ground layer.
signal integrity
The BQ257XXEVM uses a 4-layer PCB (top layer, ground layer,
signal layer and bottom layer).
2
CBUS, RAC, Q1, Input loop
High frequency
noise, ripple
VBUS capacitors, RAC, Q1 and Q2 form a small loop 1. It is best
to put them on the same side. Connect them with large copper to
reduce the parasitic resistance. Move part of CBUS to the other
side of PCB for high density design. After RAC before Q1 and Q2
power stage recommend to put 10 nF + 1 nF (0402 package)
decoupling capacitors as close as possible to IC to decoupling
switching loop high frequency noise.
Q2
3
4
5
RAC, Q1, L1, Q4
CSYS, Q3, Q4
QBAT, RSR
Current path
Output loop
Current path
Efficiency
The current path from VBUS to VSYS, through RAC, Q1, L1, Q4,
has low impedance. Pay attention to via resistance if they are not
on the same side. The number of vias can be estimated as 1 to
2A/via for a 10-mil via with 1 oz. copper thickness.
High frequency
noise, ripple
VSYS capacitors, Q3 and Q4 form a small loop 2. It is best to put
them on the same side. Connect them with large copper to
reduce the parasitic resistance. Move part of CSYS to the other
side of PCB for high density design.
Efficiency, battery
voltage detection
Place QBAT and RSR near the battery terminal. The current path
from VBAT to VSYS, through RSR and QBAT, has low
impedance. Pay attention to via resistance if they are not on the
same side. The device detects the battery voltage through SRN
near battery terminal.
6
7
Q1, Q2, L1, Q3,
Q4
Power stage
Thermal, efficiency Place Q1, Q2, L1, Q3 and Q4 next to each other. Allow enough
copper area for thermal dissipation. The copper area is
suggested to be 2x to 4x of the pad size. Multiple thermal vias
can be used to connect more copper layers together and
dissipate more heat.
RAC, RSR
Current sense
Regulation accuracy Use Kelvin-sensing technique for RAC and RSR current sense
resistors. Connect the current sense traces to the center of the
pads, and run current sense traces as differential pairs.
8
9
Small capacitors
BST capacitors
IC bypass caps
HS gate drive
Noise, jittering,
ripple
Place VBUS cap, VCC cap, REGN caps near IC.
High frequency
noise, ripple
Place HS MOSFET boost strap circuit capacitor close to IC and
on the same side of PCB board. Capacitors SW1/2 nodes are
recommended to use wide copper polygon to connect to power
stage and capacitors BST1/2 node are recommended to use at
least 8mil trace to connected to IC BST1/2 pins.
Copyright © 2023 Texas Instruments Incorporated
96
Submit Document Feedback
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
表12-1. PCB Layout Guidelines (continued)
RULES COMPONENTS
FUNCTION
IMPACT
GUIDELINES
10
Ground partition
Measurement
Separate analog ground(AGND) and power grounds(PGND) is
accuracy, regulation preferred. PGND should be used for all power stage related
accuracy, jitters,
ripple
ground net. AGND should be used for all sensing, compensation
and control network ground for example ACP/ACN/COMP1/
COMP2/CMPIN/CMPOUT/IADPT/IBAT/PSYS. Connect all
analog grounds to a dedicated low-impedance copper plane,
which is tied to the power ground underneath the IC exposed
pad. If possible, use dedicated COMP1, COMP2 AGND traces.
Connect analog ground and power ground together using power
pad as the single ground connection point.
12.2 Layout Example
12.2.1 Layout Example Reference Top View
Based on the above layout guidelines, the buck-boost charger layout example top view is shown below including
all the key power components.
图12-1. Buck-Boost Charger Layout Reference Example Top View
12.2.2 Inner Layer Layout and Routing Example
For both input sensing resistor and charging current sensing resistor, differential sensing and routing method are
suggested and highlighted in below figure. Use wide trace for gate drive traces, minimum 15 mil trace width.
Connect all analog grounds to a dedicated low-impedance copper plane, which is tied to the power ground
underneath the IC exposed pad. Suggest using dedicated COMP1, COMP2 analog ground traces shown in
below figure.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
97
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
图12-2. Buck-Boost Charger Gate Drive/Current Sensing/AGND Signal Layer Routing Example
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
98
Submit Document Feedback
Product Folder Links: BQ25720
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Semiconductor and IC Package Thermal Metrics Application Report
• BQ2571x Evaluation Module User's Guide
• QFN/SON PCB Attachment Application Report
13.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
99
Product Folder Links: BQ25720
English Data Sheet: SLUSDU3
BQ25720
ZHCSO21 –MAY 2021
www.ti.com.cn
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU3
100 Submit Document Feedback
Product Folder Links: BQ25720
重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25720RSNR
ACTIVE
QFN
RSN
32
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
BQ25720
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
©2020 ICPDF网 联系我们和版权申明