BQ25887 [TI]
适用于 USB 输入、集成式电池均衡的 I2C 2 节 2A 升压电池充电器;
| 型号： | BQ25887 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 输入、集成式电池均衡的 I2C 2 节 2A 升压电池充电器 电池 |
| 文件： | 总86页 (文件大小：4014K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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BQ25887
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
具有电池平衡功能且适用于 USB 输入的 BQ25887 I2C 控制型 2 节电池、
2A 升压模式电池充电器
1 特性
•
高精度
–
–
–
±0.5% 充电电压调节
1
•
高效的 2A、1.5MHz 开关模式升压充电器
±5% 充电电流调节
±7.5% 输入电流调节
–
在 5V 适配器、7.6V 电池、充电电流为 1A 下
的充电效率为 93.4%
–
–
针对 USB 输入和 2 节锂离子电池进行了优化
用于轻负载运行的可选低功耗 PFM 模式
•
安全
–
–
在充电下的电池温度检测
热调节和热关断
•
单个输入，支持 USB 输入适配器
–
–
–
支持 3.9V 至 6.2V 的输入电压范围，绝对最大
输入电压额定值为 20V
2 应用
输入电流限制（500mA 至 3.3A，精度为 100-
mA），支持 USB2.0、USB3.0 标准适配器
•
•
•
•
电动玩具和机器人玩具
虚拟现实耳麦
通过高达 5.5V 的输入电压限制进行最大功率跟
踪
IP 网络摄像头
无人机有效载荷控制
•
电池平衡和 I2C 控制功能
3 说明
–
–
集成式 FET，可支持高达 400mA 的平衡电流
采用默认寄存器设置的自动电池平衡功能
BQ25887 是一款高度集成的 2A 升压开关模式电池充
电管理器件，适用于 2 节 (2s) 锂离子和锂聚合物电
池。BQ25887 具有 I2C 控制和电池平衡功能，适用于
USB 输入。
•
•
输入电流优化器 (ICO)，无需过载适配器即可最大
限度地提高输入功率
集成式 16 位 ADC，用于系统监控（总线电压和电
流、电池电压、充电电流、以及 NTC 和裸片温
度）
器件信息(1)
器件型号
BQ25887
封装
封装尺寸（标称值）
•
高集成度包括所有 MOSFET、电流检测和环路补偿
VQFN (24)
4.00mm x 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
5V @ 3A
VREF
VBUS
PMID
STAT
ILIM
SNS
SW
ICHG=2A
BTST
BAT
REGN
VREF
MID
SDA
CBSET
REGN
SCL
/INT
Host
TS
/PG
CD
`
BQ25887
PSEL
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSD89
BQ25887
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 30
8.5 Register Maps ........................................................ 31
Application and Implementation ........................ 69
9.1 Application Information............................................ 69
9.2 Typical Application .................................................. 69
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements.............................................. 11
7.7 Typical Characteristics............................................ 13
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
9
10 Power Supply Recommendations ..................... 74
11 Layout................................................................... 74
11.1 Layout Guidelines ................................................. 74
11.2 Layout Example .................................................... 75
12 器件和文档支持 ..................................................... 76
12.1 器件支持 ............................................................... 76
12.2 文档支持................................................................ 76
12.3 接收文档更新通知 ................................................. 76
12.4 支持资源................................................................ 76
12.5 商标....................................................................... 76
12.6 静电放电警告......................................................... 76
12.7 Glossary................................................................ 76
13 机械、封装和可订购信息....................................... 77
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (May 2019) to Revision B
Page
•
•
•
•
•
已更改 更改了“应用” 部分 ....................................................................................................................................................... 1
已删除 删除了无 OTG 和无电源路径，目标位置： 说明 ....................................................................................................... 1
已添加 note to Absolute Maximum Ratings ........................................................................................................................... 7
已添加 图 79 ........................................................................................................................................................................ 72
已添加 图 80 ......................................................................................................................................................................... 72
Changes from Original (February 2019) to Revision A
Page
•
已更改 将“预告信息”更改为“生产数据”.................................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
BQ25887
www.ti.com.cn
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
5 Device Comparison Table
PART NUMBER
VBUS Operating Range
USB Detection
Power path
BQ25882
3.9 to 6.2 V
D+/D-
Yes
BQ25883
3.9 to 6.2 V
D+/D-
BQ25886
4.3 to 6.2 V
D+/D-
BQ25887
3.9 to 6.2 V
PSEL
Yes
Yes
No
Cell Balancing
OTG
No
No
No
Yes
Up to 2 A
Yes
Up to 2 A
Yes
Up to 2 A
No
No OTG
Yes
16 bit ADC
Control Interface
Status Pin
I2C
I2C
Standalone
STAT, /PG
4x4 QFN-24
I2C
/PG
STAT, /PG
4x4 QFN-24
STAT, /PG
4x4 QFN-24
Package
2.1x2.1 WCSP-25
Copyright © 2019, Texas Instruments Incorporated
3
BQ25887
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
www.ti.com.cn
6 Pin Configuration and Functions
RGE Package
24-Pin VQFN
Top View
24
23
22
21
20
19
1
18
17
16
15
14
13
SW
PG
2
SW
STAT
3
CD
SNS
SNS
BQ25887
RGE, 4x4
4
SDA
5
SCL
BAT
BAT
6
INT
7
8
9
10
11
12
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Open drain active low power good indicator – Connect to the pull up rail via 10-kΩ resistor. LOW
indicates a good input source if the input voltage is within VVBUS_OP, and can provide more than
IPOORSRC (30mA).
PG
1
DO
DO
DI
Open drain charge status indicator – Connect to the pull-up rail via 10-kΩ resistor. LOW indicates
charge in progress. HIGH indicates charge complete or charge disabled. When any fault occurs, the
STAT pin blinks at 1Hz. The STAT function can be disabled when the STAT_DIS bit is set.
STAT
CD
2
3
Active High Chip Disable Pin – Pull CD high to disable charge and place the device in HIZ mode.
ADC operation and I2C is still allowed when CD is high. Converter is enabled when CD pin is LOW
and EN_CHG bit is 1. CD pin is internally pulled low with 900-kΩ resistor.
SDA
SCL
4
5
DIO
DI
I2C Interface Data – Connect SDA to the pull up rail through a 10-kΩ resistor.
I2C Interface Clock – Connect SCL to the pull up rail through a 10-kΩ resistor.
Open drain active Interrupt Output – Connect INT to the pull up rail via a 10-kΩ resistor. The INT
pin sends active low, 256-µs pulse to the host to report charger device status and fault.
INT
6
DO
Temperature Qualification Voltage – Connect a negative temperature coefficient thermistor.
Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends
when TS pin is out of range. Recommend 103AT-2 thermistor.
TS
7
AI
Input Current Limit (IINDPM) – ILIM pin sets the maximum input current and can be used to
monitor input current. IINDPM loop regulates ILIM pin voltage at 0.8V. When ILIM pin is less than
0.8V, the input current can be calculated by IIN = KILIM x VILIM / (RILIM x 0.8V). A resistor
connected from ILIM pin to ground sets the input current limit as maximum (IINMAX = KILIM /
RILIM). When ILIM pin is short to GND, the input current limit is set to maximum by ILIM. The actual
input current limit is the lower limit set by ILIM pin (when EN_ILIM bit is HIGH) or IINDPM register
bits. Input current limit less than 500mA is not supported on ILIM pin. The ILIM pin function can be
disabled when EN_ILIM bit is 0. If ILIM pin is not used, pull this pin to GND.Do not float this pin.
ILIM
MID
8
9
AI
AI
Voltage Input for Mid Point Between Cells in 2S1P Configuration – Connect MID to the negative
terminal of the top cell and the positive terminal of the bottom cell. This pin measures the voltage of
the bottom cell for cell balancing and VMID ADC measurement. For protection of bottom cell reverse
plug in, connect a 300 ohm resistor in series between MID pin and mid connection point of the two
battery cell.
4
Copyright © 2019, Texas Instruments Incorporated
BQ25887
www.ti.com.cn
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Power pin for Cell Balancing – Connect CBSET to the mid point between the two batteries in 2S
configuration with a current limit resistor. The resistor value determines the cell balancing current as
calculated in Cell Balancing Section. The resistor chosen should not exceed 400 mA for cell
balancing.
CBSET
10
P
Gate Drive Supply – Bias supply for internal MOSFETs driver and IC. Bypass REGN to GND with a
4.7-µF ceramic capacitor. REGN current limit is 50 mA.
REGN
BTST
BAT
11
P
P
PWM High-side Driver Supply – Internally, BTST is connected to the cathode of the boot-strap
diode. Connect a 47nF bootstrap capacitor from SW to BTST.
12
Battery Power Connection – Connect minimum recommended 10-µF capacitance after derating
closely to the BAT pin and GND.
13, 14
15, 16
P
Sense Output – Charge current sense pin. Place a 44-µF ceramic capacitor on this pin for stability
of this output.
SNS
AO
SW
17, 18
19, 20
P
Inductor Connection – Connect to the switched side of the external inductor.
GND
–
Ground Return
Blocking MOSFET Connection – The minimum recommended total input low-ESR capacitance on
VBUS and PMID, after applied derating, is 10 uF. At least 1-uF is recommended at VBUS with the
remainder at PMID. Typical value for PMID is 10 uF.
PMID
21, 22
P
Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at least 1-
µF ceramic capacitor, placed as close to the IC as possible.
VBUS
PSEL
23
24
P
Power Source Selection – HIGH indicates USB host source (500mA) and LOW indicates adapter
source (3.0A).
DI
Copyright © 2019, Texas Instruments Incorporated
5
BQ25887
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
-0.3
-0.3
MAX
20
8.5
12
13
19
6
UNIT
V
VBUS (converter not switching)
PMID (converter not switching)
V
BAT, SNS, MID, CBSET (converter not switching)
-0.3
V
(2)
SW
-0.3
V
Voltage Range (with respect to GND unless otherwise
specified)
BTST
-0.3
-0.3
-0.3
-0.3
-0.3
V
REGN, STAT, /PG, TS
ILIM
V
5
V
BTST to SW
6
V
SDA, SCL, /INT, CD, PSEL,
6
V
Voltage Range (with respect to GND unless otherwise
specified)
BAT to CBSET
/INT, STAT, /PG
0
12
V
Output Sink Current
6
150
150
mA
°C
Junction Temperature, TJ
Storage temperature, Tstg
–40
–40
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
(2) -2V for 50ns
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
6.2
3.3
2.2
5
UNIT
VVBUS
IVBUS
Input Voltage
3.9
V
A
A
A
Average input current (VBUS)
Average charge current (IBAT)
RMS discharging current with internal MOSFET
IBAT
IBAT_RMS
9 (up to
1us)
IBAT_PK
Peak discharging current with internal MOSFET
A
VBAT
TA
Battery Voltage
9.2(1)
V
Operating free-air temperature range
-40
85
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on SW pin. A tight layout minimizes
switching noise.
6
版权 © 2019, Texas Instruments Incorporated
BQ25887
www.ti.com.cn
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
bq25887
THERMAL METRIC(1)
RGE (VQFN)
24-PIN
32.4
UNIT
RΘJA
Junction-to-ambient thermal resistance (JEDEC (1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
26.7
10.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ΨJB
10.6
RΘ JC(bot)
3.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
QUIESCENT CURRENTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBAT = 9 V, No VBUS, SCL, SDA = 0 V
or 1.8 V, TJ=25C, ADC Disabled
12
12
30
30
1.5
3
14 µA
20 µA
38 µA
48 µA
IBAT
Battery discharge current (BAT)
Input supply current (VBUS) in HIZ
Input supply current (VBUS)
VBAT = 9 V, No VBUS, SCL, SDA = 0 V
or 1.8 V, TJ < 85C, ADC Disabled
VBUS = 5 V, High-Z Mode, no battery,
ADC Disabled, 25℃
IVBUS_HIZ
VBUS = 5 V, High-Z Mode, no battery,
ADC Disabled, <85℃
VBUS = 5 V, VBAT = 7.6 V, converter not
switching
3
mA
mA
IVBUS
VBUS = 5 V, VBAT = 7.6 V, converter
switching
VBUS/VBAT POWER UP
VVBUS_OP VBUS operating range
VVBUS_UVLO_RISING VBUS rising for active I2C, no battery VBUS rising
3.9
6.2
3.68
6.6
V
V
3.3
VBUS over-voltage rising threshold
VBUS over-voltage falling threshold
Battery for active I2C
VBUS rising
6.2
5.9
3.7
V
VVBUS_OV
VBUS falling
6.4
V
VBAT_UVLO_RISING
VBAT rising
4
3.7
15
4.42
V
VPOORSRC_FALLING Bad adapter detection threshold
IPOORSRC Bad adapter detection current source
BATTERY CHARGER
VBUS falling below VPOORSRC_FALLING
V
mA
Typical charge voltage regulation
range
VCELLREG_RANGE
3.4
4.6
V
VCELLREG_STEP
VCELLREG_ACC
VCELLREG_ACC
ICHG_RANGE
Typical charge voltage step
Charge voltage
5
4.2
mV
V
VREG = 4.20 V, TJ = 0°C to 85°C,
VREG = 4.35 V, TJ = 0°C to 85°C
4.179
4.328
100
4.221
4.372
Charge voltage
4.35
V
Charge current regulation range
Charge current regulation step
2200 mA
mA
ICHG_STEP
50
Fast Charge current regulation
accuracy
ICHG = 1000 mA, VBAT = 6.2 V or 7.6 V,
TJ = 0°C to 85°C
ICHG_ACC
ICHG_ACC
-7.5
-15
7.5
15
25
%
%
%
Fast Charge current regulation
accuracy
ICHG = 500mA, VBAT = 6.2 V or 7.6 V, TJ
= 0°C to 85°C
Fast Charge current regulation
accuracy
ICHG = 250 mA, VBAT = 6.2 V or 7.6 V,
TJ = 0°C to 85°C
ICHG_ACC
-25
50
IPRECHG_RANGE
Precharge current range
800 mA
Copyright © 2019, Texas Instruments Incorporated
7
BQ25887
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IPRECHG_STEP
Typical precharge current step
50
mA
VBAT = 5.2 V, IPRECHG = 200 mA, TJ =
25°C
170
237 mA
245 mA
IPRECHG_ACC
Precharge current accuracy
VBAT = 5.2 V, IPRECHG = 200 mA, TJ =
0°C to 85°C
150
50
ITERM_RANGE
ITERM_STEP
Termination current range
800 mA
mA
Typical termination current step
50
ICHG = 1.5A, ITERM = 150 mA, TJ = 25°C
143
120
45
157 mA
ICHG = 1.5A, ITERM = 150 mA, TJ = 0°C
to 85°C
180 mA
60 mA
75 mA
ITERM_ACC
Termination current accuracy
ICHG = 1.5A, ITERM = 50 mA, TJ = 25°C
ICHG = 1.5A, ITERM = 50 mA, TJ = 0°C to
85°C
22
Short Battery Voltage rising threshold
to start pre-charging
VCELL_SHORT_RISING
VCELL rising
VCELL falling
2.05
1.85
2.2
2
2.35
2.15
V
V
Short Battery Voltage falling
threshold to stop pre-charging
VCELL_SHORT_FALLIN
G
VTOPCELL<2.2V, VBOTCELL<VREG-
VRCHG; Or VBOTCELL<2.2V,
VTOPCELL<VREG-VRCHG
Low Battery Voltage trickle charging
current
IBAT_SHORT
100
mA
VCELL rising, VBATLOW = 2.8 V
VCELL rising, VBATLOWV = 3.0 V
VCELL falling, VBATLOW = 2.8 V
VCELL falling, VBATLOWV = 3.0 V
2.65
2.85
2.45
2.65
2.8
3
2.95
3.15
2.75
2.95
V
V
VCELL LOWV Rising threshold to
start fast-charging
VCELL_LOWV_RISING
2.6
2.8
100
32
V
VCELL_LOWV_FALLIN VCELL LOWV falling threshold to
start fast-charging
G
V
VCELL_RECHG
RON_QHS (Q2)
Recharge threshold below VCELLREG VCELL falling, VCELL_RECHG[1:0] = 01
mV
High-side switching MOSFET on-
resistance between SW and
SNS (Q2)
TJ = 25°C
35 mΩ
47 mΩ
46 mΩ
63 mΩ
16 mA
TJ = – 40°C to 125°C
TJ = 25°C
32
42
Low-side switching MOSFET on-
resistance between SW and GND
(Q3)
RON_QLS (Q3)
IBAT_DISCHG
TJ = – 40°C to 125°C
VBAT = 8V, EN_BAT_DISCHG = 1
42
BAT Discharge current source
8
11.5
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE
VINDPM_STEP
Input voltage regulation range
Input voltage regulation step
3.9
5.5
V
mV
V
100
3.9
4.4
VINDPM = 3.9 V
VINDPM = 4.4 V
3.783
4.268
500
4.017
4.532
VINDPM
Input voltage limit
V
IINDPM_RANGE
IINDPM_STEP
Input current regulation range
Input current regulation step
3300 mA
mA
100
469
IINDPM = 500 mA
IINDPM = 900 mA
IINDPM = 2500 mA
IINDPM = 3000 mA
438
765
500 mA
900 mA
2500 mA
3000 mA
832
IINDPM_ACC
Input current regulation limit
IINMAX = KILIM/RILIM
2125
2550
2312
2775
A x
Ω
KILIM
Input Current regulation by ILIM pin
1110
Input Current regulation by ILIM pin = 0.5A
Input Current regulation by ILIM pin = 0.9A
Input Current regulation by ILIM pin = 1.5A
TJ = 25°C
457
839
505
909
1518
33
553 mA
980 mA
1624 mA
37 mΩ
Input current regulation limit, IINMAX
KILIM/RILIM
=
IINDPM
1413
Blocking MOSFET on-resistance
between VBUS and PMID (QBLK)
RON_QBLK (Q1)
TJ = – 40°C to 125°C
33
51 mΩ
8
Copyright © 2019, Texas Instruments Incorporated
BQ25887
www.ti.com.cn
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
THERMAL REGULATION AND THERMAL SHUTDOWN
Junction temperature regulation
accuracy
TREG
TREG = 120°C
Temperature Increasing
120
°C
Thermal Shutdown Rising threshold
TSHUT_RISING
150
120
°C
°C
Thermal Shutdown Falling threshold Temperature Decreasing
JEITA THERMISTOR COMPARATOR (BOOST MODE)
TS pin voltage rising. T1 (0°C)
VT1
threshold, Charge suspended below As Percentage to REGN
this temperature.
72.75
67.75
44.25
73.25
1.3
73.75
68.75
45.25
%
%
%
%
%
%
%
%
TS pin voltage falling. Charge re-
enabled to ICHG/2 and VREG above As Percentage to REGN
this temperature
VT1_HYS
TS pin voltage rising. T2 (10°C)
threshold, charge set to ICHG/2 and As Percentage to REGN
VREG below this temperature
VT2
68.25
1.2
TS pin voltage falling. Charge set to
VT2_HYS
ICHG and VREG above this
temperature
As Percentage to REGN
As Percentage to REGN
As Percentage to REGN
TS pin voltage falling. T3 (45°C)
threshold, charge set to ICHG and
8.1 V above this temperature.
VT3
44.75
1
TS pin voltage rising. Charge set to
ICHG and VREG below this
temperature
VT3_HYS
TS pin voltage falling. T5 (60°C)
threshold, charge suspended above As Percentage to REGN
this temperature.
VT5
33.875 34.375 34.875
1.35
TS pin voltage rising. Charge set to
VT5_HYS
ICHG and 8.1 V below this
temperature
As Percentage to REGN
Oscillator frequency
BOOST MODE CONVERTER
FSW
PWM switching frequency
1.35
1.5
1.65 MHz
400 mA
CELL BALANCING
Maximum recommended cell
balancing current
VCELL = 4.2V, RCBSET = 9.5Ω,
RDSON_QCBX = 1Ω
ICB_MAX
Cell balance enabled (REG0x2A[0] = 1);
MOSFET on resistance between
BAT and MID
VCELL_HS > 3.7 V, VCELL_HS >
VCELL_LS, VBAT - VMID - VMID > 80 mV,
ICB ≤ 400 mA
RDSON_QCBH
1
1
1.2
Ω
Ω
Cell balance enabled (REG0x2A[0] = 1);
MOSFET on resistance between MID VCELL_LS > 3.7 V, VCELL_LS > VCELL_HS
and GND
,
RDSON_QCBL
1.2
VMID - (VBAT - VMID) > 80 mV, ICB ≤
400 mA
Cell balance function qualification
threshold
VCBEN_RISING
VCBEN_HYS
Cell balance enabled rising threshold
3.65
40
3.7
3.75
V
Cell balance function qualification
hysteresis
Cell balance enabled falling hysteresis
200
mV
Cell balance enabled (REG0X2A[0]=1);
VCELL_LS or VCELL_HS>3.7V, increase
the voltage delta between the two cells
Cell balance pre-qualification mode
to qualification mode threshold range
VQUAL_TH_RANGE
VQUAL_TH_STEP
VQUAL_TH
180 mV
mV
Cell balance pre-qualification mode
to qualification mode threshold step
size
Cell balance enabled (REG0X2A[0]=1);
VCELL_LS or VCELL_HS>3.7V, increase
the voltage delta between the two cells
10
80
Cell balance enabled (REG0X2A[0]=1);
VCELL_LS or VCELL_HS>3.7V, increase
the voltage delta between the two cells
Cell balance pre-qualification mode
to qualification mode threshold.
mV
Copyright © 2019, Texas Instruments Incorporated
9
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www.ti.com.cn
Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Cell balance enabled (REG0x2A[0] =
1); Difference between the two cells to turn
on cell balancing MOSFET
Balance discharge start cell voltage
difference threshold range
VDIFF_START_RANGE
40
190 mV
Cell balance enabled (REG0x2A[0] =
1); Difference between the two cells to turn
on cell balancing MOSFET
Balance discharge start cell voltage
difference threshold step size
VDIFF_START_STEP
10
mV
mV
Cell balance enabled (REG0x2A[0] =
1); Difference between the two cells to turn
on cell balancing MOSFET set to 120mV
(REG0x29[3:0] = 1000)
Balance discharge start cell voltage
difference threshold
VDIFF_START
120
Cell balance enabled (REG0x2A[0] =
1); Difference between the two cells to turn
on cell balancing MOSFET set to 80mV
(REG0x29[3:0] = 0100)
Balance discharge start cell voltage
difference threshold
VDIFF_START
80
mV
Cell balance enabled (REG0x2A[0] =
1); Difference between the two cells to turn
off cell balancing MOSFET
Balance discharge stop cell voltage
difference threshold range
VDIFF_END_RANGE
30
100 mV
mV
Cell balance enabled (REG0x2A[0] =
1); Difference between the two cells to turn
off cell balancing MOSFET
Balance discharge stop cell voltage
difference threshold step size
VDIFF_END_STEP
10
70
Cell balance enabled (REG0x2A[0] =
1); Difference between the two cells to turn
off cell balancing MOSFET set to
(REG0x29[3:0] = 1000,
Balance discharge stop cell voltage
difference threshold
VDIFF_END
mV
mV
REG0x28[7:5]=010)
Cell balance enabled (REG0x28[7] =
1); Difference between the two cells to turn
off cell balancing MOSFET set to 45mV
(REG0x29[3:0] = 0100,
Balance discharge stop cell voltage
difference threshold
VDIFF_END
40
REG0x28[7:5]=001)
VCELL rising, as percentage of
VCELLREG
VCELL_OVP_RISING
Cell over voltage rising threshold
102.5
100.8
400
104
102
500
105
%
%
VCELL rising, as percentage of
VCELLREG
VCELL_OVP_FALLING Cell over voltage falling threshold
103.3
Cell Balance MOSFET over-current
protection
IQCBX_OC
ICB > 500mA
600 mA
15 µA
Voltage difference between the two battery
cells ≤ 400mV
IMID_BIAS
MID pin bias current
REGN LDO
VREGN
REGN LDO output voltage
REGN LDO current limit
VVBUS = 5 V, IREGN = 20 mA
VVBUS = 5 V, VREGN = 3.8 V
4.7
50
4.8
5.15
V
IREGN
mA
Analog-to-Digital Converter (ADC)
ADC_SAMPLE[1:0] = 11
ADC_SAMPLE[1:0] = 10
ADC_SAMPLE[1:0] = 01
ADC_SAMPLE[1:0] = 00
ADC_SAMPLE[1:0] = 11
ADC_SAMPLE[1:0] = 10
ADC_SAMPLE[1:0] = 01
ADC_SAMPLE[1:0] = 00
24
12
6
ms
ms
ms
ms
bits
bits
bits
bits
tADC_CONV
Conversion time, each measurement
3
14
13
12
10
15
14
13
12
ADCRES
Effective resolution
ADC MEASUREMENT RANGES AND LSB
IBUS_ADC_RANGE
IBUS_ADC_LSB
ADC BUS current range
ADC BUS current LSB
ADC BAT current range
0
0
4
4
A
mA
A
1
IBAT_ADC_RANGE
10
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IBAT_ADC_LSB
ADC BAT current LSB
ADC BUS voltage range
ADC BUS voltage LSB
ADC BAT voltage range
ADC BAT voltage LSB
1
mA
VBUS_ADC_RANGE
VBUS_ADC_LSB
VBAT_ADC_RANGE
VBAT_ADC_LSB
0
6.5
10
V
mV
V
1
1
0
mV
VCELLTOP_ADC_RAN
GE
ADC MID voltage range
0
0
5
V
mV
V
VCELLTOP_ADC_LSB ADC MID voltage LSB
1
VCELLBOT_ADC_RAN
GE
ADC MID voltage range
5
VCELLBOT_ADC_LSB ADC MID voltage LSB
1
0.098
0.5
mV
%
VTS_ADC_RANGE
VTS_ADC_LSB
VTDIE_ADC_RANGE
VTDIE_ADC_LSB
ADC TS voltage range
ADC TS voltage LSB
20
0
80
%
ADC Die temperature range
ADC Die temperature LSB
150 °C
°C
I2C INTERFACE (SCL, SDA)
Input high threshold level, SDA and
SCL
VIH
Pull-up rail 1.8 V
1.3
V
VIL
Input low threshold level
Output low threshold level
High level leakage current
Pull-up rail 1.8 V
Sink current = 5 mA
Pull-up rail 1.8 V
0.4
0.4
1
V
V
VOL
IBIAS
uA
LOGIC I/O PIN (CD, PSEL)
VIH_CD
Input high threshold level, CD
1.3
1.3
V
V
VIL_CD
Input low threshold level, CD
High level leakage current, CD
Input high threshold level, PSEL
Input low threshold level, PSEL
High level leakage current, PSEL
0.4
IIN_BIAS_CD
VIH_PSEL
VIL_PSEL
IIN_BIAS_PSEL
Pull-up rail 1.8 V
Pull-up rail 1.8 V
2.5 uA
V
0.4
1
V
uA
LOGIC O PIN (/INT, /PG, STAT)
VOL
Output low threshold level
High level leakage current
Sink current = 5 mA
Pull-up rail 1.8 V
0.4
1
V
IOUT_BIAS
µA
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
VBUS/BAT POWER UP
VBUS rising above VBUS_OV threshold to
converter turn off
tVBUS_OV
VBUS OVP reaction time
Bad adapter detection duration
200
30
ns
tPOORSRC
BATTERY CHARGER
ms
tTERM_DGL
Deglitch time for charge termination
Charge current falling below ITERM
250
250
ms
ms
BAT voltage falling below VRECHG = 100
mV
tRECGH_DGL
Deglitch time for recharge threshold
Deglitch time for battery over-voltage
to disable charge
tBAT_OVP_DGL
1
µs
tTOP_OFF
tSAFETY
Typical Top-Off Timer Accuracy
Charge Safety Timer Accuracy
TOP_OFF_TIMER = 30 min
CHG_TIMER = 12 hours
24
30
12
36 min
10.8
13.2 hr
I2C INTERFACE
fSCL
SCL clock frequency
1000 kHZ
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Timing Requirements (continued)
PARAMETER
TEST CONDITIONS
MIN
10
0
NOM
MAX UNIT
ns
tSU_STA
tHD_DAT
trDA
Data set-up time
Data hold time
70 ns
80 ns
80 ns
Rise time of SDA signal
Fall time of SDA signal
10
10
tfDA
DIGITAL CLOCK AND WATCHDOG TIMER
fLPDIG
fDIG
Digital low power clock
Digital clock
REGN LDO disabled
18
30
45 kHZ
REGN LDO enabled
1.35
1.5
1.65 MHz
WATCHDOG[1:0] = 160 s, REGN LDO
disabled
tWDT
tWDT
Watchdog Reset time
Watchdog Reset time
100
136
160
160
sec
sec
WATCHDOG[1:0] = 160 s, REGN LDO
enabled
12
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
7.7 Typical Characteristics
CVBUS = 1µF, CPMID= 10µF, CSNS= 44µF, CBAT = 10µF, L = 1µH (DFE252012F-1R0) (unless otherwise specified)
95
94
93
92
91
90
89
88
87
86
85
95
94
93
92
91
90
89
88
87
86
85
VBAT = 7.6 V
VBAT = 8.0 V
VBAT = 7.6 V
VBAT = 8.0 V
0
0.2 0.4 0.6 0.8
1
Charge Current (A)
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
Charge Current (A)
1.2 1.4 1.6 1.8
2
D001
D001
VBUS = 5V
图 1. Charge Efficiency vs. Charge Current
VBUS = 5V
L = 1µH (IHLP2525CZER1R0k01)
图 2. Charge Efficiency vs. Charge Current
10
7.5
5
10
7.5
5
VBAT = 6.6 V
VBAT = 7.6 V
VBAT = 6.6 V
VBAT = 7.6 V
2.5
0
2.5
0
-2.5
-5
-2.5
-5
-7.5
-10
-7.5
-10
0
0.2 0.4 0.6 0.8
1
ICHG Setting (A)
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
ICHG Setting (A)
1.2 1.4 1.6 1.8
2
D004
D004
VBUS = 5V
VBUS = 5V
L = 1µH (IHLP2525CZER1R0k01)
图 3. Charge Current Accuracy vs. ICHG Setting
图 4. Charge Current Accuracy vs. ICHG Setting
0
-1
3.0
2.5
-40°C
-20°C
25°C
85°C
VBAT = 6.6 V
VBAT = 7.6 V
-2
2.0
-3
1.5
-4
-5
1.0
-6
0.5
-7
0.0
-8
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-9
-10
-11
-12
-13
-14
-15
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IINDPM Setting (A)
3.8
4.0
4.2
4.4
4.6
4.8
VINDPM Setting (V)
5.0
5.2
5.4
5.6
D012
D013
VBUS = 5.0V
VBAT = 7.6V
VBAT = 7.6V
图 6. Input Voltage Limit Accuracy vs. VINDPM Setting
图 5. Input Current Limit Accuracy vs. IINDPM Setting
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Typical Characteristics (接下页)
CVBUS = 1µF, CPMID= 10µF, CSNS= 44µF, CBAT = 10µF, L = 1µH (DFE252012F-1R0) (unless otherwise specified)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.15
ICHG = 0.5A
ICHG = 1.0A
ICHG = 1.4A
TREG = 60°C
TREG = 80°C
TREG = 100°C
TREG = 120°C
0.1
0.05
0
-0.05
50
60
70
80
90 100 110 120 130 140 150
Die Temperature (°C)
90
95
100
105
110
Die Temperature (°C)
115
120
125
130
D014
D015
VBUS = 5V
VBAT = 7.6V
图 7. TREG Profiles
ICHG = 100mA
VBUS =
5V
VBAT = ICHG = 0.5A, 1.0A, 1.4A
7.6V
图 8. Max Current Temperature Profile
14
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8 Detailed Description
8.1 Overview
The BQ25887 device is a highly integrated 2-A switch-mode battery charger for 2s Li-Ion and Li-Polymer battery.
It integrates the input blocking FET (Q1, QBLK), high-side switching FET (Q2, QHS), and low-side switching FET
(Q3, QLS). The device also integrates the boot-strap diode for high-side gate drive.
8.2 Functional Block Diagram
VBUS
PMID
VVBUS_UVLO_RISING
QBLK
(Q1)
+
UVLO
QBLK
CONTROL
REGN
BTST
REGN
REGN
LDO
EN_HIZ
+
VBUS_OVP
VVBUS_OV
VO,REF
SNS
QHS
(Q2)
VVBUS
VINDPM
SNS
6.2V
+
+
+
+
BAT_OVP
SW
BAT
+
IIN
BAT
+
VBAT_OVP
QLS
(Q3)
REGN
DC-DC
CONTROL
VBAT_REG
IINDPM
IC_TJ
TREG
ICHG
+
GND
ICHG_REG
EN_CHARGE
EN_HIZ
IQ3
+
+
Q3_OCP
GND
ILSOCP
VBTST œ VSW
REFRESH
VBTST_REFRESH
VPOORSRC
CONVERTER
CONTROL
STATE
+
+
POORSRC
VVBUS
SNS
REF
DAC
IC_TJ
TSHUT
MACHINE
TSHUT
IBUS
ILIM
RSNS
ICHG
VBUS
VBAT
PSEL
PG
USB
DETECTION
VCELLTOP
ADC
VCELLBOT
TDIE
BAT
VTS
BQ25887
QCBH
VREG - VRECHG
BAT
RECHRG
+
+
MID
STAT
ICHG
ITERM
TERMINATION
BATLOWV
CBSET
CHARGE
CONTROL
STATE
QCBL
VBAT_LOWV
BAT
+
+
MACHINE
INT
VBAT_UVLO_RISING
BAT
BATUVLO
BATTERY
SENSING
THERMISTOR
VTS
I2C
INTERFACE
TS_SUSPEND
TS
SCL
SDA
CD
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8.3 Feature Description
8.3.1 Device Power-On-Reset
The internal bias circuits are powered from either VBAT or VBUS when it rises above VVBUS_UVLO_RISING or
VBAT_UVLO_RISING. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
8.3.2 Device Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the boost converter is started. The power up
sequence from input source is as listed:
1. Poor Source Qualification
2. Input Source Type Detection based on PSEL to set default Input Current Limit (IINDPM) register and input
source type
3. Power Up REGN LDO
4. Converter Power-up
8.3.2.1 Poor Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to start the boost converter.
1. VBUS voltage below VVBUS_OVP
2. VBUS voltage above VPOORSRC when pulling IPOORSRC (typical 15mA)
If VBUS_OVP is detected (condition 1 above), the device automatically retries detection once the over-voltage fault
goes away. If a poor source is detected (condition 2 above), the device repeats poor source qualification routine
every 2 seconds. After 7 consecutive failures, the device sets VBUS_STAT[2:0] = '0b100', EN_HIZ = 1, and goes
to HIZ mode. On BQ25887 adapter re-plugin and/or EN_HIZ bit toggle is required to restart device operation.
The EN_HIZ bit is cleared automatically when the adapter is plugged in. If the fault is not removed, the part will
enter HIZ mode again after the 7 consecutive failures.
8.3.2.2 Input Source Type Detection
After the PG_STAT bit is set and input source is qualified, the charger device runs input source type detection
when AUTO_INDET_EN bit is set.
The BQ25887 sets input current limit through PSEL pin. After input source type detection, the following registers
and pins are changed:
1. Input Current Limit (IINDPM) register is changed to set current limit
2. Input Voltage Limit (VINDPM) register is changed to set default limit (if EN_VINDPM_RST = 1, otherwise
VINDPM value remains unchanged)
3. VBUS_STAT bits change to reflect the detected source
4. INT pin pulses to notify the host
5. PG pin is pulled LOW, and PG_STAT bit is set to '1'
After detection is completed, the host can over-write IINDPM or VINDPM registers to change the input current, or
input voltage limit if needed. The charger input current is always limited by the lower of IINDPM register , ILIM
pin, or Input Current Optimizer (ICO) setting when ICO is enabled.
When AUTO_INDET_EN is disabled, the Input Source Type Detection is bypassed, and the Input Current Limit
(IINDPM) register remains unchanged from previous value. When EN_VINDPM_RST is disabled, the Input
Voltage Limit (VINDPM) register remains unchanged from previous value.
8.3.2.2.1 PSEL Sets Input Current Limit
The BQ25887 has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB
PHY device output to decide whether the input is USB host or charging port. PSEL HIGH sets the input current
limit to 500 mA and PSEL LOW sets the input current limit to 3 A. Automatic start ICO is disabled when PSEL is
HIGH. When no input source is connected, input current limit will not be updated by PSEL change.
16
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Feature Description (接下页)
During default mode, after input source type detection is completed with an input source already plugged in, the
PSEL pin is monitored. When the pin status changes, the input current limit is changed based on the pin status.
During host mode, after input source type detection is completed with an input source already plugged in, the
PSEL pin is NOT monitored. The host needs to set the FORCE_INDET bit to 1 in order to read the PSEL value.
After the detection is completed, the input current limit (IINDPM), and the VBUS_STAT bits can be changed due
to the detection result.
8.3.2.2.2 Force Input Current Limit Detection
In host mode, the host can force the device to run Input Current Limit Detection by setting FORCE_INDET bit.
After the detection is completed, FORCE_INDET bit returns to 0 by itself and input result is updated.
8.3.2.3 Power Up REGN Regulator (LDO)
The REGN LDO supplies internal bias circuits as well as the QHS and QLS gate drive. The LDO also provides
bias rail to TS external resistors. The pull-up rail of STAT and PG can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid.
1. VBUS above VVBUS_UVLO_RISING in boost mode or VBUS below VVBUS_UVLO_RISING in buck mode
2. Poor Source Qualification detects a valid input source
3. Input Source Type Detection completes and sets appropriate input current limit
4. After 220-ms delay is complete
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device
is in HIZ.
8.3.2.4 Converter Power Up
After the input current limit is set, the PG pin is pulled LOW, the PG_STAT and VBUS_STAT bits are changed,
and the converter is enabled, allowing the QHS and QLS to start switching. Before charging begins, the battery
discharge source (IBAT_DISCHG) is enabled automatically to detect the presence of battery. The host can
enable IBAT_DISCHG via the EN_BAT_DISCHG bit at any point during operation, including in Battery Only or
HIZ modes. The device provides soft-start when converter output voltage is ramped up.
As a battery charger, the device deploys a highly efficient 1.5-MHz boost switching regulator. The fixed frequency
oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,
charge current and temperature, simplifying output filter design.
In order to improve light-load efficiency, the device switches to PFM (Pulse Frequency Modulation) control at light
load when battery is below 6.4V or charging is disabled. During the PFM operation, the switching duty cycle is
set by the ratio of SNS and VBUS.
8.3.3 Input Current Optimizer (ICO)
The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without
overloading the input source. The algorithm automatically identifies maximum input current limit of a power
source without staying in VINDPM to avoid input source overload.
On BQ25887, this feature is enabled by default (EN_ICO = 1) and can be disabled by setting EN_ICO bit to 0.
After DCP type input source is detected based on the procedures describe above (Input Source Type Detection).
The algorithm runs automatically when EN_ICO bit is set. The algorithm can also be forced to execute by setting
FORCE_ICO bit regardless of input source type detected .
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Feature Description (接下页)
表 1. Input Current Optimizer Automatic Operation
INPUT CURRENT LIMIT
(IINDPM)
AUTOMATIC START ICO
DEVICE
INPUT SOURCE
ALGORITHM
PSEL = HI
500 mA
3.0 A
Disable
BQ25887
PSEL = LOW
Enable
The actual input current limit used by the Dynamic Power Management is reported in ICO_ILIM register while
Input Current Optimizer is enabled (EN_ICO = 1) or set by IINDPM register when the algorithm is disabled
(EN_ICO = 0). In addition, the current limit is clamped by ILIM pin unless EN_ILIM bit is 0 to disable ILIM pin
function.
When the algorithm is enabled, it runs continuously to adjust input current limit of Dynamic Power Management
(IINDPM) using ICO_ILIM register until ICO_STAT[1:0] and ICO_FLAG bits are set (the ICO_FLAG bit indicates
any change in ICO_STAT[1:0] bits). The algorithm operates depending on battery voltage:
1. When voltage at BAT pin is below 6.2 V, the algorithm starts ICO_ILIM register with IINDPM which is the
maximum input current limit allowed by system
2. When voltage at BAT is above 6.2 V, the algorithm starts ICO_ILIM register with 500mA which is the
minimum input current limit to minimize adapter overload
When optimal input current is identified, the ICO_STAT[1:0] and ICO_FLAG bits are set to indicate input current
limit in ICO_ILIM register would not be changed until the algorithm is forced to run by the following event (these
events also reset the ICO_STAT[1:0] bits to '01'):
1. A new input source is plugged-in, or EN_HIZ bit is toggled
2. IINDPM register is changed
3. VINDPM register is changed
4. FORCE_ICO bit is set to 1
5. VBUS_OVP event
8.3.4 Battery Charging Management
The BQ25887 charges 2-cell Li-Ion battery with up to 2.2-A charge current for high capacity battery.
8.3.4.1 Autonomous Charging Cycle
When battery charging is enabled (EN_CHG = 1 and CD pin is LOW;), the device autonomously completes a
charging cycle without host involvement. The device default charging parameters are listed in 表 2 below. On
BQ25887, the host can always control the charging operation and optimize the charging parameters by writing to
the corresponding registers through I2C.
表 2. Charging Parameter Default Settings
DEFAULT MODE
Charging Voltage
Charging Current
Pre-Charge Current
Termination Current
Temperature Profile
Safety Timer
BQ25887
4.2V/Cell
1.50 A
150 mA
150 mA
JEITA
12 hours
Disabled
Topoff Timer
A new charge cycle starts when the following conditions are valid:
1. Converter starts
2. Battery charging is enabled by I2C register bit (EN_CHG = 1 and CD pin is LOW and ICHG register is not 0
mA)
3. No thermistor fault on TS
4. No safety timer fault
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The charger automatically terminates the charging cycle when the charging current is below termination
threshold, charge voltage is above recharge threshold, and device is not in DPM mode or thermal regulation.
When
a
full battery voltage is discharged below recharge threshold (threshold selectable via
VCELL_RECHG[1:0] bits on BQ25887), the device automatically starts a new charging cycle. After the charge is
done, toggle CD pin or EN_CHG bit can initiate a new charging cycle.
The STAT output indicates the charging status of: charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). If no battery is connected, the STAT pin blinks as capacitance connected at BAT
charges, discharges, then recharges. The STAT output can be disabled by setting STAT_DIS bit. In addition, the
status register (CHRG_STAT) indicates the different charging phases as:
•
•
•
•
•
•
•
000 – Not Charging
001 – Trickle Charge (VBAT < VBAT_SHORT
010 – Pre-charge (VBAT_SHORT < VBAT < VBAT_LOWV
011 – Fast-charge (CC mode)
100 – Taper Charge (CV mode)
101 – Top-off Timer Charging
110 – Charge Termination Done
)
)
When the charger transitions to any of these states, including when charge cycle is completed, an INT is
asserted to notify the host.
8.3.4.2 Battery Charging Profile
The device charges the battery in five phases: trickle charge, pre-charge, constant current, constant voltage, and
top-off timer charging (optional). At the beginning of a charging cycle, the device checks the battery voltage and
regulates current/voltage accordingly.
表 3. Default Charging Current Setting
VBAT
< VCELL_SHORT
CHARGING CURRENT
IBAT_SHORT
IPRECHG
REGISTER DEFAULT SETTING
CHRG_STAT
100 mA
150 mA
1500 mA
001
010
011
VCELL_SHORT – VCELL_LOWV
> VCELL_LOWV
ICHG
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If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. In this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate, as explained in the Charging Safety Timer section.
Regulation Voltage
VCELLREG[7:0]
Battery Voltage
Charge Current
ICHG[5:0]
Charge Current
VBATLOWV
VBAT_SHORT
IPRECHG[3:0]
ITERM[3:0]
IBAT_SHORT
Trickle Charge
001
Pre-charge
010
Fast-Charge
CC
Taper-Charge
CV
Top-off Timer
(optional)
CHRG_STAT[2:0]
011
101
110
100
Precharge Timer
(2hrs)
Safety Timer
CHG_TIMER[1:0]
图 9. Battery Charging Profile
8.3.4.3 Cell Balancing During Charging
Some applications require cell balancing when the user can replace one or both of the cells in the 2S1P
configuration. When charging two batteries with different voltages, cell balancing is required, as the cell with the
higher voltage is at risk of being overcharged. For extremely unbalanced cells, charging the lower voltage cell as
well as fast cell balancing is desired.
The BQ25887 implements a passive cell balancing scheme with a recommended maximum discharge current of
400 mA. Balancing current is limited by external resistors placed between the CBSET pin and the mid-point of
the two cells. Low side cell voltage is sensed at MID pin. Cell balancing can be enabled in the I2C registers.
The Cell Balancing current limit resistor, RCBSET, can be calculated as below.
ICB_LIM = VCELLREG / (RCBSET+RDSON_QCBX
)
For example, the maximum recommended cell balancing current is 400 mA. For 4.2-V battery cell, RCBSET can be
calculated as 9.5 Ω (typical).
Cell balancing status register, CB_STAT, HS_CV_STAT and LS_CV_STAT is active in both automatic cell
balancing mode and manual cell balancing mode.
The default setting of the cell balancing parameters are below.
表 4. Cell Balancing Default Setting
PARAMETER
REGISTER
DEFAULT VALUE
Enable Auto Cell Balancing Mode
(CB_AUT0_EN)
REG0x2A [6]
1 = Enable
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表 4. Cell Balancing Default Setting (接下页)
PARAMETER
REGISTER
DEFAULT VALUE
Disable Charge for Accurate Cell Balancing
Measurement (CB_CHG_DIS)
1 = Charge Disable for Cell Balancing
Voltage Measurement
REG0x2A [7]
Voltage Threshold Enter Cell Balancing
Qualification Mode from Pre-Qualification
Mode (VQUAL_TH)
REG0x29h [7:4]
1111 = Disable Pre-Qualification Mode
Voltage Threshold Enter Cell Balancing
Active Mode from Qualification Mode
(VDIFF_START)
REG0x29h [3:0]
REG0x28 [ 7:5]
REG0x0x28 [4]
0100 = 80 mV
001 = 40 mV
0 = 2 min
Voltage Threshold Exit Cell Balancing Offset
from VDIFF_START (VDIFF_END_OFFSET)
Time Interval between Taking Measurements
in Pre-Qualification
Mode(TCB_QUAL_INTERVAL)
Time Interval between Taking Measurements
in Cell Balancing Active Mode
(TCB_ACTIVE)
REG0x28 [3:2]
REG0x28 [1]
10 = 2 min
10 = 1 sec
Time Delay between Charge Disable and
Cell Voltage Measurement (TSETTLE)
Qualifica-
tion
Cell Balancing Active
VDIFF_END
Exit Cell Balancing
Tickle Charge
VCELL_REG
Pre-Charge
Pre-Qual
Normal
Charge
VDIFF_START
VQUAL_TH
VCBEN
3.7
V
VCELL_LOWV
3V
VCELL_SHORT
2.2V
ICHG
ITERM
IPRECHG
IBAT_UVLOZ
0A
TCB_Active
TCB_QUAL_INTERVAL
TSETTLE+measur
ement time
图 10. Cell Balancing Timing Diagram
8.3.4.4 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current.
When termination occurs, the STAT pin goes HIGH (charge current will continue to taper if top-off timer is
enabled), status register CHRG_STAT is set to 110, and an INT pulse is asserted to the host. Termination is
temporarily disabled when the charger device is in input current, voltage or thermal regulation. Termination can
be permanently disabled by writing 0 to EN_TERM bit prior to charge termination.
At low termination currents (50 mA - 100 mA), due to the comparator offset, the actual termination current may
be up to 20% higher than the termination target. In order to compensate for comparator offset, a programmable
top-off timer (default disabled) can be applied after termination is detected.The top-off timer will follow safety
timer constraints, such that if safety timer is suspended, so will the top-off timer. Similarly, if safety timer is
doubled, so will the top-off timer. CHRG_STAT reports whether the top off timer is active via the 101 code. Once
the Top-Off timer expires, the CHRG_STAT register is set to 110 and an INT pulse is asserted to the host.
Top-off timer gets reset (set to 0 and counting resumes when appropriate) for any of the following conditions:
1. Charge disable to enable
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2. Termination status low to high
3. REG_RST register bit is set (disables top-off timer)
The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer
value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host
when entering top-off timer segment as well as when top-off timer expires. All charge cycle related INT pulses
(including top-off timer INT pulses) can be masked by CHRG_MASK bit.
8.3.4.5 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
8.3.4.5.1 JEITA Guideline Compliance in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range. At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge
current or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V / cell.
On BQ25887, the charger provides flexible voltage/current settings beyond JEITA requirement. The Voltage
setting at warm temperature (T3-T5) can be VCELLREG, 4.0 V, 4.15 V, or charge suspended (configured by
JEITA_VSET [1:0]). The fast charge current setting at warm temperature (T3-T5) can be 100%, or 40% of fast
charge current, ICHG (configured by JEITA_ISETH). The fast charge current setting at cool temperature (T1-T2)
can be 100%, 40%, or 20% of fast charge current, ICHG, or charge suspend (configured by JEITA_ISETC[1:0]).
Whenever the charger detects "warm" or "cool" temperature, termination is automatically disabled regardless of
JEITA_VSET, JEITA_ISETH and JEITA_ISETC register bit settings.
REGN
TS
BQ2588x
图 11. TS Resistor Network
ISETC=11
VSET =11
ISETH=1
100%
VREG
80%
60%
40%
20%
VSET =10
VSET = 01
4.15V
4.0V
ISETC=10
ISETC=01
ISETC=00
ISETH=0
VSET = 00
T1
0°C
T2
10°C
T3
45°C
T5
60°C
T1
0°C
T2
10°C
T3
45°C
T5
60°C
TS Temperature
TS Temperature
图 12. TS Charging Values
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Assuming a 103AT NTC (Negative Temperature Coefficient) thermistor on the battery pack as shown above, the
value of RT1 and RT2 can be determined by:
≈
∆
«
’
÷
◊
1
1
RNTC,T1 ì RNTC,T 5
ì
-
VT 5 VT1
RT2 =
RT1=
≈
∆
«
’
≈
’
÷
◊
1
1
RNTC,T1
ì
-1 - R
ì
-1
÷
∆
«
NTC,T 5
VT1
VT 5
◊
(1)
(2)
1
-1
VT1
1
1
+
RT 2 RNTC,T1
Select 0°C to 60°C range for Li-ion or Li-polymer battery:
RNTC,T1 = 27.28 kΩ
RNTC,T5 = 3.02 kΩ
RT1 = 5.24 kΩ
RT2 = 30.31 kΩ
8.3.4.6 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault
register TMR_STAT bit is set to 1, and an INT pulse is asserted to the host. The safety timer feature can be
disabled by clearing EN_TIMER bit.
During input voltage, current or thermal regulation or cell balancing active mode (cell balancing discharging), the
safety timer counts at half clock rate as the actual charge current is likely to be below the register setting. For
example, if the charger is in input current regulation (IINDPM_STAT=1) throughout the whole charging cycle, and
the safety timer is set to 12 hours, then the timer will expire in 24 hours. This half clock rate feature can be
disabled by setting TMR2X_EN = 0. Changing the TMR2X_EN bit while the device is running has no effect on
the safety timer count, other than forcing the timer to count at half the rate under the conditions dictated above.
During faults which disable charging, or supplement mode, timer is suspended. Since the timer is not counting in
this state, the TMR2X_EN bit has no effect. Once the fault goes away, safety timer resumes. If the charging
cycle is stopped and started again, the timer gets reset.
The safety timer is reset for the following events:
1. Charging cycle stop and restart (toggle CD pin, EN_CHG bit, or charged battery falls below recharge
threshold).
2. BAT voltage changes from pre-charge to fast-charge or vice versa (in host-mode or default mode).
The precharge safety timer (fixed 2hr counter that runs when VBAT < VBAT_LOWV), follows the same rules as the
fast-charge safety timer in terms of getting suspended, reset, and counting at half-rate when TMR2X_EN is set.
8.3.5 Integrated 16-Bit ADC for Monitoring
The device includes a 16-bit ADC to monitor critical system information based on the device’s modes of
operation. The control of the ADC is done through the ADC Control Register (Address = 15h) [reset = 30h]. The
ADC_EN bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE bit allows
continuous conversion or one-shot behavior. After a one-shot conversion finishes, the ADC_EN bit is cleared,
and must be re-asserted to start a new conversion.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if either the
VVBUS>VVBUS_UVLO_RISING or VBAT>VBAT_UVLO_RISING is valid. If no adapter is present, and the VBAT is less than
VBAT_UVLO_RISING, the device will not perform an ADC measurement, nor update the ADC read-back values in
REG17 through REG24. Additionally, the device will immediately reset ADC_EN bit without sending any interrupt.
The same will happen if the ADC is enabled when all ADC channels are disabled. It is recommended to read
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back ADC_EN after setting it to '1' to ensure ADC is running a conversion. If the charger changes mode (for
example, if adapter is connected, EN_HIZ goes to '1', or CD goes high,) while an ADC conversion is running, the
conversion is interrupted. Once the mode change is complete, the ADC resumes conversion, starting with the
channel where it was interrupted. When device is in HIZ mode, ADC conversion can still be enabled through I2C.
In HIZ mode, device power up internally to start ADC convertion and turn back down when ADC conversion is
completed.
When TS_ADC conversion performs in battery only mode, the REGN is powered and extra battery current would
be drawn. Battery current can be kept low by disabling the TS_ADC conversion in battery only mode.
The integrated ADC has two rate conversion options: a one-shot mode and a continuous conversion mode set by
the ADC_RATE bit. By default, all ADC parameters will be converted in one-shot or continuous conversion mode
unless disabled in the ADC Function Disable Register (Address = 16h) [reset = 00h]. If an ADC parameter is
disabled by setting the corresponding bit in REG16, then the read-back value in the corresponding register will
be from the last valid ADC conversion or the default POR value (all zeros if no conversions have taken place). If
an ADC parameter is disabled in the middle of an ADC measurement cycle, the device will finish the conversion
of that parameter, but will not convert the parameter starting the next conversion cycle. Even though no
conversion takes place when all ADC measurement parameters are disabled, the ADC circuitry is active and
ready to begin conversion as soon as one of the bits in the ADC Function Disable register is set to ‘0’. If all
channels are disabled in one-shot conversion mode, the ADC_EN bit is cleared.
The ADC_DONE_STAT and ADC_DONE_FLAG bits signal when a conversion is completed in one-shot mode
only. This event produces an INT pulse, which can be masked with ADC_DONE_MASK. During continuous
conversion mode, the ADC_DONE_STAT bit has no meaning and will be '0'. The ADC_DONE_FLAG bit will
remain unchanged in continuous conversion mode.
ADC conversion operates independently of the faults present in the device. ADC conversion will continue even
after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set
ADC_EN = ‘0’ to disable the ADC. ADC conversion is interrupted upon adapter plug-in, and will only resume until
after Input Source Type Detection is complete. ADC readings are only valid for DC states and not for transients.
When host writes ADC_EN = 0, the ADC stops immediately, and ADC measurement values correspond to last
valid ADC reading.
A recommended method to exit ADC conversion is described below:
1. Write ADC_RATE to one-shot, and the ADC will stop at the end of a complete cycle of conversions, or
2. Disable all ADC conversion channels, and the ADC will stop at the end of the current measurement.
8.3.6 Status Outputs
8.3.6.1 Power Good Indicator (PG)
The PG_STAT bit goes HIGH and open drain PG pin goes low to indicate a good input source when:
1. VBUS above VVBUS_UVLO_RISING
2. VBUS below VVBUS_OV threshold
3. VBUS above VPOORSRC (typ. 3.7 V) when IPOORSRC (typ. 30 mA) current is applied (not a poor source)
4. Input Source Type Detection is completed
5. CD pin is LOW
8.3.6.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin
function can be disabled via the STAT_DIS bit.When CD is high, the device is in HIZ mode and STAT will not
reflect charging state.
表 5. STAT Pin State
CHARGING STATE
STAT INDICATOR
Charging in progress (including trickle charge, pre-charge, fast-
charge, recharge)
LOW
Charging complete (including top-off)
Sleep mode, charge disable
HIGH
HIGH
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表 5. STAT Pin State (接下页)
CHARGING STATE
STAT INDICATOR
Charge suspend (Input over-voltage, TS fault, timer fault or battery
over-voltage)
Blinking at 1Hz
8.3.6.3 Interrupt to Host
In some applications, the host does not always monitor the charger operation. The INT pin notifies the system
host on the device operation. By default, the following events will generate an active-low, 256-µs INT pulse.
1. Good input source detected
–
–
VVBUS < VVBUS_OV threshold
VVBUS > VPOORSRC (typ. 3.7 V) when IPOORSRC (typ. 30 mA) current is applied (not a poor source)
2. VBUS_STAT changes state (VBUS_STAT any bit change)
3. Good input source removed
4. Entering IINDPM regulation
5. Entering VINDPM regulation
6. Entering IC junction temperature regulation (TREG)
7. I2C Watchdog timer expired
–
At initial power up, this INT gets asserted to signal I2C is ready for communication
8. Charger status changes state (CHRG_STAT value change), including Charge Complete
9. TS_STAT changes state (TS_STAT any bit change)
10. VBUS over-voltage detected (VBUS_OVP)
11. Junction temperature shutdown (TSHUT)
12. Cell over-voltage detected (CELLOVP)
13. Cell over-voltage detected (HS_OV or LS_OV)
14. Charge safety timer expired
15. A rising edge on any of the *_STAT bits
Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur.
Three bits exist for each one of these events:
•
•
•
The STAT bit holds the current status of each INT source
The FLAG bit holds information on which source produced an INT, regardless of the current status
The MASK bit is used to prevent the device from sending out INT for each particular event
When one of the above conditions occurs (a rising edge on any of the *_STAT bits), the device sends out an INT
pulse and keeps track of which source generated the INT via the FLAG registers. The FLAG register bits are
automatically reset to zero after the host reads them, and a new edge on STAT bit is required to re-assert the
FLAG.
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IINDPM_STAT
IINDPM_FLAG
TREG_STAT
TREG_FLAG
INT
I2C Flag Read
图 13. INT Generation Behavior Example
8.3.7 Input Current Limit on ILIM Pin
For safe operation, the BQ2588x has an additional hardware pin on ILIM to limit maximum input current. The
maximum input current is set by a resistor from ILIM pin to ground as:
KILIM
=
I
INMAX
RILIM
(3)
The actual input current limit is the lower value between ILIM pin setting and register setting (IINDPM). For
example, if the register setting is 3.3 A (0x1C), and ILIM has a 820-Ω resistor (KILIM = 1276 max) to ground for
1.55 A, the input current limit is 1.55 A. ILIM pin can be used to set the input current limit rather than the register
settings when EN_ILIM bit is set. The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the
device enters input current regulation (refer to section). Entering IINDPM through ILIM pin sets the
IINDPM_STAT and FLAG bits, and produces and interrupt to host. The interrupt can be masked via the
IINDPM_MASK bit.
The ILIM pin can also be used to monitor input current when EN_ILIM is set. The voltage on ILIM pin is
proportional to the input current. ILIM can be used to monitor input current with the following relationship:
K
ìV
ì0.8V
ILIM
ILIM
I
=
IN
R
ILIM
(4)
For example, if ILIM pin is set with 820-Ω resistor, and the ILIM voltage 0.5V, the actual input current is 0.795 A
to 0.973 A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 0.8 V. If ILIM pin
is shorted, the input current limit is set by the register.
The ILIM pin function can be disabled by setting the EN_ILIM bit to 0. When the pin is disabled, both input
current limit function and monitoring function are not available.
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8.3.8 Voltage and Current Monitoring
The device closely monitors the input voltage, as well as internal FET currents for safe boost and buck mode
operation.
8.3.8.1 Voltage and Current Monitoring in Boost Mode
8.3.8.1.1 Input Over-Voltage Protection
The valid input voltage range for boost mode operation is VVBUS_OP. If VBUS voltage exceeds VVBUS_OV, the
device stops switching immediately to protect the power FETs. During input over-voltage, an INT pulse is
asserted to signal the host, and the VBUS_OVP_STAT and VBUS_OVP_FLAG fault registers get set. The
device automatically starts switching again when the over-voltage condition goes away.
8.3.8.1.2 Input Under-Voltage Protection
The valid input voltage range for boost mode operation is VVBUS_OP. If VBUS voltage falls below VPOORSRC during
operation, the device stops switching. During input under-voltage, an INT pulse is asserted to signal the host,
and the PG_STAT bit gets cleared. The PG_FLAG bit will get set to signal this event. The device automatically
attempts to restart switching when the under-voltage condition goes away.
8.3.9 Thermal Regulation and Thermal Shutdown
8.3.9.1 Thermal Protection in Boost Mode
The device monitors internal junction temperature, TJ, to avoid overheating and limits the IC surface temperature
in boost mode. When the internal junction temperature exceeds the preset thermal regulation limit (TREG bits),
the device reduces charge current. A wide thermal regulation range from 60°C to 120°C allows optimization for
the system thermal performance.
During thermal regulation, the actual charging current is usually below the programmed value in ICHG registers.
Therefore, termination is disabled, the safety timer runs at half the clock rate, the status register TREG_STAT bit
goes high, and an INT is asserted to the host.
Additionally, the device has thermal shutdown to turn off the converter when IC surface temperature exceeds
TSHUT. The fault register bits TSHUT_STAT and TSHUT_FLAG are set and an INT pulse is asserted to the host.
The converter turns back on when IC temperature is below TSHUT_HYS
.
8.3.10 Battery Protection
8.3.11 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA), and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is a device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 0x6A, receiving control inputs from the master device like
micro-controller or digital signal processor through REG00 – REG2C. Register read beyond REG2C (0x2C),
returns 0xFF. The I2C interface supports both standard mode (up to 100kbits/s), and fast mode (up to 400
kbits/s). When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be
connected to the positive supply voltage via a current source or pull-up resistor.
8.3.11.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on SCL line is LOW. One clock pulse is generated for each data
bit transferred.
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SDA
SCL
Data line stable;
Data valid
Change of
data allowed
图 14. Bit Transfers on the I2C bus
8.3.11.2 START and STOP Conditions
All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SCL
SDA
SCL
STOP (P)
图 15. START and STOP conditions on the I2C bus
START (S)
8.3.11.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the Most
Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, it can hold the SCL line low to force the master into a wait state (clock
stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL
line.
28
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Acknowledgeme
nt signal from
receiver
Acknowledgement
signal from slave
MSB
1
SDA
2
7
8
9
1
2
8
9
SCL S or Sr
P or Sr
ACK
ACK
START or
Repeated
START
STOP or
Repeate
d START
图 16. Data Transfer on the I2C Bus
8.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The ACK signaling takes place after byte. The ACK bit allows the receiver to signal the transmitter that the byte
was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock
pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this 9th clock pulse.
A NACK is signaled when the SDA line remains HIGH during the 9th clock pulse. The master can then generate
either a STOP to abort the transfer or a repeated START to start a new transfer.
8.3.11.5 Slave Address and Data Direction Bit
After the START signal, a slave address is sent. This address is 7 bits long, followed by the 8 bit as a data
direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
The device 7-bit address is defined as 1101 011' (0x6B) by default. The address bit arrangement is shown
below.
Slave Address
1
1
0
1
0
1
1
R/W
图 17. 7-Bit Addressing (0x6B)
SDA
SCL
S
8
9
8
9
8
9
P
1-7
1-7
1-7
DATA
START
ADDRESS
R/W ACK
DATA
ACK
ACK
STOP
图 18. Complete Data Transfer on the I2C Bus
8.3.11.6 Single Write and Read
图 19. Single Write
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图 20. Single Read
If the register address is not defined, the charger IC sends back NACK and returns to the idle state.
8.3.11.7 Multi-Write and Multi-Read
The charger device supports multi-read and multi-write of all registers.
图 21. Multi-Write
图 22. Multi-Read
8.4 Device Functional Modes
8.4.1 Host Mode and Default Mode
The BQ2588x is a host controlled charger, but it can operate in default mode without host management. In
default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode.
When the charger is in default mode, WD_STAT bit is HIGH. When the charger is in host mode, WD_STAT bit is
LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings. During default mode, any change on PSEL pin will make real time internal
reference change.
In default mode, the device keeps charging the battery with default 12-hour fast charging safety timer.
A I2C write to the registers transitions the charger from default mode to host mode and watchdog timer is reset.
All the device parameters can be programmed by the host. To keep the device in host mode, the host has to
reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set), or
disable watchdog timer by setting WATCHDOG bits = 00.
30
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Device Functional Modes (接下页)
When the watchdog timer (WD_STAT bit = 1) is expired, the device returns to default mode and all registers are
reset to default values except as detailed in the Register Maps section. The Watchdog timer will be reset on any
write if the watchdog timer has expired.
POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Start watchdog timer
Host programs registers
Y
I2C Write?
N
Default Mode
Reset watchdog timer
Reset selective registers
Y
N
WD_RST bit = 1?
N
N
Y
Y
I2C Write?
Watchdog Timer
Expired?
图 23. Watchdog Timer Flow Chart
8.5 Register Maps
Default I2C Slave Address: 0x6B (1101 011B + R/W)
表 6. I2C Registers
Address
00h
Access Type
Acronym
REG00
REG01
REG02
REG03
REG04
REG05
REG06
REG07
REG08
REG09
REG0A
REG0B
REG0C
REG0D
REG0E
Register Name
Section
Go
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Cell Voltage Limit
Charge Current Limit
Input Voltage Limit
Input Current Limit
Precharge and Termination Control
Charger Control 1
Charger Control 2
Charger Control 3
Charger Control 4
Reserved
01h
Go
02h
Go
03h
Go
04h
Go
05h
Go
06h
Go
07h
Go
08h
Go
09h
Go
0Ah
0Bh
0Ch
0Dh
0Eh
ICO Current Limit
Charger Status 1
Charger Status 2
NTC Status
Go
R
Go
R
Go
R
Go
R
FAULT Status
Go
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表 6. I2C Registers (接下页)
Address
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
Access Type
Acronym
REG0F
REG10
REG11
REG12
REG13
REG14
REG15
REG16
REG17
REG18
REG19
REG1A
REG1B
REG1C
REG1D
REG1E
REG1F
REG20
REG21
REG22
REG23
REG24
REG25
REG26
REG27
REG28
REG29
REG2A
REG2B
REG2C
Register Name
Charger Flag 1
Charger Flag 2
Fault Flag
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
R
R
R
R/W
R/W
R/W
R/W
R/W
R
Charger Mask 1
Charger Mask 2
Fault Mask
ADC Control
ADC Function Disable
IBUS ADC1
R
IBUS ADC0
R
ICHG ADC1
R
ICHG ADC0
R
VBUS ADC1
R
VBUS ADC0
R
VBAT ADC1
R
VBAT ADC0
R
VCELLTOP ADC1
VCELLTOP ADC0
TS ADC1
R
R
R
TS ADC0
R
TDIE ADC1
R
TDIE ADC0
R/W
R
Part Information
VCELLBOT ADC1
VCELLBOT ADC0
Cell Balancing Control 1
Cell Balancing Control 2
Cell Balancing Status and Control
Cell Balancing Flag
Cell Balancing Mask
R
R/W
R/W
R/W
R
R/W
Complex bit access types are encoded to fit into small table cells. 表 7 shows the codes that are used for access
types in this section.
表 7. I2C Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset Value
-n
Value after reset
Undefined value
-X
32
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8.5.1 Cell Voltage Regulation Limit Register (Address = 00h) [reset = A0h]
REG00 is shown in 图 24 and described in .
Return to Summary Table.
图 24. REG00 Register
Bit
7
6
5
4
3
2
1
0
Field
VCELLREG[7:0]
表 8. REG00 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VCELLREG[7]
VCELLREG[6]
VCELLREG[5]
VCELLREG[4]
VCELLREG[3]
VCELLREG[2]
VCELLREG[1]
VCELLREG[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
640 mV
320 mV
160 mV
80 mV
40 mV
20 mV
10 mV
5 mV
Cell Charge voltage limit
Offset: 3.40 V
Range: 3.40 V to 4.60 V
Default 4.20 V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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8.5.2 Charger Current Limit Register (Address = 01h) [reset = 5Eh]
REG01 is shown in 图 25 and described in 表 9.
Return to Summary Table.
图 25. REG01 Register
Bit
7
6
5
4
3
2
1
0
Field
EN_HIZ
EN_ILIM
ICHG[5:0]
表 9. REG01 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
EN_HIZ
R/W
Yes
Yes
Enable HIZ Mode:
0 – Disable (default)
1 – Enable
6
EN_ILIM
R/W
Yes
Yes
Enable ILIM Pin Function:
0 – Disable
1 – Enable (default)
5
4
3
2
1
0
ICHG[5]
ICHG[4]
ICHG[3]
ICHG[2]
ICHG[1]
ICHG[0]
R/W
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1600 mA
800 mA
400 mA
200 mA
100 mA
50 mA
Fast Charge Current Limit
Offset: 0 mA
Range: 100 mA – 2200 mA
Default 1500 mA
Note: ICHG > 2.2 A (2Ch) clamped to 2.2 A. ICHG < 100 mA (01h)
clamped at 100 mA
34
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8.5.3 Input Voltage Limit Register (Address = 02h) [reset = 84h]
REG02 is shown in 图 26 and described in 表 10.
Return to Summary Table.
图 26. REG02 Register
Bit
7
6
5
4
3
2
1
0
Reset
Field
1h
0h
0h
04h
EN_VINDPM_R EN_BAT_DISC PFM_OOA_DIS
ST HG
VINDPM[4:0]
表 10. REG02 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
EN_VINDPM_RST
R/W
Yes
Yes
Enable VINDPM automatic reset upon adapter plugin:
0 – Disable VINDPM reset when adapter is plugged in
1 – Enable VINDPM reset when adapter is plugged in (VINDPM resets to default
value after Input Source Type Detection) (Default)
6
5
EN_BAT_DISCHG
PFM_OOA_DIS
R/W
R/W
Yes
Yes
Yes
No
Enable BAT pin discharge load (IBAT_DISCHG):
0 – Disable load (Default)
1 – Enable BAT discharge load
PFM Out-of-Audio (OOA) Mode Disable:
0 – Out-of-audio mode enabled while converter is in PFM (Default)
1 – Out-of-audio mode disabled while converter is in PFM
4
3
2
1
0
VINDPM[4]
VINDPM[3]
VINDPM[2]
VINDPM[1]
VINDPM[0]
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
1600 mV
800 mV
400 mV
200 mV
100 mV
Absolute Input Voltage Limit:
Offset: 3.9 V
Range: 3.9 V – 5.5 V
Default: 4.3 V
Note: VINDPM > 5.5 V (10h) clamped to 5.5 V. VINDPM register is
reset upon adapter plug-in if EN_VINDPM_RST = 1.
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8.5.4 Input Current Limit Register (Address = 03h) [reset = 39h ]
REG03 is shown in 图 27 and described in 表 11.
Return to Summary Table.
图 27. REG03 Register
Bit
7
6
5
4
3
2
1
0
Field
FORCE_ICO
FORCE_INDET
EN_ICO
IINDPM[4:0]
表 11. REG03 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
FORCE_ICO
R/W
Yes
Yes
Force Start Input Current Optimizer (ICO):
0 – Do not force ICO (default)
1 – Force ICO start
Note: This bit can only be set and always returns 0 after ICO starts. This bit only
valid when EN_ICO = 1.
6
5
FORCE_INDET
EN_ICO
R/W
R/W
Yes
Yes
Yes
No
Force PSEL Detection:
0 – Not in PSEL detection (default)
1 – Force PSEL detection
Input Current Optimization (ICO) Algorithm Control:
0 – Disable ICO
1 – Enable ICO (default)
4
3
2
1
0
IINDPM[4]
IINDPM[3]
IINDPM[2]
IINDPM[1]
IINDPM[0]
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
1600 mA
800 mA
400 mA
200 mA
100 mA
Input Current Limit:
Offset: 500 mA
Range: 500 mA – 3300 mA
Default: 3000 mA
Note: IINDPM > 3300 mA (1Ch) clamped to 3300 mA. Actual input
current limit is lower of I2C, ICO_ILIM,ILIM pin or PSEL.
36
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8.5.5 Precharge and Termination Current Limit Register (Address = 04h) [reset = 22h]
REG04 is shown in 图 28 and described in 表 12.
Return to Summary Table.
图 28. REG04 Register
Bit
7
6
5
4
3
2
1
0
Field
IPRECHG[3:0]
ITERM[3:0]
表 12. REG04 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
IPRECHG[3]
IPRECHG[2]
IPRECHG[1]
IPRECHG[0]
ITERM[3]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
400 mA
200 mA
100 mA
50 mA
Precharge Current Limit:
Offset: 50 mA
Range: 50 mA – 800 mA
Default: 150 mA
Yes
Yes
Yes
Yes
400 mA
200 mA
100 mA
50 mA
Termination Current Limit:
Offset: 50 mA
Range: 50 mA – 800 mA
Default: 150 mA
ITERM[2]
Yes
ITERM[1]
Yes
ITERM[0]
Yes
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8.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Dh]
REG05 is shown in 图 29 and described in 表 13.
Return to Summary Table.
图 29. REG05 Register
Bit
7
6
5
4
3
2
1
0
Field
EN_TERM
STAT_DIS
WATCHDOG[1:0]
EN_TIMER
CHG_TIMER[1:0]
TMR2X_EN
表 13. REG05 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
EN_TERM
R/W
Yes
Yes
Termination Control:
0 – Disable termination
1 – Enable termination (default)
6
STAT_DIS
R/W
Yes
Yes
STAT Pin Disable:
0 – Enable STAT pin function (default)
1 – Disable STAT pin function
5
4
WATCHDOG[1]
WATCHDOG[0]
R/W
R/W
Yes
Yes
Yes
Yes
I2C Watchdog Timer Settings:
00 – Disable WD Timer
01 – 40 s (default)
10 – 80 s
11 – 160 s
3
EN_TIMER
R/W
Yes
Yes
Charging Safety Timer Enable
0 – Disable
1 – Enable (Default)
2
1
CHG_TIMER[1]
CHG_TIMER[0]
R/W
R/W
Yes
Yes
Yes
Yes
Fast Charge Timer Setting
00 – 5 hrs
01 – 8 hrs
10 – 12 hrs (Default)
11 – 20 hrs
0
TMR2X_EN
R/W
Yes
Yes
Safety Timer during DPM or TREG
0 – Safety timer always count normally
1 – Safety timer slowed by 2X during input DPM or TREG (Default)
38
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8.5.7 Charger Control 2 Register (Address = 06h) [reset = 7Dh]
REG06 is shown in 图 30 and described in 表 14.
Return to Summary Table.
图 30. REG06 Register
Bit
7
6
5
4
3
2
1
0
Field
Reserved
AUTO_INDET_
EN
TREG[1:0]
EN_CHG
CELLLOWV
VRECHG[1:0]
表 14. REG06 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
Reserved
R/W
R/W
Yes
Yes
Yes
Reserved bit always reads 0.
AUTO_INDET_EN
Yes
Automatic PSEL Detection Enable:
0 – Disable PSELL detection when VBUS plugs in
1 – Enable PSEL detection when VBUS plugs in (default)
5
4
TREG[1]
TREG[0]
R/W
R/W
Yes
Yes
Yes
Yes
Thermal Regulation Threshold
00 – 60°C
01 – 80°C
10 – 100°C
11 – 120°C (Default)
3
2
EN_CHG
R/W
R/W
Yes
Yes
Yes
Yes
Charger Enable Configuration
0 – Charge Disable
1 – Charge Enable (default)
Note: If EN_OTG and EN_CHG are set simultaneously, EN_CHG takes priority
CELLLOWV
Battery precharge to fast-charge threshold:
0 – 2.8 V
1 – 3.0 V (default)
1
0
VCELL_RECHG[1]
VCELL_RECHG[0]
R/W
R/W
Yes
Yes
No
No
100 mV
50 mV
Cell Recharge Threshold Offset (below VCELLREG)
Offset: 50 mV
Range: 50 mV – 200 mV
Default: 100 mV
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8.5.8 Charger Control 3 Register (Address = 07h) [reset = 00h]
REG07 is shown in 图 31 and described in 表 15.
Return to Summary Table.
图 31. REG07 Register
Bit
Reset
Field
7
0h
6
0h
5
4
3
2
1
0
0h
TOPOFF_TIMER[1:0]
0h
PFM_DIS
WD_RST
Reserved
表 15. REG07 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
PFM_DIS
R/W
Yes
No
PFM Mode Disable control:
0 – Enable PFM operation (default)
1 – Disable PFM operation
6
WD_RST
R/W
Yes
Yes
I2C Watchdog Timer Reset:
0 – Normal
1 – Reset (Bit goes back to 0 after timer reset)
5
4
TOPOFF_TIMER[1]
TOPOFF_TIMER[0]
R/W
R/W
Yes
Yes
Yes
Yes
Top-off Timer Control :
00 – Disabled (default)
01 – 15 mins
10 – 30 mins
11 – 45 mins
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
No
No
No
No
No
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
This bit reads back 1.
Reserved bit always reads 0
40
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8.5.9 Charger Control 4 Register (Address = 08h) [reset = 0Dh]
REG08 is shown in 图 32 and described in 表 16.
Return to Summary Table.
图 32. REG08 Register
Bit
7
6
0h
5
4
3
2
1h
1
0
Reset
Field
1h
JEITA_VSET[1:0]
1h
JEITA_ISETC[1:0]
Reserved[2:0]
JEITA_ISETH
表 16. REG08 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
RESERVED
RESERVED
RESERVED
R
No
No
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
R
No
No
R
No
No
JEITA_VSET[1]
JEITA_VSET[0]
R/W
R/W
Yes
Yes
Yes
Yes
JEITA High Temp. (45C – 60C) Voltage Setting:
00 – Charge Suspend
01 – Set VREG to 8.0V (default)
10 – Set VREG to 8.3V
11 – VREG unchanged
2
JEITA_ISETH
R/W
Yes
Yes
JEITA High Temp. (45C – 60C) Current Setting (percentage with respect to
ICHG REG01[5:0]):
0 – 40% of ICHG
1 – 100% of ICHG (default)
1
0
JEITA_ISETC[1]
JEITA_ISETC[0]
R/W
R/W
Yes
Yes
Yes
Yes
JEITA Low Temp. (0C – 10C) Current Setting (percentage with respect to ICHG
REG01[5:0]):
00 – Charge Suspend
01 – 20% of ICHG (default)
10 – 40% of ICHG
11 – 100% of ICHG
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8.5.10 Reserved Register (Address = 09h) [reset = 00h]
REG09 is shown in 图 33 and described in 表 17.
Return to Summary Table.
图 33. REG09 Register
Bit
7
6
5
4
3
2
1
0
Reset
Field
0h
Reserved[7:0]
表 17. REG09 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
7:0
Field
Type
Description
RESERVED
R
No
No
Reserved bit always reads 0h
42
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8.5.11 ICO Current Limit in Use Register (Address = 0Ah) [reset = XXh]
REG0A is shown in 图 34 and described in 表 18.
Return to Summary Table.
图 34. REG0A Register
Bit
7
6
5
4
3
2
1
0
Reset
Field
0
0
0
X
X
X
X
X
RESERVED
RESERVED
RESERVED
ICO_ILIM[4:0]
表 18. REG0A Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
ICO_ILIM[4]
ICO_ILIM[3]
ICO_ILIM[2]
ICO_ILIM[1]
ICO_ILIM[0]
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
No
No
No
No
No
No
No
1600 mA
800 mA
400 mA
200 mA
100 mA
Input Current Limit in use when ICO is enabled:
Offset: 500 mA
Range: 500 mA – 3300 mA
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8.5.12 Charger Status 1 Register (Address = 0Bh) [reset = XXh]
REG0B is shown in 图 35 and described in 表 19.
Return to Summary Table.
图 35. REG0B Register
Bit
7
X
6
5
4
3
X
2
1
0
Reset
Field
X
X
X
X
X
X
Reserved
IINDPM_STAT VINDPM_STAT
TREG_STAT
WD_STAT
CHRG_STAT[2:0]
表 19. REG0B Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
Reserved
R
R
No
No
No
No
Reserved bit always reads 0
IINDPM_STAT
VINDPM_STAT
TREG_STAT
WD_STAT
IINDPM Status:
0 – Normal
1 – In IINDPM Regulation (ILIM pin or IINDPM register)
5
4
3
R
R
R
No
No
No
No
No
No
VINDPM Status:
0 – Normal
1 – In VINDPM Regulation
IC Thermal regulation Status:
0 – Normal
1 – In Thermal Regulation
I2C Watchdog Timer Status bit:
0 – Normal
1 – WD Timer expired
2
1
0
CHRG_STAT[2]
CHRG_STAT[1]
CHRG_STAT[0]
R
R
R
No
No
No
No
No
No
Charge Status bits:
000 – Not Charging
001 – Trickle Charge (VBAT < VBAT_SHORT)
010 – Pre-charge (VBAT_UVLO_RISING < VBAT < VBAT_LOWV)
011 – Fast-charge (CC mode)
100 – Taper Charge (CV mode)
101 – Top-off Timer Charging
110 – Charge Termination Done
111 – Reserved
44
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8.5.13 Charger Status 2 Register (Address = 0Ch) [reset = XXh]
REG0C is shown in 图 36 and described in 表 20.
Return to Summary Table.
图 36. REG0C Register
Bit
7
X
6
5
4
3
2
1
0
X
Reset
Field
X
X
X
0
X
X
PG_STAT
VBUS_STAT[2:0]
RESERVED
ICO_STAT[1]
ICO_STAT[0]
Reserved
表 20. REG0C Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
PG_STAT
R
No
No
Power Good Status:
0 – Not Power Good
1 – Power Good
6
5
4
VBUS_STAT[2]
VBUS_STAT[1]
VBUS_STAT[0]
R
R
R
No
No
No
No
No
No
VBUS Detection Status
000 – No Input
001 – USB Host SDP ---> PSEL High
010 - USB CDP (1.5 A)
011 – Adapter (3.0 A) ---> PSEL low
100 – POORSRC detected 7 consecutive times
101 - Unknown Adapter (500 mA)
110 - Non-standard Adapter (1 A/2 A/2.1 A/2.4 A)
3
2
1
RESERVED
ICO_STAT[1]
ICO_STAT[0]
R
R
R
No
No
No
No
No
No
Reserved bit always reads 0h
Input Current Optimizer (ICO) Status:
00 – ICO Disabled
01 – ICO Optimization is in progress
10 – Maximum input current detected
11 – Reserved
0
Reserved
R
No
No
Reserved bit always reads 0h
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8.5.14 NTC Status Register (Address = 0Dh) [reset = 0Xh]
REG0D is shown in 图 37 and described in 表 21.
Return to Summary Table.
图 37. REG0D Register
Bit
7
0
6
0
5
4
3
2
1
0
Reset
Field
0
0
0
X
X
X
RESERVED
RESERVED
RESERVED
RESERVED
TS_STAT[2:0]
表 21. REG0D Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TS_STAT[2]
TS_STAT[1]
TS_STAT[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
Yes
Yes
Yes
Yes
No
NTC (TS) Status:
000 – Normal
010 – TS Warm
011 – TS Cool
101 – TS Cold
110 – TS Hot
No
No
46
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8.5.15 FAULT Status Register (Address = 0Eh) [reset = XXh]
REG0E is shown in 图 38 and described in 表 22.
Return to Summary Table.
图 38. REG0E Register
Bit
7
6
5
0
4
X
3
2
1
0
X
Reset
Field
X
X
0
0
0
VBUS_OVP_ST TSHUT_STAT
AT
Reserved
TMR_STAT
RESERVED
RESERVED
RESERVED
Reserved
表 22. REG0E Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
VBUS_OVP_STAT
R
No
No
Input over-voltage Status:
0 – Normal
1 – Device in over-voltage protection
6
TSHUT_STAT
R
No
No
IC Temperature shutdown Status:
0 – Normal
1 – Device in thermal shutdown protection
5
4
RESERVED
TMR_STAT
R
R
No
No
No
No
Reserved bit always reads 0h
Charge Safety timer Status:
0 – Normal
1 – Charge Safety timer expired
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
No
No
No
No
No
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
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8.5.16 Charger Flag 1 Register (Address = 0Fh) [reset = 00h]
REG0F is shown in 图 39 and described in 表 23.
Return to Summary Table.
图 39. REG0F Register
Bit
7
0
6
0
5
0
4
3
0
2
1
0
Reset
Field
0
0
0
0
Reserved
IINDPM_FLAG VINDPM_FLAG
TREG_FLAG
WD_FLAG
RESERVED
RESERVED
CHRG_FLAG
表 23. REG0F Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
Reserved
R
R
Yes
No
No
Reserved bit always reads 0
IINDPM_FLAG
VINDPM_FLAG
TREG_FLAG
WD_FLAG
Yes
IINDPM Regulation INT Flag:
0 – Normal
1 – IINDPM signal rising edge detected
5
4
3
R
R
R
Yes
Yes
Yes
No
No
No
VINDPM regulation INT Flag:
0 – Normal
1 – VINDPM signal rising edge detected
IC Temperature Regulation INT Flag:
0 – Normal
1 – TREG signal rising edge detected
I2C Watchdog INT Flag:
0 – Normal
1 – WD_STAT signal rising edge detected
2
1
0
RESERVED
RESERVED
CHRG_FLAG
R
R
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
Charge Status INT Flag:
0 – Normal
1 – CHRG_STAT[2:0] bits changed (transition to any state)
48
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8.5.17 Charger Flag 2 Register (Address = 10h) [reset = 00h]
REG10 is shown in 图 40 and described in 表 24.
Return to Summary Table.
图 40. REG10 Register
Bit
7
0
6
5
4
3
2
0
1
0
0
Reset
Field
0
0
0
0
0
PG_FLAG
RESERVED
RESERVED
VBUS_FLAG
RESERVED
TS_FLAG
ICO_FLAG
Reserved
表 24. REG10 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
PG_FLAG
R
Yes
No
Power Good INT Flag:
0 – Normal
1 – PG signal toggle detected
6
5
4
RESERVED
RESERVED
VBUS_FLAG
R
R
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
VBUS Status INT Flag:
0 – Normal
1 – VBUS_STAT[2:0] bits changed (transition to any state)
3
2
RESERVED
TS_FLAG
R
R
Yes
Yes
No
No
Reserved bit always reads 0h
TS Status INT Flag:
0 – Normal
1 – TS_STAT[2:0] bits changed (transition to any state)
1
0
ICO_FLAG
R
R
Yes
Yes
No
No
Input Current Optimizer (ICO) INT Flag:
0 – Normal
1 – ICO_STAT[1:0] changed (transition to any state)
RESERVED
Reserved bit always reads 0h
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8.5.18 FAULT Flag Register (Address = 11h) [reset = 00h]
REG11 is shown in 图 41 and described in 表 25.
Return to Summary Table.
图 41. REG11 Register
Bit
7
0
6
0
5
0
4
3
2
1
0
0
Reset
Field
0
0
0
0
VBUS_OVP_FL TSHUT_FLAG
AG
Reserved
TMR_FLAG
RESERVED
RESERVED
RESERVED
Reserved
表 25. REG11 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
VBUS_OVP_FLAG
R
Yes
No
Input over-voltage INT Flag:
0 – Normal
1 – Entered VBUS_OVP Fault
6
TSHUT_FLAG
R
Yes
No
IC Temperature shutdown INT Flag:
0 – Normal
1 – Entered TSHUT Fault
5
4
RESERVED
TMR_FLAG
R
R
Yes
Yes
No
No
Reserved bit always reads 0h
Charge Safety timer Fault INT Flag:
0 – Normal
1 – Charge Safety timer expired rising edge detected
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
Yes
Yes
Yes
Yes
No
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
50
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.19 Charger Mask 1 Register (Address = 12h) [reset = 00h]
REG12 is shown in 图 42 and described in 表 26.
Return to Summary Table.
图 42. REG12 Register
Bit
7
0
6
1
5
1
4
1
3
2
1
0
Reset
Field
0
0
0
0
ADC_DONE_M IINDPM_MASK VINDPM_MASK TREG_MASK
ASK
WD_MASK
RESERVED
RESERVED
CHRG_MASK
表 26. REG12 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
ADC_DONE_MASK
R/W
Yes
No
No
No
No
No
ADC Conversion INT Mask Flag (only one-shot mode)
0 – ADC_DONE does produce INT pulse
1 – ADC_DONE does produce not INT pulseReserved bit always reads 0
IINDPM_MASK
VINDPM_MASK
TREG_MASK
WD_MASK
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
IINDPM Regulation INT Mask
0 – IINDPM entry produces INT pulse
1 – IINDPM entry does not produce INT pulse
VINDPM Regulation INT Mask
0 – VINDPM entry produces INT pulse
1 – VINDPM entry not produce INT pulse
IC Temperature Regulation INT Mask
0 – TREG entry produces INT pulse
1 – TREG entry produce INT pulse
I2C Watchdog Timer INT Mask
0 – WD_STAT rising edge produces INT pulse
1 – WD_STAT rising edge does not produce INT
2
1
0
RESERVED
RESERVED
CHRG_MASK
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
R
R/W
Charge Status INT Mask
0 – CHRG_STAT[2:0] bit change produces INT
1 – CHRG_STAT[2:0] bit change does not produce INT pulse
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8.5.20 Charger Mask 2 Register (Address = 13h) [reset = 00h]
REG13 is shown in 图 43 and described in 表 27.
Return to Summary Table.
图 43. REG13 Register
Bit
7
0
6
5
4
3
2
0
1
0
0
Reset
Field
0
0
0
0
0
PG_MASK
RESERVED
RESERVED
VBUS_MASK
RESERVED
TS_MASK
ICO_MASK
Reserved
表 27. REG13 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
PG_MASK
R/W
Yes
No
Power Good INT Mask:
0 – PG toggle produces INT pulse
1 – PG toggle does not produce INT pulse
6
5
4
RESERVED
RESERVED
VBUS_MASK
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
R
R/W
VBUS Status INT Mask:
0 – VBUS_STAT[2:0] bit change produces INT
1 – VBUS_STAT[2:0] bit change does not produces INT
3
2
RESERVED
TS_MASK
R
Yes
Yes
No
No
Reserved bit always reads 0h
R/W
TS Status INT Mask:
0 – TS_STAT[2:0] bit change produces INT
1 – TS_STAT[2:0] bit change does not produces INT pulse
1
0
ICO_MASK
RESERVED
R/W
R
Yes
Yes
No
No
Input Current Optimizer (ICO) INT Mask:
0 – ICO_STAT rising edge produces INT
1 – ICO_STAT rising edge does not produce INT
Reserved bit always reads 0h
52
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.21 FAULT Mask Register (Address = 14h) [reset = 00h]
REG14 is shown in 图 44 and described in 表 28.
Return to Summary Table.
图 44. REG14 Register
Bit
7
0
6
0
5
0
4
3
0
2
1
0
0
Reset
Field
0
0
0
VBUS_OVP_M TSHUT_MASK
ASK
Reserved
TMR_MASK
SNS_SHORT_
MASK
RESERVED
RESERVED
Reserved
表 28. REG14 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
VBUS_OVP_MASK
R/W
Yes
No
Input over-voltage INT Mask:
0 – VBUS_OVP rising edge produces INT pulse
1 – VBUS_OVP rising edge does not produce INT pulse
6
TSHUT_MASK
R/W
Yes
No
Thermal Shutdown INT Mask:
0 – TSHUT rising edge produces INT pulse
1 – TSHUT rising edge does not produce INT pulse
5
4
RESERVED
TMR_MASK
R
Yes
Yes
No
No
Reserved bit always reads 0h
R/W
Charge Safety Timer Fault INT Mask:
0 – Timer expired rising edge produces INT pulse
1 – Timer expired rising edge does not produce INT pulse
3
SNS_SHORT_MASK
R/W
Yes
No
SNS Short Fault INT Mask:
0 – SNS short rising edge produces INT pulse
1 – SNS short rising edge does not produce INT pulse
2
1
0
RESERVED
RESERVED
RESERVED
R
R
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
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8.5.22 ADC Control Register (Address = 15h) [reset = 30h]
REG15 is shown in 图 45 and described in 表 29.
Return to Summary Table.
图 45. REG15 Register
Bit
7
0
6
5
1
4
1
3
2
1
0
Reset
Field
0
0
0
0
0
ADC_EN
ADC_RATE
ADC_SAMPLE[1:0]
RESERVED
RESERVED
RESERVED
RESERVED
表 29. REG15 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
ADC_EN
R/W
Yes
Yes
ADC Control:
0 – Disable ADC
1 – Enable ADC
6
ADC_RATE
R/W
Yes
No
0 – Continuous conversion
1 – One-shot conversion
5
4
ADC_SAMPLE[1]
ADC_SAMPLE[0]
R/W
R/W
Yes
Yes
No
No
Sample Speed of ADC:
00 – 15 bit effective resolution
01 – 14 bit effective resolution
10 – 13 bit effective resolution
11 – 12 bit effective resolution
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
Yes
Yes
Yes
Yes
No
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
Reserved bit always reads 0h
54
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.23 ADC Function Disable Register (Address = 16h) [reset = 00h]
REG16 is shown in 图 46 and described in 表 30.
Return to Summary Table.
图 46. REG16 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
1
0
0
0
Reset
Field
0
IBUS_ADC_DIS ICHG_ADC_DI VBUS_ADC_DI VBAT_ADC_DI
Reserved
TS_ADC_DIS
VCELL_ADC_D TDIE_ADC_DIS
IS
S
S
S
表 30. REG16 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
IBUS_ADC_DIS
R/W
Yes
No
No
No
No
0 – Enable conversion
1 – Disable conversion
ICHG_ADC_DIS
VBUS_ADC_DIS
VBAT_ADC_DIS
R/W
R/W
R
Yes
Yes
Yes
0 – Enable conversion
1 – Disable conversion
0 – Enable conversion
1 – Disable conversion
0 – Enable conversion
1 – Disable conversion
3
2
RESERVED
R
Yes
Yes
No
No
Reserved bit always reads 0h
TS_ADC_DIS
R/W
0 – Enable conversion
1 – Disable conversion
1
0
VCELL_ADC_DIS
TDIE_ADC_DIS
R/W
R/W
Yes
Yes
No
No
0 – Enable conversion
1 – Disable conversion
0 – Enable conversion
1 – Disable conversion
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8.5.24 IBUS ADC 1 Register (Address = 17h) [reset = 00h]
REG17 is shown in 图 47 and described in 表 31.
Return to Summary Table.
图 47. REG17 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
IBUS_ADC[15:8]
表 31. REG17 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
IBUS_ADC[15]
IBUS_ADC[14]
IBUS_ADC[13]
IBUS_ADC[12]
IBUS_ADC[11]
IBUS_ADC[10]
IBUS_ADC[9]
IBUS_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
Yes
16384 mA
8192 mA
4096 mA
Yes
Yes
Yes
2048 mA
1024 mA
512 mA
256 mA
VBUS Current Reading (positive current flows into VBUS pin,
negative current flows out ot VBUS pin):
Range: 0 A – 4 A
Yes
Yes
Yes
8.5.25 IBUS ADC 0 Register (Address = 18h) [reset = 00h]
REG18 is shown in 图 48 and described in 表 32.
Return to Summary Table.
图 48. REG18 Register
Bit
7
0
6
0
5
0
4
3
2
0
1
0
0
0
Reset
Field
0
0
IBUS_ADC[7:0]
表 32. REG18 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
IBUS_ADC[7]
IBUS_ADC[6]
IBUS_ADC[5]
IBUS_ADC[4]
IBUS_ADC[3]
IBUS_ADC[2]
IBUS_ADC[1]
IBUS_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mA
64 mA
32 mA
16 mA
8 mA
VBUS Current Reading (positive current flows into VBUS pin,
negative current flows out ot VBUS pin):
Range: 0 A – 4 A
Yes
Yes
Yes
Yes
Yes
4 mA
Yes
2 mA
Yes
1 mA
56
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.26 ICHG ADC 1 Register (Address = 19h) [reset = 00h]
REG19 is shown in 图 49 and described in 表 33.
Return to Summary Table.
图 49. REG19 Register
Bit
7
6
0
5
0
4
0
3
2
0
1
0
0
0
Reset
Field
0
0
RESERVED
ICHG_ADC[14:8]
表 33. REG19 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
Reserved
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Reserved register always reads 0h.
ICHG_ADC[14]
ICHG_ADC[13]
ICHG_ADC[12]
ICHG_ADC[11]
ICHG_ADC[10]
ICHG_ADC[9]
ICHG_ADC[8]
Yes
16384 mA
8192 mA
4096 mA
Yes
Yes
Yes
2048 mA
1024 mA
512 mA
256 mA
Charge Current Reading:
Range: 0 A – 4 A
Yes
Yes
Yes
8.5.27 ICHG ADC 0 Register (Address = 1Ah) [reset = 00h]
REG1A is shown in 图 50 and described in 表 34.
Return to Summary Table.
图 50. REG1A Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
ICHG_ADC[7:0]
表 34. REG1A Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
ICHG_ADC[7]
ICHG_ADC[6]
ICHG_ADC[5]
ICHG_ADC[4]
ICHG_ADC[3]
ICHG_ADC[2]
ICHG_ADC[1]
ICHG_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mA
64 mA
32 mA
16 mA
8 mA
Charge Current Reading:
Range: 0 A – 4 A
Yes
Yes
Yes
Yes
Yes
4 mA
Yes
2 mA
Yes
1 mA
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8.5.28 VBUS ADC 1 Register (Address = 1Bh) [reset = 00h]
REG1B is shown in 图 51 and described in 表 35.
Return to Summary Table.
图 51. REG1B Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VBUS_ADC[15:8]
表 35. REG1B Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VBUS_ADC[15]
VBUS_ADC[14]
VBUS_ADC[13]
VBUS_ADC[12]
VBUS_ADC[11]
VBUS_ADC[10]
VBUS_ADC[9]
VBUS_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
16384 mV
Yes
Yes
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
VBUS Voltage reading
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
256 mV
8.5.29 VBUS ADC 0 Register (Address = 1Ch) [reset = 00h]
REG1C is shown in 图 52 and described in 表 36.
Return to Summary Table.
图 52. REG1C Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VBUS_ADC[7:0]
表 36. REG1C Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VBUS_ADC[7]
VBUS_ADC[6]
VBUS_ADC[5]
VBUS_ADC[4]
VBUS_ADC[3]
VBUS_ADC[2]
VBUS_ADC[1]
VBUS_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mV
64 mV
32 mV
16 mV
8 mV
VBUS Voltage Reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
4 mV
Yes
2 mV
Yes
1 mV
58
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.30 VBAT ADC 1 Register (Address = 1Dh) [reset = 00h]
REG1D is shown in 图 53 and described in 表 37.
Return to Summary Table.
图 53. REG1D Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VBAT_ADC[15:8]
表 37. REG1D Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VBAT_ADC[15]
VBAT_ADC[14]
VBAT_ADC[13]
VBAT_ADC[12]
VBAT_ADC[11]
VBAT_ADC[10]
VBAT_ADC[9]
VBAT_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
16384 mV
Yes
Yes
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
VBAT Voltage reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
256 mV
8.5.31 VBAT ADC 0 Register (Address = 1Eh) [reset = 00h]
REG1E is shown in 图 54 and described in 表 38.
Return to Summary Table.
图 54. REG1E Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VBAT_ADC[7:0]
表 38. REG1E Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VBAT_ADC[7]
VBAT_ADC[6]
VBAT_ADC[5]
VBAT_ADC[4]
VBAT_ADC[3]
VBAT_ADC[2]
VBAT_ADC[1]
VBAT_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mV
64 mV
32 mV
16 mV
8 mV
VBAT Voltage reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
4 mV
Yes
2 mV
Yes
1 mV
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8.5.32 VCELLTOP ADC 1 Register (Address = 1Fh) [reset = 00h]
REG1F is shown in 图 55 and described in 表 39.
Return to Summary Table.
图 55. REG1F Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VCELLTOP_ADC[15:8]
表 39. REG1F Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VCELLTOP_ADC[15]
VCELLTOP_ADC[14]
VCELLTOP_ADC[13]
VCELLTOP_ADC[12]
VCELLTOP_ADC[11]
VCELLTOP_ADC[10]
VCELLTOP_ADC[9]
VCELLTOP_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
16384 mV VCELLTOP Voltage reading:
Yes
Range: 0 V – 5 V
Yes
8192 mV
Note: cell balancing voltage measurement is measured through
internal comparator. ADC reading may not reflect the actual cell
balancing voltage measurement.
Yes
4096 mV
2048 mV
1024 mV
512 mV
256 mV
Yes
Yes
Yes
Yes
8.5.33 VCELLTOP ADC 0 Register (Address = 20h) [reset = 00h]
REG20 is shown in 图 56 and described in 表 40.
Return to Summary Table.
图 56. REG20 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VCELLTOP_ADC[7:0]
表 40. REG20 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VCELLTOP_ADC[7]
VCELLTOP_ADC[6]
VCELLTOP_ADC[5]
VCELLTOP_ADC[4]
VCELLTOP_ADC[3]
VCELLTOP_ADC[2]
VCELLTOP_ADC[1]
VCELLTOP_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mV
64 mV
32 mV
16 mV
8 mV
VCELLTOP Voltage reading:
Range: 0 V – 5 V
Note: cell balancing voltage measurement is measured through
internal comparator. ADC reading may not reflect the actual cell
balancing voltage measurement.
Yes
Yes
Yes
Yes
Yes
4 mV
Yes
2 mV
Yes
1 mV
60
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.34 TS ADC 1 Register (Address = 21h) [reset = 00h]
REG21 is shown in 图 57 and described in 表 41.
Return to Summary Table.
图 57. REG21 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
TS_ADC[15:8]
表 41. REG21 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
Sign bit: overall results reported in two's complement.
7
6
5
4
3
2
1
0
TS_ADC[15]
TS_ADC[14]
TS_ADC[13]
TS_ADC[12]
TS_ADC[11]
TS_ADC[10]
TS_ADC[9]
TS_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
50.0 %
25.0 %
TS as percentage of REGN reading:
Range: 0% – 94.9%
Yes
8.5.35 TS ADC 0 Register (Address = 22h) [reset = 00h]
REG22 is shown in 图 58 and described in 表 42.
Return to Summary Table.
图 58. REG22 Register
Bit
7
0
6
0
5
0
4
3
2
0
1
0
0
0
Reset
Field
0
0
TS_ADC[7:0]
表 42. REG22 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
TS_ADC[7]
TS_ADC[6]
TS_ADC[5]
TS_ADC[4]
TS_ADC[3]
TS_ADC[2]
TS_ADC[1]
TS_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
12.50 %
6.25 %
TS as percentage of REGN reading:
Range: 0% – 94.9%
Yes
Yes
3.125 %
1.563 %
0.781 %
0.391 %
0.195 %
0.098 %
Yes
Yes
Yes
Yes
Yes
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8.5.36 TDIE ADC 1 Register (Address = 23h) [reset = 00h]
REG23 is shown in 图 59 and described in 表 43.
Return to Summary Table.
图 59. REG23 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
TDIE_ADC[15:8]
表 43. REG23 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
Sign bit: overall results reported in two's complement.
7
6
5
4
3
2
1
0
TDIE_ADC[15]
TDIE_ADC[14]
TDIE_ADC[13]
TDIE_ADC[12]
TDIE_ADC[11]
TDIE_ADC[10]
TDIE_ADC[9]
TDIE_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
128 °C
TDIE (IC Temperature) reading:
Range: 0°C – 128°C
8.5.37 TDIE ADC 0 Register (Address = 24h) [reset = 00h]
REG24 is shown in 图 60 and described in 表 44.
Return to Summary Table.
图 60. REG24 Register
Bit
7
0
6
0
5
0
4
3
2
0
1
0
0
0
Reset
Field
0
0
TDIE_ADC[7:0]
表 44. REG24 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
TDIE_ADC[7]
TDIE_ADC[6]
TDIE_ADC[5]
TDIE_ADC[4]
TDIE_ADC[3]
TDIE_ADC[2]
TDIE_ADC[1]
TDIE_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
64 °C
32 °C
16 °C
8 °C
TDIE (IC Temperature) reading:
Range: 0°C – 128°C
Yes
Yes
Yes
Yes
4°C
Yes
2 °C
Yes
1 °C
Yes
0.5 °C
62
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.38 Part Information Register (Address = 25h) [reset = 28h]
REG25 is shown in 图 61 and described in 表 45.
Return to Summary Table.
图 61. REG25 Register
Bit
7
0
6
0
5
1
4
0
3
1
2
0
1
0
0
Reset
Field
0
REG_RST
PN[3:0]
DEV_REV[2:0]
表 45. REG25 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
REG_RST
R/W
Yes
No
Register Reset:
0 – Keep current register settings
1 – Reset to default register value and reset safety timer (bit resets to 0 after
register reset is complete)
6
5
4
3
2
1
0
PN[3]
R
R
R
R
R
R
R
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
0101: BQ25887
PN[2]
PN[1]
PN[0]
DEV_REV[2]
DEV_REV[1]
DEV_REV[0]
Device revision: 001
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8.5.39 VCELLBOT ADC 1 Register (Address = 26h) [reset = 00h]
REG26 is shown in 图 62 and described in 表 46.
Return to Summary Table.
图 62. REG26 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VCELLBOT_ADC[15:8]
表 46. REG26 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VCELLBOT_ADC[15]
VCELLBOT_ADC[14]
VCELLBOT_ADC[13]
VCELLBOT_ADC[12]
VCELLBOT_ADC[11]
VCELLBOT_ADC[10]
VCELLBOT_ADC[9]
VCELLBOT_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
16384 mV
Yes
Yes
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
Bottom Cell Voltage from MID to GND Voltage reading:
Range: 0 V – 5 V
Yes
Yes
Yes
Yes
Yes
256 mV
8.5.40 VCELLBOT ADC 0 Register (Address = 27h) [reset = 00h]
REG27 is shown in 图 63 and described in 表 47.
Return to Summary Table.
图 63. REG27 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VCELLBOT_ADC[7:0]
表 47. REG27 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VCELLBOT_ADC[7]
VCELLBOT_ADC[6]
VCELLBOT_ADC[5]
VCELLBOT_ADC[4]
VCELLBOT_ADC[3]
VCELLBOT_ADC[2]
VCELLBOT_ADC[1]
VCELLBOT_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mV
64 mV
32 mV
16 mV
8 mV
Bottom Cell Voltage from MID to GND Voltage reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
4 mV
Yes
2 mV
Yes
1 mV
64
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.41 Cell Balancing Control 1 Register (Address = 28h) [reset = 2Ah]
REG28 is shown in 图 64 and described in 表 48.
Return to Summary Table.
图 64. REG28 Register
Bit
7
0
6
5
1
4
0
3
1
2
0
1
1
0
0
Reset
Field
0
VDIFF_END_OFFSET[2:0]
TCB_QUAL_IN
TERVAL
TCB_ACTIVE[1:0]
TSETTLE[1:0]
表 48. REG28 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
VDIFF_END_OFFSET[ R/W
2]
Yes
No
No
No
Cell balancing exit threshold is programmed as an offset from the
VDIFF_START. Range is 30 mV to 100 mV with 10-mV resolution. Note that
VDIFF_END_OFFSET should be less than the selected VDIFF_START.
VDIFF_END = VDIFF_START – VDIFF_END_OFFSET. If VDIFF_END is less
than 10 mV, then the charger should clamp VDIFF_END to 10 mV.
000 – 30 mV
001 – 40 mV (Default)
010 – 50 mV
6
5
VDIFF_END_OFFSET[ R/W
1]
Yes
Yes
VDIFF_END_OFFSET[ R/W
0]
011 – 60 mV
100 – 70 mV
101 – 80 mV
110 – 90 mV
111 – 100 mV
4
TCB_QUAL_INTERVAL R/W
Yes
No
Options for the interval between taking measurements to enter cell balancing
mode:
0 – 2 min (default)
1 – 4 min
3
2
TCB_ACTIVE[1]
TCB_ACTIVE[0]
R/W
R/W
Yes
Yes
No
No
Register to select time interval to stop charging and cell balancing discharging for
cell voltage measurements
00 – 4 s
01 – 32 s
10 – 2 min (default)
11 – 4 min
1
0
TSETTLE[1]
TSETTLE[0]
R/W
R/W
Yes
Yes
No
No
Register to set delay between charge disable and voltage measurement.
00 – 10 ms
01 – 100 ms
10 – 1 s (default)
11 – 2 s
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8.5.42 Cell Balancing Control 2 Register (Address = 29h) [reset = F4h]
REG29 is shown in 图 65 and described in 表 49.
Return to Summary Table.
图 65. REG29 Register
Bit
7
1
6
1
5
1
4
1
3
0
2
1
1
0
0
0
Reset
Field
VQUAL_TH
VDIFF_START
表 49. REG29 Register Field Descriptions
Reset by
REG_RST
Reset by
Bit
Field
Type
Description
WATCHDOG
7
6
5
4
VQUAL_TH [3]
VQUAL_TH [2]
VQUAL_TH [1]
VQUAL_TH [0]
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
No
No
No
No
80 mV
40 mV
20 mV
10 mV
The threshold from cell balancing pre-qualification mode to cell
balancing qualification mode. This is the differential threshold between
the two cells when charging is enabled. Offset is 40mV. Range from
40mV to 180mV with 10mV step.
0000 – 40 mV
0001 – 50 mV
0010 – 60 mV
0011 – 70 mV
0100 – 80 mV
0101 – 90 mV
0110 – 100 mV
0111 – 110 mV
1000 – 120 mV
1001 – 130 mV
1010 – 140 mV
1011 – 150 mV
1100: 160 mV
1101 – 170 mV
1110 – 180 mV
1111 – Disable pre-qualification (Default)
3
2
1
0
VDIFF_START [3]
VDIFF_START [2]
VDIFF_START [0]
VDIFF_START [1]
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
No
No
No
No
80 mV
40 mV
20 mV
10 mV
The threshold from cell balancing qualification mode to cell balancing
active mode. This is the differential threshold between the two cells
when charging is enabled. Offset is 40mV. Range from 40 mV to 190
mV with 10-mV step. Default VDIFF_START is 0100 (80 mV)
0000 – 40 mV
0001 – 50 mV
0010 – 60 mV
0011 – 70 mV
0100 – 80 mV (Default)
0101 – 90 mV
0110 – 100 mV
0111 – 110 mV
1000 – 120 mV
1001 – 130 mV
1010 – 140 mV
1011 – 150 mV
1100 – 160 mV
1101 – 170 mV
1110 – 180 mV
1111 – 190 mV
66
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
8.5.43 Cell Balancing Status and Control Register (Address = 2Ah) [reset = 81h]
REG29 is shown in 图 66 and described in 表 50.
Return to Summary Table.
图 66. REG2A Register
Bit
7
1
6
1
5
0
4
3
2
1
0
Reset
Field
0
0
0
0
0
CB_CHG_DIS CB__AUTO_EN
CB_STAT
HS_CV_STAT
LS_CV_STAT
HS_OV_STAT
LS_OV_STAT
CB_OC_STAT
表 50. REG2A Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
CB_CHG_DIS
R/W
Yes
Yes
Yes
No
No
No
Bit to disable charge for accurate cell balancing measurement. CB discharge will
still be disabled for measurement.
0 – Charge is continuous during cell balancing cell voltage measurement
1 – Charge is disabled during cell balancing cell voltage measurement. (Default)
CB_AUTO_EN
CB_STAT
R/W
R
Bit to enable automatic cell balancing mode. This bit must be low to allow the
manual cell discharge function.
0 – Disable auto cell balancing
1 – Enable auto cell balancing (Default)
Anytime cell balance is active, the is bit is set to high. Once cell balance is exit,
this bit returns to low.
0 – Cell balance not active or cell balance is exit.
1 – Cell balance active mode.
4
3
2
1
0
HS_CV_STAT
LS_CV_STAT
HS_OV_STAT
LS_OV_STAT
CB_OC_STAT
R
R
R
R
R
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
If this bit is set, the high side cell is in CV mode
If this bit is set, the low side cell is in CV mode
If this bit is set, the high side cell is in over-voltage
If this bit is set, the low side cell is in over-voltage
If this bit is set, the Cell Balance Over-Current Protection is active
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8.5.44 Cell Balancing Flag Register (Address = 2Bh) [reset = 00h]
REG2A is shown in 图 67 and described in 表 51.
Return to Summary Table.
图 67. REG2B Register
Bit
7
0
6
0
5
0
4
3
2
1
0
Reset
Field
0
0
0
0
0
QCBH_EN
QCBL_EN
CB_FLAG
HS_CV_FLAG
LS_CV_FLAG
HS_OV_FLAG
LS_OV_FLAG
CB_OC_FLAG
表 51. REG2B Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
QCBH_EN
QCBL_EN
CB_FLAG
R/W
R/W
R
Yes
Yes
Yes
No
No
No
Bit to turn on QCBH to discharge the top cell.
0 – Turn off QCBH (Default)
1 – Turn on QCBH
Bit to turn on QCBL to discharge the bottom cell.
0 – Turn off QCBL (Default)
1 – Turn on QCBL
Cell balancing status INT Flag
0 – Normal
1 – Entered or exited cell balancing
4
3
2
1
0
HS_CV_FLAG
LS_CV_FLAG
HS_OV_FLAG
LS_OV_FLAG
CB_OC_FLAG
R
R
R
R
R
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
If this bit is set, the high side cell balancing FET is in CV mode, or has been in
CV mode. This bit is cleared upon read.
If this bit is set, the low side cell balancing FET is in CV mode, or has been in CV
mode. This bit is cleared upon read.
If this bit is set, the high side cell is in over-voltage, or has been in over-voltage.
This bit is cleared upon read.
If this bit is set, the low side cell is in over-voltage, or has been in over-voltage.
This bit is cleared upon read.
If this bit is set, the Cell Balance Over-Current Protection is active, or has been
active. This bit is cleared upon read.
8.5.45 Cell Balancing Mask Register (Address = 2Ch) [reset = 00h]
REG2B is shown in 图 68 and described in 表 52.
Return to Summary Table.
图 68. REG2C Register
Bit
7
0
6
0
5
0
4
3
2
0
1
0
0
0
Reset
Field
0
0
Reserved
Reserved
CB_MASK
HS_CV_MASK
LS_CV_MASK
HS_OV_MASK LS_OV_MASK CB_OC_MASK
表 52. REG2C Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
Reserved
Reserved
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0h
Reserved bit always reads 0h
R
CB_MASK
R/W
When set, the device will not send an interrupt on the INT pin when the device
enters or exits cell balance mode.
4
3
2
1
0
HS_CV_MASK
LS_CV_MASK
HS_OV_MASK
LS_OV_MASK
CB_OC_MASK
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
When set, the device will not send an interrupt on the INT pin when the high side
cell balancing FET is in CV mode.
When set, the device will not send an interrupt on the INT pin when the low side
cell balancing FET is in CV mode.
When set, the device will not send an interrupt on the INT pin when the high side
cell is in over-voltage.
When set, the device will not send an interrupt on the INT pin when the low side
cell is in over-voltage.
When set, the device will not send an interrupt on the INT pin when the Cell
Balance Over-Current Protections is active.
68
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the BQ25887 configured as an I2C controlled device and a 2s battery charger
with cell balancing for Li-Ion and Li-polymer batteries used in a wide range of E-cig and other portable devices. It
integrates an input blocking FET (QBLK, Q1), high-side switching FET (QHS, Q2), and low-side switching FET
(QLS, Q3). The device also integrates a bootstrap diode for the high-side gate drive.
9.2 Typical Application
5V @ 3A
VREF
VBUS
2.2K ꢁ
STAT
1 ꢀF
383Ω
Q1
ILIM
PMID
SNS
10 ꢀF
Q2
44 ꢀF
ICHG=2A
BAT
RSNS
1ꢀH
SW
47nF
10 ꢀF
BTST
Q3
4.7ꢀF
REGN
VREF
MID
300 ꢁ*
QCBH
CBSET
SDA
RCBSET
VREGN
SCL
/INT
/PG
CD
QCBL
Host
TS
BQ25887
`
PSEL
GND
*Note: 300Q Œꢀ•]•š}Œ }v aL5 ‰]v ]• µ•ꢀꢁ š} o]u]š šZꢀ ꢂµŒŒꢀvš ]v šZꢀ ꢂꢃ•ꢀ ÁZꢀŒꢀ šZꢀ ꢄ}šš}u ꢂꢀoo ]• ‰oµPPꢀꢁ ]v ŒꢀÀꢀŒ•oÇ
图 69. BQ25887 (Cell Balancing and I2C) Typical Application Diagram
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
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Typical Application (接下页)
9.2.1 Design Requirements
For this design example, use the parameters shown in 表 53 below.
表 53. Design Parameters
PARAMETER
VBUS voltage range
VALUE
3.9 V to 6.2 V
2.4 A
Input current limit (IINDPM[4:0])
Fast charge current limit (ICHG[5:0])
Battery Regulation Voltage (VCELLREG[7:0])
1.5 A
4.2 V
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The device has 1.5-MHz switching frequency to allow the use of small inductor and capacitor values. The
inductor saturation current should be higher than the input current (IIN) plus half the ripple current (IRIPPLE):
I
RIPPLE
ISAT í IIN +
2
(5)
The inductor ripple current (IRIPPLE) depends on input voltage (VVBUS), duty cycle (D = VBAT/VBUS), switching
frequency (fSW) and inductance (L):
V
BUS ì(VSYS-VBUS
)
IRIPPLE
=
VSYS ì fSW ì L
(6)
The maximum inductor ripple current happens in the vicinity of D = 0.5. Usually inductor ripple is designed in the
range of (20 – 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical
design.
9.2.2.2 Input (VBUS / PMID) Capacitor
The input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst
case RMS ripple current occurs when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then
the worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50% and can be estimated
by
I
RIPPLE
IPMID
=
ö 0.29ì IRIPPLE
2ì 3
(7)
A low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed close to the PMID and GND pins of the IC. Voltage rating of the capacitor must be higher than normal
input voltage level. 25-V rating or higher capacitor is preferred for up to 5-V input voltage. A minimum 10-μF
capacitor is suggested for up to 3.3-A input current. Keep in mind, long impedance cable would cause significant
voltage drop with higher inrush current. For optimal performance, 44-uF cap on PMID is recommended. In
addition, a minimum 1-μF capacitor is suggested at VBUS pin.
9.2.2.3 Output (VSNS) Capacitor
The SYS capacitor is the boost converter output capacitor and should also have enough ripple current rating to
absorb output switching ripple current. The output capacitor RMS current ICOUT is given:
D
ICSYS, rms = IOUT ì
1- D
(8)
The output capacitor voltage ripple is a function of the boost output current (IOUT), and can be calculated as
follows:
70
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BQ25887
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
I
OUT ì D
DVSYS
=
f
SW ìCSYS
(9)
A low ESR ceramic capacitor such as X7R or X5R is preferred for SNS decoupling capacitor and should be
placed close to the SNS and GND pins of the IC. Voltage rating of the capacitor must be higher than normal
output voltage level. 16-V rating or higher capacitor is preferred. Minimum 44-μF capacitor is suggested for up to
2.2-A boost converter output current.
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9.2.3 Application Curves
CVBUS = 1 µF, CPMID= 10 µF, CBAT = 10 µF, CSNS = 44 µF, L = DFE252012F-1R0 (1 µH) (unless otherwise specified)
VBUS = 5 V
VBAT = 6.0 V
ICHG = 1 A
VBUS = 5 V
VBAT = 7.4 V
ICHG = 1 A
图 70. Adapter Power Up with Charge Enabled
图 71. Charge Enable
VBUS = 5 V
VBAT = Open
Charge disabled
VBUS = 5 V
VBAT = 7.4 V
ICHG = 1 A
图 73. Adapter Plug-in with No Battery Charge Disabled
图 72. Charge Disabled
VBUS = 5 V
VBAT = 7.6 V
ICHG = 1 A
VBUS = 5 V
VBAT = 8.4 V
Charge disabled
图 74. Boost Mode PWM Switching
图 75. Boost Mode PFM Switching
72
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BQ25887
www.ti.com.cn
ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
CVBUS = 1 µF, CPMID= 10 µF, CBAT = 10 µF, CSNS = 44 µF, L = DFE252012F-1R0 (1 µH) (unless otherwise specified)
DCP Adapter
VBAT = 8.0 V
Charge enabled
VBUS = 5 V
VBAT = 8.4 V
Charge disabled
图 77. VINDPM Transient Response
图 76. System Load Transient Response
DCP Adapter
VBAT = 8.0 V
Charge enabled
图 78. IINDPM Transient Response
图 79. Charge Cycle with the Bottom Cell Voltage Higher
Than the Top Cell Voltage
图 80. Charge Cycle with the Top Cell Voltage Higher Than the Bottom Cell Voltage
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www.ti.com.cn
10 Power Supply Recommendations
In order to provide an output voltage, the device requires a power supply between 3.9-V and 6.2-V input with at
least 500-mA current rating connected to VBUS or a 2-cell Li-Ion battery with voltage > VBAT_UVLO connected
to BAT..
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loops is important to prevent electrical and magnetic field
radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB
according to this specific order is essential.
1. Put SNS output capacitor as close to SNS and GND pins as possible. Ground connections need to be tied to
the IC ground with a short copper trace connection or GND plane.
2. Place PMID input capacitor as close as possible to PMID pins and PGND pins and use shortest copper trace
connection or GND plane.
3. Place inductor input terminal to SW pins as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the input current. Minimize
parasitic capacitance from this area to any other trace or plane.
4. Decoupling capacitors should be placed on the same side of and next to the IC and make trace connection
as short as possible.
5. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0-Ω resistor to tie analog ground to power ground.
6. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
7. Via size and number should be enough for a given current path.
8. Route MID as sensing trace away from switching nodes such as SW.
Refer to the EVM design and the Layout Example below for the recommended component placement with trace
and via locations.
74
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BQ25887
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
11.2 Layout Example
图 81. PCB Layout Example
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www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
《BQ2588x 升压电池充电器评估模块用户指南》
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
76
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ZHCSJR3B –FEBRUARY 2019–REVISED NOVEMBER 2019
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
77
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25887RGER
BQ25887RGET
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ25887
BQ25887
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25887RGER
BQ25887RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Nov-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25887RGER
BQ25887RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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