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BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

支持对单节电池进行快速充电的 BQ25910 I²C 控制型 6A 三级开关模式

并联电池充电器

1 特性

2 应用

1

•

并联充电器可在双充电器配置下提供快速充电

•

智能手机

•

高效的 750kHz 开关模式三级降压并联充电器

平板电脑

无线充电

–

降低了纹波以支持低厚度电感器

便携式电子产品

电子销售点 (ePOS)

在 1.5A 电流（5V 输入）下具有 95.4% 的充电

效率

–

在 3A 电流（9V 输入）下具有 93.3% 的充电效

率

3 说明

–

与传统小尺寸降压转换器相比，效率更加出色

BQ25910 是一款适用于单节锂离子和锂聚合物电池的

集成式三级开关模式并联电池充电管理器件。利用三级

转换器，可在保持最高开关模式工作效率的同时降低解

决方案尺寸，并提高功率密度。该器件支持通过高输

入电压为各种便携设备快速充电。该解决方案集成了反

•

单个输入，支持 USB 输入和可调高电压适配器

–

支持 3.9V 至 14V 输入电压范围，绝对最大输

入电压额定值为 20V

–

输入电流限制（500mA 至 3.6A，分辨率为

100mA），支持 USB2.0、USB3.0 标准和高电

压适配器

向阻断 FET (Q_BLK) 和四个开关 FET（Q_HSA、Q_HSB

、

Q

_LSB、Q_LSA）。具有充电和系统设置的 I²C 串行接口

使得此器件成为一个真正的灵活解决方案。

–

通过高达 14V 的输入电压限制 (VINDPM) 进行

最大功率跟踪

•

灵活的 I²C 模式，可实现最优系统性能

器件信息⁽¹⁾

高集成度包括所有 MOSFET、电流感应和环路补偿

器件型号

BQ25910

封装

封装尺寸（标称值）

DSBGA (36)

2.41mm x 2.44mm

–

无损充电电流感应，无需感应电阻器

•

待机模式下具有小于 10µA 的低电池泄漏电流

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

高精度

简化原理图

–

±0.4% 充电电压调节

±10% 充电电流调节

±7.5% 输入电流调节

远程差分电池电量感应

USB

VBUS

SW

BTST

SYS

I2C Bus

•

安全

Host

BAT

Control

–

热调节和热关断

Master

输入 UVLO 和过压保护

电池过压保护

输入动态电源管理 (DPM)

充电安全计时器

CFLY+

VBUS

I_CHG

飞跨电容短路保护

输出电压短路保护

SW

I2C Bus

CFLYœ

•

采用 36 焊球 WCSP 封装

Host

BATP

+

Control

BATN

BQ25910

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSDU0

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

7.5 Programming .......................................................... 24

7.6 Register Maps......................................................... 28

Application and Implementation ........................ 43

8.1 Application Information............................................ 43

8.2 Typical Application ................................................. 43

Power Supply Recommendations...................... 50

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Timing Requirements.............................................. 10

6.7 Typical Characteristics............................................ 11

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 21

8

9

10 Layout................................................................... 51

10.1 Layout Guidelines ................................................. 51

10.2 Layout Example .................................................... 52

11 器件和文档支持 ..................................................... 53

11.1 器件支持................................................................ 53

11.2 接收文档更新通知 ................................................. 53

11.3 社区资源................................................................ 53

11.4 商标....................................................................... 53

11.5 静电放电警告......................................................... 53

11.6 Glossary................................................................ 53

12 机械、封装和可订购信息....................................... 53

7

4 修订历史记录

Changes from Revision A (February 2018) to Revision B

Page

•

已更改 t_{BAT_LOWV_DGL}from 20 ms to 170 ms in Timing Requirements section...................................................................... 11

Changed DEV_REV default value from 0b001 to 0b010 in REG0D register Part Information Register (Address = Dh)

[reset = 0Ah] ........................................................................................................................................................................ 42

Changes from Original (September 2017) to Revision A

Page

•

已更改将“预告信息”更改为“生产数据”.................................................................................................................................... 1

2

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

5 Pin Configuration and Functions

BQ25910-YFF (I²C controlled)

36-Pin DSBGA

Top View

6

1

2

3

4

5

GND

VBUS

PMID

CFLY+

SW

CFLYœ

A

B

C

D

E

F

GND

VBUS

CDRV+

CDRVœ

SCL

PMID

SDA

CFLY+

INT

SW

CFLYœ

BATP

SW

IND_

SNS

CAUX

REGN

BATN

(1) Top View = Xray through a soldered down part with A1 starting in upper left hand corner.

3

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Negative Battery Sense Terminal – Kelvin connect via 100-Ω resistor as close as possible

to negative battery terminal

BATN

F4

AI

Positive Battery Sense Terminal – Kelvin connect via 100-Ω resistor as close as possible

to positive battery terminal

BATP

CAUX

F5

F2

AI

P

Auxiliary Capacitor – Bypass CAUX to GND with at least a 4.7-μF, 10-V ceramic capacitor

Gate Drive Supply Positive Terminal – CDRV is used to generate multilevel gate drive

CDRV+

CDRV–

D1

E1

P

rails.

Connect a 220-nF, 6.3-V ceramic capacitor across CDRV+ and CDRV-.

Gate Drive Supply Negative Terminal – CDRV is used to generate multilevel gate drive

rails.

Connect a 220-nF, 6.3-V ceramic capacitor across DRV+ and DRV-.

A3

B3

C3

D3

A5

B5

C5

D5

E5

A6

B6

C6

D6

E6

Flying Capacitor Positive Terminal – Connect 20-μF, 16-V ceramic capacitor across

CFLY+ and CFLY–. Refer to Application and Implementation section for more information on

selecting CFLY.

CFLY+

CFLY–

P

Flying Capacitor Negative Terminal – Connect 20-μF, 16-V ceramic capacitor across

CFLY+ and CFLY–. Refer to Application and Implementation section for more information on

selecting CFLY.

GND

-

Ground Return

Output Inductor Sense Input – Kelvin connect as close as possible to the output of the

switched inductor.

IND_SNS

INT

F6

E3

AI

Open-Drain Interrupt Output – Connect INT to the logic rail via a 10-kΩ resistor. The INT

pin sends active low, 256-μs pulse to the host to report charger device status and fault.

DO

A2

B2

C2

D2

Reverse Blocking MOSFET and QHSA MOSFET Connection – Given the total input

capacitance, place 1 μF on VBUS, and the rest on PMID, as close to the device as possible.

Typical value: 10-μF, 25-V ceramic capacitor

PMID

P

Gate Drive Supply – Bias supply for internal MOSFETs driver and device. Bypass REGN to

GND with a 4.7-μF, 10-V ceramic capacitor.

I²C Interface Open-Drain Clock Line – Connect SCL to the logic rail through a 10-kΩ

REGN

SCL

F3

F1

E2

P

DI

resistor.

I²C Interface Open-Drain Data Line – Connect SDA to the logic rail through a 10-kΩ

resistor.

SDA

DIO

A4

B4

C4

D4

E4

A1

B1

C1

Inductor Connection – Connect to the switched side of the external inductor

(Recommended: 330 nH for up to 9-V applications or 470 nH for up to 12-V applications).

Refer to Application and Implementation section for more information on selecting inductor.

SW

P

Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at

least 1-μF, 25-V ceramic capacitor, placed as close to the device as possible.

VBUS

4

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–2

MAX

20

UNIT

VBUS (converter not switching)

PMID (converter not switching)

CDRV+, CDRV-

V

–0.3

20

16⁽²⁾

CFLY+

Voltage range (with

respect to GND)

CFLY+ to SW, SW to

CFLY–, CFLY– to GND,

CAUX to GND

DC

7

Pulse < 30ns

–0.3

11

V

BATP, BATN, IND_SNS

REGN

–0.3

6

V

Voltage range (with

respect to GND)

SDA, SCL, /INT

/INT

–0.3

6

V

Output sink current

6

150

mA

°C

Junction Temperature, T_J

Storage temperature, T_stg

–40

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) This condition is contingent on the fact that 0V < V_CFLY< 8V

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101⁽²⁾

±250

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

NOM

MAX

14⁽¹⁾

3.3

UNIT

V

V_VBUS

I_VBUS

I_SW

Input voltage

3.9

Average input current (VBUS)

Average output current (SW)

Battery voltage (BATP - BATN)

Operating free-air temperature

A

6

A

V_BAT

T_A

4.775

85

V

–40

°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either CFLY+, SW, or CFLY- pins. A

tight layout minimizes switching noise.

6.4 Thermal Information

BQ25910

THERMAL METRIC⁽¹⁾

YFF (DSBGA)

36-PINS

52.8

UNIT

R_ΘJA

R_ΘJC(top)

R_ΘJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

0.3

11.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.2

Ψ_JB

11.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

6.5 Electrical Characteristics

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

QUIESCENT CURRENTS

TEST CONDITIONS

MIN

TYP

MAX UNIT

Battery discharge current (BATP,

BATN, SW)

VBAT = 4.5V, VBUS = 0 - 5V, SCL, SDA =

0V or 1.8V, T_J< 85°C, EN_CHG = 0

I_BAT

6.5

10 μA

30 μA

50 μA

VBUS = 5V, High-Z Mode, no battery

I_{VBUS_HIZ}

Input supply current (VBUS) in HIZ

VBUS < V_{VBUS_OV}, High-Z Mode, no

battery

VBUS > V_SLEEPZ, V_BAT= 3.8V, ICHG = 0A,

converter not switching

20 μA

I_VBUS

Input supply current (VBUS)

VBUS > V_SLEEPZ, V_BAT= 3.8V, converter

switching, IOUT = 0A

13

mA

VBUS / VBAT POWER UP

V_{VBUS_OP}

VBUS operating range

VBUS rising for active I2C, no battery VBUS rising

3.9

3.6

14

V

V_{VBUS_UVLOZ}

VBUS falling, VBUS - VBAT,

VBAT = 4V, T_J= 0°C - 85°C

V_SLEEP

Enter sleep mode threshold

Exit sleep mode threshold

15

60

110 mV

275 mV

VBUS rising, VBUS - VBAT,

VBAT = 4V, T_J= 0°C - 85°C

V_SLEEPZ

115

220

VBUS over-voltage rising threshold

VBUS over-voltage falling threshold

Battery for active I2C, no VBUS

Bad adapter detection threshold

Bad adapter detection current source

VBUS rising

VBUS falling

14

13.3

2.3

14.3

14.7

14

V

V_{VBUS_OV}

13.65

V_{BAT_UVLOZ}

V_POORSRC

V

3.7

20

V

I_POORSRC

mA

POWER-PATH

Top reverse blocking MOSFET on-

R_{ON_QBLK}(QBLK) resistance between VBUS and PMID T_J= –40°C - 125°C

(QBLK)

14

22

12

8

22 mΩ

40 mΩ

20 mΩ

13 mΩ

Outer, high-side switching MOSFET

R_{ON_QHSA}(Q1)

R_{ON_QHSB}(Q3)

R_{ON_QLSB}(Q4)

R_{ON_QLSA}(Q2)

on-resistance between PMID and

CFLY+ (Q1)

T_J= –40°C - 125°C

Inner, high-side switching MOSFET

on-resistance between CFLY+ and

SW (Q3)

Inner, low-side switching MOSFET

on-resistance between SW and

CFLY- (Q4)

Outer, low-side switching MOSFET

on-resistance between CFLY- and

GND (Q2)

8

BATTERY CHARGER

Typical charge voltage regulation

range

V_{REG_RANGE}

V_{REG_STEP}

V_{REG_ACC}

I_{CHG_RANGE}

I_{CHG_STEP}

I_{CHG_ACC}

3.5

4.775

V

mV

%

Typical charge voltage regulation

step

5

VREG = 4.2V or 4.35V or 4.4V,

T_J= –40°C - 85°C

Charge voltage regulation accuracy

-0.4

0.4

Typical charge current regulation

range

1000

6000 mA

mA

Typical charge current regulation

step

50

ICHG = 2A, 3A, 4A, 5A, 6A,

T_J= –40°C - 85°C

Charge current regulation accuracy

-10

10

%

7

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VBUS = 9V, ICHG = 4A, ITERM = 1.0A,

T_J= 0°C - 85°C

Termination current regulation

accuracy

I_{TERM_ACC}

0.9

1

1.1

2.15

3.3

A

V

V_{BAT_SHORT}

Short battery voltage falling threshold VBAT falling

VBAT LOWV Rising threshold to

1.85

3.1

2.00

3.2

VBAT rising, VBATLOW = 3.2V

start fast-charging

V_{BAT_LOWV}

VBAT LOWV Falling threshold to

stop fast-charging

VBAT falling, VBATLOW = 3.2V

VBAT rising, VBATLOW = 3.5V

VBAT falling, VBATLOW = 3.5V

2.9

3.4

3.2

3

3.5

3.3

3.1

3.6

3.4

V

VBAT LOWV Rising threshold to

start fast-charging

V_{BAT_LOWV}

VBAT LOWV Falling threshold to

stop fast-charging

R_BATP

R_BATN

BATP Input resistance

BATN Input resistance

VBAT = 4V, VBUS = 5V, EN_CHG = 0

0.6

MΩ

INPUT VOLTAGE / CURRENT REGULATION

V_{INDPM_RANGE}

V_{INDPM_STEP}

Input voltage regulation range

Input voltage regulation step

3.9

14

V

mV

V

100

4.3

7.8

VINDPM = 4.3V

VINDPM = 7.8V

VINDPM = 10.8V

4.121

7.566

10.476

500

4.447

8.034

V_{INDPM_ACC}

Input voltage regulation accuracy

V

10.8 11.124

V

I_{INDPM_RANGE}

I_{INDPM_STEP}

Input current regulation range

Input current regulation step

3600 mA

mA

100

IINDPM = 500mA, T_J= –40°C - 85°C

IINDPM = 1500mA, T_J= –40°C - 85°C

IINDPM = 2500mA, T_J= –40°C - 85°C

IINDPM = 3000mA, T_J= –40°C - 85°C

410

1275

2125

2540

500 mA

1500 mA

2500 mA

3000 mA

I_{INDPM_ACC}

Input current regulation accuracy

BATTERY OVER-VOLTAGE PROTECTION

Battery over-voltage rising threshold VBAT rising, as percentage of VREG

Battery over-voltage falling threshold VBAT falling, as percentage of VREG

102

100

104

102

106

103

%

V_{BAT_OVP}

THERMAL REGULATION AND THERMAL SHUTDOWN

TREG = 80°C

80

120

150

120

°C

Junction temperature regulation

accuracy

T_REG

TREG = 120°C

Thermal Shutdown Rising threshold

T_SHUT

Temperature Increasing

Thermal Shutdown Falling threshold Temperature Decreasing

BUCK MODE OPERATION

F_SW

PWM switching frequency

Maximum PWM Duty Cycle

Switching-node frequency

1.35

1.5

97

1.65 MHz

%

D_MAX

REGN LDO

V_VBUS= 12V, I_REGN= 40mA

V_VBUS= 5V, I_REGN= 20mA

V_VBUS= 5V, V_REGN= 3.8V

4.85

4.7

50

5

V

V_REGN

I_REGN

REGN LDO output voltage

REGN LDO current limit

4.8

mA

8

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

I2C INTERFACE (SCL, SDA)

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input high threshold level, SDA and

SCL

V_IH

Pull-up rail 1.8V

1.3

V

Input low threshold level, SDA and

SCL

V_IL

Pull-up rail 1.8V

Sink current = 5mA

Pull-up rail 1.8V

0.4

1

V

V_OL

I_BIAS

Output low threshold level, SDA

High level leakage current, SDA and

SCL

μA

LOGIC OUTPUT PIN (/INT)

V_OL

Output low threshold level

High level leakage current

Sink current = 5mA

Pull-up rail 1.8V

0.4

1

V

I_{OUT_BIAS}

μA

9

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

MAX UNIT

6.6 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

TYP

VBUS/BAT POWER UP

VBUS rising above V_{BUS_OV}threshold to

converter turn off

t_{VBUS_OV}

VBUS OVP reaction time

200

30

ns

t_POORSRC

Bad adapter detection duration

ms

BATTERY CHARGER

Deglitchg time for BAT_LOWV

VBAT crossing VBAT_LOWV threshold

(rising and falling)

t_{BAT_LOWV_DGL}

170

250

1

ms

comparator

t_{TERM_DGL}

Deglitch time for charge termination

Charge current falling below I_TERM

Deglitch time for battery over-voltage

to disable charge

t_{BATOVP_DGL}

µs

t_SAFETY

Charge Safety Timer Accuracy

CHG_TIMER[1:0] = 12 hours

10.8

12

13.2 hr

I2C INTERFACE

f_SCL

SCL clock frequency

1000 kHz

DIGITAL CLOCK AND WATCHDOG TIMER

f_DIG

Digital clock

REGN LDO enabled

1.35

136

1.5

1.65 MHz

sec

WATCHDOG[1:0] = 160s, REGN LDO

enabled

t_WDT

Watchdog Reset time

160

10

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

6.7 Typical Characteristics

96

95

94

93

92

91

90

89

88

3

96

95

94

93

92

91

90

89

88

87

86

3

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

V_BUS= 5 V

V_BUS= 9 V

V_BUS= 12 V

V_BUS= 5 V

V_BUS= 9 V

V_BUS= 12 V

V_BUS= 5 V

V_BUS= 9 V

V_BUS= 5 V

V_BUS= 9 V

87

86

0.3

0

1

2

3

Change Current (A)

4

5

6

0

1

2

3

Charge Current (A)

4

5

6

D001

D002

VBAT = 3.8 V, Inductor = DFE252012F-R47 (470 nH, 23 mΩ max)

VBAT = 3.8 V, Inductor = HMLQ25201B-R33 (330 nH, 17 mΩ

max)

图 2. Charge Efficiency vs Charge Current

图 1. Charge Efficiency vs Charge Current

15

V_BUS= 5 V, I_CHG= 2.5 A

V_BUS= 9 V, I_CHG= 2.5 A

V_BUS= 12 V, I_CHG= 2.5 A

V_BUS= 5 V

V_BUS= 9 V

V_BUS= 12 V

10

5

0

5

0

-5

-10

-15

-10

-15

2.9

3.1

3.3

3.5

3.7

V_BAT(V)

3.9

4.1

4.3

4.5

1

2

3

ICHG Setting (A)

4

5

6

D010

D003

VBAT = 3.8 V

图 3. Charge Current Accuracy vs Battery Voltage

图 4. Charge Current Accuracy vs I²C ICHG Setting

15

10

5

0.5

I_CHG= 1.5 A

I_CHG= 2.5 A

I_CHG= 3.5 A

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-5

V_BUS= 5 V

V_BUS= 9 V

V_BUS= 12 V

-10

-15

-40

-20

0

20

40

60

80

100

3.5

3.7

3.9

4.1

VREG Setting (V)

4.3

4.5

4.7

Temperature (èC)

D011

D004

VBUS = 5 V, VBAT = 3.8 V

图 5. Charge Current Accuracy vs Temperature

图 6. Battery Voltage Regulation Accuracy vs I²C VREG

Setting

11

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

Typical Characteristics (接下页)

1300

1200

1100

1000

900

0.5

V_BAT= 4.1 V

0.4

0.3

0.2

0.1

0

V_BAT= 4.2 V

V_BAT= 4.35 V

V_BAT= 4.4 V

-0.1

-0.2

-0.3

-0.4

-0.5

V_BUS= 5 V

V_BUS= 9 V

V_BUS= 12 V

800

700

-40

-20

0

20

40

60

80 90

0

10

20

30

40

50

60

70

80

90

Temperature (èC)

D012

D005

VBUS = 9 V

VREG = 4.35 V

图 7. Battery Voltage Regulation Accuracy vs Temperature

图 8. Termination Current vs Temperature

0

-1

10

5

I_INDPM= 500 mA

I_INDPM= 900 mA

I_INDPM= 1.5 A

I_INDPM= 2.0 A

I_INDPM= 3.0 A

-2

-3

-4

-5

0

-6

-7

-5

-8

-9

-10

-11

-10

-15

-20

-12

V_BUS= 5 V

V_BUS= 9 V

V_BUS= 12 V

-13

-14

-15

0

0.5

1

1.5

IINDPM Setting (A)

2

2.5

3

3.5

-40

-20

0

20

40

60

80

100

Temperature (èC)

D007

D013

VBAT = 3.8 V

VBUS = 5 V, VBAT = 3.8 V

图 9. Input Current Limit Accuracy vs I²C IINDPM Setting

图 10. Input Current Limit Accuracy vs Temperature

3

2

1.8

T_REG= 60èC

T_REG= 80èC

T_REG= 100èC

T_REG= 120èC

2

1

1.6

1.4

1.2

1

0

0.8

0.6

0.4

0.2

0

-1

-2

-3

-0.2

3

4

5

6

7

8

9

VINDPM Setting (V)

10

11

12

13

40

60

80

100

120

140

160

180

Temperature (èC)

D008

D009

ICHG = 1.9 A

图 12. Charge Current vs Temperature

图 11. Input Voltage Limit Accuracy vs I²C VINDPM Setting

12

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

7 Detailed Description

7.1 Overview

The BQ25910 is an integrated three-level switch-mode parallel battery charge management device for single cell

Li-ion and Li-polymer batteries. Utilization of the three-level converter maintains highest switch-mode operation

efficiency while reducing solution footprint and increasing power density. The device supports fast charging with

high input voltage for a wide range of portable devices. The solution integrates reverse-blocking FET (Q_BLK), and

four switching FETs (Q_HSA, Q_HSB, Q_LSB, Q_LSA). The I²C serial interface with charging and system settings makes

the device a truly flexible solution.

The device supports a wide range of input sources, including standard USB host port, USB charging port, and

USB compliant adjustable high voltage adapter. The device is compliant with USB 2.0 and USB 3.0 power

specifications with input current and voltage regulation.

After initiating a charging cycle with host control, the device completes a charging cycle without software control.

It automatically detects battery voltage and charges the battery in two-phases: constant current and constant

voltage. At the end of the charging cycle, the charger automatically terminates when the charge current is below

a preset limit (termination current) in the constant voltage phase.

The device provides various safety features for battery charging, including charging safety timer, battery over-

voltage, and over-current protections. Thermal regulation reduces charge current when the device junction

temperature exceeds 120°C (programmable via I²C). The INT output immediately notifies the host when the

charger changes state or a fault occurs.

The BQ25910 is available in space-saving 36-bump 2.41 x 2.44 mm²WCSP.

13

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

7.2 Functional Block Diagram

The device is a highly integrated 6-A three-level switch-mode parallel battery charger for single-cell Li-ion and Li-

polymer batteries. It integrates a reverse-blocking FET (QBLK), four switching FETs for three-level operation

(QHSA – QLSA), and bootstrap cap control to drive HS gates.

VBUS

PMID

QBLK

V_{VBUS_UVLO}

1 ꢀF

+

UVLO

BLKFET

CONTROL

10 ꢀF

QHSA

V_SLEEP

REGN

BATLOWV

EN_CHG

SLEEP

REGN

LDO

4.7 ꢀF

CFLY+

VBUS_ OVP

V_{VBUS_OV}

V_O,REF

QHSB

D0

2x 10 ꢀF

SR0

V_VBUS

VBAT

+

V_{BAT_OVP}

D180

SR180

VSW

BAT_OVP

V_INDPM

GATE DRIVERS,

CURRENT SENSE,

CFLY PRE-CHARGE

AND MONITOR

+

I_IN

QLSB

+

VBAT

DC-DC

CONTROL

330nH/

470nH

+

I_INDPM

V_{BAT_REG}

OCP

IC_T_J

T_REG

+

ICHG

CFLYœ

I_{CHG_REG}

QLSA

EN_CHARGE

GND

CFLY_FAULT

REF

DAC

V_POORSRC

V_VBUS

IND_SNS

+

POORSRC

CONVERTER

CONTROL

STATE

I_{C_TJ}

TSHUTDOWN

+

MACHINE

T_SHUT

BATP

20 ꢀF

VBAT

BATSNS

BATN

ICHG

I_TERM

TERMINATION

BATLOWV

+

CAUX

FETS &

CONTROL

CAUX

CHARGE

CONTROL

STATE

V_{BAT_LOWV}

VBAT

+

MACHINE

4.7 ꢀF

INT

V_{BAT_SHORT}

VBAT

BATSHORT

+

I2C

INTERFACE

BOOTSTRAP

CAP CONTROL

CDRV+

BQ25910

220 nF

SCL

SDA

CDRVœ

图 13. BQ25910 I²C Controlled Functional Block Diagram

7.3 Feature Description

7.3.1 Device Power-On-Reset (POR)

The internal bias circuits are powered from the higher voltage of VBUS and VBAT. When V_VBUSrises above

V_{VBUS_UVLOZ}, or V_BATrises above V_{BAT_UVLOZ}, the sleep comparator and battery depletion comparator are active.

I²C interface is ready for communication and all the registers are reset to default value. The host can access all

the registers after POR.

14

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

Feature Description (接下页)

7.3.2 Device Power Up from Battery without Input Source

If only battery is present, the device consumes up to I_BATquiescent current. The REGN LDO stays off to

minimize the current draw. I²C interface is ready for communication as long as V_BATis above V_{BAT_UVLOZ}

.

7.3.3 Device Power Up from Input Source

When an input source is plugged in, and the EN_CHG bit is set to 1, the device checks the input source voltage

and battery voltage to turn on REGN LDO, all the bias circuits and begin charging. The startup sequence from

input source is as listed:

1. Power up REGN LDO

2. Poor source qualification

3. C_FLYand C_AUXpre-charging routine

4. Converter Power-up

7.3.4 Power Up REGN LDO

The REGN LDO supplies internal bias circuits and power FET gate drivers. The pull-up rail of INT can be

connected to REGN as well. The REGN LDO is enabled when all the following conditions are met:

1. VBUS above V_{BUS_UVLOZ}

2. VBUS above V_BAT+ V_SLEEPZ

3. VBUS below V_{VBUS_OV}

4. V_BATabove V_{BAT_LOWV}

5. EN_CHG bit = 1

6. ICHG ≠ 0 A

If one of the above conditions is not met, the device is in high impedance mode (HIZ) with REGN LDO off. The

device draws less than I_{VBUS_HIZ}from VBUS in this state.

7.3.5 Poor Source Qualification

After REGN LDO powers up, the device checks the current capability of the input source. The input source has

to meet the following requirements in order to operate the buck converter:

1. VBUS voltage below V_{VBUS_OV}

2. VBUS voltage above V_POORSRCwhen pulling I_POORSRC(typical 20 mA)

Once the conditions are met, the status register bit PG_STAT is set high and the INT pin is pulsed to signal the

host. If VBUS_OV is detected (condition 1 above), the device automatically retries detection once the over-

voltage fault goes away. If a poor source is detected (condition 2 above), the device repeats poor source

qualification routine every 2 seconds. After 7 consecutive failures, the device sets POORSRC_STAT, sends an

INT pulse to notify the host, goes to HIZ mode and resets EN_CHG bit. Adapter re-plugin and/or EN_CHG toggle

is required to restart device operation.

7.3.6 Converter Power-Up

Prior to converter switching, the flying and auxiliary capacitors, CFLY, and CAUX are charged to VBUS/2. After

the capacitors have been pre-charged, the converter is enabled and the switching FETs Q_HSA– Q_LSBstart

switching. As a battery charger, the device deploys a highly-efficient 750-kHz three-level step-down switching

regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of

input voltage, battery voltage, charge current and temperature, simplifying output filter design.

The charge current is soft-started into the desired value by starting from 300 mA and increasing the current up to

ICHG programmed value over time. This "soft-start" also applies when increasing the ICHG register value while

charging.

15

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

Feature Description (接下页)

7.3.7 Three-Level Buck Converter Theory of Operation

The three-level converter is a combination of a switched capacitor and a switched inductor circuit. Assuming the

flying capacitor, CFLY, remains balanced at VIN/2, the VSW node can be presented with three different voltages:

VIN, VIN/2, and GND. The gate driving scheme is similar to a two-phase buck converter. The outer FETs (QHSA

and QLSA) are driven with a complimentary signal with duty cycle D = VOUT/VIN. The inner FETs (QHSB and

QLSB) are driven with a second complimentary signal of equal duty cycle, but phase shifted by 180°. By

employing this driving scheme, there is a smooth transition around 50% duty ratio, where the VSW node moves

from presenting GND and VIN/2 to presenting VIN and VIN/2.

The three-level can achieve higher efficiency which cannot be easily obtained using traditional buck converter.

The high efficiency is due to reduced inductor ripple (volt-seconds), reduced switching loss, and use of a

compact inductor with lower DCR. The device integrates low R_DSONFETs to optimize conduction loss. It also

integrates control circuit to monitor CFLY stability and pre-conditioning.

D < 0.50

L

V_SW

V_IN

V_SW

V_IN/2

QHSA

QHSB

QLSB

V_O

+

V_O

œ

+

t

+

V_IN

œ

C_O

C_FLY

D > 0.50

V_O

V_SW

V_IN

QLSA

V_IN/2

t

图 14. (a) Three-Level Buck Converter Circuit, (b) Time-Domain V_SWand V_OWaveforms, and (c) Inductor

Current Ripple Comparison Across Duty Ratio

D < 0.50

L

V_SW

QHSA

QHSB

QHSA

QHSB

QHSA

QHSB

QLSB

QLSA

+

V_O

œ

+

V_IN

V_OV_IN

œ

C_O

C_FLY

œ

QLSA

图 15. Three-Level Buck Converter States for Duty Ratios < 0.50

D > 0.50

L

V_SW

QHSA

QHSB

QHSA

QHSB

QLSB

QHSA

QHSB

QLSB

+

V_O

œ

+

V_O

œ

+

V_IN

V_OV_IN

œ

C_O

C_FLY

œ

QLSA

图 16. Three-Level Buck Converter States for Duty Ratios > 0.50

16

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

Feature Description (接下页)

7.3.8 Host Mode and Default Mode

7.3.8.1 Host Mode and Default Mode in BQ25910

The BQ25910 is a host controlled charger, and will automatically shut off when the I²C watchdog timer is not

reset within the timer period. In default (HIZ) mode, the device automatically disables charging until the host

writes the EN_CHG bit high again and resets the watchdog timer via the WD_RST bit. When the charger is in

default mode, WD_STAT bit is HIGH. When the charger is in host mode, WD_STAT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired. All the registers are in the

default settings. In default mode, the device remains in HIZ mode and will not charge the battery.

Writing a 1 to the WD_RST bit forces the charger out of default mode and into host mode. All the device

parameters can be programmed by the host. To keep the device in host mode, the host has to reset the

watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set), or disable

watchdog timer by setting WATCHDOG bits = 00.

When the watchdog timer is expired (WD_STAT bit = 1), the device returns to default mode and registers are

reset to default values except as detailed in the I²C register section. As long as the watchdog timer is expired

(WD_STAT bit = 1), the device remains in Default Mode without charging the battery, regardless of the EN_CHG

bit state. In order to enable charge after watchdog expired, write WD_RST = 1, and EN_CHG = 1.

POR

Watchdog timer expired

Reset registers

I2C interface enabled

Default Mode

Watchdog timer expired

Reset selective registers

Y

N

Watchdog Timer

Expired?

WD_RST bit = 1?

N

Y

Host Mode

Start Watchdog timer

Host programs registers

WD_RST bit = 1?

N

Y

图 17. Watchdog Timer Flow Chart

The REG_RST bit can be used to reset all of the registers (except STATUS registers) to their default value at

any time.

7.3.9 Battery Charging Management

The device charges single-cell Li-Ion battery with up to 6-A charge current for high-capacity battery.

7.3.9.1 Autonomous Charging Cycle

When battery charging is enabled (EN_CHG bit = 1) and the battery is above V_{BAT_LOWV}, the device

autonomously completes a charging cycle. The device default charging parameters are listed in 表 1. The host

can always control the charging operations and optimize the charging parameters by writing to the corresponding

registers through I²C.

17

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

Feature Description (接下页)

表 1. Charging Parameter Default Settings

PARAMETER

VBAT to start fast charge (VBATLOWV)

Charging voltage (VREG)

VALUE

3.5 V

4.350 V

3.500 A

1.000 A

12 hours

Charging current (ICHG)

Termination current (ITERM)

Safety timer (CHG_TIMER)

A new charge cycle starts when the following conditions are valid:

•

Converter starts

Battery charging is enabled by EN_CHG bit, and ICHG register is not 0 mA

Battery voltage above V_{BAT_LOWV}

No safety timer fault

The charger device automatically terminates the charging cycle when the charging current is below termination

threshold, and device not in DPM mode or thermal regulation. Once termination is detected, an INT is asserted

to the host and the EN_CHG bit gets reset to zero. After the charge is done, EN_CHG bit can initiate a new

charging cycle.

Once a charging cycle is complete, an INT pulse is asserted to notify the host. In addition the status register

(CHRG_STAT) indicates the different charging phases (any change in CHRG_STAT will generate an INT to

notify the host):

•

000: Charging disable

001: Reserved

010: Reserved

011: Fast charge (constant current mode)

100: Taper charge (constant voltage mode)

101: Reserved

110: Reserved

111: Reserved

7.3.10 Master Charger and Parallel Charger Interactions

A master charger is required in the system to manage pre-charging and full termination of the battery. The

BQ25910 monitors the battery voltage and compares it to V_{BAT_LOWV}to ensure battery can safely take fast-

charge current. Once the BQ25910 turns on and begins fast-charging, the host has two options: disable (HIZ) the

master charger, or continue running the master charger along with the parallel charger.

For the first option, once battery voltage reaches V_{BAT_LOWV}, the master charger maintains the BATFET on to

supply system from battery (EN_HIZ = 1 on master charger), and the BQ25910 provides both the charge current

and system current if required. It is recommended to select V_{BAT_LOWV}equal to minimum system voltage in order

to maintain system operation during transition. The BQ25910 will then fast-charge the battery up to VREG and

continue to regulate voltage while battery current tapers down. After the BQ25910 detects termination, the host

can re-enable the master charger to regulate battery voltage in CV mode down to lower termination currents.

The second mode of operation requires both chargers to stay on. In order to maximize efficiency, it is

recommended to run the master charger at lower charge current than the BQ25910. For example, the master

charger might be set at 1 A and the BQ25910 at 3.5 A to achieve total charge current of 4.5 A. In this mode of

operation, the master charger provides mostly system current, while the BQ25910 provides mostly charge

current. In this mode of operation, the BQ25910 can select V_{BAT_LOWV}as low as the battery dictates for fast-

charge, since the master charger can maintain system voltage regulation and ensure system continues to

operate through the transition. After the BQ25910 detects termination, the master charger automatically

continues to regulate battery voltage in CV mode down to lower termination current.

图 18 shows both options with charge current for each device as well as battery voltage.

18

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

Voltage

4.35V

BATP - BATN

SYS_MIN

3.5V

BATP - BATN

Current

Time

4.5A

BQ2591x

ICHG

Master Charger

ICHG

2A

Time

Master Charger:

HIZ or

ICHG ≤ 1A

Master Charger:

Pre-charges BAT

HIZ or

ICHG ≤ 1A

ITERM << 0.5A

BQ25910:

Off

BQ25910:

Off

BQ25910:

ICHG = 4.5A

BQ25910:

ITERM = 1A

图 18. Master Charger and BQ25910 Handoff

7.3.11 Battery Charging Profile

The device charges the battery in two phases: constant current, and constant voltage. At the beginning of a

charging cycle, the device checks the battery voltage and regulates current / voltage as needed. If the battery

voltage is below V_{BAT_LOWV}, it is the master charger responsibility to increase VBAT up to V_{BAT_LOWV}so the

parallel charger can initiate fast charging. As BAT increases to V_{BAT_LOWV}, the master charger can stay in HIZ

and the BQ25910 can start fast-charging the battery with up-to 6-A ICHG. Alternatively, the master charger can

remain on to maintain the system load from adapter, while the BQ25910 charges the battery. The default

charging settings can be found in 表 2.

表 2. Battery Charger Setting

VBAT

< 2 V

CHARGING CURRENT

Master controlled (IBATSHORT )

Master controlled (IPRECHG )

ICHG

REG DEFAULT SETTING

BQ25910 off

3.500 A

CHRG_STAT

000

011

100

2 V – V_{BAT_LOWV}

> V_{BAT_LOWV}

VREG

TAPER down to ITERM

4.350 V

19

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less

than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is

counted at half the clock rate.

BQ25910 Charge Cycle

Fast Charge

ICHG

BQ25910 on

VREG

Battery Current

Battery Voltage

VBATLOWV

ITERM

3.0V

0A

Pre-Charge

Master

Charger

CC

Master

Charger

CV

Master

Charger

CC

BQ25910

CV

BQ25910

CHRG_STAT[2:0]

000

011

100

000

图 19. Battery Charging Profile Highlighting Parallel Charger Region of Operation

After the device signals charge termination done (CHRG_TERM_FLAG = 1), the master charger may choose to

continue charging in CV mode or finish the charging cycle completely. The BQ25910 will not start a re-charge

cycle automatically, and a toggle on EN_CHG bit is required to restart a charge cycle.

7.3.11.1 Charging Termination

The device terminates a charge cycle when the battery voltage is at VREG, and the current is below termination

current (ITERM). After the charging cycle is completed, the converter turns off and enters HIZ mode. At this

point, the master charger can continue charging the battery down to a lower termination current, or just provide

the system load from the adapter through its buck converter.

When termination occurs, the status register CHRG_STAT is set to 000, the CHRG_TERM_FLAG is set to 1,

and an INT pulse is asserted to the host. The CHRG_TERM_FLAG should be used to determine if termination

was detected. Termination is temporarily disabled when the charger device is in input current, input voltage or

thermal regulation.

Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination. In this case, the device will

continue regulating the battery voltage to VREG value until the safety timer runs out or until the EN_CHG bit is

cleared.

7.3.11.2 Differential Battery Voltage Remote Sensing

For high current charging systems, resistance between the charger output and battery cell terminal such as

board routing, connector, MOSFETs and sense resistor can force the charging process to move from constant

current to constant voltage too early, thereby increasing charge time. To speed up the charging cycle, the device

provides differential remote sensing terminals for battery positive and negative terminals, which can extend the

constant current charge time to deliver maximum power to the battery.

The device regulates BATP – BATN = V_BATto the programmed VREG voltage. By connecting the sense

terminals as close the battery as possible, the charger can deliver maximum charging power to battery. The

kelvin connections to the battery can be made via a 100-Ω resistor.

20

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

7.3.11.3 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The

user can program fast charge safety timer through I²C (CHG_TIMER bits). When safety timer expires, the

TMR_FLAG bit is set to 1, and an INT pulse is asserted to the host. The safety timer feature can be disabled via

I²C using EN_TIMER bit.

During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge

current is likely to be below the register setting. For example, if the charger is in input current regulation

(IINDPM_STAT = 1) throughout the whole charging cycle, and the safety timer is set to 5 hours, then the timer

will expire in 10 hours. This half clock rate feature can be disabled by setting TMR2X_EN = 0. Changing the

TMR2X_EN bit while the device is running has no effect on the safety timer count, other than forcing the timer to

count at half the rate under the conditions dictated above.

7.4 Device Functional Modes

7.4.1 Lossless Current Sensing

In high current charging systems, extra resistance between the charger output and the battery contribute to

power loss and temperature rise. The BQ25910 regulates the output current without the need of a sense resistor,

thereby reducing system power loss and operating temperature. Switching FET current information is used in

conjunction to inductor DCR sensing to regulate output current accurately. For optimal operation, the voltage

drop across the DCR should be below 180 mV. For example, to achieve 6-A charging, the DCR should be below

30 mΩ. In addition to lossless current regulation, the switching FET current is monitored on a cycle-by-cycle

basis to ensure safe operation.

7.4.2 Dynamic Power Management

To meet maximum current limit in USB spec and avoid over-loading the adapter, the device features Dynamic

Power Management (DPM), which continuously monitors the input current and input voltage. When input source

is over-loaded, either the current exceeds the input current limit (IINDPM) or the voltage falls below the input

voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input

current limit and the input voltage rises above the input voltage limit.

During DPM mode, the status register bits VINDPM_STAT (VINDPM) and/or IINDPM_STAT (IINDPM) is/are set

to 1. 图 20 shows the IINDPM response with 9-V/1.33-A (12-W) adapter, 4.0-V battery, 3.5-A charge current, and

BQ25910 in CV mode.

21

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

Device Functional Modes (接下页)

SYSTEM

LOAD

I_SYS

V_BUS

SYS

VBUS

BQ25898

(Hi-Z Mode)

BAT

I_OUT,910

I_BUS

SW2

VBUS

I_BAT

+

VBAT

-

GND

BQ25910

V_BUS

9.0V

8.5V

4A

3A

2A

I_OUT

I_BAT

I_BUS

1A

0A

I_SYS

-1A

CV

IINDPM

CV

图 20. DPM Response

7.4.3 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT pin notifies the system

host on the device operation. By default, the following events will generate an active-low, 256-μs INT pulse.

1. Good input source detected (three conditions below met)

–

V_VBUS> V_BAT(not in sleep)

V_VBUS< V_{VBUS_OV}

V_VBUS> V_VPOORSRC(typ 3.7 V) when I_POORSRC(typ 20 mA) current is applied (not a poor source)

2. Good input source removed

3. POORSRC routine failed 7 consecutive times (connected adaptor was found to be a poor source)

4. Capacitor pre-charge routine failed (CFLY / CAUX failed to pre-charge)

5. Entering IINDPM regulation

6. Entering VINDPM regulation

7. Entering device Junction Temperature Regulation

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Device Functional Modes (接下页)

8. I²C Watchdog timer expired

–

At initial power-up, this INT gets asserted to signal I²C is ready for communication

9. Charger changes state (CHRG_STAT value change)

10. VBUS over-voltage detected

11. Junction temperature shutdown (TSHUT)

12. Battery over-voltage detected (BATOVP)

13. CFLY fault detected

14. Charge Safety Timer Expired

Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur.

Three bits exist for each one of these events:

•

The STAT bit holds the current status of each INT source

The FLAG bit holds information on which source produced an INT, regardless of current status.

The MASK bit is used to prevent the device from sending out INT for each particular event.

When one of the above conditions occurs, the device sends out an INT pulse and keeps track of which source

generated the INT via the FLAG registers. The FLAG register bits are automatically reset to zero after the host

reads them, and a new edge on STAT bit is required to re-assert the FLAG.

IINDPM_STAT

IINDPM_FLAG

TREG_STAT

TREG_FLAG

INT

I2C Flag Read

图 21. INT Generation Behavior Example

7.4.4 Protections

7.4.4.1 Voltage and Current Monitoring

The device closely monitors the input and output voltage, as well as switching FET currents for safe buck mode

operation.

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Device Functional Modes (接下页)

7.4.4.1.1 Input Over-Voltage (V_{VBUS_OV}

)

The valid input voltage range for buck mode operation is V_{VBUS_OP}. If VBUS voltage exceeds V_{VBUS_OV}, the

device stops switching immediately to protect the power FETs. During input over-voltage, an INT pulse is

asserted to signal the host, and the VBUS_OVP_STAT and VBUS_OVP_FLAG fault register bits get set. The

device automatically starts switching again when the over-voltage condition goes away.

7.4.4.1.2 Input Under-Voltage (V_POORSRC

)

The valid input voltage range for buck mode operation is V_{VBUS_OP}. If VBUS voltage falls below V_POORSRC, the

device stops switching. During input under-voltage, an INT pulse is asserted to signal the host, and the

PG_STAT bit gets cleared. The PG_FLAG bit will get set to signal this event. The device automatically attempts

to restart switching when the under-voltage condition goes away.

7.4.4.1.3 Flying Capacitor Over- or Under-Voltage Protection (V_{CFLY_OVP}and V_{CFLY_UVP}

)

Under normal operating conditions the flying capacitor is balanced by the converter. However, during line

transients or other failures, capacitor mis-balance is possible. The device constantly monitors the flying capacitor

voltage. If VCFLY exceeds the protection limits, the device stops switching immediately. When this fault is

detected, an INT pulse is asserted to notify the host, and the CFLY_STAT and CFLY_FLAG fault register bits get

set. The device automatically attempts to re-balance the cap and resumes charging if successful. If the device

fails to re-balance CFLY, the CAP_COND_STAT and CAP_COND_FLAG fault register bits get set, and an

EN_CHG toggle is required to re-attempt charging.

7.4.4.1.4 Over Current Protection

The device monitors the outer switching FET current on a cycle-by-cycle basis . If an over-current is detected,

the device responds by forcing the switching FETs to immediately discharge the inductor current and attempt

current ramp-up once again.

7.4.4.2 Thermal Regulation and Thermal Shutdown

The device monitors internal junction temperature T_Jto avoid overheating the chip and limits the device surface

temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit

(TREG bits), the device reduces charge current. A wide thermal regulation range from 60°C to 120°C allows the

user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed value in ICHG registers.

Therefore, termination is disabled, the safety timer runs at half the clock rate, the status register TREG_STAT bit

goes high, and an INT is asserted to the host.

Additionally, the device has thermal shutdown to turn off the converter when device surface temperature exceeds

T_SHUT. The fault register TSHUT_STAT is set and an INT pulse is asserted to the host. The converter turns back

on when device temperature is below T_{SHUT_HYS}

.

7.4.4.3 Battery Protection

7.4.4.3.1 Battery Over-Voltage Protection (BATOVP)

The battery over-voltage limit is clamped at 4% above the battery regulation voltage. When battery over-voltage

occurs, the charger device immediately disables charge. The fault register BATOVP_STAT bit goes high and an

INT pulse is asserted to signal the host.

7.5 Programming

7.5.1 Serial Interface

The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device

status reporting. I²C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial

data line (SDA), and a serial clock line (SCL). Devices can be considered as masters or slaves when performing

data transfers. A master is a device which initiates a data transfer on the bus and generates the clock signals to

permit that transfer. At that time, any device addressed is considered a slave.

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Programming (接下页)

The device operates as a slave device with address 4BH, receiving control inputs from the master device like

micro-controller or digital signal processor through REG00-REG0D. Register read beyond REG0D (0x0D) returns

0xFF. The I²C interface supports both standard mode (up to 100 kbits/s), and fast mode (up to 400 kbits/s).

When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the

positive supply voltage via a current source or pull-up resistor.

7.5.2 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on SCL line is LOW. One clock pulse is generated for each data

bit transferred.

SDA

SCL

Data line stable;

Data valid

Change of

data allowed

图 22. Bit Transfers on the I²C Bus

7.5.3 START and STOP Conditions

All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The

bus is considered busy after the START condition, and free after the STOP condition.

SDA

SCL

SDA

SCL

STOP (P)

START (S)

图 23. START and STOP Conditions on the I²C Bus

7.5.4 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the Most

Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has

performed some other function, it can hold the SCL line low to force the master into a wait state (clock

stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL

line.

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Programming (接下页)

Acknowledgement

signal from receiver

Acknowledgement

signal from slave

MSB

SDA

SCL

S or Sr

1

2

8

9

1

2

8

9

P or Sr

7

ACK

START or

Repeated

START

STOP or

Repeated

START

图 24. Data Transfer on the I²C Bus

7.5.5 Acknowledge (ACK) and Not Acknowledge (NACK)

The ACK signaling takes place after byte. The ACK bit allows the receiver to signal the transmitter that the byte

was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock

pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse

so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this 9th clock

pulse. A NACK is signaled when the SDA line remains HIGH during the 9th clock pulse. The master can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

7.5.6 Slave Address and Data Direction Bit

After the START signal, a slave address is sent. This address is 7 bits long, followed by the 8 bit as a data

direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

The device 7-bit address is defined as 1001 011’ (0x4BH) by default. The address bit arrangement for 4BH is

shown in 图 25.

Slave Address

1

0

1

0

1

R / W

图 25. 14: 7-Bit Addressing (4BH)

SDA

SCL

S

1-7

8

9

1-7

8

9

1-7

8

9

P

START

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

图 26. Complete Data Transfer on I²C Bus

7.5.7 Single Read and Write

图 27. Single Write

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Programming (接下页)

图 28. Single Read

If the register address is not defined, the charger device sends back NACK and returns to the idle state.

7.5.8 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write of all registers.

图 29. Multi-Write

图 30. Multi-Read

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7.6 Register Maps

7.6.1 I²C Registers

Table 3 lists the memory-mapped registers for the I²C. All register offset addresses not listed in Table 3 should

be considered as reserved locations and the register contents should not be modified.

Table 3. I²C Register Summary Table

Address

0h

Access Type

Acronym

REG00

REG01

REG02

REG03

REG04

REG05

REG06

REG07

REG08

REG09

REG0A

REG0h

REG0C

REG0D

Register Name

Battery Voltage Limit

Charge Current Limit

Input Voltage Limit

Input Current Limit

RESERVED

Section

Go

R/W

R

1h

Go

2h

Go

3h

Go

4h

Go

5h

Charger Control 1

Charger Control 2

INT Status

Go

6h

Go

7h

Go

8h

R

FAULT Status

INT Flag

Go

9h

R

Go

Ah

Bh

Ch

Dh

R

FAULT Flag

Go

R/W

INT Mask

Go

FAULT Mask

Go

Part Information

Go

Complex bit access types are encoded to fit into small table cells. Table 4 shows the codes that are used for

access types in this section.

Table 4. I²C Access Type Codes

Access Type

Code

Description

Read Type

R

Read

Write Type

W

Write

Reset Value

-n

Value after reset

Undefined value

-X

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7.6.1.1 Battery Voltage Regulation Limit Register (Address = 0h) [reset = AAh]

REG00 is shown in Figure 31 and described in Table 5.

Return to Summary Table.

Figure 31. REG00 Register

7

6

5

4

3

2

1

0

VREG[7:0]

R/W-AAh

Table 5. REG00 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

VREG[7]

VREG[6]

VREG[5]

VREG[4]

VREG[3]

VREG[2]

VREG[1]

VREG[0]

R/W

Yes

640 mV

320 mV

160 mV

80 mV

40 mV

20 mV

10 mV

5 mV

Charge voltage limit:

Offset: 3.5 V

Range: 3.5 V to 4.775 V

Default 4.35 V

Yes

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7.6.1.2 Charger Current Limit Register (Address = 1h) [reset = 46h]

REG01 is shown in Figure 32 and described in Table 6.

Return to Summary Table.

Figure 32. REG01 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

ICHG[6:0]

R/W-46h

Table 6. REG01 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

RESERVED

R/W

Yes

Reserved bit always reads 0h

6

5

4

3

2

1

0

ICHG[6]

ICHG[5]

ICHG[4]

ICHG[3]

ICHG[2]

ICHG[1]

ICHG[0]

R/W

Yes

3200 mA

Fast charge current limit

Offset: 0 mA

Range: 0 mA to 6000 mA

Default: 3500 mA

NOTE: ICHG > 6 A (78h) clamped to 6 A

ICHG < 300 mA (06h) clamped to 0 A

1600 mA

800 mA

400 mA

200 mA

100 mA

50 mA

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7.6.1.3 Input Voltage Limit Register (Address = 2h) [reset = 04h]

REG02 is shown in Figure 33 and described in Table 7.

Return to Summary Table.

Figure 33. REG02 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

VINDPM[6:0]

R/W-04h

Table 7. REG02 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

RESERVED

R/W

Yes

No

Reserved bit always reads 0h

6400 mV

6

5

4

3

2

1

0

VINDPM[6]

VINDPM[5]

VINDPM[4]

VINDPM[3]

VINDPM[2]

VINDPM[1]

VINDPM[0]

R/W

Yes

No

Absolute input-voltage limit

3200 mV

1600 mV

800 mV

400 mV

200 mV

100 mV

Offset: 3.9 V

Range: 3.9 V to 14 V

Default: 4.3 V

NOTE: VINDPM > 14 V (65h) clamped to 14 V

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7.6.1.4 Input Current Limit Register (Address = 3h) [reset = 13h]

REG03 is shown in Figure 34 and described in Table 8.

Return to Summary Table.

Figure 34. REG03 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

INDPM[5:0]

R/W-13h

Table 8. REG03 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7-6

RESERVED

R/W

Yes

No

Reserved bit always reads 0h

5

4

3

2

1

0

INDPM[5]

INDPM[4]

INDPM[3]

INDPM[2]

INDPM[1]

INDPM[0]

R/W

Yes

No

3200 mA

Input current limit

Offset: 500 mA

Range: 500 mA to 3600 mA

Default: 2400 mA

NOTE: INDPM > 3600 mA (1Fh) clamped to 3600mA

1600 mA

800 mA

400 mA

200 mA

100 mA

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7.6.1.5 Reserved Register (Address = 4h) [reset = 03h]

REG04 is shown in Figure 35 and described in Table 9.

Return to Summary Table.

Figure 35. REG04 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

R/W-3h

Table 9. REG04 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

RESERVED

Type

Description

7-0

R/W

Yes

Reserved bit always reads 03h

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7.6.1.6 Charger Control 1 Register (Address = 5h) [reset = 9Dh]

REG05 is shown in Figure 36 and described in Table 10.

Return to Summary Table.

When the WATCHDOG[1:0] bits change (writing the same value does not change these bits), the internal

counter is reset. The same applies for the CHG_TIMER bits (changing the value in the register will reset the

CHG_TIMER).

Figure 36. REG05 Register

7

6

5

4

3

2

1

0

EN_TERM

R/W-1h

WD_RST

R/W-0h

WATCHDOG[1:0]

R/W-1h

EN_TIMER

R/W-1h

CHG_TIMER[1:0]

R/W-2h

TMR2X_EN

R/W-1h

Table 10. REG05 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

EN_TERM

R/W

Yes

Termination control

0h = Disable termination

1h = Enable termination

6

WD_RST

R/W

Yes

I²C watchdog-timer reset

0h = Normal

1h = Reset (bit returns to 0 after time reset)

5-4

WATCHDOG[1:0]

I²C watchdog-timer settings

0h = Disable watchdog timer

1h = 40 s

2h = 80 s

3h = 160 s

3

EN_TIMER

R/W

Yes

Charging safety-timer enable

0h = Disable

1h = Enable

2-1

CHG_TIMER[1:0]

Fast-charge safety timer setting

0h = 5 hours

1h = 8 hours

2h = 12 hours

3h = 20 hours

0

TMR2X_EN

R/W

Yes

Safety timer behavior during DPM or TREG

0h = Safety timer always counts normally

1h = Safety timer count slowed by 2x during input DPM or

TREG

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7.6.1.7 Charger Control 2 Register (Address = 6h) [reset = 33h]

REG06 is shown in Figure 37 and described in Table 11.

Return to Summary Table.

When the watchdog timer expires (WD_STAT = 1h), the EN_CHG bit is held in reset. To enable the charger after

the watchdog expires, write a value of 1h to the WD_RST bit and a value of 1h to the EN_CHG bit.

Figure 37. REG06 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

TREG[1:0]

R/W-3h

EN_CHG

R/W-0h

RESERVED

R/W-0h

VBATLOWV[1:0]

R/W-3h

Table 11. REG06 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

7-6

5-4

Field

Type

R/W

Description

RESERVED

TREG[1:0]

Yes

Reserved bit always reads 0h

Thermal regulation threshold

0h = 60°C

1h = 80°C

2h = 100°C

3h = 120°C

3

EN_CHG

R/W

Yes

Charger enable configuration

0h = Charger disabled

1h = Charger enabled

2

RESERVED

R/W

Yes

No

Reserved bit always reads 0h

1-0

VBATLOWV[1:0]

V_{BAT_LOWV}threshold to start charging at ICHG programmed

setting:

0h = 2.6 V

1h = 2.9 V

2h = 3.2 V

3h = 3.5 V

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7.6.1.8 INT Status Register (Address = 7h) [reset = X]

REG07 is shown in Figure 38 and described in Table 12.

Return to Summary Table.

Figure 38. REG07 Register

7

6

5

4

3

2

1

CHRG_STAT[2:0]

R-X

0

PG_STAT

R-X

INDPM_STAT

R-X

VINDPM_STAT

R-X

TREG_STAT

R-X

WD_STAT

R-X

Table 12. REG07 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

PG_STAT

R

Yes

No

Power-good status

0h = Not power good

1h = Power good

6

INDPM_STAT

VINDPM_STAT

TREG_STAT

WD_STAT

R

INDPM status

0h = Normal

1h = In INDPM regulation

5

VINDPM status

0h = Normal

1h = In VINDPM regulation

4

Device thermal-regulation status

0h = Normal

1h = In thermal regulation

3

I²C watchdog-timer status

0h = Normal

1h = Watchdog timer expired

2-0

CHRG_STAT[2:0]

Yes

Charge status

0h = Not charging

1h = Reserved

2h = Reserved

3h = Fast charging (CC mode)

4h = Taper charging (CV mode)

5h = Reserved

6h = Reserved

7h = Reserved

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7.6.1.9 FAULT Status Register (Address = 8h) [reset = X]

REG08 is shown in Figure 39 and described in Table 13.

Return to Summary Table.

When the watchdog timer expires (WD_STAT = 1h), the VBUS_OVP_STAT, TSHUT_STAT, BATOVP_STAT,

and CFLY_STAT bits are held in reset until the watchdog fault is cleared (WD_RST bit = 1h, or changing the

WATCHDOG[1:0] bits).

Figure 39. REG08 Register

7

6

5

4

3

2

1

0

VBUS_OVP_STA

T

TSHUT_STAT

BATOVP_STAT

CFLY_STAT

RESERVED

CAP_COND_STA POORSRC_STA

RESERVED

T

R-X

R-0h

R-X

R-0h

Table 13. REG08 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

VBUS_OVP_STAT

TSHUT_STAT

BATOVP_STAT

CFLY_STAT

R

Yes

Input-overvoltage status

0h = Normal

1h = Device in overvoltage protection

6

5

4

R

Device temperature-shutdown status

0h = Normal

1h = Device in thermal-shutdown protection

Battery overvoltage status

0h = Normal

1h = BATOVP (VBAT > VBATOVP)

Flying capacitor status

0h = Normal

1h = Flying capacitor fault (VCFLY_UVP or OVP)

Reserved bit always reads 0

3

2

Reserved

R

Yes

CAP_COND_STAT

Capacitor precondition status

0h = Normal

1h = CFLY or CAUX precondition failed

1

0

POORSRC_STAT

RESERVED

R

Yes

Poor-source-detection status

0h = Normal

1h = POORSRC routine failed 7 consecutive times

Reserved bit always reads 0

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7.6.1.10 INT Flag Status Register (Address = 9h) [reset = 00h]

REG09 is shown in Figure 40 and described in Table 14.

Return to Summary Table.

All bits in REG09 are automatically cleared after a read.

Figure 40. REG09 Register

7

6

5

4

3

2

1

0

PG_FLAG

INDPM_FLAG

VINDPM_FLAG

TREG_FLAG

WD_FLAG

CHRG_TERM_FL

AG

RESERVED

CHRG_FLAG

R-0h

Table 14. REG09 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

PG_FLAG

R

Yes

No

Power-good INT flag

0h = Normal

1h = PG-signal toggle detected

INDPM_FLAG

VINDPM_FLAG

TREG_FLAG

R

INDPM-regulation INT flag

0h = Normal

1h = INDPM-signal rising edge detected

VINDPM-regulation INT flag

0h = Normal

1h = VINDPM-signal rising edge detected

Device temperature-regulation INT flag

0h = Normal

1h = TREG-signal rising edge detected

WD_FLAG

I²C-watchdog INT flag

0h = Normal

1h = WD_STAT-signal rising edge detected

CHRG_TERM_FLAG

Charger-termination INT flag

0h = Normal

1h = Charger-termination signal rising edge detected

1

0

RESERVED

R

Yes

No

Reserved bit always reads 0

CHRG_FLAG

Charger status INT flag

0h = Normal

1h = CHRG_STAT[2:0] bits changed (transition to any state)

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7.6.1.11 FAULT Flag Register (Address = Ah) [reset = 00h]

REG0A is shown in Figure 41 and described in Table 15.

Return to Summary Table.

All bits in REG0A are automatically cleared after a read.

Figure 41. REG0A Register

7

6

5

4

3

2

1

0

VBUS_OVP_FLA

G

TSHUT_FLAG

BATOVP_FLAG

CFLY_FLAG

TMR_FLAG

CAP_COND_FLA POORSRC_FLA

RESERVED

G

R-0h

Table 15. REG0A Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

VBUS_OVP_FLAG

TSHUT_FLAG

BATOVP_FLAG

CFLY_FLAG

R

Yes

No

Input-overvoltage INT flag

0h = Normal

1h = VBUS_OVP signal rising edge detected

6

5

4

3

2

1

0

R

Thermal-shutdown INT flag

0h = Normal

1h = TSHUT signal rising edge detected

Battery-overvoltage INT flag

0h = Normal

1h = BATOVP signal rising edge detected

Flying capacitor fault INT flag

0h = Normal

1h = Flying capacitor fault signal rising edge detected

TMR_FLAG

Charger safety-timer fault INT flag

0h = Normal

1h = Charger safety-timer expired rising edge

CAP_COND_FLAG

POORSRC_FLAG

RESERVED

Capacitor precondition fault INT flag

0h = Normal

1h = CAP_COND_STAT signal rising edge detected

Poor-source-fault INT flag

0h = Normal

1h = POORSRC_STAT signal rising edge detected

Reserved bit always reads 0

39

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

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7.6.1.12 INT Mask Register (Address = Bh) [reset = 00h]

REG0h is shown in Figure 42 and described in Table 16.

Return to Summary Table.

Figure 42. REG0h Register

7

6

5

4

3

2

1

0

PG_MASK

INDPM_MASK

VINDPM_MASK

TREG_MASK

WD_MASK

CHRG_TERM_M

ASK

RESERVED

CHRG_MASK

R/W-0h

Table 16. REG0h Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

PG_MASK

R/W

Yes

No

Power-good INT mask

0h = PG toggle produces INT pulse

1h = PG toggle does not produce INT pulse

INDPM_MASK

VINDPM_MASK

TREG_MASK

R/W

INDPM-regulation INT mask

0h = INDPM entry produces INT pulse

1h = INDPM entry does not produce INT pulse

VINDPM-regulation INT mask

0h = VINDPM entry produces INT pulse

1h = VINDPM entry does not produce INT pulse

Device temperature-regulation INT mask

0h = TREG entry produces INT pulse

1h = TREG entry does not produce INT pulse

WD_MASK

I²C watchdog-timer INT mask

0h = WD_STAT rising edge produces INT pulse

1h = WD_STAT rising edge does not produce INT pulse

CHRG_TERM_MASK

Charger-termination INT mask

0h = CHRG-termination detection produces INT pulse

1h = CHRG-termination detection does not produce INT pulse

1

0

RESERVED

R/W

Yes

No

Reserved bit always reads 0

CHRG_MASK

Charger-status INT mask

0h = CHRG_STAT[2:0] bit change produces INT pulse

1h = CHRG_STAT[2:0] bit change does not produce INT pulse

40

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

7.6.1.13 FAULT Mask Register (Address = Ch) [reset = 00h]

REG0C is shown in Figure 43 and described in Table 17.

Return to Summary Table.

Figure 43. REG0C Register

7

6

5

4

3

2

1

0

VBUS_OVP_MAS

K

TSHUT_MASK

BATOVP_MASK

CFLY_MASK

TMR_MASK

CAP_COND_MA POORSRC_MAS

RESERVED

SK

K

R/W-0h

Table 17. REG0C Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

VBUS_OVP_MASK

TSHUT_MASK

BATOVP_MASK

CFLY_MASK

R/W

Yes

No

Input overvoltage INT mask

0h = VBUS_OVP rising edge produces INT pulse

1h = VBUS_OVP rising edge does not produce INT pulse

6

5

4

3

2

R/W

Thermal-shutdown INT mask

0h = TSHUT rising edge produces INT pulse

1h = TSHUT rising edge does not produce INT pulse

Battery-overvoltage INT mask

0h = BATOVP rising edge produces INT pulse

1h = BATOVP rising edge does not produce INT pulse

Flying capacitor fault INT mask

0h = CFLY-fault rising edge produces INT pulse

1h = CFLY-fault rising edge does not produce INT pulse

TMR_MASK

Charger safety-timer fault INT mask

0h = Timer expired rising edge produces INT pulse

1h = Timer expired rising edge does not produce INT pulse

CAP_COND_MASK

Capacitor precondition-fault INT mask

0h = CAP_COND_FLAG rising edge produces INT pulse

1h = CAP_COND_FLAG rising edge does not produce INT

pulse

1

0

POORSRC_MASK

RESERVED

R/W

Yes

No

Poor-source-fault INT mask

0h = POORSRC_FLAG rising edge produces INT pulse

1h = POORSRC_FLAG rising edge does not produce INT pulse

Reserved bit always reads 0

41

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

7.6.1.14 Part Information Register (Address = Dh) [reset = 0Ah]

REG0D is shown in Figure 44 and described in Table 18.

Return to Summary Table.

Figure 44. REG0D Register

7

6

5

4

3

2

1

0

REG_RST

R/W-0h

PN[3:0]

R-1h

DEV_REV[2:0]

R-2h

Table 18. REG0D Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

REG_RST

R/W

No

Register preset

0h = Keep the current register settings

1h = Reset to default register values and reset the safety timer

NOTE: This bit resets to 0 after the register reset is complete.

6-3

2-0

PN[3:0]

R

No

Part number

1h = BQ25910

DEV_REV[2:0]

Device revision: 2h

42

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

A typical application consists of the device configured as an I²C controlled single cell, parallel battery charger for

Li-Ion and Li-polymer batteries used in a wide range of smartphones and other portable devices. It integrates an

input reverse-block FET (QBLK), four switching FETs for three-level operation (QHSA – QLSA), and a bootstrap

cap control to drive HS gates.

8.2 Typical Application

VBUS

SYSTEM

LOAD

SW

1 mF

20 mF

GND

SYS

PMID1

10 mF

BQ25600 /

BQ25898 /

PMIC

I2C Bus

BAT

10 mF

VBUS

CFLY +

1 mF

10 mF 10 mF

I_CHG1

PMID2

SW2

470nH /

330nH

10 mF

20 mF

CDRV+

CDRV-

CFLY -

220 nF

IND_

SNS

100ꢀ

VDD

+

BATP

BATN

VBAT

-

GND

SDA

SCL

INT

Host

REGN

CAUX

4.7 mF

BQ25910

4.7 mF

图 45. BQ25910 Application Test Configuration

43

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

Typical Application (接下页)

8.2.1 Design Requirements

For this design example, use the parameters shown in 表 19.

表 19. Design Parameters

PARAMETER

Input Voltage Range

Input Current Limit

VALUE

3.9 V to 14 V

2.4 A

Fast Charge Current

Battery Regulation Voltage

3.5 A

4.35 V

8.2.2 Detailed Design Procedure

8.2.2.1 External Passive Recommendation

The following part numbers are recommended for correct operation of BQ25910.

表 20. Recommended External Components

PASSIVE

UP TO 9VBUS ±10%

HMLQ25201B-R33

MPIM252010E-R33

UP TO 12VBUS ±10%

DFE252012F-R47

DFE252010F-R47

Inductor

CFLY (10 μF, X5R, 16 V)

CAUX (4.7 μF, X5R, 16 V)

2x GRM188R61C106MAALD

1x GRM155R61A475MEAAD

8.2.2.2 Inductor Selection

The BQ25910 is a three-level converter with a fixed switching frequency of 750 kHz, allowing the use of small

inductor and capacitor values. The inductor saturation current should be higher than the output current (I_CHG

)

plus half the ripple current (I_RIPPLE):

I_RIPPLE

I_SATí I_CHG

+

2

(1)

The inductor ripple current depends on input voltage (V_BUS), duty cycle (D = V_BAT/V_BUS), switching frequency (f_sw)

and inductance (L):

2

VBUS 0.5ì D - 0.5 - D - 0.5

(

)

(

I_RIPPLE

=

Lf_sw

(2)

The maximum inductor ripple current happens with D = 1/3 or D = 2/3. The recommended value of inductance is

330 nH for 9-V applications or 470 nH for 12-V applications (750 kHz).

44

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

图 46. Inductor Current Ripple as function of V_BUSwith Fixed V_BAT

表 21. Recommended Inductor values

VBUS

INDUCTOR VALUE

330 nH

3.9 V < VBUS < 10 V

3.9 V < VBUS < 14 V

470 nH

8.2.2.3 Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS current occurs when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst

case capacitor RMS current I_CINoccurs where the duty cycle is closest to 50% and can be estimated by the

following equation:

I_CIN= I_CHGD 1-D

(

)

(3)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed as close as possible to PMID and GND pins. Voltage rating of the capacitor must be higher than normal

input voltage level. 25-V rating or higher capacitor is preferred for 12-V input voltage. 10-μF capacitance is

suggested for up-to 6-A charging current.

8.2.2.4 Flying Capacitor

Flying capacitor selection must meet criteria related to current ripple and voltage ripple. Just as the input

capacitor, the flying capacitor should also have enough ripple current rating to absorb the RMS current through it:

I²

≈

’

2 0.5 - D - 0.5 I²

+

RIPPLE

I_CFLY

=

∆

÷

◊

(

)

CHG

∆

12

«

(4)

This function becomes maximum when D = 0.5, because at that point the capacitor is in series with the inductor

for a complete switching cycle, and their RMS currents are the same. The flying capacitor should be sized to

handle the full charge current in the scenario where D = 0.5.

45

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

图 47. Flying Capacitor RMS Current vs. V_BUSwith Fixed V_BATand I_CHG

Additionally, the flying capacitor voltage ripple should be kept under 10% of V_BUS/2 to ensure loop stability. This

quantity is given by the following equation:

I_CHG0.5 - D - 0.5

(

)

DV_CFLY

=

C_FLYf_SW

(5)

It is recommended to use at least two 16-V, 10-μF, low ESR ceramic capacitors in parallel to achieve both RMS

current rating and maintain voltage ripple <10% in the flying capacitor for up-to 6-A charge current application.

The following curve shows what the ripple voltage of CFLY might look like for such a configuration by taking into

account voltage derating of the capacitor and plugging the effective capacitance value into equation above at

different charge currents and V_BUSvoltages.

图 48. Flying Capacitor Ripple Voltage vs. V_BUSwith Fixed V_BAT

表 22. Recommended CFLY Values

CHARGE CURRENT

ICHG < 3.5 A

CFLY CONFIGURATION

1 x 0603 (10 μF, X5R, 16 V)

2 x 0603 (10 μF, X5R, 16 V)

ICHG > 3.5 A

46

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

8.2.2.5 Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The

output capacitor RMS current I_COUTis given:

I_RIPPLE

I_COUT

=

ö 0.29ìI_RIPPLE

2 3

(6)

The output capacitor voltage ripple can be calculated as follows:

I_RIPPLE

DV_SYS

=

16C_Of_SW

(7)

At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the

output filter LC. The preferred ceramic capacitor is 20 μF, 6.3 V or higher rating, X7R or X5R.

8.2.3 Application Curves

CBUS = 1 µF, CPMID = 10 µF, CBAT = 20 µF, CFLY = 20 µF, L = DFE252012F-R47 (470 nH) (unless otherwise noted)

VBUS = 5 V, VBAT = 3.8 V

图 49. Adapter Power Up with Charge Enabled

VBUS = 12 V, VBAT = 3.8 V

图 50. HV Adapter Power Up with Charge Enabled

VBUS = 5 V, VBAT = 3.5 V, ICHG = 3 A

图 51. Charge Disable

VBUS = 12 V, VBAT = 3.5 V, ICHG = 4 A

图 52. HV Adapter Charge Disable

47

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

CBUS = 1 µF, CPMID = 10 µF, CBAT = 20 µF, CFLY = 20 µF, L = DFE252012F-R47 (470 nH) (unless otherwise noted)

VBUS = 5 V -> 12 V -> 5 V, VBAT = 4 V, ICHG = 1 A

VBUS = 12 V, VBAT = 4.35 V, ICHG = 4 A, IBAT = 1 A -> 4 A ->

1 A

CH 1 = VBUS, CH2 = ILOAD, CH3 = CFLY differential, CH4 =

VBAT

CH 1 = VBUS, CH2 = SW, CH3 = CFLY differential, CH4 =

VBAT

图 54. Load Transient Response in CV Mode

图 53. Line Transient Response in CC Mode

VBUS = 5 V, VBAT = 3.8 V, ICHG = 2 A, (D > 50%)

VBAT = 4.1 V, VINDPM = 4.3 V

图 56. PWM Switching Waveform

图 55. VINDPM Response

VBUS = 8 V, VBAT = 3.8 V, ICHG = 2 A, (D approx. 50%)

VBUS = 12 V, VBAT = 3.8 V, ICHG = 2 A (D < 50%)

图 57. PWM Switching Waveform

图 58. PWM Switching Waveform

48

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

CBUS = 1 µF, CPMID = 10 µF, CBAT = 20 µF, CFLY = 20 µF, L = DFE252012F-R47 (470 nH) (unless otherwise noted)

VBUS = 12 V, VBAT = 3.8 V

图 60. Adapter Removal

VBUS = 5 V, VBAT = 3.8 V

图 59. Adapter Removal

49

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

9 Power Supply Recommendations

In order to charge single-cell Li-Ion battery, the device requires a power supply between 3.9 V and 14 V with at

least 500-mA current rating connected to VBUS. Additionally, a single-cell Li-Ion battery with voltage > V_{BAT_LOWV}

should be connected between at the output of the switched inductor, between BATP and BATN terminals.

50

BQ25910

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ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

10 Layout

10.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loops is important to prevent electrical and magnetic field

radiation and high-frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB

according to this specific order is essential.

1. Utilize at least four-layer board for optimal layout, and assign one layer as solid ground plane near the IC to

minimize high-frequency current path

2. Place flying capacitor as close to CLFY+ and CLFY– bumps as possible. Minimize the copper area of this

trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging

current. Do not use multiple layers in parallel for this connection.

3. Place input capacitor as close as possible to PMID bumps and PGND bumps and use solid GND plane

underneath the IC. Use plenty of vias close to PMID capacitor GND terminal and IC PGND bumps to ensure

low parasitic connection to GND plane.

4. Place inductor input terminal as close to SW bumps as possible. Minimize the copper area of this trace to

lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current.

5. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the device

ground with a short copper trace connection or GND plane.

6. Decoupling capacitors should be placed next to the device and make trace connection as short as possible.

7. Ensure that there are sufficient thermal vias directly under bumps of the power FETs, connecting to copper

on other layers.

8. The via size and number should be enough for a given current path.

9. Route BATP and BATN away from switching nodes such as SW and CFLY+, CFLY–.

Refer to the EVM design and 图 61 for the recommended component placement with trace and via locations.

51

BQ25910

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

www.ti.com.cn

10.2 Layout Example

GND

0603

SW

1008

0603

PMID

C+

C-

VBUS

PMID

SDA

C+

SW

C-

GND

BAT

GND

VBUS

CDRV+

CDRV-

SCL

C+

C-

0603

SW

CDRV+

CDRV-

C+

SW

0603

INT

SW

GND

IND_

SNS

CAUX

REGN

BATN

BATP

REGN

CAUX

GND

0402

GND

SCL

SDA

/INT

BATN

BATP

图 61. BQ25910 PCB Layout Example

52

BQ25910

www.ti.com.cn

ZHCSHR0B –SEPTEMBER 2017–REVISED SEPTEMBER 2019

11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

11.1.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航栏。

53

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

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PACKAGE MATERIALS INFORMATION

www.ti.com

18-Nov-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ25910YFFR

BQ25910YFFT

DSBGA

YFF

36

3000

250

180.0

8.4

2.54

0.76

4.0

8.0

Q1

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Nov-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ25910YFFR

BQ25910YFFT

DSBGA

YFF

36

3000

250

182.0

20.0

250

Pack Materials-Page 2

PACKAGE OUTLINE

YFF0036

DSBGA - 0.625 mm max height

S

C

A

L

E

4

.

5

0

DIE SIZE BALL GRID ARRAY

B

E

A

BUMP A1

CORNER

D

C

0.625 MAX

SEATING PLANE

0.05 C

BALL TYP

0.30

0.12

2 TYP

SYMM

F

E

D: Max = 2.472 mm, Min =2.412 mm

E: Max = 2.444 mm, Min =2.384 mm

D

C

SYMM

2

TYP

B

A

0.3

0.2

36X

0.015

C A

B

0.4 TYP

1

2

4

5

6

3

0.4 TYP

4222008/A 03/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YFF0036

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

36X ( 0.23)

(0.4) TYP

1

2

4

5

6

A

B

C

SYMM

D

E

F

SYMM

LAND PATTERN EXAMPLE

SCALE:25X

0.05 MAX

0.05 MIN

(

0.23)

(

0.23)

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4222008/A 03/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YFF0036

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

36X ( 0.25)

(R0.05) TYP

1

3

4

5

2

6

A

B

(0.4)

TYP

METAL

TYP

C

D

E

F

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4222008/A 03/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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型号：	BQ25910YFFR
厂家：	TEXAS INSTRUMENTS
描述：	用于并联充电应用的 I2C 单节 6A 三级降压电池充电器 \| YFF \| 36 \| -40 to 85 电池
文件：	总62页 (文件大小：2309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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