BQ2944L9DRBT [TI]
Voltage Protection for 2-Series, 3-Series, or 4-Series Cell Li-Ion Batteries (Second-Level Protection); 电压保护2系列， 3系列，或4节串联锂离子电池（第二级保护）
| 型号： | BQ2944L9DRBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Voltage Protection for 2-Series, 3-Series, or 4-Series Cell Li-Ion Batteries (Second-Level Protection) |
| 文件： | 总17页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq29440, bq2944L0
bq29449, bq2944L9
www.ti.com
SLUSA15B –MARCH 2010–REVISED JUNE 2010
Voltage Protection for 2-Series, 3-Series, or 4-Series Cell Li-Ion Batteries
(Second-Level Protection)
Check for Samples: bq29440, bq2944L0, bq29449, bq2944L9
1
FEATURES
APPLICATIONS
•
Second-Level Protection in Li-Ion Battery
Packs
•
2-Series, 3-Series, or 4-Series Cell Secondary
Protection
–
–
–
Notebook Computers
Power Tools
Portable Equipment and Instrumentation
•
•
External Capacitor-Controlled Delay Timer
Low Power Consumption ICC < 2 µA Typical
[VCELL(ALL) < VPROTECT
]
•
•
•
High-Accuracy Overvoltage Protection:
±25 mV With TA = 0°C to 60°C
Fixed Overvoltage Protection Thresholds:
4.30 V, 4.35 V
Small 8L QFN Package
DESCRIPTION
The bq2944x is a secondary overvoltage protection IC for 2-series, 3-series, or 4-series cell lithium-ion battery
packs that incorporates a high-accuracy precision overvoltage detection circuit.
FUNCTION
The voltage of each cell in a battery pack is compared to an internal reference voltage. If any cells reach an
overvoltage condition, the bq2944x device starts a timer that provides a delay proportional to the capacitance on
the CD pin. Upon expiration of the internal timer, the OUT pin changes from a low state to a high state. An
optional latch configuration is available that holds the OUT pin in a high state indefinitely after an overvoltage
condition has satisfied the specified delay timer period. The latch is released when the CD pin is shorted to GND.
T
T
DRB Package
(Top View)
1
2
3
4
8
7
6
5
VC1
VC2
VC3
GND
OUT
VDD
CD
VC4
P0012-02
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq29440, bq2944L0
bq29449, bq2944L9
SLUSA15B –MARCH 2010–REVISED JUNE 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TA
PART NUMBER OUT PIN PACKAGE
PACKAGE
PACKAGE
OVP
ORDERING INFORMATION(2)
TAPE AND REEL TAPE AND REEL
(LARGE)(3) (SMALL)(4)
LATCH
OPTION
DESIGNATOR MARKING
-40°C
to
+85°C
BQ29440
BQ2944L0
BQ29449
BQ2944L9
No
Yes
No
QFN-8
DRB
440
44L0
449
4.35 V
4.35 V
4.30 V
4.30 V
BQ29440DRBR
BQ2944L0DRBR
BQ29449DRBR
BQ2944L9DRBR
BQ29440DRBT
BQ2944L0DRBT
BQ29449DRBT
BQ2944L9DRBT
Yes
44L9
(1) Example: bq2944L0DRBR is a device with the OUT latch option with a VOV threshold of 4.35 V.
Contact Texas Instruments for other VOV threshold options.
(2) For the most current package and ordering information, see the Package Addendum at the end of this document, or the TI website at
www.ti.com.
(3) Large tape and reel quantity is 3,000 units.
(4) Small tape and reel quantity is 250 units.
THERMAL INFORMATION
bq2944x
THERMAL METRIC(1)
DRB
8 PINS
50.5
25.1
19.3
0.7
UNITS
qJA
Junction-to-ambient thermal resistance(2)
(3)
qJC(top)
qJB
Junction-to-case(top) thermal resistance
(4)
Junction-to-board thermal resistance
°C/W
(5)
yJT
Junction-to-top characterization parameter
(6)
yJB
Junction-to-board characterization parameter
18.9
5.2
(7)
qJC(bottom)
Junction-to-case(bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
PIN FUNCTIONS
PIN NAME
CD
PIN NO.
DESCRIPTION
Connection to external capacitor for programmable delay time
Ground pin
6
4
8
1
2
3
5
7
GND
OUT
VC1
Output
Sense voltage input for top cell
VC2
Sense voltage input for second-to-top cell
Sense voltage input for third-to-top cell
Sense voltage input for fourth-to-top cell (bottom cell)
Power supply
VC3
VC4
VDD
2
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bq29440, bq2944L0
bq29449, bq2944L9
www.ti.com
SLUSA15B –MARCH 2010–REVISED JUNE 2010
FUNCTIONAL BLOCK DIAGRAM
RVD
CVD
VDD
RIN
VC1
140 nA
CIN
RIN
VC2
CIN
RIN
VC3
OUT
CIN
RIN
1.2 V (typ)
VC4
CIN
GND
CD
CCD
B0394-01
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE / UNITS
–0.3 to 28 V
–0.3 to 28 V
–0.3 to 8 V
Supply voltage range, VMAX
Input voltage range, VIN
VDD–GND
VC1–GND, VC2–GND, VC3–GND
VC1–VC2, VC2–VC3, VC3–VC4, VC4–GND
CD–GND
–0.3 to 8 V
Output voltage range, VOUT
OUT–GND
–0.3 to 28 V
–65°C to 150°C
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
4
NOM
MAX UNIT
Supply voltage, VDD
25
5
V
Input voltage range
VC1–VC2, VC2–VC3, VC3–VC4, VC4–GND
CCD (See Figure 7.)
0
V
td(CD) delay-time capacitance
Voltage monitor filter resistance
Voltage monitor filter capacitance
Supply voltage filter resistance
Supply voltage filter capacitance
Operating ambient temperature range, TA
0.1
1
µF
kΩ
µF
kΩ
µF
°C
RIN (See Figure 7.)
0.1
0.01
0.1
CIN (See Figure 7.)
0.1
RVD (See Figure 7.)
1
CVD (See Figure 7.)
0.1
–40
110
Copyright © 2010, Texas Instruments Incorporated
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bq29440, bq2944L0
bq29449, bq2944L9
SLUSA15B –MARCH 2010–REVISED JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
Typical values stated where TA = 25°C and VDD = 17 V, MIN/MAX values stated where TA = –40°C to 110°C and VDD = 4 V to
25 V (unless otherwise noted).
PARAMETER
TEST CONDITION
MIN NOM MAX UNIT
Overvoltage bq29449
detection
4.30
VPROTECT
V
bq29440
voltage
4.35
Overvoltage detection
hysteresis
VHYS
VOA
VOA_DRIFT
For non-latch devices only
200
–10
300 400
10
mV
mV
Overvoltage detection
accuracy
TA = 25°C
TA = 0°C to 60°C
–0.4
–0.6
0.4
0.6
Overvoltage threshold
temperature drift
(1)
mV/°C
s/µF
TA = –40°C to 110°C
TA = 0°C to 60°C
Note: Does not include external capacitor variation
6.5
6.0
8.5
8.5
13
16
Overvoltage delay time
scale factor
XDELAY
TA = –40°C to 110°C
Note: Does not include external capacitor variation
Overvoltage delay time
XDELAY_CTM scale factor in Customer See CUSTOMER TEST MODE.
Test Mode
0.08
s/µF
Overvoltage detection
charging current
ICD(CHG)
ICD(DSG)
(See Figure 1.)
(See Figure 2.)
140
60
nA
µA
Overvoltage detection
discharging current
Overvoltage detection
external capacitor
comparator threshold
VCD
1.2
2
V
µA
V
(VC1–VC2) = (VC2–VC3) = (VC3–VC4) = (VC4–GND) = 3.5 V
(See Figure 3.)
ICC
Supply current
3.5
9.5
(VC1–VC2), (VC2–VC3), (VC3–VC4) and
(VC4–GND) = VPROTECTMAX, VDD = 20V,
IOH = 0 to -10 µA
6.5
2.0
8.0
(VC1–VC2), (VC2–VC3), (VC3–VC4) and
(VC4–GND) = VPROTECTMAX, VDD = 4V,
IOL = -10 µA, TA = 0°C to 60°C
VOUT
OUT pin drive voltage
3.0
3.5
V
(VC1–VC2), (VC2–VC3), (VC3–VC4) and
(VC4–GND) = 4 V, IOL = 0 µA
0.1
4
V
OUT = 0 V, (VC1–VC2), (VC2–VC3), (VC3–VC4) or
(VC4–GND) > VPROTECT, VDD = 18 V
IOUT(SHORT) OUT short circuit current
mA
(1)
tr(OUT)
OUT output rise time
CL = 1 nF, VDD = 4 V to 25 V, VOH(OUT) = 0 V to 5 V
5
2
µs
(1)
ZO(OUT)
OUT output impedance
kΩ
Measured at VC1, (VC1–VC2), (VC2–VC3), (VC3–VC4) and
(VC4–GND) = 3.5 V,
TA = 0°C to 60°C (See Figure 3.)
–0.3
–0.3
1.5
0.3
µA
µA
IIN
Input current at VCx pins
Measured at VC2, VC3 or VC4, (VC1–VC2), (VC2–VC3),
(VC3–VC4) and (VC4–GND) = 3.5 V,
TA = 0°C to 60°C (See Figure 3.)
(1) Specified by design. Not 100% tested in production.
4
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Product Folder Link(s): bq29440 bq2944L0 bq29449 bq2944L9
bq29440, bq2944L0
bq29449, bq2944L9
www.ti.com
SLUSA15B –MARCH 2010–REVISED JUNE 2010
TYPICAL CHARACTERISTICS
ICD CHARGE CURRENT
vs
ICD DISCHARGE CURRENT
vs
TEMPERATURE
TEMPERATURE
-80
-90
80
75
70
65
60
55
50
45
-100
-110
-120
-130
-140
-150
-160
-170
-180
-40
-20
0
20
40
60
80
100
40
-40
Temperature (°C)
-20
0
20
40
60
80
100
G001
Temperature (°C)
G002
Figure 1. ICD Charge Current
Figure 2. ICD Discharge Current
ICC
IIN
IIN
IIN
1
VC1
OUT
VDD
CD
8
7
6
5
2
3
4
VC2
VC3
GND
VC4
IIN
Figure 3. ICC, IIN Measurement
APPLICATIONS INFORMATION
PROTECTION (OUT) TIMING AND DELAY TIME CAPACITOR SIZING
The bq2944x uses an external capacitor to set delay timing during an overvoltage condition. When any of the
cells exceed the overvoltage threshold, the bq2944x activates an internal current source of nominally 140 nA,
which charges the external capacitor. When the external capacitor charges up to a voltage of nominally 1.2 V,
the OUT pin transitions from a low state to a high state, by means of an internal pull-up network, to a regulated
voltage of no more than 9.5 V when IOH = 0 mA.
Copyright © 2010, Texas Instruments Incorporated
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bq29440, bq2944L0
bq29449, bq2944L9
SLUSA15B –MARCH 2010–REVISED JUNE 2010
www.ti.com
VPROTECT
Cell Voltage
VC1–VC2
VC2–VC3
VC3–VC4
VC4–GND
VPROTECT – VHYS
td
OUT
L
H
T0461-01
Figure 4. Timing for Overvoltage Sensing
Sizing the external capacitor is based on the desired delay time as follows:
td
=
cCD
xDELAY
Where td is the desired delay time and xDELAY is the overvoltage delay time scale factor, expressed in seconds
per microFarad. xDELAY is nominally 8.5 s/µF. For example, if a nominal delay of 3 seconds is desired, the
customer should use a CCD capacitor that is 3 s / 8.5 s/µF = 0.35 µF.
The delay time is calculated as follows:
1.2V ´C
[
]
CD
td =
ICD
If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the
internal current source is disabled and an internal discharge block is employed to discharge the external
capacitor down to 0 V. In this instance, the OUT pin remains in a low state.
For latched versions of the bq2944x, if an overvoltage condition has caused the OUT pin to transition to a high
state, the external capacitor remains charged even after the overvoltage condition has been removed. In this
instance, the OUT pin remains in a high state.
For non-latched versions, the OUT pin is allowed to transition back from a high to low state when the overvoltage
condition is no longer present, and the external capacitor is discharged down to 0 V.
6
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bq29440, bq2944L0
bq29449, bq2944L9
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SLUSA15B –MARCH 2010–REVISED JUNE 2010
BATTERY CONNECTION FOR 2-SERIES, 3-SERIES, AND 4-SERIES CELL CONFIGURATIONS
Figure 5, Figure 6, and Figure 7 show the 2-series, 3-series, and 4-series cell configurations.
RVD
1
2
3
4
VC1
VC2
VC3
GND
OUT
VDD
CD
8
7
6
5
CVD
RIN
RIN
CIN
CIN
CCD
VC4
Figure 5. 2-Series Cell Configuration
RVD
1
2
3
4
VC1
VC2
VC3
GND
OUT
VDD
CD
8
7
6
5
RIN
RIN
RIN
CIN
CIN
CIN
CVD
CCD
VC4
Figure 6. 3-Series Cell Configuration
RVD
1
2
3
4
VC1
VC2
VC3
GND
OUT
VDD
CD
8
7
6
5
RIN
RIN
RIN
RIN
CIN
CIN
CIN
CIN
CVD
CCD
VC4
Figure 7. 4-Series Cell Configuration
Copyright © 2010, Texas Instruments Incorporated
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SLUSA15B –MARCH 2010–REVISED JUNE 2010
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CELL CONNECTION SEQUENCE
The recommended cell connection sequence begins from the bottom of the stack, as follows:
1. GND
2. VC4
3. VC3
4. VC2
5. VC1
While not advised, connecting the cells in a sequence other than that described above does not result in errant
activity on the OUT pin. For example:
1. GND
2. VC4, VC3, VC2, or VC1
3. Remaining VCx pin
4. Remaining VCx pin
5. Remaining VCx pin
It is also recommended that the overvoltage delay timing capacitor, CCD, be propagated before connecting the
cells.
CUSTOMER TEST MODE
Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker
customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such,
individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate
overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use.
To enter CTM, VDD should be set to approximately 9.5 V higher than VC1. When CTM is entered, the device
switches from the normal overvoltage delay time scale factor, xDELAY, to a significantly reduced factor, xDELAY_CTM
,
thereby reducing the delay time during an overvoltage condition. The CTM overvoltage delay time is similar to
the equation presented in PROTECTION (OUT) TIMING AND DELAY TIME CAPACITOR SIZING with the
substitution of xDELAY_CTM in place of xDELAY
:
td_CTM = CCD ´ xDELAY _ CTM
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into Customer Test Mode. Also, avoid exceeding Absolute Maximum Voltages for the
individual cell voltages (VC1–VC2), (VC2–VC3), (VC3–VC4), and (VC4–GND).
Stressing the pins beyond the rated limits may cause permanent damage to the
device.
To exit CTM, the device should be powered off before being powered back on.
For latched versions of the bq2944x, the external CCD capacitor must be externally discharged if any overvoltage
functionality is exercised during protection testing. This can be accomplished by shorting the CD pin to GND. If
the CCD capacitor is not explicitly discharged, a residual charge may cause the overvoltage delay time to be
inaccurate.
Space
8
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SLUSA15B –MARCH 2010–REVISED JUNE 2010
REVISION HISTORY
Changes from Original (March 2010) to Revision A
Page
•
Changed VOUT first Test Condition - From: VDD = 25V To: VDD = 20V. MAX value From: 9.0 To 9.5 .................................. 4
Changes from Revision A (March 2010) to Revision B
Page
•
•
•
•
•
•
•
•
Changed the low power consumption value from 3 µA to 2 µA Typical ............................................................................... 1
Changed the Ordering Information ....................................................................................................................................... 2
Changed the Functional Block Diagram ............................................................................................................................... 3
Changed the Electrical Characteristics ................................................................................................................................. 4
Changed the Protection (Out) Timing Section to Protection (Out) Timing and Delay Time Capacitor Sizing ...................... 5
Added the 2-series and 3-series cell configurations ............................................................................................................. 7
Added the Cell Connection Sequence Section ..................................................................................................................... 8
Changed the Test Mode Section .......................................................................................................................................... 8
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
BQ29440DRBR
BQ29440DRBT
BQ29449DRBR
BQ29449DRBT
BQ2944L0DRBR
BQ2944L0DRBT
BQ2944L9DRBR
BQ2944L9DRBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
8
8
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Request Free Samples
Purchase Samples
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Request Free Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Request Free Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2010
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ29440DRBR
BQ29440DRBT
BQ29449DRBR
BQ29449DRBT
BQ2944L0DRBR
BQ2944L0DRBT
BQ2944L9DRBR
BQ2944L9DRBT
SON
SON
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
8
8
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ29440DRBR
BQ29440DRBT
BQ29449DRBR
BQ29449DRBT
BQ2944L0DRBR
BQ2944L0DRBT
BQ2944L9DRBR
BQ2944L9DRBT
SON
SON
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRB
DRB
DRB
DRB
8
8
8
8
8
8
8
8
3000
250
346.0
190.5
346.0
190.5
346.0
190.5
346.0
190.5
346.0
212.7
346.0
212.7
346.0
212.7
346.0
212.7
29.0
31.8
29.0
31.8
29.0
31.8
29.0
31.8
3000
250
3000
250
3000
250
Pack Materials-Page 2
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