BQ4016 [TI]
1024Kx8 Nonvolatile SRAM; 1024Kx8非易失SRAM
| 型号： | BQ4016 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1024Kx8 Nonvolatile SRAM |
| 文件： | 总11页 (文件大小：860K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4016/bq4016Y
1024Kx8 Nonvolatile SRAM
At t his tim e t he in tegr a l en er gy
Features
➤ Data retention in the absence of
General Description
source is switched on to sustain the
m em or y u n t il a ft er VCC r et ur ns
valid.
The CMOS bq4016 is a nonvolatile
8,388,608-bit static RAM organized
as 1,048,576 words by 8 bits. The in-
tegral control circuitry and lithium
energy source provide reliable non-
volatility coupled with the unlimited
write cycles of standard SRAM.
power
➤ Automatic write-protection
during power-up/power-down
cycles
Th e bq4016 u ses extr em ely low
s t a n dby cu r r en t CMOS SRAMs,
coupled with a small lithium coin
cell to provide nonvolatility without
long write-cycle times and the write-
cycle lim it a tion s a ssocia ted with
EEPROM.
➤ Conventional SRAM operation;
unlimited write cycles
Th e con tr ol cir cu it r y con s ta n t ly
monitors the single 5V supply for an
out-of-tolerance condition. When VCC
falls out of tolerance, the SRAM is
un condition ally wr ite-pr otected to
p r even t a n in a dver t en t w r it e
operation.
➤ 10-year minimum data retention
in absence of power
The bq4016 has the same interface
as industry-standard SRAMs and re-
quires no external circuitry.
➤ Battery internally isolated until
power is applied
Pin Connections
Pin Names
Block Diagram
A0–A19
Address inputs
DQ0–DQ7 Data input/output
CE
Chip enable input
Output enable input
Write enable input
+5 volt supply input
Ground
OE
WE
VCC
VSS
NC
No connect
Selection Guide
Maximum
Access
Negative
Supply
Maximum
Access
Negative
Supply
Part
Part
Number
Time (ns)
Tolerance
Number
Time (ns)
Tolerance
bq4016MC -70
bq4016YMC -70
70
-5%
70
-10%
Sept. 1996 B
1
bq4016/bq4016Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4016 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4016 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC
. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
P ower -down /power -u p con t r ol cir cu it r y con sta n tly
monitors the VCC supply for a power-fail-detect threshold
VPFD. The bq4016 monitors for VPFD = 4.62V typical for
use in systems with 5% supply tolerance. The bq4016Y
monitors for VPFD = 4.37V typical for use in systems with
10% supply tolerance.
The internal coin cells used by the bq4016 have an
extremely long shelf life. The bq4016 provides data
retention for more than 10 years in the absence of sys-
tem power.
When VCC falls below the VPFD threshold, the SRAM
a utom a tica lly wr ite-pr otects the data . All outputs
become high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com-
pletion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
As shipped from Benchmarq, the integral lithium cells
are electrically isolated from the memory. (Self-discharge
in t his con dition is a ppr oxim ately 0.5% per yea r .)
Following the first application of VCC, this isolation is
broken, and the lithium backup provides data retention
on subsequent power-downs.
Truth Table
Mode
Not selected
CE
H
L
WE
X
OE
X
I/O Operation
High Z
High Z
DOUT
Power
Standby
Active
Output disable
Read
H
H
L
H
L
Active
Write
L
L
X
DIN
Active
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
-0.3 to 7.0
V
VT ≤ VCC + 0.3
TOPR
TSTG
TBIAS
Operating temperature
Storage temperature
Temperature under bias
0 to +70
-40 to +70
-10 to +70
+260
°C
°C
°C
°C
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolu te Ma xim u m Ratin gs are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.
Sept. 1996 B
2
bq4016/bq4016Y
Recommended DC Operating Conditions (T = 0 to 70°C)
A
Symbol
Parameter
Minimum
Typical
Maximum
Unit
V
Notes
bq4016Y
bq4016
4.5
4.75
0
5.0
5.0
0
5.5
VCC
Supply voltage
5.5
0
V
VSS
VIL
VIH
Supply voltage
V
Input low voltage
Input high voltage
-0.3
2.2
-
0.8
V
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (T = 0 to 70°C, V
≤ V
≤ V
CCmax
)
A
CCmin
CC
Symbol
ILI
Parameter
Minimum
Typical
Maximum
± 2
Unit
Conditions/Notes
VIN = VSS to VCC
Input leakage current
-
-
µA
µA
CE = VIH or OE = VIH or
WE = VIL
ILO
Output leakage current
-
-
± 2
VOH
VOL
ISB1
Output high voltage
Output low voltage
Standby supply current
2.4
-
-
-
V
V
IOH = -1.0 mA
IOL = 2.1 mA
CE = VIH
-
-
0.4
12
5
mA
0V ≤ VIN ≤ 0.2V,
CE ≥ VCC - 0.2V,
or VIN ≥ VCC - 0.2
ISB2
Standby supply current
Operating supply current
-
-
2.5
75
5
mA
mA
Min. cycle, duty = 100%,
CE = VIL ,II/O = 0mA,
ICC
115
A19 < VIL or A19 > VIH
,
4.55
4.30
-
4.62
4.37
3
4.75
4.50
-
V
V
V
bq4016
VPFD
Power-fail-detect voltage
Supply switch-over voltage
bq4016Y
VSO
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Sept. 1996 B
3
bq4016/bq4016Y
Capacitance (T = 25°C, F = 1MHz, V
CC
= 5.0V)
Minimum
A
Symbol
CI/O
Parameter
Input/output capacitance
Input capacitance
Typical
Maximum
Unit
pF
Conditions
-
-
-
-
20
20
Output voltage = 0V
Input voltage = 0V
CIN
pF
Note:
These parameters are sampled and not 100% tested.
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
5 ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
1.5 V (unless otherwise specified)
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (T = 0 to 70°C, V
CCmin
≤ V
≤ V
)
CCmax
A
CC
-70
Symbol
tRC
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Min.
Max.
-
Read cycle time
70
-
tAA
Address access time
70
70
35
-
Output load A
tACE
tOE
Chip enable access time
Output enable to output valid
Chip enable to output in low Z
-
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
5
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
5
-
0
25
25
-
0
10
Sept. 1996 B
4
bq4016/bq4016Y
1,2
Read Cycle No. 1 (Address Access)
1,3,4
Read Cycle No. 2 (CE Access)
1,5
Read Cycle No. 3 (OE Access)
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL
5. Device is continuously selected: CE = VIL
.
.
.
Sept. 1996 B
5
bq4016/bq4016Y
Write Cycle (T = 0 to 70°C, V
≤ V
≤ V
)
A
CCmin
CC
CCmax
-70
Min.
Max.
Symbol
tWC
Parameter
Write cycle time
Units
ns
Conditions/Notes
70
65
65
-
-
-
tCW
Chip enable to end of write
Address valid to end of write
ns
(1)
(1)
tAW
ns
Measured from address valid to
beginning of write. (2)
tAS
Address setup time
Write pulse width
0
55
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Measured from beginning of write to
end of write. (1)
tWP
Write recovery time
(write cycle 1)
Measured from WE going high to
end of write cycle. (3)
tWR1
tWR2
tDW
tDH1
tDH2
Write recovery time
(write cycle 2)
Measured from CE going high to end
of write cycle. (3)
15
30
0
Measured to first low-to-high
transition of either CE or WE.
Data valid to end of write
Data hold time
(write cycle 1)
Measured from WE going high to
end of write cycle. (4)
Measured from CE going high to end
of write cycle. (4)
Data hold time
(write cycle 2)
10
tWZ
tOW
Write enabled to output in high Z
Output active from end of write
0
5
25
-
ns
ns
I/O pins are in output state. (5)
I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Sept. 1996 B
6
bq4016/bq4016Y
1,2,3
Write Cycle No. 1 (WE-Controlled)
1,2,3,4,5
Write Cycle No. 2 (CE-Controlled)
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
Sept. 1996 B
7
bq4016/bq4016Y
Power-Down/Power-Up Cycle (T = 0 to 70°C)
A
Symbol
tPF
Parameter
Minimum
Typical
Maximum
Unit
µs
Conditions
VCC slew, 4.75 to 4.25 V
VCC slew, 4.25 to VSO
300
10
0
-
-
-
-
-
-
tFS
µs
tPU
VCC slew, VSO to VPFD (max.)
µs
Time during which
SRAM is write-protected
after VCC passes VFPD on
power-up.
tCER
Chip enable recovery time
40
80
120
ms
Data-retention time in
absence of VCC
tDR
10
-
-
years
TA = 25°C. (2)
Delay after VCC slews
down past VPFD before
SRAM is write-protected.
tWPT
Write-protect time
40
100
150
µs
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e
m a y a ffect d a ta in tegr ity.
Power-Down/Power-Up Timing
Sept. 1996 B
8
bq4016/bq4016Y
Data Sheet Revision History
Change No.
Page No.
Description
Changed from “Preliminary” to “Final” data sheet
1
All
Notes:
Change 1 = Sept 1996 B changes from J une 1995.
.
MC: 36-Pin C-Type Module
(C-Type Module)
36-Pin MC
Dimension
Minimum
0.365
0.015
0.017
0.008
2.070
0.710
0.590
0.090
0.120
0.175
Maximum
A
A1
B
C
D
E
0.375
-
0.023
0.013
2.100
0.740
0.630
0.110
0.150
0.210
e
G
L
S
All dimensions are in inches.
Sept. 1996 B
9
bq4016/bq4016Y
Ordering Information
bq4016 MC -
Tem p er atu r e:
blank = Commercial (0 to +70°C)
Sp eed Op tion s:
70 = 70 ns
P a ck a ge Op tion :
MC = C-type module
Su p p ly Toler a n ce:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4016 1024K x 8 NVSRAM
Sept. 1996 B
10
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