BQ4850YMA-85 [TI]
RTC Module With 512Kx8 NVSRAM; RTC模块512Kx8 NVSRAM
| 型号： | BQ4850YMA-85 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | RTC Module With 512Kx8 NVSRAM |
| 文件： | 总16页 (文件大小：620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4850Y
RTC Module With 512Kx8 NVSRAM
The clock and alarm registers are
General Description
Features
du a l-por t r ea d/wr it e SRAM loca-
➤ I n t e gr a t e d S R AM , r e a l-t im e
clock, crystal, power-fail control
circuit, and battery
The bq4850Y RTC Module is a non-
volatile 4,194,304-bit SRAM organ-
ized as 524,288 words by 8 bits with
a n in t egr a l a ccessible r ea l-t im e
clock.
tions that are updated once per sec-
ond by a clock control circuit from
the internal clock counters. The
dual-port registers allow clock up-
dates to occur without interrupting
n or m a l a ccess t o t h e r est of t h e
SRAM array.
➤ Real-Time Clock counts seconds
through years in BCD format
The device combines an internal lith-
ium battery, quartz crystal, clock and
power-fail chip, and a full CMOS
SRAM in a plastic 32-pin DIP mod-
ule. The RTC Module directly re-
places industry-standard SRAMs and
also fits into many EPROM and EE-
PROM sockets without any require-
ment for special write timing or limi-
tations on the number of write cycles.
➤ RAM-like clock access
The bq4850Y also contains a power-
fail-detect circuit. The circuit dese-
lects the device whenever VCC falls
below tolerance, providing a high de-
gree of data security. The battery is
electrically isolated when shipped
from the factory to provide maxi-
mum battery capacity. The battery
remains disconnected until the first
➤ Pin-compatible with industry-
standard 512K x 8 SRAMs
➤ Unlimited write cycles
➤ 10-year minimum data retention
and clock operation in the absence
of power
➤ Automatic power-fail chip dese-
Registers for the rea l-time clock,
alarm and other special functions
are located in registers 7FFF8h–
7FFFFh of the memory array.
application of VCC
.
lect and write-protection
➤ Soft wa r e clock ca libr a t ion for
gr e a t e r t h a n ±1 m in u t e p e r
month accuracy
Pin Connections
Pin Names
A0–A18
CE
Address input
Chip enable
A
32
1
V
18
CC
A
A
31
30
2
3
A
A
16
14
15
17
4
WE
A
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
Write enable
Output enable
12
5
A
A
A
A
A
A
A
13
7
6
5
4
3
2
OE
6
A
8
A
9
A
11
OE
7
DQ0–DQ7 Data in/data out
8
9
VCC
VSS
+5 volts
Ground
10
11
12
13
14
15
16
A
10
CE
DQ
DQ
DQ
DQ
DQ
A
1
0
0
A
DQ
DQ
DQ
7
6
5
4
3
1
2
V
SS
32-Pin DIP Module
PN485001.eps
Aug. 1996
1
bq4850Y
in clu din g m em or y a n d clock in t er fa ce, a n d da t a -
retention modes.
Functional Description
Figure 1 is a block diagram of the bq4850Y. The follow-
ing sections describe the bq4850Y functional operation,
Time-
Base
Oscillator
Internal
Quartz
Crystal
.
.
.
-
.
-
-
.
.
8
64
64
4
3
:
16 1 MUX
Control/Status
Registers
CE
OE
DQ -DQ
P
Bus
I/F
Clock Alarm and
Calendar Bytes
0
7
Clock/Calendar
Update
AD -AD
0
18
User Buffer
(8 Bytes)
WE
Storage
Registers
(524,288 Bytes)
Power-
Fail
V
CC
Write-
Protect
Control
Internal
Battery
BD-961
Figure 1. Block Diagram
Truth Table
VCC
CE
VIH
VIL
VIL
VIL
X
OE
X
WE
X
Mode
Deselect
Write
DQ
Power
Standby
Active
< VCC (max.)
High Z
DIN
X
VIL
VIH
VIH
X
> VCC (min.)
VIL
VIH
X
Read
DOUT
Active
Read
High Z
High Z
High Z
Active
< VPFD (min.) > VSO
Deselect
Deselect
CMOS standby
X
X
X
Battery-backup mode
≤ VSO
Aug. 1996
2
bq4850Y
Figure 2 illustrates the address map for the bq4850Y.
Table 1 is a map of the bq4850Y registers.
Address Map
The bq4850Y provides 8 bytes of clock and control status
registers and 524,288 bytes of storage RAM.
Clock and
Control Status
Registers
7FFFF
0
1
2
3
4
5
6
7
Year
Month
Date
7FFFF
7FFFE
7FFFD
7FFFC
7FFFB
7FFFA
8 Bytes
7FFF8
7FFF7
Days
Hours
Minutes
Seconds 7FFF9
Control 7FFF8
32,760
Bytes
Storage
RAM
0000
MM-961
Figure 2. Address Map
Table 1. bq4850Y Clock and Control Register Map
Address
7FFFF
7FFFE
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
7FFF8
D7
D6
D5
10 Years
X
D4
D3
D2
Year
D1
D0
Range (h)
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–31
Register
Year
X
X
X
X
10 Month
Month
Date
Month
Date
10 Date
X
FTE
X
X
X
X
Day
Hours
Days
X
10 Hours
Hours
Minutes
Seconds
Control
X
10 Minutes
10 Seconds
S
Minutes
Seconds
OSC
W
R
Calibration
Notes:
X = Unused bits; can be written and read.
Clock/Calendar data in 24-hour BCD format.
OSC = 1 stops the clock oscillator.
Aug. 1996
3
bq4850Y
The internal coin cell maintains data in the bq4850Y af-
ter the initial application of VCC for an accumulated pe-
riod of at least 10 years when VCC is less than VSO. As
system power returns and Vcc rises above VSO, the bat-
tery is disconnected, and the power supply is switched to
Memory Interface
Read Mode
The bq4850Y is in read mode whenever OE (output en-
able) is low and CE (chip enable) is low. The device ar-
chitecture allows ripple-through access of data from
eight of 4,194,304 locations in the static storage array.
Thus, the unique address specified by the 19 address in-
puts defines which one of the 524,288 bytes of data is to
be accessed. Valid data is available at the data I/O pins
within tAA (address access time) after the last address
input signal is stable, providing that the CE and OE
(output enable) access times are also satisfied. If the CE
and OE access times are not met, valid data is available
after the latter of chip enable access time (tACE) or out-
put enable access time (tOE).
external VCC
. Write-protection continues for tCER after
VCC reaches VPFD to allow for processor stabilization.
After tCER, normal RAM operation can resume.
Clock Interface
Reading the Clock
The interface to the clock and control registers of the
bq4850Y is the same as that for the general-purpose
storage memory. Once every second, the user-accessible
clock/calendar locations are updated simultaneously
from the internal real time counters. To prevent reading
data in transition, updates to the bq4850Y clock regis-
ters should be halted. Updating is halted by setting the
read bit D6 of the control register to 1. As long as the
read bit is 1, updates to user-accessible clock locations
are inhibited. Once the frozen clock information is re-
trieved by reading the appropriate clock memory loca-
tions, the read bit should be reset to 0 in order to allow
updates to occur from the internal counters. Because the
internal counters are not halted by setting the read bit,
reading the clock locations has no effect on clock accu-
racy. Once the read bit is reset to 0, within one second
the internal registers update the user-accessible regis-
ters with the correct time. A halt command issued dur-
ing a clock update allows the update to occur before
freezing the data.
CE and OE control the state of the eight three-state
data I/O signals. If the outputs are activated before tAA
,
the data lines are driven to an indeterminate state until
tAA. If the address inputs are changed while CE and OE
remain low, output data remains valid for tOH (output
data hold time), but goes indeterminate until the next
address access.
Write Mode
The bq4850Y is in write mode whenever WE and CE are
active. The start of a write is referenced from the
latter-occurring falling edge of WE or CE. A write is ter-
minated by the earlier rising edge of WE or CE. The ad-
dresses must be held valid throughout the cycle. CE or
WE must return high for a minimum of tWR2 from CE or
tWR1 from WE prior to the initiation of another read or
write cycle.
Setting the Clock
Bit D7 of the control register is the write bit. Like the
read bit, the write bit when set to a 1 halts updates to
the clock/calendar memory locations. Once frozen, the
locations can be written with the desired information in
24-hour BCD format. Resetting the write bit to 0 causes
the written values to be transferred to the internal clock
counters and allows updates to the user-accessible regis-
ters to resume within one second. Use the write bit, D7,
only when updating the time registers (7FFFF–7FFF9).
Data-in must be valid tDW prior to the end of write and
remain valid for tDH1 or tDH2 afterward. OE should be
kept high during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a low on
CE and OE, a low on WE disables the outputs tWZ after
WE falls.
Data-Retention Mode
With valid VCC applied, the bq4850Y operates as a
conventional static RAM. Should the supply voltage
decay, t h e RAM a u t om a t ica lly power-fa il deselect s,
Stopping and Starting the Clock Oscillator
The OSC bit in the seconds register turns the clock on or
off. If the bq4850Y is to spend a significant period of
time in storage, the clock oscillator can be turned off to
preserve battery capacity. OSC set to 1 stops the clock
oscillator. When OSC is reset to 0, the clock oscillator is
turned on and clock updates to user-accessible memory
locations occur within one second.
write-protecting itself tWPT after VCC falls below VPFD
.
All outputs become high impedance, and all inputs are
treated as “don’t care.”
If power-fail detection occurs during a valid access, the
memory cycle continues to completion. If the memory
cycle fa ils t o t er m in a t e wit h in t im e t WP T, wr it e-
protection takes place. When VCC drops below VSO, the
control circuit switches power to the internal energy
source, which preserves data.
The OSC bit is set to 1 when shipped from the Bench-
marq factory.
Aug. 1996
4
bq4850Y
Calibrating the Clock
0
-20
The bq4850Y real-time clock is driven by a quartz con-
trolled oscillator with a nominal frequency of 32,768 Hz.
The quartz crystal is contained within the bq4850Y
package along with the battery. The clock accuracy of
the bq4850Y module is tested to be within 20ppm or
about 1 minute per month at 25°C. The oscillation rates
of crystals change with temperature as Figure 3 shows.
To compensate for the frequency shift, the bq4850Y of-
fers onboard software clock calibration. The user can
adjust the calibration based on the typical operating
temperature of individual applications.
-40
-60
-80
-100
-120
The software calibration bits are located in the control
register. Bits D0–D4 control the magnitude of correc-
tion, and bit D5 the direction (positive or negative) of
correction. Assuming that the oscillator is running at
exactly 32,786 Hz, each calibration step of D0–D4 ad-
justs the clock rate by +4.068 ppm (+10.7 seconds per
month) or -2.034 ppm (-5.35 seconds per month) depend-
ing on the value of the sign bit D5. When the sign bit is
1, positive adjustment occurs; a 0 activates negative ad-
justment. The total range of clock calibration is +5.5 or
-2.75 minutes per month.
-30 -20 -10
0
10 20 30 40 50 60 70
Temperature ( C)
GR485001
Figure 3. Frequency Error
ister is set to a 1, and the oscillator is running at exactly
32,768 Hz, the LSB of the seconds register toggles at
512 Hz. Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024 Hz
indicates a (1E6 0.01024)/512 or +20 ppm oscillator fre-
quency error, requiring ten steps of negative calibration
(10 -2.034 or -20.34) or 001010 to be loaded into the cali-
bration byte for correction. To read the test frequency,
the bq4850Y must be selected and held in an extended
read of the seconds register, location 7FFF9, without
having the read bit set. The frequency appears on DQ0.
The FTE bit must be set using the write bit control. The
FTE bit must be reset to 0 for normal clock operation to
resume.
Two methods can be used to ascertain how much cali-
bration a given bq4850Y may require in a system. The
first involves simply setting the clock, letting it run for a
month, and then comparing the time to an accurate
known reference like WWV radio broadcasts. Based on
the variation to the standard, the end user can adjust
the clock to match the system’s environment even after
the product is packaged in a non-serviceable enclosure.
The only requirement is a utility that allows the end
user to access the calibration bits in the control register.
The second approach uses a bq4850Y test mode. When
the frequency test mode enable bit FTE in the days reg-
Aug. 1996
5
bq4850Y
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
-0.3 to 7.0
V
V
T ≤ VCC + 0.3
TOPR
TSTG
TBIAS
Operating temperature
0 to +70
-40 to +70
-10 to +70
+260
°C
°C
°C
°C
Storage temperature (VCC off; oscillator off)
Temperature under bias
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional
operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Ex-
posure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (T = T
)
OPR
A
Symbol
VCC
Parameter
Supply voltage
Minimum
Typical
Maximum
Unit
V
Notes
4.5
0
5.0
5.5
0
VSS
Supply voltage
0
-
V
VIL
Input low voltage
Input high voltage
-0.3
2.2
0.8
V
VIH
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
Aug. 1996
6
bq4850Y
DC Electrical Characteristics (T = T
≤ V
≤ V
CC CCmax)
A
OPR, VCCmin
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
VIN = VSS to VCC
ILI
Input leakage current
-
-
± 1
µA
CE = VIH or OE = VIH or
WE = VIL
ILO
Output leakage current
-
-
± 1
µA
VOH
VOL
ISB1
Output high voltage
Output low voltage
Standby supply current
2.4
-
-
-
0.4
5
V
V
IOH = -1.0 mA
IOL = 2.1 mA
CE = VIH
-
-
3
mA
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2V
ISB2
Standby supply current
-
0.1
1
mA
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA
ICC
Operating supply current
-
-
90
mA
VPFD
VSO
Power-fail-detect voltage
Supply switch-over voltage
4.30
-
4.37
3
4.50
-
V
V
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
A
CC
Symbol
CI/O
Parameter
Minimum
Typical
Maximum
Unit
pF
Conditions
Output voltage = 0V
Input voltage = 0V
Input/output capacitance
Input capacitance
-
-
-
-
10
10
CIN
pF
Note:
These parameters are sampled and not 100% tested.
Aug. 1996
7
bq4850Y
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
Input pulse levels
Input rise and fall times
5 ns
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 4 and 5
Figure 4. Output Load A
Figure 5. Output Load B
Read Cycle (T = T
≤ V
≤ V
CC CCMAX)
A
OPR, VCCmin
Parameter
–85
Min.
Max.
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
tRC
Read cycle time
85
-
-
85
85
45
-
tAA
Address access time
Output load A
tACE
tOE
Chip enable access time
-
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
Output enable to output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
5
0
-
0
35
25
-
0
10
Aug. 1996
8
bq4850Y
1,2
Read Cycle No. 1 (Address Access)
1,3,4
Read Cycle No. 2 (CE Access)
1,5
Read Cycle No. 3 (OE Access)
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL
5. Device is continuously selected: CE = VIL
.
.
.
Aug. 1996
9
bq4850Y
Write Cycle (T =T
V
V
≤ V
A
OPR , CCMIN ≤ CC
CCMAX)
–85
Min.
85
Max.
Symbol
tWC
Parameter
Write cycle time
Units
ns
Conditions/Notes
-
-
-
tCW
Chip enable to end of write
Address valid to end of write
75
ns
(1)
(1)
tAW
75
ns
Measured from address valid to begin-
ning of write. (2)
tAS
Address setup time
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Measured from beginning of write to
end of write. (1)
tWP
Write pulse width
65
5
Measured from WE going high to end
of write cycle. (3)
tWR1
tWR2
tDW
tDH1
tDH2
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Measured from CE going high to end of
write cycle. (3)
15
35
0
Measured to first low-to-high transi-
tion of either CE or WE.
Measured from WE going high to end
of write cycle. (4)
Measured from CE going high to end of
write cycle. (4)
10
tWZ
tOW
Write enabled to output in high Z
Output active from end of write
0
0
30
-
ns
ns
I/O pins are in output state. (5)
I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Aug. 1996
10
bq4850Y
1,2,3
Write Cycle No. 1 (WE-Controlled)
1,2,3,4,5
Write Cycle No. 2 (CE-Controlled)
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
Aug. 1996
11
bq4850Y
Power-Down/Power-Up Cycle (T = T
A
OPR)
Typical
Symbol
tPF
Parameter
Minimum
300
Maximum
Unit
µs
Conditions
VCC slew, 4.50 to 4.20 V
VCC slew, 4.20 to VSO
-
-
-
-
tFS
10
µs
VCC slew, VSO to VPFD
(max.)
tPU
0
-
-
µs
Time during which SRAM is
write-protected after VCC
passes VFPD on power-up.
tCER
Chip enable recovery time
40
100
200
ms
Data-retention time in
absence of VCC
tDR
10
40
-
-
years TA = 25°C. (2)
Delay after VCC slews down
tWPT
Write-protect time
100
160
µs
past VPFD before SRAM is
write-protected.
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e
m a y a ffect d a ta in tegr ity.
Power-Down/Power-Up Timing
1
Aug. 1996
12
bq4850Y
MA: 32-Pin A-Type Module
(
)
32-Pin MA A-Type Module
Inches
Millimeters
Dimension
Min.
0.365
0.015
0.017
0.008
1.670
0.710
0.590
0.090
0.120
0.075
Max.
0.375
-
Min.
Max.
9.53
-
A
A1
B
C
D
E
9.27
0.38
0.023
0.013
1.700
0.740
0.630
0.110
0.150
0.110
0.43
0.58
0.33
43.18
18.80
16.00
2.79
3.81
2.79
0.20
42.42
18.03
14.99
2.29
e
G
L
3.05
S
1.91
Aug. 1996
13
bq4850Y
Ordering Information
bq4850Y MA -
Sp eed Op tion s:
85 = 85 ns
Pa ck a ge Op tion :
MA = A-type module
Device:
bq4850Y 512K x 8 Real-Time Clock Module
Aug. 1996
14
Notes
15
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