BQ78Z100DRZR [TI]
适用于 1 至 2 节电池的 Impedance Track™ 电池电量监测计 | DRZ | 12 | -40 to 85;
| 型号： | BQ78Z100DRZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 1 至 2 节电池的 Impedance Track™ 电池电量监测计 | DRZ | 12 | -40 to 85 电池 |
| 文件： | 总37页 (文件大小：1321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq78z100
ZHCSE72 –SEPTEMBER 2015
bq78z100 Impedance Track™ 用于 1 节和 2 节串联锂离子/锂聚合物电池
组的电量监测计
查询样片: bq78z100
1 特性
3 说明
1
•
•
•
高精度库伦计数器，输入偏移误差 < 1µV（典型
值）
bq78z100 器件提供了一套基于电池组的全集成解决方
案，其具有闪存可编程的定制精简指令集 CPU
(RISC)、安全保护以及认证功能，适用于 1 节和 2 节
锂离子和锂聚合物电池组。
高侧场效应晶体管 (FET) 驱动器，允许在故障期间
进行串行总线通信
具有双路独立模数转换器 (ADC) 的模拟前端
bq78z100 电量监测计通过 I2C 兼容接口或单线制
HDQ 接口进行通信，并将超低功耗的高速德州仪器
(TI) bqBMP 处理器、高精度模拟测量功能、集成闪
存、大量的外设和通信端口、N 沟道 FET 驱动器以及
SHA-1 认证转换响应器完美融合于一套完整的高性能
电池管理解决方案。
–
支持电流和电压的同步采样
•
•
总线通信接口选项
–
–
I2C
HDQ
SHA-1 哈希消息验证码 (HMAC) 响应器，用于提高
电池组安全性
–
存储在安全存储器中的分裂密钥 (Split Key) (2
× 64)
bq78z100 器件提供有大量的电池和系统安全功能，其
中包括针对电池的放电过流、充电短路和放电短路功
能，针对 N 沟道 FET 的 FET 保护，内部 AFE 看门狗
以及电池平衡功能。 该器件可通过固件添加更多保护
特性，例如过压、欠压、过热等。
•
可编程的保护功能：
–
–
–
–
–
–
放电过流
充电短路
放电短路
过电压
器件信息(1)
部件号
bq78z100
封装
VSON (12)
封装尺寸（标称值）
欠电压
4.00mm x 2.50mm
过热
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
支持 1mΩ 至 3mΩ 电流感测电阻
紧凑型 12 引脚小外形尺寸无引线 (SON) 封装
(DRZ)
4 简化电路原理图
Pack
+
10 M
10 M
Fuse
2 应用
13
100
1 µF
5
1
2
3
VC1
VSS
SRN
12
11
PWPD
2 s
0.1
µF
•
•
•
便携式和可佩戴式健康器件
1 s
VC2
PBI
0.1 µF
5.1 k
5.1 k
便携式无线电
工业数据收集
SRP
TS1
10
9
2.2 µF
Battery
cells
4
5
CHG
10k
10
100
100
100
PACK
8
SCL
Comm
Bus
MM3Z5V6C
100
6
7
SDA/HDQ
DSG
MM3Z5V6C
100
100
Pack–
1 to 3 mΩ
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSC23
bq78z100
ZHCSE72 –SEPTEMBER 2015
www.ti.com.cn
目录
7.22 Data Flash............................................................... 9
7.23 Current Protection Thresholds .............................. 10
7.24 Current Protection Timing ..................................... 10
7.25 N-CH FET Drive (CHG, DSG)............................... 11
7.26 I2C and HDQ Interface I/O.................................... 11
7.27 I2C Interface Timing .............................................. 12
7.28 HDQ Interface Timing ........................................... 12
7.29 Typical Characteristics ......................................... 14
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 22
Applications and Implementation ...................... 24
9.1 Application Information............................................ 24
9.2 Typical Applications ............................................... 24
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Supply Current .......................................................... 5
7.6 Power Supply Control ............................................... 5
7.7 Low-Voltage General Purpose I/O, TS1 ................... 6
7.8 Power-On Reset (POR) ............................................ 6
7.9 Internal 1.8-V LDO................................................... 6
7.10 Current Wake Comparator...................................... 6
7.11 Coulomb Counter.................................................... 7
7.12 ADC Digital Filter .................................................... 7
7.13 ADC Multiplexer ...................................................... 7
7.14 Cell Balancing Support ........................................... 8
7.15 Internal Temperature Sensor .................................. 8
7.16 NTC Thermistor Measurement Support.................. 8
7.17 High-Frequency Oscillator....................................... 8
7.18 Low-Frequency Oscillator ....................................... 8
7.19 Voltage Reference 1 ............................................... 9
7.20 Voltage Reference 2 ............................................... 9
7.21 Instruction Flash...................................................... 9
8
9
10 Power Supply Requirements ............................. 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 30
12.1 文档支持................................................................ 30
12.2 社区资源................................................................ 30
12.3 商标....................................................................... 30
12.4 静电放电警告......................................................... 30
12.5 Glossary................................................................ 30
13 机械、封装和可订购信息....................................... 31
5 修订历史记录
日期
修订版本
注释
2015 年 9 月
*
最初发布版本
2
Copyright © 2015, Texas Instruments Incorporated
bq78z100
www.ti.com.cn
ZHCSE72 –SEPTEMBER 2015
6 Pin Configuration and Functions
1
12
11
10
9
VSS
VC1
VC2
2
SRN
3
SRP
PBI
4
CHG
PACK
DSG
TS1
5
6
8
SCL
13
PWPD
7
SDA/HDQ
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VSS
DRZ
1
P
Device ground
Analog input pin connected to the internal coulomb counter peripheral for integrating a small
voltage between SRP and SRN where SRP is the top of the sense resistor.
SRN
SRP
2
3
IA
Analog input pin connected to the internal coulomb counter peripheral for integrating a small
voltage between SRP and SRN where SRP is the top of the sense resistor.
IA
TS1
4
5
IA
I/O
I/O
O
Input for ADC to the oversampled ADC channel
Serial Clock for the I2C interface; requires an external pullup when used
Serial Data for the I2C and HDQ interfaces; requires an external pullup
N-Channel FET drive output pin
SCL
SDA/HDQ
DSG
6
7
PACK
CHG
PBI
8
IA, P
O
Pack sense input pin
9
N-Channel FET drive output pin
10
P
Power supply backup input pin
Sense voltage input pin for most positive cell, balance current input for most positive cell. Primary
power supply input and battery stack measurement input (BAT)
VC2
11
12
IA, P
VC1
IA
—
Sense voltage input pin for least positive cell, balance current input for least positive cell
Exposed Pad, electrically connected to VSS (external trace)
PWPD
Copyright © 2015, Texas Instruments Incorporated
3
bq78z100
ZHCSE72 –SEPTEMBER 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
30
UNIT
Supply voltage range, VCC
VC2, PBI
PACK
V
V
V
V
30
TS1
VREG + 0.3
0.3
SRP, SRN
Input voltage range, VIN
VC1 + 8.5 or
VSS + 30
VC2
VC1 – 0.3
V
V
VSS + 8.5 or
VSS + 30
VC1
VSS – 0.3
–0.3
Output voltage range, VO
CHG, DSG
32
±50
110
±300
150
V
Maximum VSS current, ISS
mA
°C
Functional Temperature, TFUNC
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature range, TSTG
–40
–65
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 26 V (unless otherwise noted)
MIN
2.2
NOM
MAX
26
UNIT
VCC
Supply voltage
VC2, PBI
V
V
V
VSHUTDOWN– Shutdown voltage
VSHUTDOWN+ Start-up voltage
VPACK < VSHUTDOWN–
VPACK > VSHUTDOWN– + VHYS
1.8
2.0
2.2
2.05
2.25
2.45
Shutdown voltage
hysteresis
VHYS
VSHUTDOWN+ – VSHUTDOWN–
250
mV
SDA/HDQ, SCL
TS1
5.5
VREG
0.2
SRP, SRN
VC2
–0.2
VVC1
VVSS
VIN
Input voltage range
V
VVC1 + 5
VVSS + 5
26
VC1
PACK
VO
Output voltage range CHG, DSG
External PBI capacitor
26
V
CPBI
2.2
µF
Operating
temperature
TOPR
–40
85
°C
4
Copyright © 2015, Texas Instruments Incorporated
bq78z100
www.ti.com.cn
ZHCSE72 –SEPTEMBER 2015
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
bq78z100
THERMAL METRIC(1)
DRZ
12 PINS
186.4
90.4
UNIT
RθJA, High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
110.7
96.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
90
RθJC(bottom)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Supply Current
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
CHG = ON, DSG = ON, No Flash Write and CPU = ON
400
500
INORMAL
NORMAL mode
µA
CHG = ON, DSG = ON, No Flash Write and CPU =
Halted
250
300
CHG = OFF, DSG = ON, No Communication on Bus
CHG = OFF, DSG = OFF, No Communication on Bus
90
38
160
µA
ISLEEP
SLEEP mode
120
ISHUTDOWN
SHUTDOWN mode
0.5
2
µA
7.6 Power Supply Control
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
VVC2 < VSWITCHOVER–
VVC2 > VSWITCHOVER– + VHYS
VSWITCHOVER+ – VSWITCHOVER–
MIN
TYP
MAX UNIT
VC2 to PACK
VSWITCHOVER–
VSWITCHOVER+
VHYS
2.0
2.1
2.2
3.2
V
V
switchover voltage
PACK to VC2
3.0
3.1
switchover voltage
Switchover voltage
hysteresis
1000
mV
VC2 pin, VC2 = 0 V, PACK = 25 V
PACK pin, VC2 = 25 V, PACK = 0 V
1
1
Input Leakage
current
ILKG
µA
VC2 and PACK pins, VC2 = 0 V, PACK = 0 V, PBI =
25 V
1
Internal pulldown
resistance
RPACK(PD)
PACK
30
40
50
kΩ
Copyright © 2015, Texas Instruments Incorporated
5
bq78z100
ZHCSE72 –SEPTEMBER 2015
www.ti.com.cn
7.7 Low-Voltage General Purpose I/O, TS1
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VIH
High-level input
0.65 x VREG
V
VIL
Low-level input
0.35 x VREG
V
V
VOH
VOL
CIN
ILKG
Output voltage high
Output voltage low
Input capacitance
Input leakage current
IOH = – 1.0 mA
IOL = 1.0 mA
0.75 x VREG
0.2 x VREG
V
5
pF
µA
1
7.8 Power-On Reset (POR)
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Negative-going voltage
input
VREGIT–
VREG
1.51
1.55
1.59
V
Power-on reset
hysteresis
VHYS
tRST
VREGIT+ – VREGIT–
70
100
300
130
400
mV
µs
Power-on reset time
200
7.9 Internal 1.8-V LDO
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VREG
Regulator voltage
1.6
1.8
2.0
V
Regulator output over
temperature
ΔVO(TEMP)
ΔVO(LINE)
ΔVREG/ΔTA, IREG = 10 mA
±0.25%
Line regulation
ΔVREG/ΔVBAT, VBAT = 10 mA
–0 .6%
–1.5%
0.5%
1.5%
ΔVO(LOAD) Load regulation
ΔVREG/ΔIREG, IREG = 0 mA to 10 mA
Regulator output current
limit
IREG
VREG = 0.9 x VREG(NOM), VIN > 2.2 V
VREG = 0 x VREG(NOM)
ΔVBAT/ΔVREG, IREG = 10 mA, VIN > 2.5 V, f = 10 Hz
VREG
20
25
mA
mA
dB
V
Regulator short-circuit
current limit
ISC
40
40
50
Power supply rejection
ratio
PSRRREG
VSLEW
Slew rate enhancement
voltage threshold
1.58
1.65
7.10 Current Wake Comparator
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VWAKE = VSRP – VSRN WAKE_CONTROL[WK1,
WK0] = 0,0
±0.3
±0.625
±0.9
±1.8
±3.6
±7.2
mV
mV
mV
mV
VWAKE = VSRP – VSRN WAKE_CONTROL[WK1,
WK0] = 0,1
±0.6
±1.2
±2.4
±1.25
±2.5
±5.0
Wake voltage
threshold
VWAKE
VWAKE = VSRP – VSRN WAKE_CONTROL[WK1,
WK0] = 1,0
VWAKE = VSRP – VSRN WAKE_CONTROL[WK1,
WK0] = 1,1
6
Copyright © 2015, Texas Instruments Incorporated
bq78z100
www.ti.com.cn
ZHCSE72 –SEPTEMBER 2015
Current Wake Comparator (continued)
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
Temperature drift of
VWAKE accuracy
VWAKE(DRIFT)
tWAKE
0.5%
°C
Time from application
of current to wake
0.25
250
0.5
ms
µs
Wake up comparator [WKCHGEN] = 0 and [WKDSGEN] = 0 to
startup time [WKCHGEN] = 1 and [WKDSGEN] = 1
tWAKE(SU)
640
7.11 Coulomb Counter
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
Input voltage range
TEST CONDITION
MIN
–100
TYP
MAX
100
UNIT
mV
Full scale range
Differential nonlinearity
Integral nonlinearity
Offset error
–VREF1/10
+VREF1/10
±1
mV
16-bit, No missing codes
LSB
LSB
LSB
16-bit, Best fit over input voltage range
16-bit, Post-calibration
±5.2
±1.3
0.04
±131
4.3
±22.3
±2.6
Offset error drift
Gain error
15-bit + sign, Post-calibration
0.07 LSB/°C
±492 LSB
15-bit + sign, Over input voltage range
15-bit + sign, Over input voltage range
Gain error drift
9.8 LSB/°C
Effective input resistance
2.5
MΩ
7.12 ADC Digital Filter
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
ADCTL[SPEED1, SPEED0] = 0, 0
MIN
TYP
31.25
15.63
7.81
1.95
16
MAX UNIT
ADCTL[SPEED1, SPEED0] = 0, 1
tCONV
ms
Bits
Bits
ADCTL[SPEED1, SPEED0] = 1, 0
ADCTL[SPEED1, SPEED0] = 1, 1
Resolution
No missing codes, ADCTL[SPEED1, SPEED0] = 0, 0
With sign, ADCTL[SPEED1, SPEED0] = 0, 0
With sign, ADCTL[SPEED1, SPEED0] = 0, 1
With sign, ADCTL[SPEED1, SPEED0] = 1, 0
With sign, ADCTL[SPEED1, SPEED0] = 1, 1
14
13
11
9
15
14
Effective resolution
12
10
7.13 ADC Multiplexer
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
VC1–VSS, VC2–VC1
MIN
0.1980
0.0485
0.490
–0.2
TYP
0.2000
0.050
MAX
0.2020
UNIT
K
Scaling factor
VC2–VSS, PACK–VSS
0.051
—
VREF1/2
0.500
0.510
VC2–VSS, PACK–VSS
20
VIN
Input voltage range
Input leakage current
TS1
TS1
–0.2
0.8 × VREF1
0.8 × VREG
V
–0.2
VC1, VC2 cell balancing off, cell detach detection
off, ADC multiplexer off
ILKG
1
µA
Copyright © 2015, Texas Instruments Incorporated
7
bq78z100
ZHCSE72 –SEPTEMBER 2015
www.ti.com.cn
7.14 Cell Balancing Support
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Internal cell balance
resistance
RCB
RDS(ON) for internal FET switch at 2 V < VDS < 4 V
200
Ω
7.15 Internal Temperature Sensor
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
–1.9
TYP
–2.0
MAX UNIT
VTEMPP
–2.1
mV/°C
0.179
Internal temperature
sensor voltage drift
VTEMP
(1)
VTEMPP – VTEMPN
0.177
0.178
(1) Assured by design
7.16 NTC Thermistor Measurement Support
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Internal pull-up
resistance
RNTC(PU)
TS1
TS1
14.4
18
21.6
kΩ
Resistance drift over
temperature
RNTC(DRIFT)
–360
–280
–200 PPM/°C
7.17 High-Frequency Oscillator
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
16.78
MAX
UNIT
fHFO
Operating frequency
MHz
TA = –20°C to 70°C, includes frequency drift
TA = –40°C to 85°C, includes frequency drift
–2.5%
–3.5%
±0.25%
±0.25%
2.5%
3.5%
fHFO(ERR)
Frequency error
Start-up time
TA = –20°C to 85°C, Oscillator frequency within +/–3%
of nominal, CLKCTL[HFRAMP] = 1
4
ms
µs
tHFO(SU)
Oscillator frequency within +/–3% of nominal,
CLKCTL[HFRAMP] = 0
100
7.18 Low-Frequency Oscillator
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
fLFO
Operating frequency
262.144
kHz
Operating frequency in
low power mode
fLFO(LP)
247
kHz
TA = –20°C to 70°C, includes frequency drift
TA = –40°C to 85°C, includes frequency drift
–1.5%
–2.5%
±0.25%
±0.25%
1.5%
2.5%
fLFO(ERR)
Frequency error
Frequency error in low
power mode
fLFO(LPERR)
–5%
30
5%
Failure detection
frequency
fLFO(FAIL)
80
100
kHz
8
Copyright © 2015, Texas Instruments Incorporated
bq78z100
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ZHCSE72 –SEPTEMBER 2015
7.19 Voltage Reference 1
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Internal reference
voltage
VREF1
TA = 25°C, after trim
1.215
1.220
1.225
V
TA = 0°C to 60°C, after trim
TA = –40°C to 85°C, after trim
±50
±80
Internal reference
voltage drift
VREF1(DRIFT)
PPM/°C
7.20 Voltage Reference 2
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Internal reference
voltage
VREF2
TA = 25°C, after trim
1.215
1.220
1.225
V
TA = 0°C to 60°C, after trim
TA = –40°C to 85°C, after trim
±50
±80
Internal reference
voltage drift
VREF2(DRIFT)
PPM/°C
7.21 Instruction Flash
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
Data retention
TEST CONDITION
MIN
10
TYP
MAX
UNIT
Years
Cycles
Flash programming write cycles
1000
Word programming
time
tPROGWORD
TA = –40°C to 85°C
40
µs
tMASSERASE Mass-erase time
tPAGEERASE Page-erase time
IFLASHREAD Flash-read current
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
40
40
2
ms
ms
mA
IFLASHWRIT
E
Flash-write current
TA = –40°C to 85°C
TA = –40°C to 85°C
5
mA
mA
IFLASHERAS
E
Flash-erase current
15
7.22 Data Flash
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
Data retention
TEST CONDITION
MIN
10
TYP
MAX
UNIT
Years
Cycles
Flash programming write cycles
20000
Word programming
time
tPROGWORD
TA = –40°C to 85°C
40
µs
tMASSERASE Mass-erase time
tPAGEERASE Page-erase time
IFLASHREAD Flash-read current
IFLASHWRITE Flash-write current
IFLASHERASE Flash-erase current
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
40
40
1
ms
ms
mA
mA
mA
5
15
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE72 –SEPTEMBER 2015
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7.23 Current Protection Thresholds
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VOCD = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 1
–16.6
–100
OCD detection threshold
voltage range
VOCD
mV
VOCD = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 0
–8.3
–50
VOCD = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 1
–5.56
–2.78
OCD detection threshold
voltage program step
ΔVOCD
ΔVSCC
ΔVSCC
VSCD1
ΔVSCD1
VSCD2
ΔVSCD2
mV
mV
mV
mV
mV
mV
mV
VOCD = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCC = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 1
44.4
22.2
200
100
SCC detection threshold
voltage range
VSCC = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCC = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 1
22.2
11.1
SCC detection threshold
voltage program step
VSCC = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCD1 = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 1
–44.4
–22.2
–200
–100
SCD1 detection
threshold voltage range
VSCD1 = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCD1 = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 1
–22.2
–11.1
SCD1 detection
threshold voltage
program step
VSCD1 = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCD2 = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 1
–44.4
–22.2
–200
–100
SCD2 detection
threshold voltage range
VSCD2 = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCD2 = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 1
–22.2
–11.1
SCD2 detection
threshold voltage
program step
VSCD2 = VSRP – VSRN,
PROTECTION_CONTROL[RSNS] = 0
7.24 Current Protection Timing
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
OCD detection delay
time
tOCD
1
31
ms
OCD detection delay
time program step
ΔtOCD
tSCC
2
ms
µs
µs
SCC detection delay
time
0
915
SCC detection delay
time program step
ΔtSCC
61
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
0
0
915
SCD1 detection delay
time
tSCD1
ΔtSCD1
tSCD2
µs
µs
µs
1850
61
SCD1 detection delay
time program step
121
0
0
458
915
SCD2 detection delay
time
10
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE72 –SEPTEMBER 2015
Current Protection Timing (continued)
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
MIN
TYP
30.5
61
MAX
UNIT
SCD2 detection delay
time program step
ΔtSCD2
µs
VSRP – VSRN = VT – 3 mV for OCD, SCD1, and
SC2, VSRP – VSRN = VT + 3 mV for SCC
tDETECT
tACC
Current fault detect time
160
µs
Current fault delay time
accuracy
Max delay setting
–10%
10%
7.25 N-CH FET Drive (CHG, DSG)
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
RatioDSG = (VDSG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V,
10 MΩ between PACK and DSG
2.133
2.333
2.467
Output voltage ratio
—
RatioCHG = (VCHG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V,
10 MΩ between BAT and CHG
2.133
8.75
8.75
–0.4
–0.4
2.333
9.5
2.467
10.25
10.25
0.4
VDSG(ON) = VDSG – VVC2, VVC2 ≥ 4.07 V, 10 MΩ
between PACK and DSG, VVC2 = 18 V
Output voltage, CHG
and DSG on
V(FETON)
V
V
VCHG(ON) = VCHG – VVC2, VVC2 ≥ 4.07 V, 10 MΩ
between VC2 and CHG, VVC2 = 18 V
9.5
VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and
DSG
Output voltage, CHG
and DSG off
V(FETOFF)
VCHG(OFF) = VCHG – VBAT, 10 MΩ between VC2 and
CHG
0.4
VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL
4.7 nF between DSG and PACK, 5.1 kΩ between DSG
and CL, 10 MΩ between PACK and DSG
=
200
200
40
500
500
300
200
tR
Rise time
Fall time
µs
µs
VCHG from 0% to 35% VCHG(ON)(TYP), VVC2 ≥ 2.2 V, CL
4.7 nF between CHG and VC2, 5.1 kΩ between CHG
and CL, 10 MΩ between VC2 and CHG
=
VDSG from VDSG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7
nF between DSG and PACK, 5.1 kΩ between DSG and
CL, 10 MΩ between PACK and DSG
tF
VCHG from VCHG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7
nF between CHG and VC2, 5.1 kΩ between CHG and
CL, 10 MΩ between VC2 and CHG
40
7.26 I2C and HDQ Interface I/O
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SCL, SDA, VREG = 1.8 V (STANDARD and FAST
modes)
VIH
VIL
Input voltage high
0.7 × VREG
V
SCL, SDA, VREG = 1.8 V (STANDARD and FAST
modes)
Input voltage low
–0.5
0.3 × VREG
0.2 × VREG
0.4
V
V
SCL, SDA, VREG = 1.8 V, IOL = 3 mA (FAST mode)
VOL
Output low voltage
Input capacitance
SCL, SDA, VREG > 2.0 V, IOL = 3 mA (STANDARD and
FAST modes)
V
CIN
10
pF
µA
kΩ
Input leakage
current
ILKG
RPD
1
Pull-down resistance
3.3
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ZHCSE72 –SEPTEMBER 2015
www.ti.com.cn
7.27 I2C Interface Timing
Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V
to 7.6 V (unless otherwise noted)
MIN
NOM
MAX
300
UNIT
ns
tR
Clock rise time
Clock fall time
10% to 90%
90% to 10%
tF
300
ns
tHIGH
tLOW
Clock high period
Clock low period
600
1.3
ns
µs
Repeated start
setup time
tSU(START)
td(START)
600
600
ns
ns
Start for first falling
edge to SCL
tSU(DATA)
tHD(DATA)
tSU(STOP)
Data setup time
Data hold time
Stop setup time
100
0
ns
µs
ns
600
Bus free time
between stop and
start
tBUF
1.3
µs
Clock operating
frequency
fSW
SLAVE mode, SCL 50% duty cycle
400
kHz
t
t
t
t
t
f
t
w(L)
r
(BUF)
SU(STA)
w(H)
SCL
SDA
t
t
t
d(STA)
su(STOP)
f
t
r
t
t
su(DAT)
h(DAT)
REPEATED
START
STOP
START
Figure 1. I2C Timing
7.28 HDQ Interface Timing
TA = –40 to +85°C, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25°C and VBAT = 3.6 V (unless otherwise noted).
Capacitance on HDQ is 10 pF unless otherwise specified
MIN
190
190
0.5
32
NOM
MAX
500
250
50
UNIT
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
s
t(CYCH)
t(CYCD)
t(HW1)
t(DW1)
t(HW0)
t(DW0)
t(RSPS)
t(B)
Cycle time, Host to Slave
Cycle time, Slave to Host
Host sends 1 to Slave
Slave sends 1 to Host
Host sends 0 to Slave
Slave sends 0 to Host
Response time, Slave to Host
Break Time
205
50
86
145
145
950
80
190
190
40
t(BR)
Break Recovery Time
HDQ Line Rise Time to Logic 1 (1.2 V)
HDQ Reset
t(R)
950
2.2
t(RST)
1.8
12
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ZHCSE72 –SEPTEMBER 2015
Figure 2. HDQ Timing
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7.29 Typical Characteristics
0.15
0.10
8.0
6.0
Max CC Offset Error
Min CC Offset Error
4.0
0.05
2.0
0.00
0.0
œ2.0
œ4.0
œ6.0
œ8.0
œ0.05
œ0.10
œ0.15
Max ADC Offset Error
Min ADC Offset Error
0
20
40
60
80
100
120
œ40
œ20
0
20
40
60 80 100
120
œ40
œ20
Temperature (°C)
Temperature (°C)
C001
C003
Figure 3. CC Offset Error vs.Temperature
Figure 4. ADC Offset Error vs.Temperature
1.24
1.23
1.22
1.21
1.20
264
262
260
258
256
254
252
250
0
20
40
60
80
100
0
20
40
60
80
100
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C006
C007
Figure 5. Reference Voltage vs.Temperature
Figure 6. Low-Frequency Oscillator vs.Temperature
16.9
16.8
16.7
16.6
œ24.6
œ24.8
œ25.0
œ25.2
œ25.4
œ25.6
œ25.8
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C008
C009
Threshold setting is 25 mV.
Figure 7. High-Frequency Oscillator vs.Temperature
Figure 8. Overcurrent Discharge Protection Threshold
vs.Temperature
14
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ZHCSE72 –SEPTEMBER 2015
Typical Characteristics (continued)
87.4
œ86.0
œ86.2
œ86.4
œ86.6
œ86.8
œ87.0
œ87.2
87.2
87.0
86.8
86.6
86.4
86.2
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C010
C011
Threshold setting is 25 mV.
Threshold setting is –88.85 mV.
Figure 9. Short Circuit Charge Protection Threshold
vs.Temperature
Figure 10. Short Circuit Discharge 1 Protection Threshold
vs.Temperature
11.00
10.95
10.90
10.85
10.80
10.75
10.70
œ172.9
œ173.0
œ173.1
œ173.2
œ173.3
œ173.4
œ173.5
œ173.6
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C012
C013
Threshold setting is –177.7 mV.
Threshold setting is 11 ms.
Figure 12. Overcurrent Delay Time vs.Temperature
Figure 11. Short Circuit Discharge 2 Protection Threshold
vs.Temperature
452
450
448
446
444
442
440
438
436
434
432
480
460
440
420
400
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C014
C015
Threshold setting is 465 µs.
Threshold setting is 465 µs (including internal delay).
Figure 13. Short Circuit Charge Current Delay Time
vs.Temperature
Figure 14. Short Circuit Discharge 1 Delay Time
vs.Temperature
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ZHCSE72 –SEPTEMBER 2015
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Typical Characteristics (continued)
2.4984
2.49835
2.4983
2.49825
2.4982
2.49815
2.4981
2.49805
2.498
3.49825
3.4982
3.49815
3.4981
3.49805
3.498
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C016
C017
This is the VCELL average for single cell.
Figure 15. VCELL Measurement at 2.5-V vs.Temperature
Figure 16. VCELL Measurement at 3.5-V vs.Temperature
4.24805
99.25
4.248
4.24795
4.2479
99.20
99.15
99.10
99.05
99.00
4.24785
4.2478
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C018
C019
This is the VCELL average for single cell.
Figure 17. VCELL Measurement at 4.25-V vs.Temperature
ISET = 100 mA
Figure 18. I Measured vs.Temperature
16
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bq78z100
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ZHCSE72 –SEPTEMBER 2015
8 Detailed Description
8.1 Overview
The bq78z100 gas gauge is a fully integrated battery manager that employs flash-based firmware and integrated
hardware protection to provide a complete solution for battery-stack architectures composed of 1-series or 2-
series cells. The bq78z100 device interfaces with a host system via I2C or HDQ protocols. High-performance,
integrated analog peripherals enable support for a sense resistor down to 1 mΩ and simultaneous
current/voltage data conversion for instant power calculations. The following sections detail all of the major
component blocks included as part of the bq78z100 device.
8.2 Functional Block Diagram
The Functional Block Diagram shows the analog and digital peripheral content in the bq78z100 device.
High Side
N-CH FET
Drive
Cell, Stack,
Pack
Voltage
Cell
Balancing
Cell Detach
Detection
Power Mode
Control
Zero Volt
Charge
Control
Wake
Comparator
Power On
Reset
Short Circuit
Comparator
Over
Current
Comparator
Voltage
Reference2
Watchdog
Timer
Interrupt
NTC Bias
Internal
Temp
Sensor
(
AD0/RC0 TS1
)
Internal
Reset
Voltage
Reference1
ADC MUX
AFE Control
Low
Frequency
Oscillator
ADC/CC
FRONTEND
AFE COM
Engine
1.8-V LDO
Regulator
SRP
SRN
SDA/HDQ
SCL
High
Frequency
Oscillator
Low Voltage
I/O
I/O &
Interrupt
Controller
In-Circuit
Emulator
ADC/CC
Digital Filter
Timers&
PWM
AFE COM
Engine
COM
Engine
Data (8 bit)
DMAddr (16 bit)
bqBMP
CPU
PMInstr
(8 bit)
PMAddr
(16 bit)
Program
Flash
EEPROM
Data Flash
EEPROM
Data
SRAM
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ZHCSE72 –SEPTEMBER 2015
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8.3 Feature Description
8.3.1 Battery Parameter Measurements
The bq78z100 device measures cell voltage and current simultaneously, and also measures temperature to
calculate the information related to remaining capacity, full charge capacity, state-of-health, and other gauging
parameters.
8.3.1.1 bq78z100 Processor
The bq78z100 device uses a custom TI-proprietary processor design that features a Harvard architecture and
operates at frequencies up to 4.2 MHz. Using an adaptive, three-stage instruction pipeline, the bq78z100
processor supports variable instruction length of 8, 16, or 24 bits.
8.3.2 Coulomb Counter (CC)
The first ADC is an integrating converter designed specifically for coulomb counting. The converter resolution is a
function of its full-scale range and number of bits, yielding a 3.74-µV resolution.
8.3.3 CC Digital Filter
The CC digital filter generates a 16-bit conversion value from the delta-sigma CC front-end. Its FIR filter uses the
LFO clock output, which allows it to stop the HFO clock during conversions. New conversions are available every
250 ms while CCTL[CC_ON] = 1. Proper use of this peripheral requires turning on the CC modulator in the AFE.
8.3.4 ADC Multiplexer
The ADC multiplexer provides selectable connections to the VCx inputs, TS1 inputs, internal temperature sensor,
internal reference voltages, internal 1.8-V regulator, PACK input, and VSS ground reference input. In addition,
the multiplexer can independently enable the TS1 input connection to the internal thermistor biasing circuitry, and
also enables the user to short the multiplexer inputs for test and calibration purposes.
8.3.5 Analog-to-Digital Converter (ADC)
The second ADC is a 16-bit delta-sigma converter designed for general-purpose measurements. The ADC
automatically scales the input voltage range during sampling based on channel selection. The converter
resolution is a function of its full-scale range and number of bits, yielding a 38-µV resolution. The default
conversion time of the ADC is 31.25 ms, but is user-configurable down to 1.95 ms. Decreasing the conversion
time presents a tradeoff between conversion speed and accuracy, as the resolution decreases for faster
conversion times.
8.3.6 ADC Digital Filter
The ADC digital filter generates a 24-bit conversion result from the delta-sigma ADC front end. Its FIR filter uses
the LFO clock, which allows it to stop the HFO clock during conversions. The ADC digital filter is capable of
providing two 24-bit results: one result from the delta-sigma ADC front-end and a second synchronous result
from the delta-sigma CC front-end.
8.3.7 Internal Temperature Sensor
An internal temperature sensor is available on the bq78z100 device to reduce the cost, power, and size of the
external components necessary to measure temperature. It is available for connection to the ADC using the
multiplexer, and is ideal for quickly determining pack temperature under a variety of operating conditions.
8.3.8 External Temperature Sensor Support
The TS1 input is enabled with an internal 18-kΩ (Typ.) linearization pull-up resistor to support the use of a 10-kΩ
(25°C) NTC external thermistor, such as the Semitec 103AT-2. The NTC thermistor should be connected
between VSS and the individual TS1 pin. The analog measurement is then taken via the ADC through its input
multiplexer. If a different thermistor type is required, then changes to configurations may be required.
18
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ZHCSE72 –SEPTEMBER 2015
Feature Description (continued)
VREG
RNTC
ADx
NTC
Figure 19. External Thermistor Biasing
8.3.9 Power Supply Control
The bq78z100 device manages its supply voltage dynamically according to operating conditions. When VVC2
VSWITCHOVER– + VHYS, the AFE connects an internal switch to BAT and uses this pin to supply power to its internal
1.8-V LDO, which subsequently powers all device logic and flash operations. Once VC2 decreases to VVC2
>
<
VSWITCHOVER–, the AFE disconnects its internal switch from VC2 and connects another switch to PACK, allowing
sourcing of power from a charger (if present). An external capacitor connected to PBI provides a momentary
supply voltage to help guard against system brownouts due to transient short-circuit or overload events that pull
VC2 below VSWITCHOVER–
.
8.3.10 Power-On Reset
In the event of a power-cycle, the bq78z100 AFE holds its internal RESET output pin high for tRST duration to
allow its internal 1.8-V LDO and LFO to stabilize before running the AGG. The AFE enters power-on reset when
the voltage at VREG falls below VREGIT– and exits reset when VREG rises above VREGIT– + VHYS for tRST time. After
tRST, the bq78z100 AGG will write its trim values to the AFE.
tRST
normal operation
(untrimmed)
normal operation
(trimmed)
tOSU
VIT+
1.8-V Regulator
LFO
VIT–
AFE RESET
AGG writes trim values to
AFE
Figure 20. POR Timing Diagram
8.3.11 Bus Communication Interface
The bq78z100 device has an I2C bus communication interface by default, but can be configured to use the
single-wire HDQ interface. Devices for end applications that operate in HDQ mode are intended to be kept in
default I2C mode as they go through pack manufacturer production line so that they can be configured and tested
at the PCB level before they are converted to HDQ mode.
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ZHCSE72 –SEPTEMBER 2015
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Feature Description (continued)
CAUTION
If the device is configured as a single-master architecture (an application processor)
and an occasional NACK is detected in the operation, the master can resend the
transaction. However, in a multi-master architecture, an incorrect ACK leading to
accidental loss of bus arbitration can cause a master to wait incorrectly for another
master to clear the bus. If this master does not get a bus-free signal, then it must have
in place a method to look for the bus and assume it is free after some period of time.
Also, if possible, set the clock speed to be 100 kHz or less to significantly reduce the
issue described above for multi-mode operation.
8.3.12 Cell Balancing Support
The integrated cell balancing FETs included in the bq78z100 device enable the AFE to bypass cell current
around a given cell or numerous cells to effectively balance the entire battery stack. External series resistors
placed between the cell connections and the VCx input pins set the balancing current magnitude. The cell
balancing circuitry can be enabled or disabled via the CELL_BAL_DET[CB2, CB1] control register. Series input
resistors between 100 Ω and 1 kΩ are recommended for effective cell balancing.
VC2
VC1
VSS
Figure 21. Internal Cell Balancing
8.3.13 N-Channel Protection FET Drive
The bq78z100 device controls two external N-Channel MOSFETs in a back-to-back configuration for battery
protection. The charge (CHG) and discharge (DSG) FETs are automatically disabled if a safety fault (AOLD,
ASSC, ASCD, SOV) is detected, and can also be manually turned off using AFE_CONTROL[CHGEN, DSGEN]
= 0, 0. When the gate drive is disabled, an internal circuit discharges CHG to VC2 and DSG to PACK.
8.3.14 Low Frequency Oscillator
The bq78z100 AFE includes a low frequency oscillator (LFO) running at 262.144 kHz. The AFE monitors the
LFO frequency and indicates a failure via LATCH_STATUS[LFO] if the output frequency is much lower than
normal.
8.3.15 High Frequency Oscillator
The bq78z100 AGG includes a high frequency oscillator (HFO) running at 16.78 MHz. It is synthesized from the
LFO output and scaled down to 8.388 MHz with 50% duty cycle.
8.3.16 1.8-V Low Dropout Regulator
The bq78z100 AFE contains an integrated 1.8-V LDO that provides regulated supply voltage for the device CPU
and internal digital logic.
20
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ZHCSE72 –SEPTEMBER 2015
Feature Description (continued)
8.3.17 Internal Voltage References
The bq78z100 AFE provides two internal voltage references with VREF1, used by the ADC and CC, while VREF2 is
used by the LDO, LFO, current wake comparator, and OCD/SCC/SCD1/SCD2 current protection circuitry.
8.3.18 Overcurrent in Discharge Protection
The overcurrent in discharge (OCD) function detects abnormally high current in the discharge direction. The
overload in discharge threshold and delay time are configurable via the OCD_CONTROL register. The thresholds
and timing can be fine-tuned even further based on a sense resistor with lower resistance or wider tolerance via
the PROTECTION_CONTROL register. The detection circuit also incorporates a filtered delay before disabling
the CHG and DSG FETs. When an OCD event occurs, the LATCH_STATUS[OCD] bit is set to 1 and is latched
until it is cleared and the fault condition has been removed.
8.3.19 Short-Circuit Current in Charge Protection
The short-circuit current in charge (SCC) function detects catastrophic current conditions in the charge direction.
The short-circuit in charge threshold and delay time are configurable via the SCC_CONTROL register. The
thresholds and timing can be fine-tuned even further based on a sense resistor with lower resistance or wider
tolerance via the PROTECTION_CONTROL register. The detection circuit also incorporates a blanking delay
before disabling the CHG and DSG FETs. When an SCC event occurs, the LATCH_STATUS[SCC] bit is set to
1 and is latched until it is cleared and the fault condition has been removed.
8.3.20 Short-Circuit Current in Discharge 1 and 2 Protection
The short-circuit current in discharge (SCD) function detects catastrophic current conditions in the discharge
direction. The short-circuit in discharge thresholds and delay times are configurable via the SCD1_CONTROL
and SCD2_CONTROL registers. The thresholds and timing can be fine-tuned even further based on a sense
resistor with lower resistance or wider tolerance via the PROTECTION_CONTROL register. The detection circuit
also incorporates a blanking delay before disabling the CHG and DSG FETs. When an SCD event occurs, the
LATCH_STATUS[SCD1] or LATCH_STATUS[SCD2] bit is set to 1 and is latched until it is cleared and the fault
condition has been removed.
8.3.21 Primary Protection Features
The bq78z100 gas gauge supports the following battery and system level protection features, which can be
configured using firmware:
•
•
•
•
•
•
•
•
•
•
Cell Undervoltage Protection
Cell Overvoltage Protection
Overcurrent in CHARGE Mode Protection
Overcurrent in DISCHARGE Mode Protection
Overload in DISCHARGE Mode Protection
Short Circuit in CHARGE Mode Protection
Overtemperature in CHARGE Mode Protection
Overtemperature in DISCHARGE Mode Protection
Precharge Timeout Protection
Fast Charge Timeout Protection
8.3.22 Gas Gauging
This device uses the Impedance Track technology to measure and determine the available charge in battery
cells. The accuracy achieved using this method is better than 1% error over the lifetime of the battery. There is
no full charge/discharge learning cycle required. See the Theory and Implementation of Impedance Track Battery
Fuel-Gauging Algorithm Application Report (SLUA364B) for further details.
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ZHCSE72 –SEPTEMBER 2015
www.ti.com.cn
Feature Description (continued)
8.3.23 Charge Control Features
This device supports charge control features, such as:
•
Reports charging voltage and charging current based on the active temperature range—JEITA temperature
ranges T1, T2, T3, T4, T5, and T6
•
•
Provides more complex charging profiles, including sub-ranges within a standard temperature range
Reports the appropriate charging current required for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger, using the bus communication interface
•
Selects the chemical state-of-charge of each battery cell using the Impedance Track method, and reduces the
voltage difference between cells when cell balancing multiple cells in a series
•
•
•
Provides pre-charging/zero-volt charging
Employs charge inhibit and charge suspend if battery pack temperature is out of programmed range
Reports charging faults and indicates charge status via charge and discharge alarms
8.3.24 Authentication
This device supports security by:
•
•
Authentication by the host using the SHA-1 method
The gas gauge requires SHA-1 authentication before the device can be unsealed or allow full access.
8.4 Device Functional Modes
This device supports three modes, but the current consumption varies, based on firmware control of certain
functions and modes of operation:
•
•
•
NORMAL mode: In this mode, the device performs measurements, calculations, protections, and data
updates every 250-ms intervals. Between these intervals, the device is operating in a reduced power stage to
minimize total average current consumption.
SLEEP mode: In this mode, the device performs measurements, calculations, protections, and data updates
in adjustable time intervals. Between these intervals, the device is operating in a reduced power stage to
minimize total average current consumption.
SHUTDOWN mode: The device is completely disabled.
8.4.1 Lifetime Logging Features
The device supports data logging of several key parameters for warranty and analysis:
•
•
•
Maximum and Minimum Cell Temperature
Maximum Current in CHARGE or DISCHARGE Mode
Maximum and Minimum Cell Voltages
8.4.2 Configuration
The device supports accurate data measurements and data logging of several key parameters.
8.4.2.1 Coulomb Counting
The device uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement. The ADC
measures charge/discharge flow of the battery by measuring the voltage across a very small external sense
resistor. The integrating ADC measures a bipolar signal from a range of –100 mV to 100 mV, with a positive
value when V(SRP) – V(SRN), indicating charge current and a negative value indicating discharge current. The
integration method uses a continuous timer and internal counter, which has a rate of 0.65 nVh.
8.4.2.2 Cell Voltage Measurements
The bq78z100 measures the individual cell voltages at 250-ms intervals using an ADC. This measured value is
internally scaled for the ADC and is calibrated to reduce any errors due to offsets. This data is also used for
calculating the impedance of the individual cell for Impedance Track gas gauging.
22
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ZHCSE72 –SEPTEMBER 2015
Device Functional Modes (continued)
8.4.2.3 Current Measurements
The current measurement is performed by measuring the voltage drop across the external sense resistor (1 mΩ
to 3 mΩ) and the polarity of the differential voltage determines if the cell is in the CHARGE or DISCHARGE
mode.
8.4.2.4 Auto Calibration
The auto-calibration feature helps to cancel any voltage offset across the SRP and SRN pins for accurate
measurement of the cell voltage, charge/discharge current, and thermistor temperature. The auto-calibration is
performed when there is no communication activity for a minimum of 5 s on the bus lines.
8.4.2.5 Temperature Measurements
This device has an internal sensor for on-die temperature measurements, and the ability to support external
temperature measurements via the external NTC on the TS1 pin. These two measurements are individually
enabled and configured.
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ZHCSE72 –SEPTEMBER 2015
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9 Applications and Implementation
9.1 Application Information
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
The bq78z100 gas gauge is a primary protection device that can be used with a 1-series or 2-series Li-Ion/Li
Polymer battery pack. To implement and design a comprehensive set of parameters for a specific battery pack,
the user needs Battery Management Studio (bqSTUDIO), which is a graphical user-interface tool installed on a
PC during development. The firmware installed in the product has default values, which are summarized in the
bq78z100 Technical Reference Manual (SLUUB63) for this product. Using the bqSTUDIO tool, these default
values can be changed to cater to specific application requirements during development once the system
parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation,
configuration of cells, chemistry that best matches the cell used, and more are known. This data can be referred
to as the "golden image."
9.2 Typical Applications
The following is the bq78z100 application schematic for the 2-series configuration.
0.1
0.1
µF
µF
2N7002K
10 M
10 M
10 k
Fuse
13
100
1
12
VC1
VSS
0.1 µF
0.1 µF
PWPD
2 s
1 s
0.1µF
1 µF
SRN
VC2 11
PBI 10
2
3
4
5
6
5
0.1 µF
0.1 µF
0.1 µF
5.1 k
5.1 k
SRP
2.2 µF
PACK+
TS1
CHG
9
8
7
10 k
100
10
100
100
SCL
SCL
PACK
DSG
MM3Z5V6C
100
SDA/HDQ
SDA/HDQ
MM3Z5V6C
–
PACK
100
100
1 to 3 mΩ
Note:
The input filter capacitors of 0.1 µF for the SRN and SRP pins must be located near the pins of
the device.
Figure 22. bq78z100 2-Series Cell Typical Implementation
9.2.1 Design Requirements (Default)
Design Parameter
Cell Configuration
Design Capacity
Device Chemistry
Example
2s1p (2-series with 1 Parallel)
4400 mAH
100 (LiCoO2/graphitized carbon)
24
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bq78z100
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ZHCSE72 –SEPTEMBER 2015
Typical Applications (continued)
Design Parameter
Cell Overvoltage at Standard Temperature
Cell Undervoltage
Example
4300 mV
2500 mV
2300 mV
6000 mA
–6000 mA
Shutdown Voltage
Overcurrent in CHARGE Mode
Overcurrent in DISCHARGE Mode
Short Circuit in CHARGE Mode
Short Circuit in DISCHARGE 1 Mode
Safety Over Voltage
0.1 V/Rsense across SRP, SRN
0.1 V/Rsense across SRP, SRN
4500 mV
Disabled
Enabled
0°C
Cell Balancing
Internal and External Temperature Sensor
Under Temperature Charging
Under Temperature Discharging
BROADCAST Mode
0°C
Enabled
Enabled
I2C Interface
9.2.2 Detailed Design Procedure
9.2.2.1 Setting Design Parameters
For the firmware settings needed for the design requirements, refer to the bq78z100 Technical Reference
Manual (SLUUB63).
•
•
To set the 2s1p battery pack, go to data flash Configuration: DA Configuration register's bit 0 (CC0) = 1.
To set design capacity, set the data flash value to 4400 in the Gas Gauging: Design: Design Capacity
register.
•
To set device chemistry, go to data flash SBS Configuration: Data: Device Chemistry. The bqStudio
software automatically populates the correct chemistry identification. This selection is derived from using the
bqCHEM feature in the tools and choosing the option that matches the device chemistry from the list.
•
•
•
To protect against cell overvoltage, set the data flash value to 4300 in Protections: COV: Standard Temp.
To protect against cell undervoltage, set the data flash value to 2500 in the Protections: CUV register.
To set the shutdown voltage to prevent further pack depletion due to low pack voltage, program Power:
Shutdown: Shutdown voltage = 2300.
•
•
•
To protect against large charging currents when the AC adapter is attached, set the data flash value to 6000
in the Protections: OCC: Threshold register.
To protect against large discharging currents when heavy loads are attached, set the data flash value to
–6000 in the Protections: OCD: Threshold register.
Program a short circuit delay timer and threshold setting to enable the operating the system for large short
transient current pulses. These two parameters are under Protections: ASCC: Threshold = 100 for charging
current. The discharge current setting is Protections: ASCD:Threshold = –100 mV.
•
To prevent the cells from overcharging and adding a second level of safety, there is a register setting that will
shut down the device if any of the cells voltage measurement is greater than the Safety Over Voltage setting
for greater than the delay time. Set this data flash value to 4500 in Permanent Fail: SOV: Threshold.
•
•
•
•
To disable the cell balancing feature, set the data flash value to 0 in Settings: Configuration: Balancing
Configuration: bit 0 (CB).
To enable the internal temperature and the external temperature sensors: Set Settings:Configuration:
Temperature Enable: Bit 0 (TSInt) = 1 for the internal sensor; set Bit 1 (TS1) = 1 for the external sensor.
To prevent charging of the battery pack if the temperature falls below 0°C, set Protections: UTC:Threshold
= 0.
To prevent discharging of the battery pack if the temperature falls below 0°C, set Protections:
UTD:Threshold = 0.
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ZHCSE72 –SEPTEMBER 2015
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Each parameter listed for fault trigger thresholds has a delay timer setting associated for any noise filtering.
These values, along with the trigger thresholds for fault detection, may be changed based upon the application
requirements using the data flash settings in the appropriate register stated in the bq78z100 Technical Reference
Manual (SLUUB63).
9.2.3 Calibration Process
The calibration of Current, Voltage, and Temperature readings is accessible by writing 0xF081 or 0xF082 to
ManufacturerAccess(). A detailed procedure is included in the bq78z100 Technical Reference Manual
(SLUUB63) in the Calibration section. The description allows for calibration of Cell Voltage Measurement Offset,
Battery Voltage, Pack Voltage, Current Calibration, Coulomb Counter Offset, PCB Offset, CC Gain/Capacity
Gain, and Temperature Measurement for both internal and external sensors.
9.2.4 Gauging Data Updates
When a battery pack enabled with the bq78z100 is first cycled, the value of FullChargeCapacity() updates
several times. Figure 23 shows RemainingCapacity() and FullChargeCapacity(), and where those updates occur.
As part of the Impedance Track algorithm, it is expected that FullChargeCapacity() may update at the end of
charge, at the end of discharge, and at rest.
9.2.4.1 Application Curve
Figure 23. Gauging Data Updates
26
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bq78z100
www.ti.com.cn
ZHCSE72 –SEPTEMBER 2015
10 Power Supply Requirements
There are two inputs for this device, the PACK input and VC2. The PACK input can be an unregulated input from
a typical AC adapter. This input should always be greater than the maximum voltage associated with the number
of series cells configured. The input voltage for the VC2 pin will have a minimum of 2.2 V to a maximum of 26 V
with the recommended external RC filter.
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE72 –SEPTEMBER 2015
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
•
The layout for the high-current path begins at the PACK+ pin of the battery pack. As charge current travels
through the pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell
connections, and the sense resistor, and then returns to the PACK– pin. In addition, some components are
placed across the PACK+ and PACK– pins to reduce effects from electrostatic discharge.
•
The N-channel charge and discharge FETs must be selected for a given application. Most portable battery
applications are a good option for the CSD16412Q5A. These FETs are rated at 14-A, 25-V device with
Rds(on) of 11 mΩ when the gate drive voltage is 10 V. The gates of all protection FETs are pulled to the
source with a high-value resistor between the gate and source to ensure they are turned off if the gate drive
is open. The capacitors (both 0.1 µF values) placed across the FETs are to help protect the FETs during an
ESD event. The use of two devices ensures normal operation if one of them becomes shorted. For effective
ESD protection, the copper trace inductance of the capacitor leads must be designed to be as short and wide
as possible. Ensure that the voltage rating of both these capacitors are adequate to hold off the applied
voltage if one of the capacitors becomes shorted.
•
•
The quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a
temperature coefficient no greater than 50 ppm in order to minimize current measurement drift with
temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short-
circuit ranges of the bq78z100. Select the smallest value possible in order to minimize the negative voltage
generated on the bq78z100 VSS node(s) during a short circuit. This pin has an absolute minimum of –0.3 V.
Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a
1-mΩ to 3-mΩ sense resistor.
A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– pins to help in the
mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the
pack if one of the capacitors becomes shorted. Optionally, a transorb such as the SMBJ2A can be placed
across the pins to further improve ESD immunity.
•
•
In reference to the gas gauge circuit the following features require attention for component placement and
layout; Differential Low-Pass Filter, I2C communication and PBI (Power Backup Input).
The bq78z100 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from the
sense resistor to the SRP and SRN inputs of the device. Place a 0.1-μF filter capacitor across the SRP and
SRN inputs. Optional 0.1-μF filter capacitors can be added for additional noise filtering for each sense input
pin to ground, if required for your circuit. Place all filter components as close as possible to the device. Route
the traces from the sense resistor in parallel to the filter circuit. Adding a ground plane around the filter
network can add additional noise immunity.
0.1 µF
0.1 µF
0.1 µF
100
100
0.001, 50 ppm
Filter Circuit
Sense
Ground
Shield
resistor
Figure 24. bq78z100 Differential Filter
•
The bq78z100 has an internal LDO that is internally compensated and does not require an external
decoupling capacitor. The PBI pin is used as a power supply backup input pin, providing power during brief
transient power outages. A standard 2.2-μF ceramic capacitor is connected from the PBI pin to ground, as
shown in application example.
•
The I2C clock and data pins have integrated high-voltage ESD protection circuits; however, adding a Zener
28
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bq78z100
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ZHCSE72 –SEPTEMBER 2015
Layout Guidelines (continued)
diode and series resistor provides more robust ESD performance. The I2C clock and data lines have an
internal pull-down. When the gas gauge senses that both lines are low (such as during removal of the pack),
the device performs auto-offset calibration and then goes into SLEEP mode to conserve power.
11.2 Layout Example
CSD16412Q5A
CSD16412Q5A
D
G
D
G
D
S
D
S
D
S
D
S
D
S
D
S
Power Trace Line
PACK+
PACK–
Reverse Polarity
Portection
Fuse
Input filters
13
1
12
11
10
9
VC1
VC2
VSS
SRN
SRP
TS1
SCL
PWPD
2 s
2
3
Differential Input well
matched for accuracy
1 s
PBI
Thermistor
4
5
CHG
PACK
DSG
8
7
SCL
Bus
Communication
Power Ground Trace
SDA/HDQ
6
SDA/HDQ
Exposed Thermal Pad
Via connects to Power Ground
Via connects between two layers
Figure 25. bq78z100 Board Layout
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ZHCSE72 –SEPTEMBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
更多信息，请参见《bq78z100 技术参考手册》（文献编号：SLUUB63）。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
Impedance Track, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
30
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bq78z100
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ZHCSE72 –SEPTEMBER 2015
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 要获得这份数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ78Z100DRZR
BQ78Z100DRZT
ACTIVE
SON
SON
DRZ
12
12
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ78
Z100
Samples
Samples
ACTIVE
DRZ
NIPDAU
BQ78
Z100
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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23-Jun-2023
Addendum-Page 2
PACKAGE OUTLINE
VSON - 1 mm max height
DRZ0012A
PLASTIC QUAD FLATPACK- NO LEAD
4.15
3.85
B
A
PIN 1 INDEX AREA
2.65
2.35
1
0.8
C
SEATING PLANE
0.08 C
0.05
0
2.55
2.35
(0.2) TYP
2X (0.2)
6
7
SYMM
13
2.05
1.85
2X
2
10X 0.4
1
12
SYMM
0.3
12X
PIN 1 ID
(OPTIONAL)
0.1
0.1
C A B
C
0.5
0.3
12X
0.05
4218895/B 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRZ0012A
PLASTIC QUAD FLATPACK- NO LEAD
2X (2.25)
2X (0.975)
12X (0.6)
12X (0.2)
1
12
(1.95)
10X (0.4)
13
SYMM
2X (2)
(2.9)
2X (0.725)
(Ø0.2) VIA
TYP
6
7
(R0.05) TYP
4X (0.2)
SYMM
(2.45)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218895/B 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRZ0012A
PLASTIC QUAD FLATPACK- NO LEAD
2X (1.08)
4X (1.2625)
2X (0.64)
12X (0.6)
12X (0.2)
1
7
10X (0.4)
SYMM
13
2X (1.75)
(0.05) TYP
12
6
SYMM
4X (0.375)
METAL TYP
4X (0.2)
2X (2.25)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
79% PRINTED COVERAGE BY AREA
SCALE: 20X
4218895/B 03/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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