BQ79600PWRQ1_技术文档

BQ79600-Q1

ZHCSR35A –NOVEMBER 2019 –REVISED AUGUST 2020

BQ79600-Q1 具备自动主机唤醒功能且符合功能安全标准的汽车类SPI/UART 通

信接口

1 特性

2 应用

• 符合汽车应用要求

• 具有符合AEC-Q100 标准的下列特性：

• 电池管理系统(BMS)

• 其他HEV/EV

• 燃料电池

– 器件温度等级1：–40°C 至+125°C 环境工作

温度范围

• 能源存储

– 器件HBM ESD 分类等级2

– 器件CDM ESD 分类等级C4B

• 符合功能安全标准

3 说明

BQ79600-Q1 是一款通信（网桥）IC，旨在连接微控

制器 (MCU) 和 TI 电池监测 IC，例如 BQ7961X-Q1。

器件将来自 MCU 的信息转换为信号，而 TI 的电池管

理菊花链协议用于识别这种信号，并将其传输出来。来

自菊花链的信号被解码为位流，然后发送回MCU。

– 专为功能安全应用开发

– 有助于进行ISO 26262 系统设计的文档

• 安全手册

• 功能安全分析报告

– 系统可满足ASIL D 级要求

– 硬件可满足ASIL-D 要求

• 在环形架构中检测到故障时，自动唤醒BMS/BMU

系统

使用环形架构时如果检测到了任何未屏蔽的故障，则

BQ79600-Q1 可以将处于关断/睡眠模式的 MCU 和

PMIC 唤醒。

器件信息

• 支持的电源电压范围为4.75V 至40V

• UART/SPI 主机接口

• 兼容3.3V/5V 逻辑

• 隔离式差分菊花链

器件型号⁽¹⁾

BQ79600-Q1

封装尺寸（标称值）

封装

6.6mm × 5.1mm

TSSOP（16 引脚）

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 支持包含一台设备的环形架构

– 支持变压器/电容器隔离

• 经过专门设计，旨在实现BCI/EMI/EMC 稳健性

• 支持BQ7961X-Q1 系列、BQ7965X、BQ7963X 和

未来产品。

12V Battery

Battery

EN

SBC

(PMIC)

Balance and Filter

Components

Balance and Filter

Components

Balance and Filter

Components

Balance and Filter

Components

BAT

VIO

uC

NFAULT

UART

_/SPIBQ79600-Q1

BQ796XX-Q1

INH

COML

COMH

COML

COMH

COML

COMH

COML

COMH

COML

COMH

CAP

CAP or

Transfomer

CAP or

Transfomer

CAP or

Transfomer

CAP or

Transfomer

Transformer

BMU

CMU

BMU

isolation

Low Voltage

Boundary

Optional: Ring Enables Fault

and Reverse Wakeup Feature

简化版系统图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDS1

BQ79600-Q1

ZHCSR35A –NOVEMBER 2019 –REVISED AUGUST 2020

www.ti.com.cn

Table of Contents

7.5 Register Maps...........................................................37

8 Application and Implementation..................................55

8.1 Application Information............................................. 55

8.2 Typical Applications.................................................. 55

9 Power Supply Recommendations................................59

10 Layout...........................................................................60

10.1 Layout Guidelines................................................... 60

10.2 Layout Example...................................................... 60

11 Device and Documentation Support..........................63

11.1 Device Support........................................................63

11.2 第三方产品免责声明................................................63

11.3 接收文档更新通知................................................... 63

11.4 支持资源..................................................................63

11.5 Trademarks............................................................. 63

11.6 静电放电警告...........................................................63

11.7 术语表..................................................................... 63

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 规格................................................................................... 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................4

6.4 Thermal Information ...................................................4

6.5 Electrical Characteristics ............................................5

6.6 Timing Requirements .................................................6

6.7 Typical Characteristics................................................9

7 Detailed Description......................................................10

7.1 Overview...................................................................10

7.2 Functional Block Diagram.........................................10

7.3 Feature Description...................................................10

7.4 Device Functional Modes..........................................36

Information.................................................................... 64

4 Revision History

Changes from Revision * (November 2019) to Revision A (June 2020)

Page

• 将“预告信息”更改为“量产数据”.................................................................................................................. 1

2

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5 Pin Configuration and Functions

INH

16

15

14

13

12

11

DVDD

1

2

3

4

5

6

7

8

BAT

NFAULT

CVDD

COMHP

COMHN

VIO

MOSI/RX

16-TSSOP

5.1x6.6x1.2(mm)

No thermal pad

MISO/TX

COMLN

COMLP

GND

SCLK

nCS

10

9

nUART/SPI (SPI_RDY)

图5-1. PW Package 16-Pin TSSOP Top View

Pin Functions

NAME

TYPE⁽¹⁾

DESCRIPTION

NO.

VIO

3

P

Power supply input for UART/SPI input/output pins. Decouple with a 0.1μF capacitor to GND.

VIO should be powered before SCLK, nCS, RX/MOSI, TX/MISO, NFAULT, nUART/SPI

(SPI_RDY) is driven.

SCLK

6

7

4

5

DI

SPI clock input. If SPI interface is used, this pin is connected to SPI master controller. Connect

to GND with a 10-100kohm pull-down resistor. If not used, connect to GND.

nCS

Active low chip select pin for SPI interface. Connect to VIO with 10-100kohm pull-up resistor in

SPI mode. Cannot hardwire to GND in SPI mode. Connect to GND in UART mode.

RX/MOSI

TX/MISO

DI

UART receiver input or SPI master out slave in. Connect to VIO with a 10-100kohm pull-up

resistor. Don't leave it unconnected.

DO

UART transmitter output or SPI master in slave out. Pull up to VIO with a 10-100kohm pull-up

resistor at MCU side. MISO pin drives high in SPI idle mode, cannot directly support SPI

multidrop, if multidrop is needed, add a tri-state buffer between BQ79600-Q1 and MCU.

NFAULT

2

8

DO

Fault indication output. Open drain active low. Pull up to VIO with 100kohm resistor. Connect

NFAULT to host MCU GPIO. If not used, connect to GND.

nUART/SPI

(SPI_RDY)

DI/O

If used as UART mode, connect this pin to GND. If used as SPI mode, connect to VIO through

10-100kohm pull up resistor and connect this pin to MCU GPIO. This pin is used as an input pin

to select SPI or UART interface before device finishes wakeup/reset initialization (SPI

communication is ready). If SPI mode is selected, SPI_RDY has to be used by host to decide if

read/write can be initiated or needing further wait. Refer to 节7.3.2.1.2.2.1 details.

DVDD

1

P

1.8V regulated output. DVDD supplies the internal digital circuits. Bypass DVDD with a 0.22μF

(recommended) or a 0.47μF capacitor to GND.

GND

9

P

Ground.

CVDD

14

Dedicated 5V supply used for the daisy chain communications. Decouple with a 0.22μF

(recommended) or a 0.47μF to GND.

COMHN

COMHP

12

13

AC-I/O This is an AC coupled bi-directional I/O pin for daisy chain (VIF) communication. Do not apply

external DC voltage to this pin. Shall connect to COMLN/P of adjacent device through proper

AC-I/O

isolation, see 节7.3.2.1.1. Leave unconnected if (Ring Architecture) not used.

COMLN

COMLP

11

10

AC-I/O This is an AC coupled bi-directional I/O pin for daisy chain (VIF) communication. Do not apply

external DC voltage to this pin. Shall connect to COMHN/P of adjacent device through proper

AC-I/O

isolation, see 节7.3.2.1.1. Leave unconnected if (Ring Architecture) not used.

INH

16

HV-O

HV-P

Inhibit pin (PMOS open drain) to control system voltage regulators, connect 100kohm resistor

to GND. If reverse wake up feature is not used, connect this pin to BAT pin. Don’t leave this

pin floating.

BAT

15

Battery supply Input. Supply internal LDOs and wakeup circuit. Connect to external supply

through 10ohm resistor. Bypass to GND with 0.1μF.

(1) DI = digital input, DO = digital output, HV = high voltage

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6 规格

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

40

UNIT

BAT to GND

V

INH to GND (INH is lower than BAT)

VIO, CVDD to GND

40

5.5

DVDD to GND

Input Voltage

1.98

MISO/TX, MOSI/RX, nCS, SCLK, NFAULT, nUART/SPI(SPI_RDY) to

GND

VIO+0.3

V

–0.3

COMHP, COMHN, COMLP, COMLN to GND

COMHP to COMHN, COMLP to COMLN

INH current

10

6.5

4

V

–10

–6.5

mA

°C

I/O current

MISO/TX current (100pF load, VIO=5V, 10ns transition-time)

Ambient temperature

8

T_A

125

150

–40

–65

T_J

Junction temperature

T_stg

Storage temperature

(1) Stresses beyond those listed under Absolute Maximum Rating may caµse permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

±2000

±750

±500

V_(ESD)Electrostatic discharge

Corner pins (1, 8, 9 and 16)

Other pins

V

Charged device model (CDM), per

AEC Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

V_{BAT, INH}

BAT, INH (INH is equal to or lower than BAT) (Powered by 12V Battery)

5.5

24

V

VIO input (applies to nCS, MOSI/RX, MISO/TX, SLCK, nUART/SPI

(SPI_RDY), NFAULT)

V_{VIO_RANGE}

3.135

5.25

V

I_MISO/TX

I_INH

MISO/TX current

3

2

mA

°C

INH output current

Operation temperature

T_A

125

–40

6.4 Thermal Information

BQ79600-Q1

THERMAL METRIC⁽¹⁾

PW(TSSOP)

UNIT

16 PINS

102

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

°C/W

R_θJC(top)

R_θJB

28.9

49

14

Ψ_JT

4

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BQ79600-Q1

THERMAL METRIC⁽¹⁾

PW(TSSOP)

16 PINS

48.2

UNIT

Junction-to-board characterization parameter

°C/W

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

VIO = 3.3V, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OPERATION VOLTAGE

When reverse wakeup feature is used,

BAT pin is powered by "12V battery"

V_BAT

5.5

24

V

When reverse wakeup feature is not

used, BAT/CVDD are powered by

regulated 5V

V_BAT

4.75

5.25

THERMAL SHUTDOWN

T_{SHUT_R}Thermal shutdown (rising direction)

T_{SHUT_F}Thermal shutdown (falling direction)

SUPPLY CURRENTS

DieTemp sensor

126

116

138

150

141

°C

Supply current in SHUTDOWN mode

I_{SHDN_1}

VBAT shorted to CVDD, both equal to 5V,

measured through GND pin

7

µA

device powered by regulated 5V supply

Supply current in SHUTDOWN mode

I_{SHDN_2}

VBAT= 17V, CVDD self

powered, measured through GND pin

9

168

110

µA

powered by "12V" battery directly

I_VALIDATESupply current in VALIDATE mode

I_SLP(IDLE)Baseline supply current in SLEEP mode

I_{SLP_RX_O}Additional supply current to SLEEP mode

Current on BAT pin

Current on BAT pin, no fault, COMH and

COML RX disabled, no HB TX

When COML OR COMH RX is on

35

µA

base line

N

I_{SLP_TX_O}Additional supply current to SLEEP mode When COML or COMH tone transmiter is

8

4

base line

on (HB tone)

N

Current on BAT pin, no fault, no

communication, Tone RX/TX is off

I_ACT(IDLE)Baseline supply current in ACTIVE mode

3

mA

Average current into VBAT when

BQ79600 transmits 14 bytes of data

(brdcast write 8 bytes of 0x00 into

address 0X1B)

Additional average current for one of

I_COMT

10

mA

BQ79600 daisy chain transmitters is on

Supplies (AVAO_REF, always on internal supply)

V_AVAORE

AVAOREG voltage

VBAT > min VBAT

2.45

V

G

V_AVDDREF

AVDDREF OV threshold

VBAT > min VBAT, hys = 130mV

2.8

3.1

_OV

Supplies (CVDD)

No external load, C_SUPPLIES= 0.22µF,

ACTIVE mode

V_CVDD

CVDD output voltage

4.9

5.3

5

5.5

4.5

4.6

5.1

5.65

4.65

4.75

V

V_{CVDD_O}

CVDD OV rising threshold

CVDD UV falling threshold

CVDD UV rising threshold

Hys = 140mV

V

V_{CVDD_U}

4.35

4.45

V_F

V_{CVDD_U}

V_R

V_{CVDD_ILI}

CVDD current limit

53

81

mA

µF

MIT

C_CVDD

Capacitance range on CVDD pin

Not capacitor value

0.1

0.8

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VIO = 3.3V, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supplies (DVDD)

No external load, C_SUPPLIES= 0.22µF,

ACTIVE mode

V_DVDD

DVDD output voltage

1.75

1.9

1.8

1.85

2.1

V

V_{DVDD_O}

DVDD OV rising threshold

DVDD UV falling threshold

DVDD UV rising threshold

Hys = 65mV

V

V_{DVDD_U}

1.63

1.68

1.69

1.75

V_F

V_{DVDD_U}

V_R

V_{DVDD_ILI}

DVDD current limit

20

57

mA

µF

MIT

D_DVDD

Load capacitance on DVDD pin

Not capacitor value

0.1

0.8

SNIFF DETECTOR

V_{VAL_THR}Sniffer detector threshold, rising swing on Sniffer is enabled, and device is in

3.2

3.6

1

V

COMHP has to be larger than value

SHUTDOWN mode

_P

INH Driver

V_{DROP_IN}When INH is pulled up, voltage drop from

I_INH= -0.5mA

0.5

V

BAT to INH

H

V_{INH_DET}Threshold to set [INH_STAT] to '1'

Reference Voltages

2.2

2.5

Digital I/Os (TX, RX, NFAULT)

V_{VIO_UV_}

VIO UV rising

Hys = 200mV

3.1

0.1

V

R

V_VIO–

V_OH

V_OL

V_IH

V_IL

Output as logic level high (TX)

Output as logic level low (TX)

FET pull up, Iout=1mA, VIO = 3.3V or 5V

0.1

FET pull down, Iout=1mA, VIO = 3.3V or

5V

Input as logic level high (RX), requirement

for user

0.75 x

V_VIO

VIO = 3.3V or 5V

Input as logic level low (RX), requirement

for user

0.25 x

V_VIO

VIO = 3.3V or 5V

V

R_NFAULTNFAULT pull down impedance

Use 100kohm external pull up

1000

Ω

Daisy-chain Communication Bus

Common mode voltage (COML and

V_{DCCM_1}

COMH)

ACTIVE mode

2.2

1

V

Common mode voltage (COML and

V_{DCCM_2}

COMH)

SLEEP or VALIDATE mode

V_{COMM_D}COMM port data receiver threshold range

1.04

1.13

1.75

1.94

(V_COMP-V_COMN

V_{COMM_T}COMM port HB/FAULT tone receiver

threshold range (V_COMP-V_COMN

)

ATA

)

ONE

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER STATE TIMING

From V_BAT(rising) > V_PORto device ready

to receive WAKE ping, ramp up VBAT

and VIO in 10µs

t_POR2COM

1

ms

M

6

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

From receiving WAKE ping (RX ping

going low-to-high) to device in ACTIVE

mode (ready to do µART /SPI

communication) (CVDD= 0.22µF

capacitor DVDD = 0.22µF capacitor)

t_{SU(WAKE_}Startup from SHUTDOWN/VALIDATE to

2

3.5

ms

ACTIVE mode

SHUT)

From receiving SLP2ACT ping (RX ping

going low-to-high) to device in ACTIVE

mode (ready to do UART /

t_SU(SLP2AStartup from SLEEP to ACTIVE mode

260

600

µs

(with Sleep2active ping)

CT)

SPIcommunication)

From receiving WAKE ping (RX ping

going low-to-high) to device in ACTIVE

mode (ready to do UART /

t_{SU(WAKE_}Startup from SLEEP to ACTIVE mode

(with WAKE ping)

SLP)

SPIcommunication)

From receiving WAKE ping (RX ping

going low-to-high) or

CONTROL1[SOFT_RESET]=1 to device

in ACTIVE mode (ready to do UART /SPI

communication)

Reset time from ACTIVE mode to

ACTIVE mode

t_RST

600

µs

From receiving SLEEP entry condition to

enter in SLEEP mode

t_SLP

From ACTIVE to SLEEP mode

100

5

µs

From receiving SHUTDOWN entry

condition to enter in SHUTDOWN mode

(CVDD<1.2V)

From ACTIVE/SLEEP/VALIDATE to

SHUTDOWN mode

t_SHTDN

ms

t_{VALID_EN}

From fault tone toggling on COM port to

DVDD hit above 1.75V

From SHUTDOWN to VALIDATE

10

ms

TRY

t_{VALID_TIM}time to validate fault tone before transition

Start from DVDD out of reset

150

720

to SHUTDOWN state

EOUT

INH Driver TIMING

After device enters VALIDATE, from first

t_{INH_DLY}

µs

couplet of fault tone to INH pulled high

PING SIGNAL TIMING

t_{HLD_WAK}From user perspective, WAKE ping low

VBAT > VPOR, RX pin (low-pulse width)

VIO = 3.3 or 5V

2.5

12.5

250

3

ms

µs

time on MOSI/RX pin

E

From user perspective, SHUTDOWN ping VBAT > VPOR, RX pin (low-pulse

low time on MOSI/RX pin

t_{HLD_SD}

t_StA

width) VIO = 3.3 or 5V

From user perspective, SLEEPtoACTIVE

ping low time on MOSI/RX pin

VBAT > VPOR

300

Daisy-chain Communication Bus TIMING

COMM data Pulse width of data (half bit

time) for communiction

t_{PW_DC}

230

10.67

0.97

250

11

1

270

11.33

1.03

ns

µs

Time between pulses within a comm tone Transmit. From the beginning of a pulse

(HFO based).

t_COMTONE

until the beginning of the next pulse.

t_COMTONE

Comm tone pulse width(HFO based)

Transmit

_PLS

Only transmit HB tone, not FAULT

tone. From the beginning of a pulse until

the beginning of the next pulse.

Time between pulses within a fault tone

(LFO based).

t_FLTTONE

10.3

11.5

12.7

µs

t_{FLTTONE_}Fault tone or HB tone pulse width (analog

1

16

64

µs

delay based)

PLS

HEARTBEAT: Number of pulses to detect

n_HBDET

Detect

pulses

as a valid tone (dig counter)

n_FTONEDEFAULT TONE: Number of pulses to detect

as a valid tone (dig counter)

T

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HEARTBEAT: Period between

t_{HB_PERIO}HEARTBEAT Burst (from the beginning of

360

400

440

1.1

ms

a HEARTBEAT to the beginning of the

D

next HEARTBEAT)

t_{HB_TIMEO}HEARTBEAT: Timeout to considered as

0.9

1

s

not receving HEARTBEAT

UT

HEARTBEAT: If HEARTBEAT is received

t_{HB_FAST}within this time, it is considered receving

HEARTBEAT too fast

200

ms

t_{FTONE_PE}Defined by BQ7961X, FAULT TONE:

From the beginning of a FAULT TONE to

the beginning of the next FAULT TONE

50

24

ms

µs

Period between FAULT TONE Burst

RIOD

t_{FT_LATEN}

From the time device receives the tone to

the time asserts NFAULT

Fault Tone latency in Base Device

CY

I/O TIMING (TX, RX, NFAULT)

t_{RISE_TX}Rise Time

t_{FALL_TX}Fall Time

C_LOAD= 100pF, VIO=3.3V or 5V

15

ns

t_FALL/

RX pin rise/fall time

100

1.5

ns

RISE_RX

UART TIMING

UARTER UART TX/RX baud rate (either 250K or

R_BAUD 1Mbps) error

%

–1.5

15

t_UART(CLR

UART Comm Clear low time

20 bit period

bit period

)

t_{UART(RX_}UART high time after Comm Clear, before

1

sending Clear or Reset

HIGH)

SPI TIMING

SCLK

SPI clock freq

2

6

MHz

bit

n_SPI(CLR)SPI Comm Clear low time

8

t_{SPI_R}

t_{SPI_F}

SPI clock rising edge

SPI clock falling edge

25% to 75%

10

ns

t_{SPI_CLKH}SPI clock high time

t_{SPI_CLKL}SPI clock low time

70

ns

Max SPI_RDY service interval. This time

doesn't apply if total response bytes

(payload + overhead) is less than 256

bytes

Read SCLK = 6MHz, with 30% SPI BUS

idle time

t₈

1

ms

t₉

From nCS (25%) to SCLK rising (75%)

From SCLK falling (25%) to nCS (75%)

500

ns

t₁₀

From nCS rising(75%) to nCS

falling(25%)

t₁₁

Don't drop nCS while SPI_RDY is low

1

µs

ns

Timing is defined at device pins, exclude

propergation delay of PCB traces (from

device perspective)

From nCS falling (25%) to stable

MISO(L:20% H:80%)

t₁₂

42

Timing is defined at device pins, exclude

propergation delay of PCB traces (from

device perspective)

From SCLK falling (25%) to stable

MISO(L:20% H:80%)

t₁₃

ns

Timing is defined at device pins, exclude

propergation delay of PCB traces (from

device perspective)

From nCS rising (75%) to MISO drive to

'1' (80%)

t₁₄

t_SU

t_H

Setup time, refer to 75% of SCLK rising

Hold time, refer to 75% of SCLK rising

20

ns

SNIFF DETECTOR

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Number of pulses needed (digital counter) Sniffer is enabled, and device is in

n_VALIDATE

64

pulses

to transition to validate mode

SHUTDOWN mode

Timer length. Once timer expired, it resets Sniffer is enabled, and device is in

t_SNIFFIDLE

20

52

µs

the 64 counter

OSCILLATOR

SHUTDOWN mode

f_HFO

HFO frequency

31.52

32

32.48

35

MHz

µs

Reset digital if HFO is stuck or period is >

than the watchdog timer

t_HFOWDGHFO watchdog time

f_LFO

LFO frequency

235.8

262

288.2

35

kHz

µs

Reset digital if LFO is stuck or period is >

than the watchdog timer

t_LFOWDGLFO watchdog time

6.7 Typical Characteristics

图6-1. Typical COMHN and COMHP characteristic

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7 Detailed Description

7.1 Overview

The BQ79600-Q1 is a bridge IC designed to interface between microcontroller (MCU) and TI battery monitoring

ICs (BQ7961X-Q1 family). It translates between daisy chain interface and SPI/UART interface. It is fully

compatible with BQ7961X-Q1 family. When working with BQ7961X-Q1 family, BQ79600-Q1 supports automatic

host wakeup through INH pin when unmask fault is detected in high voltage battery pack. Details can be found in

节 7.3.5 and 节 7.3.4. For convenience of traceability, each device is marked by DIE IDs and PARTID which

could be found in 节7.5 Register Summary Table.

7.2 Functional Block Diagram

BAT

VIO

AVAOREF

REFSYS/

Ping

Detect

AVDDREF

Powermode

Control

INH

CVDD

VIO

DVDD

CVDD

OSC

MOSI/RX

MISO/TX

32MHz

262KHz

DVDD

nCS

SCLK

RX

COMHP

COMHN

COMLP

COMLN

nUART/SPI (SPI_RDY)

TX

Digital

Core

Daisy Chain

NFAULT

TX

RX

GND

图7-1. Functional Block Diagram

7.3 Feature Description

7.3.1 Functional Modes and Power Supply

7.3.1.1 Power Mode

The device has four power modes plus an Complete Off state. The functions supported under each power

modes are summarized in 表7-1 and the power state diagram is shown in 图7-2.

• COMPLETE OFF: The voltage at the BAT pin is less than V_BATmin, and all circuits are powered off.

• SHUTDOWN: The lowest power mode. Without VIO, device can only transition to VALIDATE. (If Sniffer used)

• SLEEP: A low power mode. Transition to ACTIVE is much faster compared to SHUTDOWN.

• ACTIVE: Full power mode. Device can communicate between MCU and daisy chain.

• VALIDATE: This state is to validate if there is real fault tone from stack devices. If fault tone is validated, drive

INH pin towards VBAT (INH pin is latched until cleared by user). Device goes back to SHUTDOWN if

t_{VALID_TIMEOUT}or sleep timer expires. (t_{VALID_TIMEOUT}timer is reset if fault tone is detected, detecting

Heartbeat tone doesn’t reset timer.) This state is bypassed if 节7.3.5 is disabled (by default). Once entered

this state, a status bit [VALIDATE_DET] is set in next ACTIVE such that host knows what happened. Without

VIO, device can only transition to SHUTDOWN. NFAULT pin is low in this mode.

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表7-1. Functions Summary

SHUTDOWN

FUNCTIONAL BLOCK⁽¹⁾

VALIDATE⁽³⁾

SLEEP

ACTIVE

Data Communication RX/TX

Time out

If VIO_UV_R = 1

Comm Timeout

Sleep Timeout

Tone RX (HB/Fault)

Depends on [DIR_SEL] and [TONE_RX_EN]

√

Tone TX (WAKE/ SLP2ACT/

SHUTDOWN/ HWRST) ⁽⁵⁾

√

Tone TX (HB)

Depends on [DIR_SEL]

and [HB_TX_EN]

COM embedded fault

Sniff detector on COM*

[FCOMM_EN] =1

If host enables this

feature ⁽²⁾

Wake/Shutdown Ping

SLP2ACT Ping

NFAULT Driver

LFO

If VIO_UV_R = 1

√

HFO

INH Driver

INH_DIS[1:0] != 2’

Holds State

INH_DIS[1:0] != 2’b11

√

b11⁽⁴⁾

CVDD/DVDD

√

Thermal Shutdown

(1) Once device in SLEEP/ACTIVE, losing VIO doesn’t directly cause change of state, it causes loss of data communication to MCU.

(2) If host writes [SNIFDET_EN] =1 & [SNIFDET_DIS] = 0 in ACTIVE mode, even device shuts down, enable signal is still valid. Sniff

detector is enabled or disabled by a latch powered by always on power supply.

(3) This mode is bypassed if sniff detector is not enabled, see register DEV_CONF1.

(4) INH can only be triggered by [INH_SET_GO] bit in ACTIVE.

(5) Device does not recognize WAKE/ SLP2ACT/ SHUTDOWN/ HWRST tone sent by stack devices.

V_BAT< Min V_BAT

COMPLETE OFF

1. Set CONTROL1[GOTO_SLEEP] = 1, OR

2. Long comm timeout occurs w/

COMM_TIMEOUT[CTL_ACT] = 0

V_BAT< Min V_BAT

V_BAT> Min V_BAT

SLEEP MODE

1. SleeptoActive Ping, OR

2. Receive WAKE Ping

1. Thermal shutdown, OR

2. SHUTDOWN Ping, OR

3. Sleep timer expires

Wake Ping

VALIDATE MODE

(bypassed by default)

ACTIVE MODE

1. Receive WAKE Ping, OR

2. Set CONTROL1[SOFT_RESET] = 1

1. Thermal shutdown, OR

2. SHUTDOWN Ping, OR

SNIFF Det = 1

if enabled

3. t_{VALID_TIMEOUT}

4. Sleep timer expires

Device reset

expires, OR

1. Thermal shutdown, OR

Wake Ping

2. Long comm timeout occurs w/

COMM_TIMEOUT[CTL_ACT] = 1, OR

3. Receive SHUTDOWN Ping, OR

SHUTDOWN MODE

4. Set CONTROL1[GOTO_SHTUTDOWN] = 1

图7-2. Power State Diagram

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7.3.1.2 Pings

A “ping” is a specific signal pattern to change power mode of BQ79600-Q1. There are total of 3 different

pings:

timing follows SPI physical

layer requirement

Hardwired to GND

nCS

RX

MOSI

WAKE Ping high-low-high

t_{HLD_WAKE}

RX

MOSI

SHUTDOWN Ping high-low-high

t_{HLD_SD}

1us: 1Mbps(default)

4us: 250Kbps

SLEEPtoACTIVE Ping high-low

t_StA

SPI mode (see notes below for SCLK control)

t_StA

UART mode

图7-3. Communication Pings

• In SPI mode, ping can be sent without SCLK toggling or host can treat sending a ping like sending a series of

logic ‘0’(drive nCS and SCLK properly, refer to SPI physical layer requirement, 节7.3.2.1.2.2).

• Device does not transmit any tones to stack devices due to the receiving of pings.

• After sending in SHUTDOWN ping, host has to wait t_SHTDNbefore sending another ping.

• If nCS = ‘1’, all of the pings above are ignored by the device.

备注

If device is shut down through SHUTDOWN ping (COMH RX and COML RX are disabled at next

wake up), host needs to send 1^stWAKE ping, wait t_{SU(WAKE_SHUT)}, and then send 2^ndWAKE ping.

表7-2. Device Behavior when SLP2ACT Ping is Sent

UART

SPI WITH SCLK TOGGLING

SPI WITHOUT SCLK TOGGLING

ACTIVE

SLEEP

[COMMCLR_DET]=1, [STOP_DET] =1

[COMCLR_ERR]=1,

[COMMCLR_DET]=0

[FMT_ERR]=1, [COMCLR_ERR]=0,

[COMMCLR_DET]=0

[COMMCLR_DET]=1, [STOP_DET] =0,

transitions to active mode

[COMCLR_ERR]=0,

[COMMCLR_DET]=0, transitions to

active mode

[FMT_ERR]=0, [COMCLR_ERR]=0,

[COMMCLR_DET]=0, transitions to active

mode

7.3.1.3 SPI/UART 选择

通过硬件选择 SPI 或 UART 接口：通过电阻器将 nUART/SPI 引脚连接到 VIO（SPI 接口），或连接到 GND

（UART 接口）。每次从关断模式切换到活动模式时，器件都会确定 UART 或 SPI 模式。在切换到活动模式之

前，所选模式被锁定。VIO 必须高于 V_{VIO_UV_R}。活动模式下，nUART/SPI 引脚用作 SPI_RDY 的输出指示。更

多信息请查阅节7.3.2.1.2.2.1。

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7.3.1.4 Digital Reset

Digital reset is when digital core of the device in reset mode. It is not a power mode. Once device comes out of

digital reset, [DRST] bit is set to '1', registers that are not included in NVM are set to RESET VALUE, registers

included in NVM would be NVM program value. There are several conditions in which the device will go through

a digital reset:

• A WAKE ping is received.

• The CONTROL1 [SOFT_RESET] = 1 command is sent in ACTIVE mode.

• Power supply faults. DVDD UV or CVDD UV is detected.

• A HFO or LFO watchdog fault will reset the digital.

7.3.1.5 Power Mode in BMS System

It is recommended to follow the power state combinations below to save system level power.

表7-3. Power Mode Combination Summary

STACK MONITORING IC

ACTIVE

BQ79600-Q1

ACTIVE

COMMENT

Recommended

SLEEP

SHUTDOWN

Other combinations

Not recommended

7.3.1.6 Power Supply

This section provides an overview of each supplies for both user cases: without using Reverse Wakeup and with

using Reverse Wakeup. See the 节7.3.6 for diagnostic control and fault detection on the power supplies block.

表7-4. Power Supply Summary

NAME

W/O REVERSE WAKEUP USER CASE

W/ REVERSE WAKEUP USER CASE

VIO

BAT

This supply is powered by regulated 3.3V or 5V from SBC (PMIC), it powers UART/SPI interface pins.

This supply is powered by regulated 5V from SBC (PMIC). This supply is powered by unregulated 12V battery.

AVAOREF

AVDDREF

DVDD

This supply is generated from VBAT. It is always on if VBAT exists. It powers REFSYS and Power mode control

block.

This supply is derived from AVAOREF. AVDDREF and AVAOREF are connected by a switch, the switch is open in

SHUTDOWN mode.

This supply is generated by the internal DVDD LDO. It is the supply for the digital circuits. It takes the input voltage

from CVDD and generates a nominal 1.8V. It will not be used to power any external circuit.

CVDD

This supply is powered by regulated 5V from SBC(PMIC). It This supply is generated by the internal CVDD LDO.

is the supply for daisy chain interface.

It is the supply for the daisy chain interface (or vertical

interface, VIF). It takes the input voltage from VBAT

and generates a nominal 5V. It will not be used to

power any external circuit.

7.3.1.7 Shutdown

Power Mode Transition Example

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ACTIVE

Sleep

Transition Transition

ACTIVE

SHUTDOWN

Complete Off

Transition

Min V_BAT

BAT

AVAOREF

VIO_UVZ

VIO ramp time is system dependent and not specified

VIO

t_POR2COMM

AVDDREF

CVDD

DVDD

t_{SU(WAKE_SHUT)}

Communication

Ready

t_SU(SLP2ACT)/

t_{SU(WAKE_SLP)}

t_SLP

e

d

o

g

d

n

o

time

i

p

m

e

E

p

K

v

i

t

e

A

l

c

S

W

A

o

d

t

n

e

n

v

i

o

i

e

c

o

i

t

i

t

i

s

n

s

Re

n

a

r

T

图7-4. Shutdown -> Active -> Sleep -> Active

Transition to Active then to Validate

as a status bit indicates device wakes

up due to SNIF_DET

VALIDATE

SHUTDOWN

ACTIVE

Complete Off

Transition

Min V_BAT

BAT

AVAOREF

VIO

t_{Depend on system}

INH enables PMIC

which enables VIO

t_POR2COMM

AVDDREF

CVDD

DVDD

t_{FTONE_PERIOD}

Fault tones from

stack device

on COMM* pins

t_{VALID_ENTRY}

t_{INH_DLY}

SNIF_DET

(internal signal)

INH

time

图7-5. Shutdown -> Validate -> Active

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7.3.2 Communication

This device is used as a bridge (base) device in daisy chain configuration, as showed in figure below. It

communicates with MCU through UART or SPI and communicates with stack devices through daisy chain

(proprietary interface). MCU always initiates communication with a Command frame. In the system, BQ devices

would never send data back to MCU before MCU requests. And MCU needs to wait all expected response

frames before sending next command frame. Thus, communication scenarios can be put into 2 categories:

• MCU sends Write Command frames to BQ devices. Write Command frames don't incur Response frame.

• MCU sends one Read Command frame to BQ devices and waits till all Response frames are received.

Half-duplex

SPI or UART

(Asynchronous

proprietary protocol )

(Asynchronous

proprietary protocol )

SPI_RDY

SCLK

zCS

BQ79600

(Base Device)

MCU

BQ796XX monitoring IC

(Stack N)

BQ796XX monitoring IC

(Stack 1)

Command Frame

Response Frame

Command Frame

Response Frame

Command Frame

Response Frame

MOSI/RX

MISO/TX

COM

Address N

Address 1

Address 0

Both Command and Response Frames shall

follow the Transaction Frame Structure

图7-6. System Communication Diagram

Rest of the section talks about how data and tone are communicated among host, bridge, and stack devices: 节

7.3.2.1 (节7.3.2.1.1 and 节7.3.2.1.2 protocol), 节7.3.2.2. It also talks about 节7.3.2.3 and 节7.3.2.4.

7.3.2.1 Data Communication Protocol

7.3.2.1.1 Frame Layer

The communication frame is defined in figure below. It is made up of 5 types of information: initialization

character (INIT), device address characters, register address character, data character(s) and CRC characters.

Each character is transmitted at UART/ SPI/ Daisy Chain physical level, whose format is defined in following 节

7.3.2.1.2 section. There are 3 types of transaction frames: Read Command Frames, Write Command Frames

and Response Frames. They follow the structure in the figure below.

INIT [7:0]

DEV ADR [7:0]

REG ADR [15:0]

DATA byte(s)

CRC [15:0]

Frames

Single Device Read

INIT

Always 0x80

DEV ADR REG ADR

Y

DATA

# of byte requested (max value

127, meaning 128)

CRC

Y

Read

Command

Frame

Y

Stack Read

Always 0xA0

Always 0xC0

Y

N

Y

N

Y

Broadcast Read

Single Device Write

Stack Write

Y

Write

Command

Frame

Actual payload (1-8 bytes)

Y

Broadcast Write

Reverse ⁽⁵⁾

Y

Y⁽⁵⁾

Y

Y⁽⁵⁾

Response Frame

Y

Actual payload (1-128 bytes)

Y

图7-7. Command/Response Frame Structure

Notes:

• When BQ79600-Q1 is used as bridge device, to read BQ devices information, host SHALL NOT use

Broadcast Read command but only Single Device Read or Stack Read. The reason is BQ79600-Q1 register

address does not overlap with stack devices, it would only return 0x00 to Broadcast Read command.

• For Stack Read command, the response is broken into individual response frames from each device

addressed. Each device (address N) in the stack waits until the device above it (address N+1) responds

before device N sends its own data back.

• After a read command frame is transmitted, the host must wait for all expected responses to return (or

timeout: t_{WAIT_READ_MAX}) before initiating a new command frame.

• A response frame is not mandatary. A response frame is only received after a read command frame.

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• Broadcast Write Reverse command frame should only be used to config [DIR_SEL] bit, not for any other

purposes. INIT byte is 0xE0, Reg address byte is 0x309 (BQ7961X-Q1), data byte is 0x80.

• Bytes received on COMH/COML are NOT propagated up to the stack; while bytes received on the SPI/UART

are propagated to COMH or COML depending on [DIR_SEL].

• Even if there is a byte error, data is still forwarded from VIF to SPI (buffer)/UART; if there is a byte error, data

doesn’t forward from SPI/UART to VIF.

Command Frame

Description

Response Frame

Description

Command/Response Frame

Description

Bit

Bit Name

Bit

7

Bit Name

RSVD

7

FRAME_TYPE

1 = Command Frame

FRAME_TYPE

0 = Response

Frame

Should always write —0“

6

Should always write —0“

Set the device address range from

0x00 to 0x3F

6

5

REQ_TYPE

000 = Single Device Read

001 = Single Device Write

010 = Stack Read

RESPONSE_BYTE

Number of the data

bytes

5:0 Device Address

011 = Stack Write

0x00 = 1 byte

0x01 = 2 bytes

:

Command/Response Frame

Description

100 = Broadcast Read

101 = Broadcast Write

110 = Broadcast Write Reverse

111 = RSVD ⁽¹⁾

4

Bit

7:0 Register

Address (MSB)

7:0 Register

Address (LSB)

Bit Name

0x7F = 128 bytes

Target or beginning of the register

address

3

2

1

0

RSVD

RSVD. This bit is ignored

Target or beginning of the register

address

DATA_SIZE

Number of data bytes, excluding

device address, register

address or CRC

Bit

7:0 Data Byte[0]

……

7:0 Data Byte [n]

Bit Name

Description

Data Byte[0]

……

000 = 1 byte

001 = 2 bytes

:

…

Data Byte[n]

111 = 8 bytes

Command/Response Frame

Bit

Bit Name

Description

7:0 CRC (MSB)

CRC-16-IBM polynomial (x16

+ x15 + x2 + 1 or

11000000000000101)

with 0xFFFF initialization

CRC-16-IBM polynomial (x16

+ x15 + x2 + 1 or

7:0 CRC (LSB)

11000000000000101)

with 0xFFFF initialization

图7-8. Frame Byte Definition

Notes:

• INIT character: (1) No function to this selection, but this selection sets the [RC_IERR] error flag.

• Device Address character: Bit 6 and 7 are reserved; 0x4F to 0xFF is decoded as 0x3F by device.

• Register Address characters: Register addresses are two bytes in length. They indicate the targeted register

address on a single byte read/write, or the beginning of the register address on a multi-byte read/write. If an

invalid register address is set on a write command, the command will be ignored. If an invalid register

address is set on a read command, a 0x00 will be returned as response.

• Data characters can be:

– Single data byte, it represents number of registers requested in Read Command Frame. The BQ79600-

Q1 supports up to 128 byte reads. The valid data byte for read command frame is 0b0000000 -

0b1111111. The MSB of the data byte is ignored for read command frames. For example, 0b10011001 is

read as 0b00011001 and returns data from 26 registers.

– Actual payload in Write Command Frame (max 8 byte) or Response Frame (max 128 byte).

• CRC characters:

– The CRC value is checked as the first step (assume no physical layer error, no [RC_IERR], no [RC_SOF],

no [RC_BYTE_ERR]) after receiving the communication frame. If the CRC is incorrect, the entire frame is

discarded and not processed. Any additional frame errors are not checked.

– The frame with CRC error is still transferred up/down the stack. Every device processing this frame will

also detect a CRC error. Hence, it is possible to have multiple devices indicating CRC fault on the same

communication frame. If a CRC error occurs in the response frame from address N+1, device N does

NOT append its own message and an invalid CRC fault is generated. For example, if device 15 finds

response frame from device 16 has invalid CRC, device 15 doesn’t send its own response frame.

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– The device uses a CRC (cyclic redundancy check) to protect data integrity during transmission. The

device uses the CRC-16-IBM polynomial (x¹⁶+ x¹⁵+ x²+ 1 ) with 0xFFFF initialization.

7.3.2.1.1.1 Calculating Frame CRC Value

The CRC calculation by the transmitter is in bit-stream order across the entire transmission frame (except for the

CRC). When determining bit-stream order for implementing the CRC algorithm, it is important to note that

protocol bytes transmit serially, least-significant bit first. 图7-9 illustrates the bit-stream order concept.

图7-9. Bit-Stream Order Explanation

The CRC (0x0000) is appended to the end of the bit-stream. This bit-stream is then initialized by XOR'ing with

0xFFFF to catch any leading 0 errors. This new bit-stream is then divided by the polynomial (0xC002) until only

the 2-byte CRC remains. During this process, the most significant 17 bits of the bit stream are XOR’d with the

polynomial. The leading zeroes of the result are removed and that result is XOR’d with the polynomial once

again. The process is repeated until only the 2-byte CRC remains. For example:

Example 1: CRC Calculation Using Polynomial Division

Command Frame = 0x80 00 02 0F 0B (0b1000 0000 0000 0000 0000 0010 0000 1111 0000 1011)

Command Frame in bit stream order

1101 0000)

= 0x01 00 40 F0 D0 (0b0000 0001 0000 0000 0100 0000 1111 0000

After Initialization (XOR with 0xFFFF) = 0b1111 1110 1111 1111 0100 0000 1111 0000 1101 0000

1111 1110 1111 1111 0100 0000 1111 0000 1101 0000 0000 0000 0000 0000 #append 0x0000 for CRC

1100 0000 0000 0010 1 #XOR with polynomial

0011 1110 1111 1101 1100 0000 1111 0000 1101 0000 0000 0000 0000 0000

11 1110 1111 1101 1100 0000 1111 0000 1101 0000 0000 0000 0000 0000 #delete leading zeros from

previous result

11 0000 0000 0000 101 #XOR with polynomial

00 1110 1111 1101 0110 0000 1111 0000 1101 0000

……

1100 0110 0000 0001 0000 0000

1100 0000 0000 0010 1 #XOR with polynomial

0000 0110 0000 0011 1000 0000

110 0000 0011 1000 0000

110 0000 0000 0001 01 #XOR with polynomial

000 0000 0011 1001 0100

0000 0011 1001 0100 #CRC result in bit stream order

1100 0000 0010 1001 #final CRC result in normal order

CRC final 0xC029

7.3.2.1.1.2 Verifying Frame CRC

There are several methods for checking the CRC of a frame. One method is to simply calculate the CRC for the

transmitted command except the last two bytes (CRC bytes) using the method described in the previous section,

and then compare that result with the transmitted CRC bytes. A more simple option is to run the entire

transmission through the CRC algorithm. If the CRC is correct, the result is 0000. In this case, the initial zero

padding of the bit-stream with 16 zeroes is not necessary. Using the previous result and running through the

algorithm produces the following results:

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Example 1: CRC Verification Using Polynomial Division:

Command Frame = 0x80 00 02 0F 0B (0b1000 0000 0000 0000 0000 0010 0000 1111 0000 1011)

CRC to Check = 0xC029

Command Frame w/ CRC in bit stream order = 0x80 00 02 0F 0B C0 29 (0b1000 0000 0000 0000 0000 0010

0000 1111 0000 1011 0000 0011 1001 0100)

After Initialization (XOR with 0xFFFF) = 0b0 1111 1110 1111 1111 0100 0000 1111 0000 1101 0000 0000

0011 1001 0100

1111 1110 1111 1111 0100 0000 1111 0000 1101 0000 0000 0011 1001 010 #delete leading zeros from

previous result

1100 0000 0000 0010 1 #XOR with polynomial

0011 1110 1111 1101 1100 0000 1111 0000 1101 0000 0000 0011 1001 0100

11 1110 1111 1101 1100 0000 1111 0000 1101 0000 0000 0011 1001 0100 #delete leading zeros from

previous result

11 0000 0000 0000 101 #XOR with polynomial

00 1110 1111 1101 0110 0000 1111 0000 1101 0000 0000 0011 1001 0100

……

1100 0110 0000 0010 1001 0100

1100 0000 0000 0010 1 #XOR with polynomial

0000 0110 0000 0000 0001 0100

1 1000 0000 0000 0101 00

1 1000 0000 0000 0101 #XOR with polynomial

0 0000 0000 0000 0000 00

0x0000 #verfiy that CRC checks out valid

备注

The result of ‘0b0000 0000 0000 0000’for the CRC indicates a successful check.

7.3.2.1.2 Physical Layer

7.3.2.1.2.1 UART

Communication between host and BQ79600-Q1 can be configured to UART mode, refer to 节 7.3.1.3. The

UART interface baud rate is default to 1Mbps at power up or digital reset. The UART interface follows the

standard serial protocol of 8-N-1 (see 图7-10), where it sends information as a START bit, followed by eight data

bits, and then one STOP bit. The STOP bit indicates the end of the byte. The protocol also supports two STOP

bits. When the device is configured as 2 stop bits ([TWO_STOP_EN] = 1, stack devices should also be set as

two stop bits), the UART response frame from the device to MCU will always return with 2 stop bits.

The UART sends data on the TX pin and receives data on the RX pin. When idle, the TX and RX are high. TX is

always pulled to VIO internally while in ACTIVE or SLEEP mode, whether enabled or disabled.

The UART interface is strictly a half-duplex interface. While transmitting, any attempted communication on RX is

ignored. The only exception is 节7.3.2.1.2.1.2.

1 or 2 bit

period

LSB

bit period = 1/ baud rate

MSB

. . .

START

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

STOP

Start is

ꢀoÁꢀÇ• Z0[

Stop is

ꢀoÁꢀÇ• Z1[

图7-10. UART Character Definition

Note: User can change baud rate using register bit [UART_VIF_BAUD] for debug purpose.

7.3.2.1.2.1.1 TX HOLD OFF

UART transmitter is configurable to wait a specified number of bit periods after the last bit reception of Single

Device read command frame from host before starting transmitting Response Frame using the TX_HOLD_OFF

register, as showed in 图 7-11. This provides time for the host to switch the bus direction at the end of its

transmission.

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备注

Host does not need to configure register TX_HOLD_OFF in BQ79600-Q1 if Stack Read command is

used. Host shall not use Broadcast Read Command.

Single Device Read

Command frame

TX_HOLD_OFF

Response frame

Last bit of the command

received at RX pin

1^stbit of the response

frame sent on TX pin

Time

图7-11. TX HOLD OFF Timing Diagram

7.3.2.1.2.1.2 UART COMM CLEAR

备注

Comm Clear concept only applies to bridge device not stack device.

Comm Clear command is used to clear the receiver and instruct it to look for a new start of frame. (Resync up

with host) The next byte following the Comm Clear is considered a "start of frame" byte. The digital receiver

continuously monitors the RX line for Comm Clear condition which is RX pin is held low for tUART (CLR) bit

periods, showed in 图7-12.

When Comm Clear is detected, FAULT_COMM1 [COMMCLR_DET] and FAULT_COMM1 [STOP_DET] are set.

[STOP_DET] flag is set because the Comm Clear timing violates the typical byte timing and the STOP bit is seen

as '0'. The only exception to this is when a COMM CLEAR is sent while BQ79600-Q1 is in sleep. If this is the

case, there is no STOP error flag.

1 bit period

RX pin

Command frame

t_UART(CLR)

t_{UART(RX_HIGH)}

图7-12. Comm Clear Timing

7.3.2.1.2.2 SPI

备注

为支持菊花链（异步协议）和SPI（同步协议）之间的通信，BQ79600-Q1 需要使用节7.3.2.1.2.2.1。

主机与 BQ79600-Q1 之间的通信可配置为 SPI 模式。请参阅节 7.3.1.3。主机始终是 SPI 主设备，而 BQ79600-

Q1 始终是从设备。在物理层，SPI 是一个五引脚接口，包括4 个通用引脚（nCS、SCLK、MOSI 和MISO）以及

SPI_RDY。在 SPI 接口上，每个位在时钟从低电平到高电平转换时被捕捉，在时钟从高电平到低电平转换时被传

输，一个字节包括 8 位，如图 7-13 所示。请注意，MISO 在空闲模式下被驱动为高电平。如果 MCU 与多个从器

件通信，请在BQ79600 MISO 和MCU 之间添加一个三态缓冲器。

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t₉

t₁₀

t₁₁

nCS

t_{SPI_CLK}

t_{SPI_CLKL}

SCLK

t_{SPI_CLKH}

t_SU

t_H

Hi or Low

LSB_n

MSB_n

MOSI

MISO

t₁₄

t₁₂

t₁₃

LSB_n

MSB_n+1

t>0

SPI_RDY

SPI_RDY high indicates host

can read/write predefined

number of bytes

SPI_RDY may go low (and it is ok)

before finish read/write this batch

One Byte

Bit 0

Bit 7

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LSB

Bit 7

bit period = t_{SPI_CLK}

图7-13. SPI 时序和字节定义

备注

虽然SPI 接口在物理层是全双工的，但在帧层，它实际上是半双工，因为菊花链仅支持半双工。这意味

着在给定的时间，MCU 和器件之间只传输一个命令帧或响应帧。

• 当命令从MCU 发送到器件时，BQ79600 TX FIFO（2 个缓冲器）应为空，0xFF 发送到MCU

（FIFO 诊断模式下除外）。

• 当响应从器件发送到MCU 时，MCU 应在0xFF 中计时

• 主机应在2MHz 至6MHz 范围内提供SPI 时钟。此范围由FIFO 的预定义大小确定。即使SPI 能够以6MHz

频率运行，它也不会增加整个系统的吞吐量，因为菊花链速度仍会限制吞吐量。

• 为避免菊花链接口上的冲突，MCU 必须等到接收到所有预期的响应帧（或等待计时器到期）后再向BQ79600

发送另一个命令帧。请参阅图7-16 中的流程图。

• 当不向器件发送命令帧时，主器件应始终将MOSI 驱动为‘1’。

• 主机读取模式：从主机角度来看，读取模式介于有效读取命令的第一个字节和接收到的最后一个预期字节之

间。

• 器件读取模式：从有效读取命令的第一个字节开始，当TX FIFO 超时且FIFO 为空时，器件为读取模式。器件

读取模式是主机读取模式的子集。（用于理解通信故障寄存器0x2301 和0x2302 的概念）

• 除Comm Clear 外，器件在退出器件读取模式之前拒绝来自MOSI 的任何数据。

• TX FIFO 超时后，SPI 模块拒绝来自菊花链（堆栈器件）或自身的任何数据List item.referenceTitle，直到再次

进入器件读取模式。

• 对于命令帧，器件使用nCS 的下降沿指示帧开始，上升沿指示帧结束。MCU 需要在整个帧（最多14 个字

符）内切换并保持nCS 处于低电平，在该帧结束时将nCS 切换回高电平。当nCS 为低电平时，冻结SCLK

是合法的。不支持命令帧中间的nCS 脉冲。

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• 对于响应帧，nCS 无需始终保持低电平，尽管它可以像发送命令帧一样。主机可以将nCS 切换为高电平，在

帧中间（字节边界处）停止SPI 读取。

nCS

IDLE

frame A

IDLE

frame B

IDLE

frame C

IDLE

Data

Supported in command frame and response frame

nCS

IDLE

1^sthalf of frame A

IDLE

2^ndhalf of frame A

IDLE

Data

Only Supported in response frame

图7-14. 发送帧时的nCS 行为

7.3.2.1.2.2.1 SPI_RDY 和SPI FIFO

SPI_RDY 是一个输出信号，指示主机数据已准备好进行通信。SPI FIFO 图7-15 是器件中用于临时存储传入/传出

数据的缓冲器。需要它们的原因如下：

• 菊花链波特率默认约为1Mbps，一旦主机请求大量数据，例如400 字节，器件的菊花链接收器会尝试将其发

送回主机，但由于器件不具有SCLK，无法控制何时读取数据。因此，当主机未读取数据时，器件需要将传入

的数据存储在TX FIFO 中。即使主机正在读取数据，仍需要FIFO 来处理SPI 和菊花链之间的波特率差异。

• 由于TX FIFO 的深度有限，因此需要SPI_RDY。如果主机请求的数据超过256 字节，而主机未及时为器件提

供服务（读出数据），则会发生数据溢出。SPI_RDY 指示主机已准备好读取或写入一定数量的数据，例如，

如果主机请求129 字节，SPI_RDY 第一次会标记128 字节就绪，第二次标记1 个字节就绪。有关详细信息，

请参阅表7-5。

COMH/COML Pins

Aprox. 1Mbps

Asynchronous

Daisy Chain Transceiver

Aprox. 1Mbps

Asynchronous

Aprox. 1Mbps

Asynchronous

Ping Buffer

128 bytes

Pong Buffer

128 bytes

32 bytes

RX FIFO

TX FIFO

BQ79600-Q1

For simplicity, the drawing only shows

dataflow from/to stack devices, it

ꢀ}ꢁ•v[š •Z}Á šZꢁ ꢀꢂšꢂ(o}Á }( Œꢁꢂꢀ (Œ}u/

write to BQ79600 itself.

SCLK: 2MHz -

6MHz

MOSI

MISO

图7-15. SPI FIFO 简化图

TX FIFO 包含两个128 字节缓冲器（一起用作乒乓缓冲器）。

1. Ping 缓冲器填满时，Pong 缓冲器应为空，以便存储传入的数据。

2. 填写Pong 缓冲器时，正在读取Ping 缓冲器。一旦被读取，缓冲器中的每个字节被复位为0xFF。在Pong 缓

冲器填满之前，Ping 缓冲器应为空（读出）。

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3. Pong 缓冲器填满后，Ping 缓冲器会接替上来。

4. 器件执行此循环（步骤1 至3），直到接收到所有响应数据。

5. 主机必须以足够快的速度读取TX FIFO，以便在Pong (Ping) 缓冲器写满之前读取Ping (Pong) 缓冲器并准备

好存储来自菊花链的数据。

表7-5. SPI_RDY 行为总结

案例编

号

高-> 低

a

低-> 高

b

主机写

入

1

2

当RX FIFO >= 16 字节时，在2μs 内。

在器件接收到读取命令帧的第1 个字节后5μs 内。

当RX FIFO < 8 个字节时，在a1 事件后2μs 内。

Ping (pong) 缓冲器填满后1us 内。

发生TX FIFO 超时

正在读取的TX 缓冲器变为空（在向外传输缓冲器中最后一个字节

主机读

取

注意：当SPI_RDY 为高电平时（主机正在读取TX

FIFO 时），可能会发生TX FIFO 超时。在这种情况

下，在事件a3 之后，SPI_RDY 会保持低电平大约

2μs，然后恢复为高电平。

的最后一位之前）

注意：一旦变为低电平，SPI_RDY 无论如何都会保持低电平

2μs。

3

注：

• SPI_RDY 仅设置标志，不控制数据流入或流出设备。

• 一旦进入设备读取模式，设备将拒绝来自主机的COMM CLEAR 以外的任何数据，a1 和b1 不再适用。

• TX FIFO 超时：SPI 模块从菊花链或BQ79600-Q1 本地接收到一个字节的数据后，计时器启动；如果30μs

内没有收到数据，则该计时器超时。

7.3.2.1.2.2.2 Flow to Read/Write BQ79600-Q1

User shall follow flow chart 图7-16 to do read from device and 图7-17 to do write to device activities.

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Device

Initialization

Start

NO

SPI_RDY = Z1[?

delay

YES

Drop nCS, Send one Single Device Read or Stack Read

Command frame, raise nCS @2-6Mbps;

M = expected total Response bytes,

i = int(M/128), K = M- i*128;

NO

YES

NO

Wait

t<= t₈

Total wait time >

t_{WAIT_READ_MAX}

Comm Clear,

Reread

SPI_RDY = Z1[?

?

YES

Drop nCS, Read K

bytes, raise nCS

i > 0?

YES

Host reads

expected # of

valid data

YES

Finish

Reading

Drop nCS, Read 128 bytes then

stop (stop SCLK, raise nCS high),

i = i -1;

NO

Comm Clear

图7-16. Flow Chart to Read from Device

备注

MCU shall check SPI_RDY pin at least every t8 (max service interval). t8 = 1ms at SCLK = 6MHz /

890μs at SCLK = 4MHz /550μs at SCLK = 2MHz assuming host starts to read TX FIFO right after

detecting SPI_RDY = '1 and SPI bus has 30% idle time in the process of reading 128 bytes.

• For response frame, nCS has to be toggled high after reading the last byte of data in the current buffer.

• t_{WAIT_READ_MAX}

– stack read/single device read from stack devices, with n stack devices, request m bytes in total (payload +

overheads, from all stack devices), wait time: (n-1)*3μs*2 + m*10μs + 100μs.

– single device read from BQ79600-Q1, request m bytes , wait time: 100μs + m*10μs.

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Start

NO

YES

NO

Total wait time >

250us?

SPI_RDY = Z1[?

Wait t

SPI_RDY = Z1[?

Comm Clear

YES

Toggle nCS low, Send 1 Write

Command frame (up to 14

bytes) @SCLK 2Mhz-6MHz,

toggle nCS high

NO

YES

More Write cmd

to send?

End

图7-17. Flow Chart to Send Write Command Frame to Device

Notes:

• Since write command frame doesn’t incur response frames, host shall discard data from MISO pin.

• If host sends partial data, the device would keep waiting the rest of command data till communication time out

happens. Refer to 节7.3.2.4 for details.

7.3.2.1.2.2.3 SPI COMM CLEAR

备注

SPI Comm Clear 命令仅适用于桥接器件，用于清除FIFO 并复位SPI 模块。

它使 BQ79600-Q1 停止发送响应；它无法停止堆栈器件向 BQ79600-Q1 发送响应数据。如果主机仍然无法与器

件通信，主机最终可以使用 SHUTDOWN ping，然后使用 WAKE ping 重启器件。器件在 ACTIVE 状态下仅响应

Comm Clear 命令。在以下情况下使用SPI Comm Clear 命令：

• SPI_RDY 为低电平超过预期时间，即READ 模式中的t_{SPI_RD_WAIT_MAX}(图7-16)，而在将写命令帧发送到器

件时为220μs。请勿在此等待时间结束前发送Comm Clear 命令。

• 主机读回的数据有CRC 错误。

• 主机无法与器件通信。

nCS

t₉

t₁₀

8 clk cycles

SCLK

t_SU

t_H

MOSI pin

Hi or Low

COMM CLEAR

图7-18. SPI Comm Clear

SPI Comm Clear 被严格定义为 nCS 切换至低电平，8 位 ‘0’，nCS 切换至高电平如图 7-18 所示。nCS 在发

送 Comm Clear 时必须保持低电平。如果在 nCS 变为高电平之前在 MOSI 引脚上检测到其他数据，则设置

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[COMCLR_ERR] 位，器件将忽略格式错误的 Comm Clear 。格式正确的 Comm Clear 仅触发

[COMMCLR_DET]。如果使用 Comm Clear，可以触发 DEBUG_SPI_FRAME [TR_SOF]（发送本地数据时）、

[RC_SOF]（接收部分数据）和[TS_WAIT]（发送菊花链数据时）。

7.3.2.1.2.3 Daisy Chain

Daisy chain is the interface (COMH/COML) communicating to stack devices. It is bi-directional and half duplex,

and, therefore, has a transmitter (TX) and receiver (RX) on both COMH and COML interfaces, 图 7-1. Signal

going in and out of daisy chain port is taken care by the device. To use the device, host does not need to know

daisy chain physical layer protocol (bit definition, byte definition and byte transferring). Host just needs to control

SPI or UART port properly. Still, for user's information, daisy chain physical layer protocol is described below.

Daisy chain bit is transmitted between COM*P and COM*N in fully differential fashion, see 图7-19.

Daisy chain byte uses an asynchronous 13-bit byte-transfer protocol. The definition of each bit in the byte is

defined in 表7-6. Byte to byte transmission is captured in 图7-20.

Z1[

Z0[

COM*P

COM*N

2 x t_{PW_DC}

t_{PW_DC}

COM*P t COMP*N

t_{PW_DC}

图7-19. Daisy Chain Bit Definition

SYNC [1:0]

DATA[7:0]

+1

COM*P t COMP*N

-1

D7

D4

D6

D1

D3

D5

D0

D2

SYNC = 2'b00

1.375us of bus idle

0.5us of bus short

6.5us nominal

Daisy Chain Byte Definition

Up to 8.375us for a byte

Byte

10.875us at 1Mbps, 40.6us at 250Kbps

Daisy Chain Byte Transfer

图7-20. Daisy Chain Byte/ Byte Transfer Definition

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表7-6. Daisy Chain Byte Definition

BIT NAME

DESCRIPTION

Preamble (half-bit)

Indicates a start of byte transaction, signaling the receiver to start sampling. This half-bit and the following 2

SYNC bits are used for extra timing information.

SYNC[1:0]

Always 0b00. The SYNC bits are used for the digital to assess the timing and noise level on the byte, improving

the detection of a '1' and '0' in a noisy environment.

Start-Of-Frame (1-bit)

The Start-Of-Frame (SOF) bit defines the byte as the INIT byte (initialization byte) in the frame, refer to 图7-8.

Stack device needs this information in order to process the communication.

Data[7:0]

The actual 8-bit payload.

Byte Error BERR (1-bit)

For BQ79600-Q1, BERR is always ‘0’in command frames sent to stack device. While in received response

frames, if it is ‘1’, it indicates last device DEBUG_COM*_PHY[PERR] = 1.

Postamble (half-bit)

Indicates the end of byte transaction.

7.3.2.2 Tone Communication Protocol

Other than data, certain information is transmitted using tone: signals to change power state of stack device

(SLP2ACT tone, WAKE tone, SHUTDOWN tone, HWRST tone), signals related to faults (FAULT tone and

HEARTBEAT tone). The definition of each tone is defined in 图7-22 and 图7-21.

Device can transmit and receive tones in summary below:

表7-7. Available Tones to BQ79600-Q1

DIRECTION

NAME

Receive

Transmit

FAULT tone and HEARTBEAT tone

SLP2ACT tone, WAKE tone, SHUTDOWN tone, HWRST tone, HEARTBEAT tone

Note:

• Device does not transmit Fault Tone as it uses 节7.3.3.2.1 to signal fault if enabled.

• SLP2ACT/WAKE/SHUTDOWN/HWRST tone transmitting is on demand when corresponding bit in register

CONTROL1 and CONTROL2 is set.

• When bridge device in SHUTDOWN, wakeup bridge device doesn’t change power mode of stack devices.

• Receiving threshold value is defined as n_HBDET, n_FTONEDETin section 6.6.

• Transmitting number is predefined by device in 表7-8.

表7-8. Transmitting Tones Summary Table

SLP2ACT

WAKE

SHUTDOWN

HWRST

HEARTBEAT (SLEEP only)

N of Couplets Transmitted in

Single Burst

30

90

270

NA

810

30

Burst Period

NA

400ms

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COM*P

COM*N

VDCCM

t_{FLTTONE_PLS}

t_FLTTONE

COM*P t COMP*N

t_{FLTTONE_PLS}

A pulse

One Burst

(N of couplets)

One Burst

(N of couplets)

t_{HB_PERIOD}or t_{FTONE_PERIOD}

图7-21. FAULT Tone and HEARTBEAT Tone Definition

COM*P

COM*N

COM*P

COM*N

VDCCM

t_{COMTONE_PLS}

t_COMTONE

COM*P t COMP*N

t_{COMTONE_PLS}

COM*P t COMP*N

t_{COMTONE_PLS}

(N of couplets)

SHUTDOWN, HEARTBEAT, HWRST Tone

(N of couplets)

WAKE, SLP2ACT Tone

图7-22. SHUTDOWN, HEARTBEAT, HWRST, SLP2ACT Tone Definition

7.3.2.3 Device Auto Addressing / Ring Communication

备注

The host starts communication at least 100µs after changing the [DIR_SEL] setting to ensure the

device finishes the COMH/COML reconfiguration.

7.3.2.3.1 Auto-Addressing

To properly communicate to every device in daisy chain, host has to assign a unique device address to every

device. This process is called Auto-addressing. This step is required every time devices come out of

SHUTDOWN or digital reset. 表 7-9 describes a procedure to bring up a system of 1 bridge device and 3 stack

devices from SHUTDOWN to a state ready to do read/write communication.

• All device addresses must be sequential

表7-9. Auto-Addressing with Figure 7-22(a), assume all devices are in SHUTDOWN

STEP

WORK WITH BQ7961X-Q1

1

2

3

4

send WAKE ping on RX (wakeup BQ79600-Q1)

single device write to BQ79600-Q1 CONTROL1 [SEND_WAKE] = 1 (wake up stack devices)

dummy stack write data 0x00 to register 0x343 to 0x34A (sync up internal DLL). These are 8 separate write commands.

brdcast write 0x01 to address 0x309 (enable auto addressing)

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表7-9. Auto-Addressing with Figure 7-22(a), assume all devices are in SHUTDOWN (continued)

STEP

WORK WITH BQ7961X-Q1

5

6

7

brdcast write consecutively to 0x306 = 0,1,2,3 (address 1-3 assigned to BQ7961X-Q1, 0 assigned to BQ79600-Q1)

brdcast write 0x02 to address 0x308 (set BQ7961X-Q1 as stack device )

single device write to device 3: data 0x03 to address 0x308 (set 3rd BQ7961X-Q1 as top of stack, BQ79600-Q1 is default to

base)

8

9

dummy stack read registers 0x343 to 0x34A (sync up internal DLL). These are 8 separate read commands.

stack read address 0x306 (read back to verify address are correct for stack devices)

single device read to BQ79600-Q1, verify 0x2001 = 0x14

10

11

finish initialization

7.3.2.3.2 Ring Communication (optional)

A ring communication (optional) allows the system to establish communication from either direction. This allows

the system to continue communicating to all stack devices even if one piece of daisy chain cable is broken.

表 7-10 describes a procedure auto address 图 7-23(b): to bring up a system of 1 bridge device and 3 stack

devices from SHUTDOWN to a state ready to do read/write communication in reverse direction.

To change communication direction from 图7-23(a) to 图7-23(b), follow the steps 2, 4-14. (Assuming all devices

in (a) are already in ACTIVE and auto addressed as described in 表7-9)

COMH

bq Monitoring IC

(Top Of Stack)

(S1)

COML

COMH

bq Monitoring IC

(S2)

COML

COMH

bq Monitoring IC

(Top of Stack)

bq Monitoring IC

(S1)

COML

COMH

bq79600

(Base, B0)

bq79600

(Base, B0)

MCU

COML

a). [DIR_SEL] = 0: Command from

COMH -> COML)

b). [DIR_SEL] = 1: Command from

COML -> COMH)

图7-23. Example to Change Communication Direction in Daisy Chain

表7-10. Auto-Addressing Figure 7-22(b), assume all devices are in SHUTDOWN

WORK WITH BQ7961X-Q1

STEP

1

2

3

4

5

6

7

8

send WAKE ping on RX (wakeup BQ79600-Q1)

single device write to BQ79600-Q1 control 1 [DIR_SEL] = 1 (change BQ79600-Q1 direction)

single device write to BQ79600-Q1 CONTROL1 [SEND_WAKE] = 1 (wake up stack devices)

dummy stack write data 0x00 to registers 0x343 to 0x34A (sync up internal DLL). These are 8 separate write commands.

brdcast write reverse 0x80 to address 0x309 (change stack devices direction DIR_SEL =1)

brdcast Write 0x02 to address 0x308⁽¹⁾

brdcast Write 0x81 to address 0x309 (enable BQ7961X-Q1 auto addressing)

brdcast Write consecutively to address 0x307 = 0,1,2,3 (address 1-3 assigned to BQ7961X-Q1, 0 assigned to BQ79600-Q1)

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表7-10. Auto-Addressing Figure 7-22(b), assume all devices are in SHUTDOWN (continued)

WORK WITH BQ7961X-Q1

STEP

9

brdcast write 0x02 to address 0x308 (set BQ7961X-Q1 as stack device )

10

single device write to device 3: data 0x03 to address 0x308 (set 3rd BQ7961X-Q1 as top of stack, BQ79600-Q1 is default to

base)

11

12

13

14

dummy stack read registers 0x343 to 0x34A (sync up internal DLL). These are 8 separate read commands.

stack read address 0x307 (read back to verify address are correct for stack device)

single device read to BQ79600-Q1, verify 0x2001 = 0x14

finish initialization

(1) Clear the previous TOP_STACK flag after communication direction is changed because top of stack device cannot be reached if one

cable is broken

7.3.2.4 Communication Timeout

In ACTIVE, there are two programmable communication timeout timers, comm timeout short (once expires,

flag fault) and comm timeout long (once expired, transition to SLEEP or SHUTDOWN). They monitor the

absence of a valid frame from either UART/SPI or daisy chain communications. A valid frame is defined as any

frame (response or command) that does NOT contain any errors that prevent the frame from being processed.

In SHUTDOWN, the timers are disabled and reset. In SLEEP, the last timer values are held frozen. The timer is

reset every time a valid response or command frame is received.

How to set the timer, timer expiration action are described in COMM_TIMEOUT. In order to avoid entering

SHUTDOWN mode before a communications timeout fault, ensure the COMM_TIMEOUT [CTS_TIME] is shorter

than the COMM_TIMEOUT [CTL_TIME].

7.3.2.5 Communication Debug Mode

The device provides a communication debug mode to ease the initial development phase. Enter/exit debug is

controlled by setting of register DEBUG_CTRL_UNLOCK. Once device is in debug mode, user is able to control

the UART/daisy chain baud rate and on/off of COMH/COML RX/TX. Please refer to register

DEBUG_COMM_CTRL. User can always read DEBUG_COMM_STAT register for comm status disregard the

setting/mode of device.

In addition to that, device provides communication low level faults (physical and frame layer)to facilitate debug.

Refer to registers from address 0x2301 –0x2307.

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7.3.3 Fault Handling

7.3.3.1 Fault Status Hierarchy/Reset/Mask

7.3.3.1.1 Fault Status Hierarchy

BQ79600-Q1 reports faults in hierarchy, as shown in 图7-24:

• Level 1 is FAULT_SUMMARY register in which each bit represents an OR function of all the bits in its own

hierarchy captured in level 2.

• Level 2 bit is the OR function of level 3 bits in its own hierarchy.

• Level 3 contains debug register bits meant to inform host frame and physical layer fault. Level 3 fault is useful

in firmware development.

• Any bit triggered in lower level would trigger higher level bit in its hierarchy, e.g. if [TXFIFO_OV] is set,

[SPI_PHY], [FAULT_COMM] would also be set.

备注

Host system can periodically poll the FAULT_SUMMARY to check the fault status and only read the

lower level fault registers if needed.

7.3.3.1.2 Fault Reset and Mask

Once fault is detected, the fault status bit is latched until cleared using the reset bit.

When a specific fault reset bit is set, the same color coded bits in level 1 to level 3 are cleared if the fault

condition is gone. If the fault condition persists and the reset bit is written, the fault status bit is not reset. For

example, if [TXFIFO_OV], [DVDD_OV] bits are set, [SPI_PHY], [FAULT_COMM] and [FAULT_PWR] are set, if

fault conditions are eliminated and write '1' to [RST_UART_SPI] and [RST_PWR], 5 faults bits would be '0'.

When a specific fault mask bit is set, the same color coded bits would be masked, meaning the fault bits will still

be set, but the faults will not be reflected in level 1, FAULT_SUMMARY register. For example, if

[MSK_UART_SPI] = 1, any bits being set marked green in level 2 and 3 won't set [FAULT_COMM] bit.

When fault is masked, it will also prevent the device from asserting the NFAULT pin when the masked faults

occur. See 节7.3.3.2 for details.

MASK/RST

MSK_REG

RST_REG

MSK_SYS

RST_SYS

MSK_PWR

RST_PWR

Mask

Reset

Bit

MSK_COML_H MSK_UART_SPI MSK_FCOMM_DET MSK_FTONE_DET MSK_HB

RST_COML_H RST_UART_SPI RST_FCOMM_DET RST_FTONE_DET RST_HB

Fault Status

Level 1

Bit

FAULT_COMM

FAULT_REG

FAULT_SYS

FAULT_PWR

Fault Summary

Level 2

Detailed Fault Register

FAULT_COMM1

FCOMM_DET

FTONE_DET

HB_FAIL

FAULT_COMM2

SPI_FRAME

FAULT_REG

CONF_MON_ERR

FACTLDERR

FAULT_SYS

FAULT_PWR

CVDD_UV_DRST

CVDD_OV

VALIDATE_DET

Bit

SPI_PHY

LFO

COML_FRAME

COML_PHY

FACT_CRC

SHUTDOWN_REC

DVDD_OV

HB_FAST

DRST

CTL

AVDDREF_OV

AVAO_SW_FAIL

UART_FRAME

COMMCLR_DET

STOP_DET

COMH_FRAME

COMH_PHY

CTS

TSHUT

INH

Level 3

Debug Info

Register

Bit

DEBUG_UART_FRAME

TR_SOF

DEBUG_SPI_FRAME DEBUG_SPI_PHY DEBUG_COML_FRAME DEBUG_COML_PHY DEBUG_COMH_FRAME DEBUG_COMH_PHY

TR_SOF

FMT_ERR

RR_IERR

PERR

RR_IERR

PERR

TR_WAIT

RC_IERR

RC_SOF

COMCLR_ERR

TXDATA_UNEXP

RXDATA_UNEXP

TXFIFO_OF

RR_SOF

BERR_TAG

SYNC2

SYNC1

BIT

RR_SOF

BERR_TAG

SYNC2

SYNC1

BIT

RC_IERR

RR_BYTE_ERR

RR_UNEXP

RR_CRC

RR_BYTE_ERR

RR_UNEXP

RR_CRC

RC_SOF

RC_BYTE_ERR

RC_CRC

RC_BYTE_ERR

RC_CRC

TXFIFO_UF

RXFIFO_OF

图7-24. Fault Status Hierarchy, Mask and Reset

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7.3.3.2 Fault Interface

Host can acquire the fault status with the following two methods:

• Host ignores NFAULT pin, constantly polls the FAULT_SUMMARY register of each device. If

FAULT_SUMMARY is non-zero, read the low level fault status registers to obtain more information.

• Host monitors NFAULT pin status. Enable fault status to pass down the daisy chain to bridge device. Enable

bridge device’s NFAULT pin to be asserted when the FAULT_SUMMARY is non-zero. When NFAULT is

triggered, host polls fault information to diagnose further.

7.3.3.2.1 NFAULT

Device integrates an NMOS open-drain output (NFAULT) to signal the MCU that a fault has occurred in the

system (either fault from BQ79600-Q1 or from monitoring IC). The NFAULT driver is enabled when

[NFAULT_EN] = 1. When BQ79600-Q1 detects an unmasked fault, NFAULT asserts low. When NFAULT is

disabled, the device will set the corresponding flag in FAULT_SUMMARY register but will not assert NFAULT.

If the fault information of stack devices are not transmitted to bridge device through 节 7.3.3.2.2, NFAULT output

only indicates faults in BQ79600-Q1.

7.3.3.2.2 Daisy Chain (COMH and COML)

When using BQ79600-Q1 NFAULT pin to signal the host under a fault detection, the stack devices have to

transfer their fault status information to the base device. The information is transmitted through COMH/L

interface through the same communication cables:

• In ACTIVE, BQ79600-Q1 detects embedded fault info in response frame from stack device.

• In SLEEP, stack device sends Heartbeat and Fault tone to BQ79600-Q1.

• In SHUTDOWN, use Sniff Detector of BQ79600-Q1 monitors stack device Fault tone.

7.3.3.2.2.1 Fault Transmitting when BQ79600-Q1 in ACTIVE

In ACTIVE mode, stack devices can embed their fault status in their response frames (refer to 图 7-7) that are

sent to BQ79600-Q1. The BQ79600-Q1 can detect their embedded fault info and sets [FTONE_DET] bit once

criteria in 图7-25 is met. Please refer to BQ7961X-Q1 on how to use embeded fault feature.

To pass on the fault status of the stack devices, the host sends a stack read which will result with response

frame pass through every device in the daisy chain, giving each device an opportunity to embed their fault status

to response frame.

CRC[7:0]

DATA MSB[7:0]

REG ADR[7:0]

INIT[7:0]

Dev ADR[7:0]

REG ADR[15:8]

SYNC [1:0]

+1

SYNC = 2'b00

SOF = 1

SOF bit of DEV ADR SOF bit of REG ADR[15:8] SOF bit of REG ADR[7:0] Fault Status

1

x

0

x

1

x

1

0

x

0

x

1

x

0

x

[FCOMM_DET] = '1'

[FCOMM_EN] = '1'

[FCOMM_EN] = '0'

[FCOMM_DET] = '0'

图7-25. Embed Fault Detection in Response Frame

7.3.3.2.2.2 Fault Transmitting when BQ79600-Q1 in SLEEP

Because data communication is not available in SLEEP mode, the device provides following options to

transmitting fault information:

• Transmit the Heartbeat tone (enabled by [HB_TX_EN], used to check integrity of cable between bridge and

first stack device). Device does not transmitted fault tone as it has NFAULT.

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• Detect Heartbeat and Fault tone, enabled, by [TONE_RX_EN].

These tones are transmitted in the same direction as a communication command frame, which is based on the

CONTROL1[DIR_SEL] setting. For the tone signal to return back to BQ79600-Q1 (so NFAULT can be triggered

if needed), a Ring architecture must be used to support transmitting fault status in SLEEP mode.

Scenario1: No Fault

Scenario3: Fault Detected

Scenario2: HB Stop

2) S2 ꢀ}ꢁ•v[š Œꢁꢂꢁ]ÀꢁŒ I. š}vꢁ ꢃ•

expected, set fault, send Fault tone

to B0

Non-bq79606

(Top of Stack)

S2

Non-bq79606

(Top of Stack)

S2

Non-bq79606

(Top of Stack)

S2

2) Receive S1 Fault tone , S2 sends

Fault tone to B0.

3) S1 has no fault, send HB tone to B0

2) S1 has no fault, send HB tone to S2

Sleep

1) S1 receives HB tone from B0 as

expected, S1 has no fault, send HB

tone to S2

1) S1 receives HB tone from B0 as

expected, S1 has fault, send Fault tone

to S2

Non-bq79606

S1

Sleep

Non-bq79606

S1

Sleep

Non-bq79606

Fault

S1

Detected

Sleep

Shutdown

MCU

Sleep

B0

(base device)

Shutdown

MCU

Sleep

B0

(base device)

Shutdown

MCU

Sleep

1)B0 detects HB tone from S2, B0

itself has no fault, send HB tone to S1

(optional)

3)B0 receivers fault tone from S2, set

[FTONE_DET], drive INH pin high,

NFAULT pin low

3)B0 receivers fault tone from S2, set

[FTONE_DET], drive INH pin high,

NFAULT pin low

B0

(base device)

IHN

图7-26. Heartbeat and Fault Tone Examples

Both the Heartbeat and Fault Tone are a type of tone similar to the communication. One main difference is a

communication tone only transmits with a single burst of couplets, while Heartbeat and Fault Tones are sent with

a burst of couplets periodically. See 图7-21 for details.

7.3.3.2.2.3 Fault Transmitting (Automatic Host Wakeup/Reverse Wakeup) when BQ79600-Q1 in SHUTDOWN

备注

This feature (Auto Host Wakeup/Reverse Wakeup) is only available if 节7.3.5 is enabled.

The purpose of this user case is to keep BQ79600-Q1 in lowest power mode while still being able to detect fault

information from stack devices. In this case, fault information transmittion is similar to that of SLEEP: top of stack

device sends HB or Fault tone to BQ79600-Q1. The difference lies in the detection of those tones in BQ79600-

Q1. In SHUTDOWN, TONE RX is off, only low power 节 7.3.5 is available. Once sniffer detects FAULT tone, it

puts device into VALIDATE mode in which full power TONE RX is available, device would validate if true Fault

tone exists or not. If yes, it triggers INH. See 图7-27 for different case.

Scenario3: Fault Detected

Scenario1: No Fault

Scenario2: HB Stop

2) Receive S1 HB tone as expected,

S2 has no fault, ꢀ}v[š •ꢁvꢀ Cꢃµoš š}vꢁ

to B0.

Non-bq79606

(Top of Stack)

S2

Non-bq79606

(Top of Stack)

S2

Non-bq79606

(Top of Stack)

S2

2) 5}ꢁ•v[š Œꢁꢂꢁ]Àꢁ {1 HB tone as

expected, S2 sends Fault tone to B0.

2) Receive S1 Fault tone , S2 sends

Fault tone to B0.

Sleep

1) Mask HB Tone RX fault from B0. S1

has no fault, send HB tone to S2.

Non-bq79606

S1

1) Mask HB Tone RX fault from B0. S1

has no fault, send HB tone to S2.

1) Mask HB Tone RX fault from B0. S1

has no fault, send HB tone to S2.

Non-bq79606

S1

Non-bq79606

Fault

S1

Sleep

Detected

Sleep

Shutdown

MCU

Shutdown

MCU

Shutdown

MCU

Shutdown

B0

(base device)

Shutdown

B0

(base device)

Shutdown

3)B0 receives Fault tone from S2,

transition to Fault Validate, validate

Fault tone from S2, drive INH pin high

3)B0 receives Fault tone from S2,

transition to Fault Validate, validate

Fault tone from S2, drive INH pin high

3)B0 ꢀ}ꢁ•v[š Œꢁꢂꢁ]Àꢁ Cꢃµoš š}vꢁ (Œ}u

S2, No Action

B0

(base device)

Shutdown

PMIC

INH

PMIC

INH INH

INH

图7-27. Reverse Wakeup User Case

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7.3.4 INH/ Reverse Wakeup

备注

INH pin is used if Reverse Wakeup feature is used. If this feature is not used, connect this pin to BAT

pin, refer to schematic in 图8-1.

Reverse wakeup feature is a mechanism where BQ79600-Q1 can wakeup the host, through INH pin, on faulty

status from either BQ79600-Q1 or stack devices like BQ7961X-Q1. MCU and its supply (PMIC/SBC) are in

SHUTDOWN for power saving on low voltage battery side.

The INH pin is a high voltage output pin that provides voltage from the BAT minus V_{DROP_INH}to enable an

external high voltage regulators (SBC, PMIC). These regulators are usually used to support the microprocessor

and VIO pin. When INH PMOS pullup is not activated, INH pin goes to a high Z state, it relies on external circuit

to define the pin voltage (in application circuit, 100kohm resistor to GND is used.)

INH PMOS pullup can be triggered:

• In SLEEP mode or VALIDATE mode if following faults are detected regardless of setting of register

FAULT_MSK: [FTONE_DET], [HB_FAIL], [HB_FAST], [AVAO_SW_FAIL], [FACT_CRC], [CONF_MON_ERR].

• In ACTIVE, INH can only be triggered by setting [INH_SET_GO] =1.

Once INH triggered, it remains latched in all modes as long as VBAT is not removed.

INH function described above can be disabled by configuring INH_DIS[1:0] = 2’b11.

Every time INH PMOS is activated, fault bit [INH] is set. To clear the fault, set INH_DIS[1:0] = 2’b11 (disarm

INH driver), then write [RST_SYS] = 1. After this, to use INH feature, set INH_DIS[1:0] = 2’b00.

As part of safety diagnostic (SM202 in Safety Manual), host can trigger INH in ACTIVE and check if pin voltage

is set properly: If INH pin voltage is higher than V_{INH_DET}, [INH_STAT] = 1.

备注

INH pin should be considered a "high voltage logic" terminal, thus should be used to drive the EN

terminal of the system’s power management device. It should be not used as a switch for power

management supply itself. This terminal is not reverse battery protected and thus should not be

connected outside of the system module.

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7.3.5 Sniff Detector

备注

Sniff detector is only used if reverse wakeup feature is used.

Sniff detector, powered by AVAOREF, is used to detect fault tone from stack device on COMH* or COML*. This

detector would trigger if it detects/counts no less than nVALIDATE of continuous couplets (either “-” or “+”)

with amplitude larger than V_{VAL_THR}. If any couplet timing interval is larger than t_SNIFFIDLE, detector/counter is

reset.

This sniff detector rejects HB tone since nVALIDATE is more than 30, both HB/Fault tone are “-” tone;

detector doesn’t expect “+”tone.

备注

The usage assumption of this detector is when system is in idle mode, BQ79600-Q1 in SHUTDOWN.

Sniff detector is only effective in SHUTDOWN. Once detector is triggered, device transitions from SHUTDOWN

to VALIDATE. The sniff detector is by default disabled when first transition from COMPLETE OFF to

SHUTDOWN. To enable the feature, host has to keep [SNIFDET_EN] = ‘1’& [SNIFDET_DIS] = ‘0’before

transitioning to SHUTDOWN. After enabling the detector, if device doesn’t transition to COMPLETE OFF, the

only way to disable the detector is to keep [SNIFDET_DIS] = ‘1’. (Disable bit has higher priority so don’t

care about the setting of [SNIFDET_EN]) before transitioning to SHUTDOWN.)

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7.3.6 Device Diagnostic

The product is developed as a safety element out of context (SEooC), with a target safety goal of ASIL-D for

communication. The following sub-sections describe the diagnostic control and fault status that can be used as

part of the safety mechanisms.

The Safety Manual and FMEDA for BQ79600-Q1 are available separately from Texas Instruments. Contact TI

Sales Associate or Applications Engineer for further information.

7.3.6.1 Power Supplies Check

7.3.6.1.1 Power Supply Diagnostic Check

The internal power supply circuits have overvoltage, undervoltage, and/or current limit checks. The table below

summarizes the diagnostics that apply for each power supply and the corresponding action when failure is

detected.

表7-11. Power Supply Diagnostic Summary

SUPPLY

OV CHECK

UV CHECK

CURRENT LIMIT

DVDD

If fails, set [DVDD_OV]

If fails, digital reset

Limit current to EC table current

limit specification

CVDD

AVAOREF

AVDDREF

VIO

If fails, set [CVDD_OV]

If fails, digital reset, set

[CVDD_UV_DRST]

Limit current to EC table current

limit specification

If fails, set [AVDDREF_OV]

(AVAOREF supplies AVDDREF)

If fails, device shuts down

If fails, set [AVDDREF_OV]

If fails, set [AVAO_SW_FAIL] or

digital reset

If fails, device losses data

communication and Ping function

7.3.6.1.2 Power Supply BIST

The device implemented a power supply BIST (Built-In Self-Test) function to test CVDD, DVDD, AVDDREF OV

detection comparator integrity. It is a command base function initiated by host. Steps below explains how it

works, and further details can be found in Safety Manual (SM017).

1. Host shall read the register FAULT_PWR to verify [CVDD_OV], [DVDD_OV], [AVDDREF_OV] are low.

2. Host shall write [PWR_DIAG_GO] = 1.

3. After 1.7ms, host shall read if [PWR_DIAG_RDY] = 1, else shall, keep waiting, reread.

4. If yes, host shall read FAULT_PWR register, [CVDD_OV], [DVDD_OV], [AVDDREF_OV] to verify the bits are

asserted.

5. Host shall reset faults above.

7.3.6.2 Thermal Shutdown

Thermal shutdown (TSHUT) event occurs when the Thermal Shutdown sensor value exceeds the thermal

shutdown temperature threshold. The sensor operates without interaction and is separated from the ADC

measured die sensor. The thermal shutdown function has a register-status indicator flag (FAULT_SYS[TSHUT])

that is saved during the shutdown event and can be read after the device is waken back up. When a TSHUT

fault occurs, the device immediately enters the SHUTDOWN mode. Any pending transactions on UART or daisy

chain are discarded. There is no fault signaling when a thermal shutdown event occurs, as the device

immediately shuts down.

To awaken the device, host shall ensure the ambient temperature is below T_{SD_FALL}and sends a WAKE ping to

the base device. Host shall not attempt to wake the device if the ambient temperature is still above T_{SD_FALL}

.

Upon waking up, the FAULT_SYS[TSHUT] bit is set. The FAULT_SYS[SHUTDOWN_REC] = 1 indicating the

prior shutdown was caused by abnormal event. See 节 7.5.17 for more details. If the system faults are

unmasked, FAULT_MSK1[MSK_SYS] = 0, the thermal shutdown will be reflected as FAULT and will be indicated

in the FAULT_SUMMARY register and the assertion of the NFAULT pin.

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7.3.6.3 Oscillators Watchdog

The oscillators are monitored by watchdog circuits. There are two oscillators in the device, the HFO and the

LFO. If these oscillators are not functioning, the device does not operate. If the HFO or LFO does not transition

within the expected time, the watchdog circuits trigger Digital Reset.

When such unexpected reset occurs, it is recommended for the host to send a SHUTDOWN ping/tone to the

problem device and follow up a WAKE ping to reset the daisy chain. If the oscillators are truly damaged, the

device will not restart and must be replaced.

In addition to the watchdog, the LFO frequency is monitored to ensure it stays within acceptable limits. If the LFO

frequency falls outside of the expected range, the FAULT_SYS_FAULT[LFO] bit is set.

7.3.6.4 Register Bit Flip Monitor

This bit flip checker monitors 2 configuration registers: DEV_CONF1, FAULT_MSK. It is always running when

device is out of SHUTDOWN. Whenever user changes those 2 register settings or any of the register bit flips,

fault bit [CONF_MON_ERR] is set.

Once user changes the setting, user shall write [CONF_MON_GO]=1 (resample 2 register values), write

[RST_REG] =1 to clear the [CONF_MON_ERR] fault, after this point, if any bit flips among those 2 registers,

[CONF_MON_ERR] is set. After device resets (receive WAKE ping or [SOFT_RESET] = 1), [CONF_MON_ERR]

= 0.

This device does not have customer register CRC check and the register bit flip monitor provides the protection

for the above mentioned customer registers.

7.3.6.5 SPI FIFO 诊断

FIFO 诊断模式为主机提供了使用RX/TX FIFO 的方法。详细的 FIFO 诊断安全机制实现(SM132)，请参阅安全手

册。

7.4 Device Functional Modes

See 节7.3.1

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7.5 Register Maps

Addr R/W Type Reset Value

Data

Hex

Bit7

"0000 0000" RSVD

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DIR0_ADDR

306 R/W

RSVD

ADDRESS[5]

SEND_SHUTDOWN SEND_WAKE

ADDRESS[4]

SEND_SLPTOACT

RSVD

ADDRESS[3]

GOTO_SHUTDOWN

RSVD

ADDRESS[2]

GOTO_SLEEP

RSVD

ADDRESS[1]

ADDRESS[0]

ADDR_WR

RSVD

DIR1_ADDR

CONTROL1

CONTROL2

DIAG_CTRL

DEV_CONF1

DEV_CONF2

TX_HOLD_OFF

SLP_TIMEOUT

COMM_TIMEOUT

SPI_FIFO_UNLOCK

FAULT_MSK

FAULT_RST

FAULT_SUMMARY

FAULT_REG

FAULT_SYS

FAULT_PWR

FAULT_COMM1

FAULT_COMM2

DEV_DIAG_STAT

PARTID

307 R/W

RSVD

ADDRESS[1]

309 R/W-AC

30A R/W-AC

2000 R/W-AC

2001 R/W

"0000 0000" DIR_SEL

"0000 0000" RSVD

SOFT_RESET

SEND_HW_RESET

FLIP_TR_CRC

RESERVED

RSVD

"0000 0000" RSVD

RSVD

CONF_MON_GO

TONE_RX_EN

RSVD

PWR_DIAG_GO

FCOMM_EN

RSVD

SPI_FIFO_DIAG_GO

TWO_STOP_EN

RSVD

FLIP_FACT_CRC

NFAULT_EN

RSVD

INH_SET_GO

HB_TX_EN

"0001 0100" SNIFDET_EN

"0000 0000" RSVD

SNIFDET_DIS

RSVD

2002 R/W

INH_DIS[1]

DLY[1]

INH_DIS[0]

DLY[0]

2003 R/W

"0000 0000" DLY[7]

"0000 0011" RSVD

DLY[6]

DLY[5]

DLY[4]

DLY[3]

DLY[2]

2004 R/W

RSVD

SLP_TIME[2]

CTL_TIME[2]

CODE[2]

SLP_TIME[1]

CTL_TIME[1]

CODE[1]

SLP_TIME[0]

CTL_TIME[0]

CODE[0]

MSK_PWR

RST_PWR

FAULT_PWR

FACT_CRC

INH

2005 R/W

"0011 0100" RSVD

CTS_TIME[2]

RSVD

CTS_TIME[1]

RSVD

CTS_TIME[0]

RSVD

CTL_ACT

CODE[3]

MSK_HB

RST_HB

FAULT_COMM

RSVD

2010 R/W

"0000 0000" RSVD

2020 R/W

"0000 0000" MSK_COML_H

"0000 0000" RST_COML_H

"0000 0000" RSVD

MSK_UART_SPI

RST_UART_SPI

RSVD

MSK_FCOMM_DET MSK_FTONE_DET

RST_FCOMM_DET RST_FTONE_DET

MSK_REG

RST_REG

FAULT_REG

CONF_MON_ERR

CTS

MSK_SYS

2030 R/W-AC

RST_SYS

2100

2101

2102

2103

2104

2105

2110

R

RSVD

FAULT_SYS

FACTLDERR

TSHUT

"0000 0000" RSVD

RSVD

"0000 0000" VALIDATE_DET LFO

RSVD

SHUTDOWN_REC DRST

CTL

"0000 0000" RSVD

"0000 0000" REV[7]

"0000 0000" ID[7]

"0000 0000" CODE[7]

"0111 1000" RSVD

"0001 0011" RSVD

"0000 0000" RSVD

RSVD

CVDD_UV_DRST

CVDD_OV

HB_FAST

COML_FRAME

RSVD

DVDD_OV

UART_FRAME

COML_PHY

RSVD

AVDDREF_OV

COMMCLR_DET

COMH_FRAME

AVAO_SW_FAIL

STOP_DET

COMH_PHY

INH_STAT

REV[0]

FCOMM_DET

RSVD

REV[6]

ID[6]

FTONE_DET

SPI_FRAME

RSVD

HB_FAIL

SPI_PHY

RSVD

PWR_DIAG_RDY

REV[1]

2120 R

2121 R

2122 R

2123 R

2124 R

2125 R

2126 R

2127 R

2128 R

2129 R

REV[5]

ID[5]

REV[4]

REV[3]

REV[2]

DIE_ID1

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DIE_ID2

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DIE_ID3

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DIE_ID4

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DIE_ID5

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DIE_ID6

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DIE_ID7

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DIE_ID8

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DIE_ID9

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

DEBUG_CTRL_UNLOCK2200 R/W

DEBUG_COMM_CTRL 2201 R/W

CODE[6]

COML_TX_EN

RSVD

FMT_ERR

RSVD

CODE[5]

COML_RX_EN

RSVD

CODE[4]

COMH_TX_EN

HW_DAISY_DRV

TXDATA_UNEXP

TR_WAIT

PERR

CODE[3]

COMH_RX_EN

COML_TX_ON

RXDATA_UNEXP

RC_IERR

BERR_TAG

RR_SOF

BERR_TAG

RR_SOF

CODE[2]

CODE[1]

USER_UART_EN

COMH_TX_ON

TXFIFO_UF

RC_BYTE_ERR

SYNC1

CODE[0]

USER_DAISY_EN

COMH_RX_ON

RXFIFO_OF

RC_CRC

BIT

UART_VIF_BAUD

COML_RX_ON

TXFIFO_OF

RC_SOF

SYNC2

DEBUG_COMM_STAT 2300

R

DEBUG_SPI_PHY

2301

2302

COMCLR_ERR

TR_SOF

RSVD

DEBUG_SPI_FRAME

DEBUG_UART_FRAME 2303

DEBUG_COMH_PHY 2304

DEBUG_COMH_FRAME 2305

DEBUG_COML_PHY 2306

DEBUG_COML_FRAME 2307

RSVD

RR_IERR

PERR

RR_BYTE_ERR

SYNC2

RR_UNEXP

SYNC1

RR_CRC

BIT

RSVD

RR_IERR

RR_BYTE_ERR

RR_UNEXP

RR_CRC

图7-28. Register Summary

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7.5.1 Register Summary Table

NVM

VALUES

ADDRESS

REGISTER

DIR0_ADDR

DESCRIPTION

R/W MODE RESET VALUE

INCLUDED IN NVM?

0x306

0x307

Device Address North Direction

Device Address South Direction

Control1

R/W

R

0x00

0x14

0x00

0x03

0x34

0x00

0x78

0x13

0x00

n/a

no

DIR1_ADDR

n/a

no

0x309

CONTROL1

n/a

no

0x30A

CONTROL2

Control2

n/a

no

0x2000

0x2001

0x2002

0x2003

0x2004

0x2005

0x2010

0x2020

0x2030

0x2100

0x2101

0x2102

0x2103

0x2104

0x2105

0x2110

0x2120

0x2121

0x2122

0x2123

0x2124

0x2125

0x2126

0x2127

0x2128

0x2129

0x2200

0x2201

0x2300

0x2301

0x2302

0x2303

0x2304

0x2305

0x2306

0x2307

DIAG_CTRL

Diagnostic Control

Device Configure1

Device Configure2

Transmitter Hold off Control

Sleep Timer

n/a

no

DEV_CONF1

n/a

no

DEV_CONF2

n/a

no

TX_HOLD_OFF

SLP_TIMEOUT

COMM_TIMEOUT

SPI_FIFO_UNLOCK

FAULT_MSK

n/a

no

n/a

no

Communication Timeout Control

FIFO Diagnostic Unlock

Fault Mask

n/a

no

n/a

no

n/a

no

FAULT_RST

Fault Reset

n/a

no

FAULT_SUMMARY

FAULT_REG

Fault Summary

n/a

no

Register Fault

R

n/a

no

FAULT_SYS

System Fault

R

n/a

no

FAULT_PWR

Power Fault

R

n/a

no

FAULT_COMM1

FAULT_COMM2

DEV_DIAG_STAT

PARTID

Communication Fault1

Communication Fault2

Diagnostic Status

Part ID

R

n/a

no

R

n/a

no

R

n/a

no

R

various

n/a

yes

no

DIE_ID1

Die ID1

R

DIE_ID2

Die ID2

R

DIE_ID3

Die ID3

R

DIE_ID4

Die ID4

R

DIE_ID5

Die ID5

R

DIE_ID6

Die ID6

R

DIE_ID7

Die ID7

R

DIE_ID8

Die ID8

R

DIE_ID9

Die ID9

R

DEBUG_CTRL_UNLOCK

DEBUG_COMM_CTRL

DEBUG_COMM_STAT

DEBUG_SPI_PHY

DEBUG_SPI_FRAME

DEBUG_UART_FRAME

DEBUG_COMH_PHY

DEBUG_COMH_FRAME

DEBUG_COML_PHY

DEBUG_COML_FRAME

Debug Control Unlock

Debug Communication Control

Debug Communication Status

SPI Physical Layer Error

SPI Frame Layer Error

UART Frame Layer Error

COMH Physical Layer Error

COMH Frame Layer Error

COML Physical Layer Error

COML Frame Layer Error

R/W

R

n/a

no

n/a

no

R

n/a

no

R

n/a

no

R

n/a

no

R

n/a

no

R

n/a

no

R

n/a

no

R

n/a

no

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7.5.2 Register: DIR0_ADDR

Address: 0x306

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

ADDRESS[5:0]

0

RW

0

RW

ADDRESS [5:0]

Follow steps in section “Device Addressing”to config this register. Always shows the current Device Address used by the device when

[DIR_SEL] = 0.

Default to 0x00 when digital core out of digital reset. MCU can re-address the device by writing a different device address to this register,

and the device will take on the new address immediately.

7.5.3 Register: DIR1_ADDR

Address: 0x307

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

ADDRESS[5:0]

0

RW

0

RW

ADDRESS [5:0]

Follow steps in section “Device Addressing”to config this register. Always shows the current Device Address used by the device when

[DIR_SEL] = 1.

Default to 0x00 when digital core out of digital reset. MCU can re-address the device by writing a different device address to this register,

and the device will take on the new address immediately.

7.5.4 Register: CONTROL1

Address: 0x0309

B7

B6

B5

B4

B3

B2

B1

B0

DIR_SEL

SEND_SHUTDO

WN

SEND_WAKE

SEND_SLPTOAC GOTO_SHUTDO

GOTO_SLEEP

SOFT_RESET

ADDR_WR

T

0

WN

0

RW

DIR_SEL

Select daisy chain comm direction. Not self-clear bit.

0: In a device, command frame travels from MCU to COMH

1: In a device, command frame travels from MCU to COML

SEND_SHUTDO Sends SHUTDOWN tone to next device up the stack. The device receiving this bit is unaffected. Self-clear bit.

WN

0: Ready

1: Send SHUTDWON tone up the stack

SEND_WAKE

Send WAKE tone up the stack. Self-clear bit.

0: Ready

1: Send WAKE tone up the stack, then reset its own

SEND_SLPTOAC Send SLEEPtoWAKE tone up the stack. Self-clear bit.

T

0: Ready

1: Send SLEEPtoWAKE tone up the stack

GOTO_SHUTDO Transition device to SHUTDOWN mode. Self-clear bit.

WN

0: Ready

1: Enter SHUTDOWN mode

GOTO_SLEEP

Transition device to SLEEP mode. Self-clear bit.

0: Ready

1: Enter SLEEP mode

SOFT_RESET

ADDR_WR

Reset the digital to OTP default. Self-clear bit.

0: Ready

1: Reset device

Enable device to start auto-addressing. See auto-addressing chapter for detail. Self cleared.

0: Not performing auto-address. Device forwards communication transaction as normal

1: Device is being auto-addressed; the 1st communication transaction it received will not be forwarded.

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7.5.5 Register: CONTROL2

Address: 0x30A

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

SEND_HW_RESE

T

SPARE

0

RW

SEND_HW_RESE Send HW_RESET tone up the stack. Self-clear bit.

T

0: Ready

1: Send HW_RESET tone to next stack device up

7.5.6 Register: DIAG_CTRL

Address: 0x2000

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

CONF_MON_GO PWR_DIAG_GO SPI_FIFO_DIAG_ FLIP_FACT_CRC

GO

FLIP_TR_CRC

INH_SET_GO

0

RW

CONF_MON_GO Resample the 2 registers (DEV_CONF1, FAULT_MSK) setting that bit flip monitor checks against. self-clear bit. For usage, refer to

paragraph: Register Bit Flip Monitor

0: No action

1: Resample 2 registers setting

PWR_DIAG_GO Indicates a power supply BIST diagnostic is initiated, self-clear bit.

0: No action

1: Initiate power BIST diagnostic

SPI_FIFO_DIAG_ Write the unlock code 0x0A to SPI_FIFO_UNLOCK and followed by writing [SPI_FIFO_DIAG_GO] = 1 to do FIFO diagnostic. For detailed

GO

steps of FIFO diagnostic, refer to safety manual. This bit is self-cleared.

0: No action

1: Initiate SPI FIFO diagnostic

FLIP_FACT_CRC An enable bit to flip the factory CRC expected value. This is for factory CRC diagnostic.

0: No action

1: flip the CRC expected value. This will cause a factory CRC fault, FAULT_REG[FACT_CRC]

FLIP_TR_CRC

INH_SET_GO

Sends a purposely incorrect communication (during transmitting response) CRC by inverting all of the calculated CRC bits

0: Send CRC as calculated

1: Send inverted CRC

This bits intentionally activates INH PMOS pull up, sets [INH] and [INH_STAT] to 1. (self-cleared)

0: mission mode

1: Trigger INH PMOS pull up

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7.5.7 Register: DEV_CONF1

Address: 0x2001

B7

SNIFDET_EN

0

B6

B5

B4

B3

B2

B1

B0

SNIFDET_DIS

TONE_RX_EN

FCOMM_EN

TWO_STOP_EN

NFAULT_EN

RESERVED

HB_TX_EN

0

1

0

1

0

RW

SNIFDET_EN

Enable the Sniff detector on COM* port, this bit is latched into AVAOREF domain, once latched in, this bit is still effective in SHUTDOWN

0: no effect

1: SNIF DET is enabled in SHUTDOWN

SNIFDET_DIS

TONE_RX_EN

Enable the Sniff detector on COM* port, this bit is latched into AVAOREF domain, once latched in, this bit is still effective in SHUTDOWN

0: no effect

1: SNIF DET is disabled in SHUTDOWN, if both SNIFDET_EN and SNIFDET_DIS are ‘1’, SNIFDET_DIS takes priority.

Enable the Tone receiver, depends on [DIR_SEL], one of the COML/COMH tone recover is enabled. COMH/COML tone receivers are

enabled in VALIDATE disregarding setting of this bit.

0: Disable

1: Enable

FCOMM_EN

Enable the fault state detection through communication in ACTIVE mode

0: Disable

1: Enable

TWO_STOP_EN Enables two stop bits for the UART in case of severe oscillator error in both the host and device

0: One STOP bit

1: Two STOP bit

NFAULT_EN

Enables the NFAULT function

0: NFAULT driver is disabled

1: NFAULT pulls low to indicate an unmasked fault is detected

RESERVED

HB_TX_EN

Reserved. Default value is 0. Please don't alter.

Enable HEARTBEAT transmitter when device is in SLEEP mode

0: Disable

1: Enable

7.5.8 Register: DEV_CONF2

Address: 0x2002

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

INH_DIS[1:0]

0

RW

0

RW

INH_DIS[1:0]

Disable INH driver (PMOS pull up). In all modes, this bit overwrites [INH_SET_GO] and fault tone detection event

00: INH function is enabled

01: INH function is enabled

10: INH function is enabled

11: INH function is DISABLED

7.5.9 Register: TX_HOLD_OFF

Address: 0x2003

B7

B6

B5

B4

B3

B2

B1

B0

DLY[7:0]

0

RW

DLY[7:0]

Set the number of bit period delay from 0 to 255, after receiving the STOP bit of a command frame and before transmitting the 1st bit of

response frame

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7.5.10 Register: SLP_TIMEOUT

Address: 0x2004

B7

B6

B5

RSVD

0

B4

B3

B2

B1

B0

SLP_TME[2:0]

0

RW

0

1

RW

SLP_TME[2:0]

This timer starts counting when device enters SLEEP or VALIDATE. When the timer expires, the device enters SHUTDOWN. The timer

reset if device wakes up to ACTIVE.

000: no timeout. Device remains in SLEEP

001: 5s

010: 10s

011: 1min

100: 10mins

101: 30mins

110: 1hour

111: 2hours

7.5.11 Register: COMM_TIMEOUT

Address: 0x2005

B7

B6

B5

B4

B3

CTL_ACT

0

B2

B1

B0

RSVD

CTS_TIME[2:0]

CTL_TIME[2:0]

0

RW

0

1

0

RW

CTS_TIME[2:0]

Set the short communication timeout. When this timer expires, the device set the FAULT_SYS [CTS] bit. This can be used as an alert to the

system to prevent a long communication timeout.

000: disable short communication timeout

001: 100ms

010: 2s

011: 10s (default)

100: 1min

101: 10mins

110: 30min

111: 1hour

CTL_ACT

Configure the device action when long communication timeout timer expires

0: set FAULT_SYS[CTL] and send device to SLEEP mode (default at reset)

1: Send the device to SHUTDOWN. FAULT_SYS[CTL] bit will not be set

CTL_TIME[2:0]

Set the long communication timeout. When this timer expires, the device takes the action configured by the [CTL_ACT] bit.

000: disable long communication timeout

001: 100ms

010: 2s

011: 10s

100: 1min (default)

101: 10mins

110: 30min

111: 1hour

7.5.12 Register: SPI_FIFO_UNLOCK

Address: 0x2010

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

CODE[3:0]

0

RW

0

RW

CODE[3:0]

In UART mode - write has no impact and read always returns 0 In SPI mode - Write the unlock code 0x0A to SPI_FIFO_UNLOCK (MSB 4

bits are don’t care, e.g. 0x2A would also unlock) and followed by writing [SPI_FIFO_DIAG_GO] = 1 to do FIFO diagnostic. For detailed

steps of FIFO diagnostic, refer to safety manual. After these bits are written, read cmd doesn’t affect them while any write cmd clears

them.

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7.5.13 Register: FAULT_MSK

Address: 0x2020

B7

B6

B5

B4

B3

B2

B1

B0

MSK_COML_H

MSK_UART_SPI MSK_FCOMM_D MSK_FTONE_DE

MSK_HB

MSK_REG

MSK_SYS

MSK_PWR

ET

0

T

0

RW

0

RW

MSK_COML_H

If this bit is set, [FAULT_COMM] bit in FAULT_SUMMARY register is not set (NFAULT won’t toggle) due to bits: [COML_FRAME],

[COMH_FRAME], [COML_PHY], [COMH_PHY] and registers: DEBUG_COMH_PHY, DEBUG_COMH_FRAME, DEBUG_COML_PHY,

DEBUG_COML_FRAME

0: Assert NFAULT and set [FAULT_COMM] if fault above is detected

1: No NFAULT action, [FAULT_COMM] not set due to faults above

MSK_UART_SPI

If this bit is set, [FAULT_COMM] bit in FAULT_SUMMARY register is not set (NFAULT won’t toggle) due to [STOP_DET],

[COMMCLR_DET], [UART_FRAME], [SPI_FRAME], [SPI_PHY] bits and DEBUG_UART_FRAME, DEBUG_SPI_PHY,

DEBUG_SPI_FRAME registers

0: Assert NFAULT and set [FAULT_COMM] if fault above is detected

1: No NFAULT action, [FAULT_COMM] not set due to faults above

MSK_FCOMM_D

ET

If this bit is set, [FAULT_COMM] bit in FAULT_SUMMARY register is not set (NFAULT won’t toggle) due to [FCOMM_DET]

0: Assert NFAULT and set [FAULT_COMM] if fault above is detected

1: No NFAULT action, [FAULT_COMM] not set due to faults above

MSK_FTONE_DE

T

If this bit is set, [FAULT_COMM] bit in FAULT_SUMMARY register is not set (NFAULT won’t toggle) due to [FTONE_DET]

0: Assert NFAULT and set [FAULT_COMM] if fault above is detected

1: No NFAULT action, [FAULT_COMM] not set due to faults above

MSK_HB

If this bit is set, [FAULT_COMM] bit in FAULT_SUMMARY register is not set (NFAULT won’t toggle) due to [HB_FAIL] and [HB_FAST]

0: Assert NFAULT and set [FAULT_COMM] if fault above is detected

1: No NFAULT action, [FAULT_COMM] not set due to faults above

MSK_REG

If this bit is set, [FAULT_REG] bit in FAULT_SUMMARY register is not set and NFAULT won’t toggle due to OTP fault. It doesn’t affect

FAULT_REG register.

0: Mask disabled

1: Mask enabled to prevent fault signaling

MSK_SYS

MSK_PWR

If this bit is set, [FAULT_SYS] bit in FAULT_SUMMARY register is not set and NFAULT won’t toggle due to SYS fault. It doesn’t affect

FAULT_SYS register.

0: Assert NFAULT if any bit from FAULT_SYS is set to ‘1’

1: No NFAULT action regardless of FAULT_SYS status

If this bit is set, [FAULT_PWR] bit in FAULT_SUMMARY register is not set and NFAULT won’t toggle due to PWR fault. It doesn’t affect

FAULT_PWR register.

0: Mask disabled

1: Mask enabled to prevent fault signaling

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7.5.14 Register: FAULT_RST

Address: 0x2030

B7

B6

B5

B4

B3

B2

B1

B0

RST_COML_H

RST_UART_SPI RST_FCOMM_DE RST_FTONE_DE

RST_HB

RST_REG

RST_SYS

RST_PWR

T

0

T

0

RW

0

RW

RST_COML_H

Reset bits: COML_FRAME, COMH_FRAME, COML_PHY, COMH_PHY and registers: DEBUG_COMH_PHY, DEBUG_COMH_FRAME,

DEBUG_COML_PHY, DEBUG_COML_FRAME. self-cleared bit.

0: Do not reset

1: Reset to 0x00

RST_UART_SPI Reset STOP_DET, COMMCLR_DET, UART_FRAME, SPI_FRAME, SPI_PHY bits and DEBUG_UART_FRAME, DEBUG_SPI_PHY,

DEBUG_SPI_FRAME registers. self-cleared bit.

0: Do not reset

1: Reset to 0x00

RST_FCOMM_DE Reset FCOMM_DET bit, self-cleared bit.

T

0: Do not reset

1: Reset to '0'

RST_FTONE_DE Reset FTONE_DET bit, self-cleared bit.

T

0: Do not reset

1: Reset to '0'

RST_HB

Reset HB_FAIL and HB_FAST bit, self-cleared bit.

0: Do not reset

1: Reset to '0'

RST_REG

RST_SYS

RST_PWR

Resets FAULT_SUMMARY [FAULT_REG] to '0', self-cleared bit.

0: Do not reset

1: Reset to '0'

This bit is self-clear to 0 after writing to 1.

0: Do not reset

1: Reset register FAULT_SYS and [FAULT_SYS] to 0x00 and ‘0’

Resets FAULT_SUMMARY [FAULT_PWR] to '0' and register FAULT_PWR, self-cleared bit.

0: Do not reset

1: Reset

7.5.15 Register: FAULT_SUMMARY

Address: 0x2100

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

FAULT_COMM

FAULT_REG

FAULT_SYS

FAULT_PWR

0

R

0

R

FAULT_COMM

Indicate communication related fault is detected (any bits in register FAULT_COMM1, FAULT_COMM2 is set)

0: No fault

1: Fault

FAULT_REG

FAULT_SYS

FAULT_PWR

Indicate registers related fault is detected

0: No fault

1: Fault

Indicates system fault is detected (any bits in register FAULT_SYS).

0: No fault

1: Fault

Indicates a power supply fault is detected (any bits in register FAULT_PWR)

0: No fault

1: Fault

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7.5.16 Register: FAULT_REG

Address: 0x2101

B7

B6

B5

RSVD

0

B4

B3

B2

B1

B0

CONF_MON_ERR

FACTLDERR

FACT_CRC

0

R

CONF_MON_ER Indicates monitored 2 registers (DEV_CONF1, FAULT_MSK) have at least one bit flip. For usage, refer to paragraph: Register Bit Flip

R

Monitor.

0: No fault

1: Fault

FACTLDERR

FACT_CRC

Indicates the factory NVM registers could not be loaded from OTP.

0: No fault

1: Fault

Indicates a CRC error has occurred in the factory register space.

0: No fault

1: Fault

7.5.17 Register: FAULT_SYS

Address: 0x2102

B7

B6

LFO

0

B5

B4

DRST

0

B3

CTL

0

B2

CTS

0

B1

B0

INH

0

VALIDATE_DET

SHUTDOWN_REC

TSHUT

0

R

0

R

VALIDATE_DET

Indicates device transitioned to VALIDATE mode

0: no transitioned to VALIDATE MODE

1: transitioned to VALIDATE MODE

LFO

Indicated LFO frequency is off by +/-25%

0: no fault

1: fault

SHUTDOWN_RE Indicates the device was shut down using SHUTDOWN ping. If this bit is set, the COML and COMH RX are both disabled at wake up as a

C

way to isolate itself from the stack. Send another wake ping or [SOFT_RESET] to re-enable COMH/L RX.

0: The previous SHUTDOWN was normal

1: The previous SHUTDOWN was caused by ping, which is not a usual SHUTDOWN method, indicating potential communication issue with

the device

DRST

CTL

Indicates a digital reset has occurred.

0: no digital reset

1: digital reset has occurred

Indicates a long communication timeout occurred. Device action is configured by [CTL_ACT]. This bit is not observable if the action is set to

device shutdown.

0: No fault

1: long communication timeout occurs. Observable if long timeout action is set to SLEEP

CTS

Indicates a short communication timeout occurred. No action from the device. This can be served as an alert to system before reaching

long communication timeout.

0: No fault

1: short communication timeout occurs

TSHUT

INH

Indicates the previous shutdown was due to thermal shutdown

0: die temp is < thermal shutdown threshold

1: the previous shutdown was to due thermal shutdown

Indicates INH PMOS is enabled

0: INH driver is off

1: INH driver enabled, pulls pin up to BAT

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7.5.18 Register: FAULT_PWR

Address: 0x2103

B7

B6

RSVD

0

B5

B4

B3

B2

B1

B0

CVDD_UV_DRST

CVDD_OV

DVDD_OV

AVDDREF_OV

AVAO_SW_FAIL

0

R

CVDD_UV_DRST Indicates CVDDUV fault caused DRST. Shutdown/power up event shall not trigger this fault.

0: no fault

1: fault

CVDD_OV

Indicates an over voltage fault on the CVDD pin

0: no fault

1: fault

DVDD_OV

Indicates an over voltage fault on the DVDD pin

0: no fault

1: fault

AVDDREF_OV

Indicates an over voltage fault on the AVDD_REF internal supply

0: no fault

1: fault

AVAO_SW_FAIL Indicates a fault is detected on the AVAO_REF switch.

0: no fault

1: fault

7.5.19 Register: FAULT_COMM1

Address: 0x2104

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

FCOMM_DET

FTONE_DET

HB_FAIL

HB_FAST

UART_FRAME

COMMCLR_DET

STOP_DET

0

R

0

R

FCOMM_DET

Indicates the fault status bit in comm frame is set by stack devices. At least a fault in stack devices happened. Only apply to non-bq79606

family

0: no fault

1: fault

FTONE_DET

HB_FAIL

Indicates the fault tone is detected, COM Port in sleep mode if work with non-bq79606 (Detection is monitoring the COML side if [DIR_SEL]

= 0 and vice versa.)

0: no fault

1: fault

Indicates HB tone is NOT detected within tHB_PERIOD, not supported with BQ79606A-Q1 ( Detection is monitoring the COML side if

[DIR_SEL] = 0 and vice versa.)

0: no fault, HB tone detected as expected

1: fault

HB_FAST

Indicates HB tone is detected within tHB_FAST (too frequent), not supported with BQ79606A-Q1 ( Detection is monitoring the COML side if

[DIR_SEL] = 0 and vice versa.) This bit could also be set when [FTONE_DET]=1 depends on how soon the Fault Tone is detected from

previous Heartbeat tone.

0: no fault

1: fault

UART_FRAME

Indicates a UART FAULT detected when receiving command or transmitting response frames Further detail of the fault information is

available in the DEBUG_UART_FRAME register

0: no fault

1: fault

COMMCLR_DET A UART/SPI communication clear signal is detected. This bit is set when Sleep2active ping is sent in UART mode. While in SPI mode, it is

not set when sleep2active ping is sent.

0: no UART/SPI Comm Clear

1: UART/SPI Comm Clear detected

STOP_DET

Indicates and unexpected STOP condition is received. Apply to UART mode. This bit is set when Sleep2active ping is sent in ACTIVE.

0: no fault

1: fault

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7.5.20 Register: FAULT_COMM2

Address: 0x2105

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

SPI_FRAME

SPI_PHY

COML_FRAME

COML_PHY

COMH_FRAME

COMH_PHY

0

R

0

R

SPI_FRAME

Indicates a SPI frame level FAULT detected when receiving command or transmitting response frames. Further detail of the fault

information is available in the DEBUG_SPI_FRAME register

0: no fault

1: fault

SPI_PHY

Indicates a SPI bit level FAULT detected when receiving command or transmitting response frames. Further detail of the fault information is

available in the DEBUG_SPI_PHY register

0: no fault

1: fault

COML_FRAME

COML_PHY

COMH_FRAME

COMH_PHY

Indicate a COML byte level fault detected when receiving response frames. Further details of the fault information is available in

DEBUG_COML_FRAME

0: no fault

1: fault

Indicate a COML bit level fault detected, which would cause at least a byte level (RC_RR) fault. Further details of the fault information are

available in DEBUG_COML_PHY register.

0: no fault

1: fault

Indicate a COMH byte level fault detected when receiving response frames. Further details of the fault information is available in

DEBUG_COMH_FRAME

0: no fault

1: fault

Indicate a COMH bit level fault detected, which would cause at least a byte level (RC_RR) fault. Further details of the fault information are

available in DEBUG_COMH_PHY register.

0: no fault

1: fault

7.5.21 Register: DEV_DIAG_STAT

Address: 0x2110

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

PWR_DIAG_RDY

INH_STAT

0

R

PWR_DIAG_RDY Indicates a power supply BIST test is done. It is cleared when [PWR_DIAG_GO] bit is set.

0: BIST is not done

1: BIST is done

INH_STAT

Indicates INH Pin see VINH_DET, this bit reflects real time value of pin INH

0: Voltage not detected

1: Voltage detected

7.5.22 Register: PARTID

Address: 0x2120

B7

B6

B5

B4

B3

B2

B1

B0

REV[7:0]

0

R

REV[7:0]

Device revision 0x00 = A0, 0x01 = A1, 0x02 = A2, etc.

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7.5.23 Register: DIE_ID1

Address: 0x2121

B7

B6

B5

B4

B3

B2

B1

B0

ID[7:0]

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

7.5.24 Register: DIE_ID2

Address: 0x2122

B7

B6

B5

B4

B3

B2

B1

B0

ID[7:0]

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

7.5.25 Register: DIE_ID3

Address: 0x2123

B7

B6

B5

B4

B3

B2

B1

B0

ID[7:0]

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

7.5.26 Register: DIE_ID4

Address: 0x2124

B7

B6

B5

B4

B3

B2

B1

B0

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

7.5.27 Register: DIE_ID5

Address: 0x2125

B7

B6

B5

B4

B3

B2

B1

B0

ID[7:0]

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

7.5.28 Register: DIE_ID6

Address: 0x2126

B7

B6

B5

B4

B3

B2

B1

B0

ID[7:0]

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

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7.5.29 Register: DIE_ID7

Address: 0x2127

B7

B6

B5

B4

B3

B2

B1

B0

ID[7:0]

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

7.5.30 Register: DIE_ID8

Address: 0x2128

B7

B6

B5

B4

B3

B2

B1

B0

ID[7:0]

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

7.5.31 Register: DIE_ID9

Address: 0x2129

B7

B6

B5

B4

B3

B2

B1

B0

ID[7:0]

0

R

ID[7:0]

Digital reset value 0x00, after factory NVM loaded successfully, it is value in the NVM.

7.5.32 Register: DEBUG_CTRL_UNLOCK

Address: 0x2200

B7

B6

B5

B4

B3

B2

B1

B0

CODE[7:0]

0

RW

0

RW

CODE[7:0]

Write the unlock code (0xA5) to this register to activate the setting in the DEBUG_COMM_CTRL register. Any other value than the unlock

code will deactivate any effect in the DEBUG_COMM_CTRL setting and return to the device’s normal setting. This register doesn't affect

DEBUG_COMM_STAT register.

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7.5.33 Register: DEBUG_COMM_CTRL

Address: 0x2201

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

COML_TX_EN

COML_RX_EN

COMH_TX_EN

COMH_RX_EN UART_VIF_BAUD USER_UART_E

N

USER_DAISY_EN

0

RW

1

0

RW

COML_TX_EN

Enable COML transmitter

0: disable

1: enable

COML_RX_EN

COMH_TX_EN

COMH_RX_EN

Enable COML receiver

0: disable

1: enable

Enable COMH transmitter

0: disable

1: enable

Enable COMH receiver

0: disable

1: enable

UART_VIF_BAUD This bit changes the baud rate of UART and Daisy Chain (Also called VIF) to 250kb/s. Useful on Daisy Chain debug. When system set all

the daisy chain devices to the 250kb/s baud rate, it slows down the response byte through the Daisy Chain to increase the robustness of

the Daisy Chain for debug purpose.

0: 1Mbps

1: 250kbps

USER_UART_EN This bit enables [UART_VIF_BAUD] setting

0: disable

1: enable

USER_DAISY_E This bit enables the setting of bits [6:3] in this register

N

0: the setting of bits [6:3 ] of current register has no effect

1: the device will configure the COML and COMH per current register setting

7.5.34 Register: DEBUG_COMM_STAT

Address: 0x2300

B7

B6

RSVD

0

B5

B4

B3

B2

B1

B0

HW_DAISY_DRV

COML_TX_ON

COML_RX_ON

COMH_TX_ON

COMH_RX_ON

0

1

0

1

R

HW_DAISY_DRV Indicates the COML and COMH are controlled by the device itself or by MCU control

0: the DEBUG_COMM_CTRL [USER_DAISY_EN] = 1. COML and COMH are under manual control through DEBUG_COMM_CTRL

register

1: COML and COMH are controlled by the device

COML_TX_ON

COML_RX_ON

COMH_TX_ON

COMH_RX_ON

Show the current COML transmitter status

0: Disabled

1: Enabled

Show the current COML receiver status

0: Disables

1: Enables

Show the current COMH transmitter status

0: Disabled

1: Enabled

Show the current COMH receiver status

0: Disabled

1: Enabled

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7.5.35 Register: DEBUG_SPI_PHY

Address: 0x2301

B7

RSVD

0

B6

B5

B4

B3

B2

B1

B0

FMT_ERR

COMCLR_ERR

TXDATA_UNEXP RXDATA_UNEXP

TXFIFO_OF

TXFIFO_UF

RXFIFO_OF

0

R

FMT_ERR

When not in Host Read mode (after sending a write cmd frame), indicates malformed cmd is received: 1. first byte of data after nCS falling

edge is 0xFF 2. devices receives not multiple of 8bit . 3. In ACTIVE, nCS pulses low without SCLK toggling (send SLP2ACT ping) Comm

clear doesn’t trigger this fault. This fault doesn’t lock down SPI interface.

0: No fault

1: Fault

COMCLR_ERR

More than 8 SCLK pulses are received during a comm clear. Once this fault is detected, device ignores the malformed comm clear. This

fault doesn’t affect SPI_RDY nor data storing into RX/TX FIFO.

0: No fault

1: Fault

TXDATA_UNEXP This fault occurs when: 1. device receives unexpected data from itself or daisy chain after a Comm clr OR 2. device receives unexpected

data from daisy chain(or from bq79600) after a TX FIFO timeout. Once this fault is detected, device doesn’t store any new data into

RX/TX FIFO. Device sends out 0xFF on MISO after current byte finished transmission(FIFO data mask happens at byte boundary).

SPI_RDY held low till Comm Clear detected. Comm Clear needed for recovery.

0: No fault

1: Fault

RXDATA_UNEXP Host sends data other than 0xFF during Device Read mode OR initiates SPI communication when SPI_RDY = 0 (e.g. While FIFO2 is being

filled up, host continues reading FIFO2 right after FIFO1 is read out. SPI_DRY is low at this point) Once this fault is detected, device

doesn’t store any new data into RX/TX FIFO. Device would sends out 0xFF on MISO after current byte finished transmission(FIFO data

mask happens at byte boundary). SPI_RDY held low till Comm Clear detected. Comm Clear needed for recovery.

0: No fault

1: Fault

TXFIFO_OF

TXFIFO_UF

If SPI module receives data (from itself or daisy chain) when current FIFO is full and 2nd FIFO is not empty (host hasn't complete reading

the 2nd FIFO). Once this fault is detected, device doesn’t store any new data into RX/TX FIFO. Device sends out 0xFF on MISO after

current byte finished transmission(FIFO data mask happens at byte boundary). SPI_RDY held low till Comm Clear detected. Comm Clear

needed for recovery.

0: No fault

1: Fault

In Host Read mode, when both FIFOs are empty and the host continues to send clocks for more read data (send 0xFF through MOSI). SPI

Slave sets this fault flag and continues to send 0xFF on MISO when host requests data. Once this fault is detected, device doesn’t store

any new data into RX/TX FIFO. Device sends out 0xFF on MISO after current byte finished transmission(FIFO data mask happens at byte

boundary). SPI_RDY held low till Comm Clear detected. Comm Clear needed for recovery. (FIFO 1 is read out, FIFO2 is still buffering, if

reading happens, it is RXDATA_UNEXP fault) Once FIFO is empty, device rejects any 0xFF until nCS going high.

0: No fault

1: Fault

RXFIFO_OF

While device is receiving command frame, more data is sent than device can accommodate in RX FIFO. Once this fault is detected, device

doesn’t store any new data into RX/TX FIFO. Device sends out 0xFF on MISO after current byte finished transmission(FIFO data mask

happens at byte boundary). SPI_RDY held low till Comm Clear detected. Comm Clear needed for recovery. Follow “Flow to send write

cmd frame into bq79600”to avoid this fault.

0: No fault

1: Fault

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7.5.36 Register: DEBUG_SPI_FRAME

Address: 0x2302

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

TR_SOF

TR_WAIT

RC_IERR

RC_SOF

RC_BYTE_ERR

RC_CRC

0

R

TR_SOF

Indicates that a SPI COMM CLEAR is received while there is data in output FIFO (SPI_RDY is 0 or SPI_RDY = 1 and receiving new data

from VIF.) If SPI_RDY = 1 and not receiving new data from VIF while receiving COMM CLEAR, it doesn’t assert this bit.

0: No fault

1: Fault

TR_WAIT

RC_IERR

Indicates that a SPI COMM CLEAR is received while there is no data in output FIFO regardless of SPI_RDY.

0: No fault

1: Fault

Detects initialization byte error in the received command frame. Example: •reserved command bits in the “INIT byte”is set, •expected

to a cmd “INIT byte’, but it is configured as response frame instead •extra data is sent other than one cmd frame during one nCS low

All bytes that follow are discarded until a Comm Clear is received or a SOF due to a properly formed new command is received (nCS

falling, etc).

0: No fault

1: Fault

RC_SOF

Detects a start-of-frame (SOF) error. Mostly, this is SPI COMM CLEAR is received on the SPI before the current frame is finished, e.g.

partial cmd frame is sent

0: No fault

1: Fault

RC_BYTE_ERR

Device receives data from the VIF that needs to go out on SPI, while host send data into device through SPI. (TXDATA_UNEXP should

also be set) CRC is not calculated and doesn’t forward communication in daisy chain. All bytes that follow are ignored until a

communication CLEAR is received.

0: No fault

1: Fault

RC_CRC

Detects CRC error in the received command frame from SPI. The frame will be considered as discarded frame. Frame CRC is calculated

only if no physical level error, IERR, BERR, SOF error detected.

0: No fault

1: Fault

7.5.37 Register: DEBUG_UART_FRAME

Address: 0x2303

B7

B6

B5

B4

B3

B2

B1

B0

RSVD

TR_SOF

TR_WAIT

RC_IERR

RC_SOF

RC_BYTE_ERR

RC_CRC

0

R

TR_SOF

Indicates that a UART COMM CLEAR is received while the device is still transmitting data to host.

0: No fault

1: Fault

TR_WAIT

RC_IERR

The device is waiting for its turn to transfer a response out but the action is terminated because: 1. the device receives a UART COMM

CLEAR signal, or 2. the device receives a new command This bit is valid when broadcast or stack read command has been issued.

0: No fault

1: Fault

Detects initialization byte error in the received command frame. Example: •a STOP error is detected, •reserved command bits in the

“INIT byte”is set, •expected a “INIT byte’, but it is configured as response frame instead (e.g. 1st byte received after COMM CLEAR

signal should but a “INIT byte”) All bytes that follow are ignored until a communication CLEAR is received.

0: No fault

1: Fault

RC_SOF

Detects a start-of-frame (SOF) error. Mostly, this is UART COMM CLEAR is received on the UART before the current frame is finished.

0: No fault

1: Fault

RC_BYTE_ERR

Other than INIT byte, if STOP error is detected in rest of byte in the frame or TX receives data while RX is using. CRC is not calculated and

doesn’t forward communication in daisy chain. All bytes that follow are ignored until a communication CLEAR is received.

0: No fault

1: Fault

RC_CRC

Detects CRC error in the received command frame from UART. The frame will be considered as discarded frame. Frame CRC is calculated

only if no physical level error, IERR, BERR, SOF error detected

0: No fault

1: Fault

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7.5.38 Register: DEBUG_COMH_PHY

Address: 0x2304

B7

B6

RSVD

0

B5

B4

PERR

0

B3

B2

B1

B0

BIT

0

BERR_TAG

SYNC2

SYNC1

0

R

PERR

Pertain to received response frame from stack device only. PERR is a lump bit of all physical errors. Any error bit that is set in this register

will also set the [PERR] bit. However, abnormality that isn’t classified in the register can also trigger the [PERR] bit (e.g. detecting missing

of data or wrong data order.)

0: no comm error detected

1: detected abnormality of the received comm frame. BERR is asserted to the forwarded communication.

BERR_TAG

SYNC2

Indicates BERR bit is set in at least one byte in received response frame from stack device

0: received response frame doesn’t have BERR

1: received response frame has BERR

Timing information extracted from the demodulation of the preamble half-bit and the two full bits of synchronization is outside of the

expected window, this bit is set and the byte is not processed.

0: No fault

1: Fault

SYNC1

BIT

If the demodulation of the preamble half-bit and the two full bits of synchronization data have errors and the timing is likely not correct, this

bit is set and the byte is not processed.

0: No fault

1: Fault

The device has detected a data bit, however, the detection samples is not enough to guarantee a strong ‘1’or ‘0’.

0: No fault

1: Fault

7.5.39 Register: DEBUG_COMH_FRAME

Address: 0x2305

B7

B6

RSVD

0

B5

B4

B3

B2

B1

B0

RR_IERR

RR_SOF

RR_BYTE_ERR

RR_UNEXP

RR_CRC

0

R

RR_IERR

Detects initialization byte error in the received response frame. This may due to improper formatting of a byte such as a frame initialization

byte is expected, but start-of-frame (SOF) bit is not set, or an invalid frame type is selected. All bytes from VIF that follows are ignored until

a SOF bit is received (BQ79600 still forwards data from VIF to UART/SPI).

0: No fault

1: Fault

RR_SOF

Valid when [DIR_SEL] = 0. Detects a start-of-frame (SOF) error on COMH. The SOF bit shall only be set in the initialization frame but the

SOF bit is set in the current frame that is not expected.

0: No fault

1: Fault

RR_BYTE_ERR

Valid when [DIR_SEL] = 0. Detected any byte errors, other than the error in the initialization byte, in the received response frame. If the

byte err is on the last byte of the CRC, it would check CRC in addition to discarding the frame. This error can be triggered by one or more

error bit set in the DEBUG_COMH_PHY register. All bytes from VIF that follows are ignored until a SOF bit is received (BQ79600 still

forwards data from VIF to UART/SPI).

0: No fault

1: Fault

RR_UNEXP

RR_CRC

If [DIR_SEL] = 1, but device received response frame from COMH which is an invalid condition and device will set this error bit.

0: No fault

1: Fault

Indicates one or more COMH response frames being discarded due to CRC error.

0: No fault

1: Fault

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7.5.40 Register: DEBUG_COML_PHY

Address: 0x2306

B7

B6

RSVD

0

B5

B4

PERR

0

B3

B2

B1

B0

BIT

0

BERR_TAG

SYNC2

SYNC1

0

R

PERR

Pertain to received response frame from stack device only. PERR is a lump bit of all physical errors. Any error bit that is set in this register

will also set the [PERR] bit. However, abnormality that isn’t classified in the register can also trigger the [PERR] bit (e.g. detecting missing

of data or wrong data order.)

0: no comm error detected

1: detected abnormality of the received comm frame. BERR is asserted to the forwarded communication.

BERR_TAG

SYNC2

Indicates BERR bit is set in at least one byte in received response frame from stack device

0: received response frame doesn’t have BERR

1: received response frame has BERR

Timing information extracted from the demodulation of the preamble half-bit and the two full bits of synchronization is outside of the

expected window, this bit is set and the byte is not processed.

0: No fault

1: Fault

SYNC1

BIT

If the demodulation of the preamble half-bit and the two full bits of synchronization data have errors and the timing is likely not correct, this

bit is set and the byte is not processed.

0: No fault

1: Fault

The device has detected a data bit, however, the detection samples is not enough to guarantee a strong ‘1’or ‘0’.

0: No fault

1: Fault

7.5.41 Register: DEBUG_COML_FRAME

Address: 0x2307

B7

B6

RSVD

0

B5

B4

B3

B2

B1

B0

RR_IERR

RR_SOF

RR_BYTE_ERR

RR_UNEXP

RR_CRC

0

R

RR_IERR

Detects initialization byte error in the received response frame. This may due to improper formatting of a byte such as a frame initialization

byte is expected, but start-of-frame (SOF) bit is not set, or an invalid frame type is selected. All bytes from VIF that follows are ignored until

a SOF bit is received (BQ79600 still forwards data from VIF to UART/SPI).

0: No fault

1: Fault

RR_SOF

Valid when [DIR_SEL] = 1. Detects a start-of-frame (SOF) error on COML. The SOF bit shall only be set in the initialization frame but the

SOF bit is set in the current frame that is not expected.

0: No fault

1: Fault

RR_BYTE_ERR

Valid when [DIR_SEL] = 1. Detected any byte errors, other than the error in the initialization byte, in the received response frame. If the

byte err is on the last byte of the CRC, it would check CRC in addition to discarding the frame. This error can be triggered by one or more

error bit set in the DEBUG_COML_PHY register. All bytes from VIF that follows are ignored until a SOF bit is received (BQ79600 still

forwards data from VIF to UART/SPI).

0: No fault

1: Fault

RR_UNEXP

RR_CRC

If [DIR_SEL] = 0, but device received response frame from COML which is an invalid condition and device will set this error bit.

0: No fault

1: Fault

Indicates one or more COML response frames being discarded due to CRC error.

0: No fault

1: Fault

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8 Application and Implementation

备注

以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

This section is concerned with the external operation, what external components are required to add to the

device to make it usable in a particular design, and how to calculate the values for those external components.

8.2 Typical Applications

8.2.1 Bridge With Reverse Wakeup in UART

The following application circuit is used when user chooses to use UART interface and any of those features:

reverse wakeup, ring architecture, fault/heartbeat tone.

12V Battery

10

Low

Voltage

Domain

How

Voltage

Domain

50V 0.1uF

AFE fault

100K Real Time Clock

KEY ON

SBC

(PMIC)

3.3V/5V

CAN_WK

0.1uF

DVDD

INH

0.22uF

5.5V-40V

BAT

Twisted pair

cabling

CVDD

VIO

Ratio:1 to 1

0.22uF

51

100K

10K

COMHP

PESD5V0L2BT

Cap/

Cap+choke/

XFMR

100pF

BQ battery

monitor

BQ battery

monitor

GPIO0

MOSI/RX

MISO/TX

1K

GPIO1

GPIO2

Isolation

51

MCU

COMHN

COMLP

SCLK

nCS

BQ79600-Q1

GPIO3

100pF

GND

nUART/SPI (SPI_RDY)

NFAULT

GPIO4

GPIO5

51

PESD5V0L2BT

GND

Cap/

Cap+choke/

XFMR

100pF

GND

1K

Isolation

51

COMLN

GND

100pF

图8-1. Typical Bridge with Reverse Wakeup in UART Applications Circuit

8.2.1.1 Design Requirements

表8-1 describes the design parameters.

表8-1. Recommended Design Requirement

PARAMETER

VALUE

UART speed

1Mbps

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 MCU Interface (UART, NFAULT)

To select UART interface, connect nCS, nUART/SPI and SCLK pins to GND. UART interface includes RX/TX

pins. They are pulled up through a 10-100kΩresistor to VIO like figure above.

NFAULT pin, if not used, connect to GND. Otherwise, pull it up wtih 100kΩto VIO.

8.2.1.2.2 Daisy Chain Interface

Given that galvanic isolation is expected between BQ79600-Q1 and stack BQ devices, transformer isolation is

recommended. 节8.2.1 shows the interface components values.

Contact TI for transformer recommendations.

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8.2.1.2.3 INH Connection

INH pin is connected to the power management IC (PMIC) enable pin such that when reverse wakeup is

triggered, INH would be pulled towards BAT and enable PMIC. INH pin should always be lower than BAT pin.

The 100kΩconnected to INH in 节8.2.1 is to make sure INH pin potential is defined when INH driver is off.

8.2.1.3 Application Performance Plot

图8-2. Command and Response Frame for Read from 2 Stack Devices

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图8-3. Zoomed View of Response Frame for 8 Registers Read from Stack Devices

8.2.2 Bridge Without Reverse Wakeup in SPI

The following application circuit is used when user chooses to use SPI interface and none of those features:

reverse wakeup, ring architecture, fault/heartbeat tone.

12V Battery

Low

Voltage

Domain

How

Voltage

Domain

5V

Real Time Clock

KEY ON

SBC

(PMIC)

3.3V/5V

CAN_WK

0.1uF

DVDD

INH

0.22uF

BAT

Twisted pair

cabling

CVDD

VIO

Ratio:1 to 1

0.22uF

51

100K 100K 10K

10K

COMHP

PESD5V0L2BT

Cap/

Cap+choke/

XFMR

100pF

BQ battery

monitor

BQ battery

monitor

GPIO0

MOSI/RX

MISO/TX

1K

GPIO1

GPIO2

Isolation

51

MCU

COMHN

COMLP

SCLK

nCS

BQ79600-Q1

GPIO3

100pF

nUART/SPI (SPI_RDY)

NFAULT

GPIO4

GPIO5

51

10K

PESD5V0L2BT

GND

Cap/

Cap+choke/

XFMR

100pF

GND

1K

Isolation

51

COMLN

GND

100pF

RED is optional

图8-4. Typical Bridge without Reverse Wakeup in SPI Applications Circuit

8.2.2.1 Design Requirements

表8-2 describes the design parameters.

表8-2. Key Requirements

PARAMETER

VALUE

SPI speed

2 - 6Mbps

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8.2.2.2 Detailed Design Procedure

8.2.2.2.1 MCU Interface (SPI, SPI_RDY, NFAULT)

To select SPI interface, connect MOSI, MISO, SCLK, nCS, nUART/SPI as figure above shows. Connect

SPI_RDY to MCU GPIO port for SPI flow control use, 节7.3.2.1.2.2.1.

NFAULT pin, if not used, connect to GND. Otherwise, pull it up wtih 100KΩto VIO.

8.2.2.2.2 Daisy Chain Interface

Refer to 节8.2.1.2.2.

8.2.2.3 Application Performance Plot

See Application Performance Plot for application performanace curve.

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9 Power Supply Recommendations

The BQ79600-Q1 can be powered by either directly from 12-V battery (nominal 9 - 16V) or regulated 5-V supply.

The design consideration for both options are described in the table below.

表9-1. Supply Design Considerations

12-V BATTERY (nominal 9 - 16 V)

REGULATED 5-V SUPPLY

3.125 - 5.25V, decouple 0.1-µF

capacitor to gnd

VIO

BAT

3.125 - 5.25V, decouple 0.1-µF capacitor to gnd

4.75 - 5.25V, decouple 0.22-µF

capacitor to gnd

Put RC between supply battery and BAT pin, R = 10Ω, C = 0.1-µF capacitor.

Make sure BAT pin sees no less than 5.5V and no larger than 40V.

CVDD

DVDD

Decouple 0.22-µF capacitor to gnd

shorted to BAT

Decouple 0.22-µF capacitor to gnd

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10 Layout

The layout for this device must be designed carefully. Any design outside these guidelines can affect the

communication robustness and EMI performance. Care must be taken in the layout of signals to and from the

device to avoid coupling noise onto sensitive inputs. The layout of ground and power connections, as well as

communication signals, should also be made carefully.

10.1 Layout Guidelines

10.1.1 Ground Planes

It is very important to establish a clean grounding scheme to ensure best performance of the device. There is

one ground pin (GND) on the device. It is a good practice to use top and bottom PCB layers for signal routing,

and use middle layers as ground planes. Even on a PCB layer that is mainly for signal routing, it is good practice

to have a small island of ground pour if possible to provide a low-impedance ground, rather than simply a via

through the ground trace to an lower ground plane. Create a keep-out area (no other traces and no ground

plane) around the daisy chain components in all PCB layers.

There is a strong recommendation to have a minimum of 4 layers in the PCB, with one fully dedicated layer as

an unbroken VSS plane (except thermal reliefs). Avoid placing tracks on this layer to maintain the unbroken

integrity of the plane structure.

10.1.2 Bypass Capacitors for Power Supplies

The bypass capacitors of the following pins must be placed as close to the device pins as possible to ensure

proper performance.

• BAT, VIO, CVDD, DVDD

10.1.3 UART/SPI communication

The UART/SPI interface (MISO/TX, MOSI/RX, SCLK, nCS, nUART/SPI_RDY) between MCU and BQ79600-Q1

shall be kept as short and straight as possible for optimized EMC performance.

10.1.4 Daisy Chain Communication

It is important to have proper layout on the COMHP/N and COMLP/N circuits in order to have the best robust

daisy chain communication.

• Keep differential traces as short as possible and as straight as possible. Minimize turns and avoid any

looping on the traces.

• Keep the differential traces on the same layers. Run the trace in parallel with shielding and matching trace

impedance.

• Place the isolation components close to the connectors.

• Create a keep-out area (no other traces and no ground plane) around the daisy chain components in all PCB

layers.

10.2 Layout Example

This section presents the BQ79600-Q1 Evaluation Module (EVM) design as a layout example. Given the EVM

doesn't have an MCU, the example of UART/SPI connection layout is not optimized.

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图10-1. Top Layer Layout

图10-2. Signal 1 Layer Layout

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图10-3. Signal 2 Layer Layout

图10-4. Bottom Layer Layout

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11 Device and Documentation Support

11.1 Device Support

11.2 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索

现有解答或提出自己的问题，获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的使用条款。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

5

0

SMALL OUTLINE PACKAGE

SEATING

PLANE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX AREA

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

B

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

A

20

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16

1

16X (0.45)

SYMM

14X (0.65)

8

9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16

1

16X (0.45)

SYMM

14X (0.65)

8

9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ79600PWRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具备自动主机唤醒功能且符合功能安全标准的汽车类 SPI/UART 通信接口 \| PW \| 16 \| -40 to 125 通信
文件：	总71页 (文件大小：3519K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ79600PWRQ1 [TI]

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