CC2540F128_16 [TI]
2.4-GHz Bluetooth low energy System-on-Chip;
| 型号： | CC2540F128_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.4-GHz Bluetooth low energy System-on-Chip |
| 文件： | 总33页 (文件大小：770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CC2540F128, CC2540F256
www.ti.com
SWRS084 –OCTOBER 2010
2.4-GHz Bluetooth® low energy System-on-Chip
Check for Samples: CC2540F128, CC2540F256
1
FEATURES
•
Peripherals
23456
• True Single-Chip BLE Solution: CC2540 Can
–
–
–
–
12-Bit ADC with Eight Channels and
Configurable Resolution
Run Both Application and BLE Protocol Stack,
Includes Peripherals to Interface With Wide
Range of Sensors, Etc.
Integrated High-Performance Op-Amp and
Ultralow-Power Comparator
•
•
6-mm × 6-mm Package
RF
General-Purpose Timers (One 16-Bit, Two
8-Bit)
–
Bluetooth low energy technology
21 General-Purpose I/O Pins (19× 4 mA, 2×
20 mA)
Compatible
–
Excellent Link Budget (up to 97 dB),
Enabling Long-Range Applications Without
External Front End
–
–
32-kHz Sleep Timer With Capture
Two Powerful USARTs With Support for
Several Serial Protocols
–
–
Accurate Digital Received Signal-Strength
Indicator (RSSI)
–
–
–
–
–
–
Full-Speed USB Interface
IR Generation Circuitry
Suitable for Systems Targeting Compliance
With Worldwide Radio Frequency
Regulations: ETSI EN 300 328 and EN 300
440 Class 2 (Europe), FCC CFR47 Part 15
(US), and ARIB STD-T66 (Japan)
Powerful Five-Channel DMA
AES Security Coprocessor
Battery Monitor and Temperature Sensor
Each CC2540 Contains a Unique 48-bit
IEEE Address
•
•
Layout
•
Development Tools
–
–
–
Few External Components
–
–
CC2540 Mini Development Kit
Reference Design Provided
Royalty-Free Bluetooth low energy Protocol
6-mm × 6-mm QFN40 Package
Stack
Low Power
–
–
SmartRF™ Software
–
–
–
–
–
–
–
Active Mode RX Down to 19.6 mA
Supported by IAR Embedded Workbench™
Software for 8051
Active Mode TX (–6 dBm): 24 mA
Power Mode 1 (3-ms Wake-Up): 235 mA
Power Mode 2 (Sleep Timer On): 0.9 mA
Power Mode 3 (External Interrupts): 0.4 mA
Wide Supply Voltage Range (2 V–3.6 V)
APPLICATIONS
•
•
•
•
•
2.4-GHz Bluetooth low energy Systems
Mobile Phone Accessories
Sports and Leisure Equipment
Consumer Electronics
Human Interface Devices (Keyboard, Mouse,
Remote Control)
Full RAM and Register Retention in All
Power Modes
•
Microcontroller
–
–
–
High-Performance and Low-Power 8051
Microcontroller Core
•
•
USB Dongles
Health Care and Medical
In-System-Programmable Flash, 128 KB or
256 KB
8-KB SRAM
A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
5
6
SmartRF is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Supported by IAR Embedded Workbench is a trademark of IAR Systems AB.
ZigBee is a registered trademark of ZigBee Alliance.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CC2540F128, CC2540F256
SWRS084 –OCTOBER 2010
www.ti.com
DESCRIPTION
The CC2540 is a cost-effective, low-power, true system-on-chip (SoC) for Bluetooth low energy applications. It
enables robust BLE master or slave nodes to be built with very low total bill-of-material costs. The CC2540
combines an excellent RF transceiver with an industry-standard enhanced 8051 MCU, in-system programmable
flash memory, 8-KB RAM, and many other powerful supporting features and peripherals. The CC2540 is suitable
for systems where very low power consumption is required. Very low-power sleep modes are available. Short
transition times between operating modes further enable low power consumption.
The CC2540 comes in two different versions: CC2540F128/F256, with 128 and 256 KB of flash memory,
respectively.
Combined with the Bluetooth low energy protocol stack from Texas Instruments, the CC2540F128/F256 forms
the market’s most flexible and cost-effective single-mode Bluetooth low energy solution.
VDD (2 V–3.6 V)
WATCHDOG
TIMER
ON-CHIP VOLTAGE
REGULATOR
RESET_N
RESET
DCOUPL
XOSC_Q2
XOSC_Q1
32-MHz
POWER-ON RESET
BROWN OUT
CRYSTAL OSC
CLOCK MUX
and
CALIBRATION
P2_4
P2_3
P2_2
P2_1
P2_0
32.768-kHz
SLEEP TIMER
CRYSTAL OSC
HIGH-
32-kHz
SPEED
DEBUG
INTERFACE
POWER MANAGEMENT CONTROLLER
RC-OSC
RC-OSC
PDATA
XRAM
IRAM
SFR
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
RAM
SRAM
8051 CPU
CORE
MEMORY
ARBITRATOR
FLASH
FLASH
DMA
UNIFIED
IRQ CTRL
FLASH CTRL
1 KB SRAM
SRAM
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
ANALOG COMPARATOR
OP-AMP
FIFOCTRL
RADIO REGISTERS
AES
ENCRYPTION
AND
DECRYPTION
DS
ADC
Link Layer Engine
AUDIO/DC
DEMODULATOR
MODULATOR
USB_N
USB_P
USB
USART 0
USART 1
RECEIVE
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
RF_P
RF_N
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
DIGITAL
ANALOG
MIXED
B0301-05
2
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Product Folder Link(s): CC2540F128 CC2540F256
CC2540F128, CC2540F256
www.ti.com
SWRS084 –OCTOBER 2010
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
MAX
UNIT
Supply voltage
All supply pins must have the same voltage
3.9
V
VDD + 0.3,
Voltage on any digital pin
V
≤ 3.9
Input RF level
10
85
dBm
°C
Storage temperature range
–40
All pads, according to human-body model, JEDEC STD 22, method
A114
2
kV
V
ESD(2)
According to charged-device model, JEDEC STD 22, method C101
500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) CAUTION: ESD sensitive device. Precautions should be used when handing the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
MIN
–40
2
MAX UNIT
Operating ambient temperature range, TA
Operating supply voltage
85
°C
V
3.6
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Power mode 1. Digital regulator on; 16-MHz RCOSC and
32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD
and sleep timer active; RAM and register retention
235
Power mode 2. Digital regulator off; 16-MHz RCOSC and
32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, and
sleep timer active; RAM and register retention
µA
0.9
Icore
Core current consumption
Power mode 3. Digital regulator off; no clocks; POR active;
RAM and register retention
0.4
Low MCU activity: 32-MHz XOSC running. No radio or
peripherals. No flash access, no RAM access.
6.7
mA
Timer 1. Timer running, 32-MHz XOSC used
Timer 2. Timer running, 32-MHz XOSC used
Timer 3. Timer running, 32-MHz XOSC used
Timer 4. Timer running, 32-MHz XOSC used
Sleep timer, including 32.753-kHz RCOSC
ADC, when converting
90
90
mA
mA
mA
mA
mA
mA
Peripheral current consumption
(Adds to core current Icore for each
peripheral unit activated)
60
Iperi
70
0.6
1.2
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CC2540F128, CC2540F256
SWRS084 –OCTOBER 2010
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UNIT
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
WAKE-UP AND TIMING
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC
Power mode 1 → Active
4
120
410
ms
ms
ms
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of regulator and 16-MHz RCOSC
Power mode 2 or 3 → Active
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC,
with 32-MHz XOSC OFF
Active → TX or RX
With 32-MHz XOSC initially on
160
150
ms
ms
RX/TX turnaround
RADIO PART
RF frequency range
Data rate and modulation format
Programmable in 2-MHz steps
2402
2480
MHz
1 Mbps, GFSK, 250 kHz deviation
RF RECEIVE SECTION
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER(1)
PARAMETER
Receiver sensitivity(2)
Receiver sensitivity(2)
Saturation(3)
Co-channel rejection(3)
Adjacent-channel rejection(3)
Alternate-channel rejection(3)
Blocking(3)
Frequency error tolerance(4)
Symbol rate error tolerance(5)
TEST CONDITIONS
MIN TYP MAX
UNIT
dBm
dBm
dBm
dB
High-gain mode
Standard mode
–93
–87
6
–5
5
±1 MHz
±2 MHz
dB
30
–30
dB
dBm
kHz
ppm
Including both initial tolerance and drift
–250
–80
250
80
Conducted measurement with a 50-Ω single-ended load.
Complies with EN 300 328, EN 300 440 class 2, FCC CFR47,
Part 15 and ARIB STD-T-66
Spurious emission. Only largest spurious
emission stated within each band.
–75
dBm
RX mode, standard mode, no peripherals active, low MCU
activity, MCU at 250 kHz
19.6
22.1
Current consumption
mA
RX mode, high-gain mode, no peripherals active, low MCU
activity, MCU at 250 kHz
(1) 0.1% BER maps to 30.8% PER
(2) The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard
mode.
(3) Results based on standard gain mode
(4) Difference between center frequency of the received RF signal and local oscillator frequency
(5) Difference between incoming symbol rate and the internally generated symbol rate
4
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Product Folder Link(s): CC2540F128 CC2540F256
CC2540F128, CC2540F256
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SWRS084 –OCTOBER 2010
RF TRANSMIT SECTION
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dBm
dB
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting
4
Output power
Delivered to a single-ended 50-Ω load through a balun using minimum
recommended output power setting
–20
24
Programmable output power
range
Delivered to a single-ended 50 Ω load through a balun
Conducted measurement with a 50-Ω single-ended load. Complies
with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB
STD-T-66(1)
Spurious emissions
–41
dBm
TX mode, –23-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
21.1
23.8
TX mode, –6-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
Current consumption
mA
TX mode, 0-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
27
TX mode, 4-dBm output power, no peripherals active, low MCU
activity, MCU at 250 kHz
31.6
Differential impedance as seen from the RF port (RF_P and RF_N)
toward the antenna
Optimum load impedance
70 + j30
Ω
(1) Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC resonator in front of the
antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect both from the signal trace to a good RF ground.
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SWRS084 –OCTOBER 2010
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32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Crystal frequency
32
MHz
Crystal frequency accuracy
requirement(1)
–40
40 ppm
ESR
C0
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
6
1
60
7
Ω
pF
pF
ms
CL
10
16
0.25
The crystal oscillator must be in power down for a
guard time before it is used again. This
requirement is valid for all modes of operation. The
need for power-down guard time can vary with
crystal type and load.
Power-down guard time
3
ms
(1) Including aging and temperature dependency, as specified by [1]
32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Crystal frequency
32.768
kHz
Crystal frequency accuracy
requirement(1)
–40
40
ppm
ESR
C0
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
40
0.9
12
130
2
kΩ
pF
pF
s
CL
16
0.4
(1) Including aging and temperature dependency, as specified by [1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2540 EM reference design with Tw = 25°C and VDD = 3 V.
PARAMETER
Calibrated frequency(1)
TEST CONDITIONS
MIN
TYP
32.753
±0.2%
0.4
MAX UNIT
kHz
Frequency accuracy after calibration
Temperature coefficient(2)
Supply-voltage coefficient(3)
Calibration time(4)
%/°C
%/V
ms
3
2
(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
(2) Frequency drift when temperature changes after calibration
(3) Frequency drift when supply voltage changes after calibration
(4) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.
6
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SWRS084 –OCTOBER 2010
16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
Frequency(1)
TEST CONDITIONS
MIN
TYP
16
MAX
UNIT
MHz
Uncalibrated frequency accuracy
Calibrated frequency accuracy
Start-up time
±18%
±0.6%
10
ms
ms
Initial calibration time(2)
50
(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
(2) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
RSSI CHARACTERISTICS
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-gain mode
–99 to –44
Useful RSSI range(1)
dBm
Standard mode
High-gain mode
–90 to –35
Absolute uncalibrated RSSI accuracy(1)
Step size (LSB value)
±4
1
dB
dB
(1) Assuming CC2540 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
–109
–112
–119
MAX
UNIT
At ±1-MHz offset from carrier
Phase noise, unmodulated
carrier
At ±3-MHz offset from carrier
At ±5-MHz offset from carrier
dBc/Hz
ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2540 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12-bit
mv/°C
/ 0.1 V
°C
Output
1480
4.5
1
Temperature coefficient
Voltage coefficient
Measured using integrated ADC, internal band-gap voltage
reference, and maximum resolution
Initial accuracy without calibration
Accuracy using 1-point calibration
Current consumption when enabled
±10
±5
°C
0.5
mA
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OP-AMP CHARACTERISTICS
TA = 25°C, VDD = 3 V, . All measurement results are obtained using the CC2540 reference designs post-calibration.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Chopping Configuration, Register APCFG = 0x07, OPAMPMC = 0x03, OPAMPC = 0x01
Output maximum voltage
Output minimum voltage
Open-loop gain
VDD – 0.07
V
V
0.07
108
dB
MHz
V/ms
V
Gain-bandwidth product
Slew rate
2
107
Input maximum voltage
Intput minimum voltage
Input offset voltage
VDD + 0.13
–55
40
mV
mV
dB
mA
CMRR Common-mode rejection ratio
Supply current
90
0.4
1.1
1.7
f = 0.01 Hz to 1 Hz
Input noise voltage
nV/√(Hz)
f = 0.1 Hz to 10 Hz
Non-Chopping Configuration, Register APCFG = 0x07, OPAMPMC = 0x00, OPAMPC = 0x01
Output maximum voltage
Output minimum voltage
Open-loop gain
VDD – 0.07
V
V
0.07
108
dB
Gain-bandwidth product
Slew rate
2
MHz
V/ms
V
107
Input maximum voltage
Intput minimum voltage
Input offset voltage
VDD + 0.13
–55
0.8
90
mV
mV
dB
CMRR Common-mode rejection ratio
Supply current
0.4
60
mA
f = 0.01 Hz to 1 Hz
Input noise voltage
nV/√(Hz)
f = 0.1 Hz to 10 Hz
65
COMPARATOR CHARACTERISTICS
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2540 reference designs, post-calibration.
PARAMETER
Common-mode maximum voltage
Common-mode minimum voltage
Input offset voltage
TEST CONDITIONS
MIN
TYP MAX UNIT
VDD
–0.3
1
V
mV
µV/°C
mV/V
nA
Offset vs temperature
Offset vs operating voltage
Supply current
16
4
230
0.15
Hysteresis
mV
8
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SWRS084 –OCTOBER 2010
ADC CHARACTERISTICS
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
VDD is voltage on AVDD5 pin
VDD is voltage on AVDD5 pin
VDD is voltage on AVDD5 pin
Simulated using 4-MHz clock speed
Peak-to-peak, defines 0 dBFS
Single-ended input, 7-bit setting
Single-ended input, 9-bit setting
Single-ended input, 10-bit setting
Single-ended input, 12-bit setting
Differential input, 7-bit setting
Differential input, 9-bit setting
Differential input, 10-bit setting
Differential input, 12-bit setting
10-bit setting, clocked by RCOSC
12-bit setting, clocked by RCOSC
7-bit setting, both single and differential
MIN
0
TYP
MAX
VDD
VDD
VDD
UNIT
V
Input voltage
External reference voltage
0
V
External reference voltage differential
0
V
Input resistance, signal
Full-scale signal(1)
197
2.97
5.7
kΩ
V
7.5
9.3
10.3
6.5
ENOB(1)
Effective number of bits
bits
8.3
10
11.5
9.7
10.9
0–20
Useful power bandwidth
Total harmonic distortion
kHz
dB
Single ended input, 12-bit setting, –6
dBFS(1)
–75.2
–86.6
THD
Differential input, 12-bit setting, –6
dBFS(1)
Single-ended input, 12-bit setting(1)
Differential input, 12-bit setting(1)
70.2
79.3
Single-ended input, 12-bit setting, –6
dBFS(1)
Signal to nonharmonic ratio
dB
dB
78.8
88.9
>84
>84
Differential input, 12-bit setting, –6
dBFS(1)
Differential input, 12-bit setting, 1-kHz
sine (0 dBFS), limited by ADC resolution
CMRR
Common-mode rejection ratio
Crosstalk
Single ended input, 12-bit setting, 1-kHz
sine (0 dBFS), limited by ADC resolution
dB
Offset
Midscale
–3
0.68%
0.05
0.9
mV
Gain error
12-bit setting, mean(1)
12-bit setting, maximum(1)
12-bit setting, mean(1)
12-bit setting, maximum(1)
DNL
INL
Differential nonlinearity
Integral nonlinearity
LSB
LSB
4.6
13.3
10
12-bit setting, mean, clocked by RCOSC
12-bit setting, max, clocked by RCOSC
Single ended input, 7-bit setting(1)
Single ended input, 9-bit setting(1)
Single ended input, 10-bit setting(1)
Single ended input, 12-bit setting(1)
Differential input, 7-bit setting(1)
Differential input, 9-bit setting(1)
Differential input, 10-bit setting(1)
Differential input, 12-bit setting(1)
29
35.4
46.8
57.5
66.6
40.7
51.6
61.8
70.8
SINAD
(–THD+N)
Signal-to-noise-and-distortion
dB
(1) Measured with 300-Hz sine-wave input and VDD as reference.
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ADC CHARACTERISTICS (continued)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
7-bit setting
MIN
TYP
20
MAX
UNIT
9-bit setting
10-bit setting
12-bit setting
36
Conversion time
ms
68
132
1.2
4
Power consumption
mA
mV/V
mV/10°C
V
Internal reference VDD coefficient
Internal reference temperature coefficient
Internal reference voltage
0.4
1.15
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V.
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
16
32
MHz
See item 1, Figure 1. This is the shortest pulse that is recognized as
a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
RESET_N low duration
Interrupt pulse duration
1
µs
ns
See item 2, Figure 1.This is the shortest pulse that is recognized as
an interrupt request.
20
RESET_N
1
2
Px.n
T0299-01
Figure 1. Control Input AC Characteristics
10
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SWRS084 –OCTOBER 2010
SPI AC CHARACTERISTICS
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
250
250
TYP MAX UNIT
Master, RX and TX
Slave, RX and TX
Master
t1
SCK period
ns
SCK duty cycle
SSN low to SCK
50%
Master
63
63
63
63
t2
t3
ns
Slave
Master
SCK to SSN high
ns
Slave
t4
t5
t6
t7
MOSI early out
MOSI late out
MISO setup
MISO hold
Master, load = 10 pF
Master, load = 10 pF
Master
7
ns
ns
ns
ns
ns
ns
ns
ns
10
90
10
Master
SCK duty cycle
MOSI setup
MOSI hold
Slave
50%
t10
t11
t9
Slave
35
10
Slave
MISO late out
Slave, load = 10 pF
Master, TX only
Master, RX and TX
Slave, RX only
Slave, RX and TX
95
8
4
Operating frequency
MHz
8
4
SCK
t2
t3
SSN
t4
t5
MOSI
D0
X
D1
t6
t7
MISO
X
D0
X
T0478-01
Figure 2. SPI Master AC Characteristics
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SCK
t2
t3
SSN
t8
t9
MISO
D0
D0
X
D1
t10
t11
MOSI
X
X
T0479-01
Figure 3. SPI Slave AC Characteristics
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DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 125°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ns
fclk_dbg
Debug clock frequency (see Figure 4)
Allowed high pulse on clock (see Figure 4)
Allowed low pulse on clock (see Figure 4)
12
t1
t2
35
35
ns
EXT_RESET_N low to first falling edge on debug
clock (see Figure 6)
t3
t4
t5
167
83
ns
ns
ns
Falling edge on clock to EXT_RESET_N high (see
Figure 6)
EXT_RESET_N high to first debug command (see
Figure 6)
83
t6
t7
t8
Debug data setup (see Figure 5)
Debug data hold (see Figure 5)
Clock-to-data delay (see Figure 5)
2
4
ns
ns
ns
Load = 10 pF
30
Time
DEBUG_CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 4. Debug Clock – Basic Timing
Time
DEBUG_CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 5. Debug Enable Timing
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Time
DEBUG_CLK
P2_2
DEBUG_DATA
(to CC2540)
P2_1
DEBUG_DATA
(from CC2540)
P2_1
t6
t7
t8
T0438-02
Figure 6. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
Input capture pulse duration
1.5
tSYSCLK
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DC CHARACTERISTICS
TA = 25°C, VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Logic-0 input voltage
0.5
Logic-1 input voltage
2.5
–50
–50
V
Logic-0 input current
Input equals 0 V
50
50
nA
nA
kΩ
V
Logic-1 input current
Input equals VDD
I/O-pin pullup and pulldown resistors
Logic-0 output voltage, 4- mA pins
Logic-1 output voltage, 4-mA pins
20
Output load 4 mA
Output load 4 mA
0.5
2.4
V
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DEVICE INFORMATION
PIN DESCRIPTIONS
The CC2540 pinout is shown in Figure 7 and a short description of the pins follows.
CC2540
RHA Package
(Top View)
40 39 38 37 36 35 34 33 32 31
DGND_USB
USB_P
USB_N
DVDD_USB
P1_5
R_BIAS
1
2
30
29
28
27
26
25
24
23
22
21
AVDD4
AVDD1
AVDD2
RF_N
3
4
5
AGND
Ground Pad
P1_4
RF_P
6
P1_3
7
AVDD3
P1_2
XOSC_Q2
XOSC_Q1
8
P1_1
9
10
DVDD2
AVDD5
11 12 13 14 15 16 17 18 19 20
P0076-05
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 7. Pinout Top View
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PIN DESCRIPTIONS
PIN NAME
PIN
28
27
24
29
21
31
40
1
PIN TYPE
DESCRIPTION
AVDD1
AVDD2
AVDD3
AVDD4
AVDD5
AVDD6
DCOUPL
DGND_USB
DVDD_USB
DVDD1
DVDD2
GND
Power (analog) 2-V–3.6-V analog power-supply connection
Power (analog) 2-V–3.6-V analog power-supply connection
Power (analog) 2-V–3.6-V analog power-supply connection
Power (analog) 2-V–3.6-V analog power-supply connection
Power (analog) 2-V–3.6-V analog power-supply connection
Power (analog) 2-V–3.6-V analog power-supply connection
Power (digital)
Ground pin
Power (digital)
Power (digital)
Power (digital)
Ground
1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
Connect to GND
4
2-V–3.6-V digital power-supply connection
39
10
—
19
18
17
16
15
14
13
12
11
9
2-V–3.6-V digital power-supply connection
2-V–3.6-V digital power-supply connection
The ground pad must be connected to a solid ground plane.
P0_0
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Port 0.0
P0_1
Port 0.1
P0_2
Port 0.2
P0_3
Port 0.3
P0_4
Port 0.4
P0_5
Port 0.5
P0_6
Port 0.6
P0_7
Port 0.7
P1_0
Port 1.0 – 20-mA drive capability
P1_1
Port 1.1 – 20-mA drive capability
P1_2
8
Port 1.2
P1_3
7
Port 1.3
P1_4
6
Port 1.4
P1_5
5
Port 1.5
P1_6
38
37
36
35
34
33
Port 1.6
P1_7
Port 1.7
P2_0
Port 2.0
P2_1
Port 2.1
P2_2
Port 2.2
P2_3/
XOSC32K_Q2
Digital I/O,
Analog I/O
Port 2.3/32.768 kHz XOSC
P2_4/
XOSC32K_Q1
32
Digital I/O,
Analog I/O
Port 2.4/32.768 kHz XOSC
RBIAS
30
20
26
Analog I/O
Digital input
RF I/O
External precision bias resistor for reference current
Reset, active-low
RESET_N
RF_N
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P
25
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
USB_N
3
2
Digital I/O
Digital I/O
Analog I/O
Analog I/O
USB N
USB_P
USB P
XOSC_Q1
XOSC_Q2
22
23
32-MHz crystal oscillator pin 1 or external-clock input
32-MHz crystal oscillator pin 2
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BLOCK DIAGRAM
A block diagram of the CC2540 is shown in Figure 8. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
VDD (2 V–3.6 V)
WATCHDOG
TIMER
ON-CHIP VOLTAGE
REGULATOR
RESET_N
RESET
DCOUPL
XOSC_Q2
XOSC_Q1
32-MHz
POWER-ON RESET
BROWN OUT
CRYSTAL OSC
CLOCK MUX
and
CALIBRATION
P2_4
P2_3
P2_2
P2_1
P2_0
32.768-kHz
SLEEP TIMER
CRYSTAL OSC
HIGH-
32-kHz
SPEED
DEBUG
INTERFACE
POWER MANAGEMENT CONTROLLER
RC-OSC
RC-OSC
PDATA
XRAM
IRAM
SFR
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
RAM
SRAM
8051 CPU
CORE
MEMORY
ARBITRATOR
FLASH
FLASH
UNIFIED
DMA
IRQ CTRL
FLASH CTRL
1 KB SRAM
SRAM
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
ANALOG COMPARATOR
OP-AMP
FIFOCTRL
RADIO REGISTERS
AES
ENCRYPTION
AND
DECRYPTION
DS
ADC
Link Layer Engine
AUDIO/DC
DEMODULATOR
MODULATOR
USB_N
USB_P
USB
USART 0
USART 1
RECEIVE
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
RF_P
RF_N
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
DIGITAL
ANALOG
MIXED
B0301-05
Figure 8. CC2540 Block Diagram
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BLOCK DESCRIPTIONS
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in Figure 8 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is
an ultralow-power SRAM that retains its contents even when the digital part is powered off (power modes 2 and
3).
The 128/256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,
ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers
between a single SFR or XREG address and flash/SRAM.
Each CC2540 contains a unique 48-bit IEEE address that can be used as the public device address for a
Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth
specfication.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the
device is in a sleep mode (power modes 1 and 2) by bringing the CC2540 back to the active mode.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators
are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code
breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform
in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an
internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode
3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power modes 1
or 2.
A built-in watchdog timer allows the CC2540 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
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Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 is a 40-bit timer used by the Bluetooth low energy stack. It has a 16-bit counter with a configurable timer
period and a 24-bit overflow counter that can be used to keep track of the number of periods that have
transpired. A 40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is
received/transmitted or the exact time at which transmission ends. There are two 16-bit timer-compare registers
and two 24-bit overflow-compare registers that can be used to give exact timing for start of RX or TX to the radio
or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free
for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead
of using some oversampling scheme, and are thus well-suited for high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,
respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The
inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a
single-ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can
automate the process of periodic sampling or conversion over a sequence of channels.
The operational amplifier is intended to provide front-end buffering and gain for the ADC. Both inputs as well as
the output are available on pins, so the feedback network is fully customizable. A chopper-stabilized mode is
available for applications that need good accuracy with high gain.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.
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TYPICAL CHARACTERISTICS
RX CURRENT IN WAIT FOR SYNC
TX CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
32.5
32
20.5
20
TX Power Setting = 4 dBm
VCC = 3 V
Gain = Standard Setting
Input = -70 dBm
VCC = 3 V
19.5
19
31.5
31
18.5
30.5
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
G001
G002
Figure 9.
Figure 10.
RX SENSITIVITY
vs
TX POWER
vs
TEMPERATURE
TEMPERATURE
-83
-84
-85
-86
-87
-88
-89
-90
-91
-92
7
6
5
4
3
2
1
0
Gain = Standard Setting
VCC = 3 V
TX Power Setting = 4 dBm
VCC = 3 V
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
G003
G004
Figure 11.
Figure 12.
RX CURRENT IN WAIT FOR SYNC
TX CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
19.7
19.68
19.66
19.64
19.62
19.6
32
31.9
31.8
31.7
31.6
31.5
31.4
31.3
31.2
31.1
31
Gain = Standard Setting
Input = -70 dBm
TA = 25°C
TA = 25°C
TX Power Setting = 4 dBm
19.58
19.56
19.54
19.52
19.5
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply Voltage (V)
Supply Voltage (V)
G005
G006
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
RX SENSITIVITY
TX POWER
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
-87
-87.2
-87.4
-87.6
-87.8
-88
5
4.8
4.6
4.4
4.2
4
Gain = Standard Setting
TA = 25°C
TA = 25°C
TX Power Setting = 4 dBm
-88.2
-88.4
-88.6
-88.8
-89
3.8
3.6
3.4
3.2
3
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply Voltage (V)
Supply Voltage (V)
G007
G008
Figure 15.
Figure 16.
RX SENSITIVITY
vs
RX INTERFERER REJECTION (SELECTIVITY)
vs
FREQUENCY
INTERFERER FREQUENCY
-87
-87.2
-87.4
-87.6
-87.8
-88
60
50
40
30
20
10
0
Gain = Standard Setting
TA = 25°C
VCC = 3 V
-88.2
-88.4
-88.6
-88.8
-89
Gain = Standard Setting
TA = 25°C
VCC = 3 V
Wanted Signal at 2426 MHz
with -67 dBm Level
-10
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G009
G010
Figure 17.
Figure 18.
TX POWER
vs
FREQUENCY
5
TA = 25°C
TX Power Setting = 4 dBm
VCC = 3 V
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G011
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Table 1. Output Power and Current Consumption(1)(2)
Typical Output Power (dBm)
Typical Current Consumption (mA)
4
0
32
27
24
21
–6
–23
(1) Measured on Texas Instruments CC2540 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz.
(2) The transmitter output power setting is programmable using a TI BLE stack vendor-specific API command. The default value is 0 dBm.
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APPLICATION INFORMATION
Few external components are required for the operation of the CC2540. A typical application circuit is shown in
Figure 20.
Optional 32-kHz Crystal(1)
C331
2-V to 3.6-V Power Supply
C401
C321
R301
RBIAS 30
DGND_USB
USB_P
USB_N
DVDD_USB
P1_5
1
2
3
4
5
6
7
8
9
L251
C252
AVDD4 29
AVDD1 28
AVDD2 27
Antenna
(50 W)
C251
C261
L252
L253
C253
RF_N
RF_P
26
25
CC2540
L261
C262
P1_4
DIE ATTACH PAD
AVDD3 24
P1_3
XOSC_Q2
23
22
P1_2
XOSC_Q1
P1_1
AVDD5 21
10 DVDD2
XTAL1
C221
C231
Power Supply Decoupling Capacitors are Not Shown
Digital I/O Not Connected
S0383-03
(1) 32-kHz crystal is mandatory when running the chip in low-power modes, except if the link layer is in the standby
state (Vol. 6 Part B Section 1.1 in [1]).
NOTE: Different antenna alternatives will be provided as reference designs.
Figure 20. CC2540 Application Circuit
Table 2. Overview of External Components (Excluding Supply Decoupling Capacitors)
Component
C221
Description
Value
12 pF
12 pF
18 pF
1 pF
32-MHz xtal loading capacitor
32-MHz xtal loading capacitor
Part of the RF matching network
Part of the RF matching network
Part of the RF matching network
Part of the RF matching network
Part of the RF matching network
32-kHz xtal loading capacitor
32-kHz xtal loading capacitor
C231
C251
C252
C253
1 pF
C261
18 pF
1 pF
C262
C321
15 pF
15 pF
1 µF
C331
C401
Decoupling capacitor for the internal digital regulator
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SWRS084 –OCTOBER 2010
Table 2. Overview of External Components (Excluding Supply Decoupling Capacitors) (continued)
Component
L251
Description
Value
2 nH
1 nH
3 nH
2 nH
56 kΩ
Part of the RF matching network
Part of the RF matching network
Part of the RF matching network
Part of the RF matching network
L252
L253
L261
R301
Resistor used for internal biasing
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. The recommended balun shown
consists of C262, L261, C252, and L252.
Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal
oscillator. See 32-MHz CRYSTAL OSCILLATOR for details. The load capacitance seen by the 32-MHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C221 C231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz
crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current
consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is
given by:
1
CL =
+ Cparasitic
1
1
+
C321 C331
(2)
A series resistor may be used to comply with the ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C401) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
References
1. Bluetooth® Core Technical Specification document, version 4.0
http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip
2. CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications/CC2540
System-on-Chip Solution for 2.4-GHz Bluetooth low energy Applications (SWRU191)
Additional Information
Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and
standard-based wireless applications for use in industrial and consumer applications. Our selection includes RF
transceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for the
sub-1- and 2.4-GHz frequency bands.
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SWRS084 –OCTOBER 2010
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PACKAGE OPTION ADDENDUM
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11-Oct-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CC2540F128RHAR
CC2540F128RHAT
CC2540F256RHAR
CC2540F256RHAT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
40
40
40
40
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Request Free Samples
Purchase Samples
2500
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
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the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC2540F128RHAR
CC2540F128RHAT
CC2540F256RHAR
VQFN
VQFN
VQFN
RHA
RHA
RHA
40
40
40
2500
250
330.0
330.0
330.0
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
12.0
12.0
12.0
16.0
16.0
16.0
Q2
Q2
Q2
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CC2540F128RHAR
CC2540F128RHAT
CC2540F256RHAR
VQFN
VQFN
VQFN
RHA
RHA
RHA
40
40
40
2500
250
333.2
333.2
333.2
345.9
345.9
345.9
28.6
28.6
28.6
2500
Pack Materials-Page 2
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