CC3230SF12RGKR_技术文档

CC3230S, CC3230SF

www.ti.com

SWRS226 – FEBRUARY 2020

CC3230S and CC3230SF SimpleLink^™Wi-Fi^®2.4GHz Wireless MCU with Coexistence

•

Multilayered security features:

– Separate execution environments

– Networking security

1 Features

•

Multiple-core architecture, system-on-chip (SoC)

Multilayered security features, help developers

protect identities, data, and software IP

Low-power modes for battery powered application

Coexistence with BLE radios (CC13x2/CC26x2)

Network-assisted roaming

Industrial temperature: –40°C to +85°C

Wi-Fi CERTIFIED^®by the Wi-Fi Alliance^®

Application microcontroller subsystem:

– Arm^®Cortex^®-M4 core at 80 MHz

– User-dedicated memory

– Device identity and key

– Hardware accelerator cryptographic engines

(AES, DES, SHA/MD5, CRC)

– Application-level security (encryption,

authentication, access control)

– Initial secure programming

– Software tamper detection

– Secure boot

– Certificate signing request (CSR)

– Unique per device key pair

Application throughput:

– UDP: 16 Mbps, TCP: 13 Mbps

– Peak: 72 Mbps

Power-Management Subsystem:

– Integrated DC/DC converters support a wide

range of supply voltage:

•

256KB of RAM

Optional 1MB of executable flash

•

– Rich set of peripherals and timers

– 27 I/O pins with flexible multiplexing options

•

UART, I2S, I²C, SPI, SD, ADC,

8-bit parallel interface

Timers and PWM

•

VBAT wide-voltage mode: 2.1 V to 3.6 V

VIO is always tied with VBAT

•

Wi-Fi network processor subsystem:

– Wi-Fi^®core:

– Advanced low-power modes:

•

802.11b/g/n 2.4 GHz

Modes:

– Access Point (AP)

– Station (STA)

– Wi-Fi Direct^®

Security:

•

Shutdown: 1 µA, hibernate: 4.5 µA

Low-power deep sleep (LPDS): 120 µA

Idle connected (MCU in LPDS): 710 µA

RX traffic (MCU active): 59 mA

TX traffic (MCU active): 223 mA

•

Wi-Fi TX power:

– 18.0 dBm at 1 DSSS

– 14.5 dBm at 54OFDM

Wi-Fi RX sensitivity:

– WEP

– WPA^™/ WPA2^™PSK

– WPA2 Enterprise

– WPA3^™Personal

– –96 dBm at 1 DSSS

– –74.5 dBm at 54 OFDM

Clock source:

– 40.0-MHz crystal with internal oscillator

– 32.768-kHz crystal or external RTC

RGK package

– 64-pin, 9-mm × 9-mm very thin quad flat

nonleaded (VQFN) package, 0.5-mm pitch

Device supports SimpleLink™ MCU Platform

developer's ecosystem

– Internet and application protocols:

•

HTTPs server, mDNS, DNS-SD, DHCP

IPv4 and IPv6 TCP/IP stack

16 BSD sockets (fully secured TLS v1.2 and

SSL 3.0)

– Built-in power management subsystem:

•

Configurable low-power profiles (always,

intermittent, tag)

Advanced low-power modes

Integrated DC/DC regulators

•

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Submit Document Feedback

1

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

•

Building security systems & e-locks

Smoke detector

Water leak detector

2 Applications

•

For Internet of Things applications, such as:

– Building and home automation:

– Appliances

•

HVAc systems & thermostat

Video surveillance, video doorbells, and low-

power camera

•

Smart home remote control

– Asset tracking

– Factory automation

– Medical and healthcare

•

CPAP

– Grid infrastructure

3 Description

The SimpleLink^™Wi-Fi^®CC3230x wireless MCU comes in two variants: CC3230S and C3230SF.

•

The CC3230S includes 256KB of RAM, IoT networking security, device identity/keys, as well as, MCU level

security features such as file system encryption, user IP (MCU image) encryption, secure boot and debug

security.

•

The CC3230SF builds on the CC3230S and integrates a user-dedicated 1MB of executable flash in addition

to the 256KB of RAM.

Simplify your IoT design with a Wi-Fi CERTIFIED™ wireless microcontroller (MCU). The SimpleLink^™Wi-Fi^®

CC3230x device family is a system-on-chip (SoC) solution that integrates two processors within a single chip,

including:

•

Application processor: Arm^®Cortex^®-M4 MCU with a user-dedicated 256KB of RAM and an optional 1MB of

executable flash

•

Network processor to run all Wi-Fi and internet logical layers. This ROM-based subsystem completely

offloads the host MCU and includes an 802.11b/g/n 2.4 GHz radio, baseband, and MAC with a powerful

hardware cryptography engine

These devices introduce new capabilities that further simplify the connectivity of things to the internet. The main

new features include

•

Bluetooth^®Low Energy and Wi-Fi 2.4-GHz radio coexistence (CC13x2/CC26x2)

Antenna selection

Up to 16 concurrent secure sockets

Certificate sign request (CSR)

Online certificate status protocol (OCSP)

Wi-Fi Alliance^®certified IoT power-saving features (such as BSS max idle, DMS, and proxy ARP)

Hostless mode for offloading template packet transmissions

Network-assisted roaming

The CC3230x device family is part of the SimpleLink™ MCU platform—a common, easy-to-use development

environment based on a single-core software development kit (SDK) with a rich tool set and reference designs.

The E2E™ community supports Wi-Fi, Bluetooth^®low energy, Sub-1 GHz, and host MCUs. For more

information, visit www.ti.com/simplelink or www.ti.com/simplelinkwifi.

Device Information ⁽¹⁾

PART NUMBER

CC3230SM2RGKR

CC3230SF12RGKR

PACKAGE

VQFN (64)

BODY SIZE (NOM)

9.00 mm × 9.00 mm

(1) For all available packages, see Section 12.

2

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

4 Functional Block Diagrams

Figure 4-1 shows the functional block diagram of the CC3230x SimpleLink Wi-Fi solution.

SPI

Flash

SPI

Peripheral

I²C

Peripheral

SSPI

GSPI

I2C

V_CCWide voltage

(2.1 to 3.6V)

BLE / 2.4 Wi-Fi

Antenna

32.768-kHz

Crystal

RF_BG

CC3230x

Wi-Fi /

BLE RF

Switch

SPDT

RF

Switch

2.4-GHz

BPF

BLE

Device

40-MHz

Crystal

COEX_IO

GPIO/

PWM

Parallel

Port

ANT_SEL_IO

I2S

BLE / 2.4 Wi-Fi

Antenna

Miscellaneous

Peripherals

Camera

sensor

Audio

codec

When using the antenna selection feature (dual antenna), an SPDT switch and 2 GPIO lines are required.

Figure 4-1. CC3230x Functional Block Diagram

Submit Document Feedback

3

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Figure 4-1 shows the hardware overview for the CC3230x device.

Figure 4-2. CC320x Hardware Overview

4

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Figure 4-3 shows an overview of the embedded software in the CC3230x device.

Customer Application

NetApp

BSD Socket

Wi-Fi^®

SimpleLink™ MCU Driver APIs

Host Interface

Network Apps

WLAN Security

and Management

TCP/IP Stack

WLAN MAC and PHY

Figure 4-3. CC3230x Embedded Software Overview

Submit Document Feedback

5

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................2

3 Description.......................................................................2

4 Functional Block Diagrams............................................ 3

5 Revision History.............................................................. 6

6 Device Comparison.........................................................7

6.1 Related Products........................................................ 8

7 Terminal Configuration and Functions..........................9

7.1 Pin Diagram................................................................ 9

7.2 Pin Attributes.............................................................10

7.3 Signal Descriptions................................................... 19

7.4 Pin Multiplexing.........................................................27

7.5 Drive Strength and Reset States for Analog and

8.13 WLAN Transmitter Out-of-Band Emissions.............42

8.14 BLE/2.4 GHz Radio Coexistence and WLAN

Coexistence Requirements......................................... 43

8.15 Thermal Resistance Characteristics for RGK

Package...................................................................... 43

8.16 Timing and Switching Characteristics..................... 43

9 Detailed Description......................................................62

9.1 Overview...................................................................62

9.2 Arm^®Cortex^®-M4 Processor Core Subsystem.........62

9.3 Wi-Fi^®Network Processor Subsystem..................... 63

9.4 Security.....................................................................65

9.5 Power-Management Subsystem...............................67

9.6 Low-Power Operating Mode..................................... 68

9.7 Memory.....................................................................70

9.8 Restoring Factory Default Configuration...................73

9.9 Boot Modes...............................................................74

9.10 Hostless Mode........................................................ 75

10 Applications, Implementation, and Layout............... 76

10.1 Application Information........................................... 76

10.2 PCB Layout Guidelines...........................................84

11 Device and Documentation Support..........................88

11.1 Tools and Software..................................................88

11.2 Firmware Updates...................................................89

11.3 Device Nomenclature..............................................89

11.4 Documentation Support.......................................... 90

11.5 Related Links.......................................................... 92

11.6 Trademarks............................................................. 92

12 Mechanical, Packaging, and Orderable

Digital Multiplexed Pins............................................... 29

7.6 Pad State After Application of Power to Device,

Before Reset Release................................................. 29

7.7 Connections for Unused Pins................................... 30

8 Specifications................................................................ 31

8.1 Absolute Maximum Ratings...................................... 31

8.2 ESD Ratings............................................................. 31

8.3 Power-On Hours (POH)............................................31

8.4 Recommended Operating Conditions.......................31

8.5 Current Consumption Summary (CC3230S)............ 32

8.6 Current Consumption Summary (CC3230SF).......... 34

8.7 TX Power Control......................................................35

8.8 Brownout and Blackout Conditions...........................37

8.9 Electrical Characteristics for GPIO Pins................... 38

8.10 Electrical Characteristics for Pin Internal Pullup

and Pulldown...............................................................39

8.11 WLAN Receiver Characteristics..............................40

8.12 WLAN Transmitter Characteristics..........................41

Information.................................................................... 93

12.1 Package Option Addendum....................................94

5 Revision History

DATE

REVISION

NOTES

February 2020

*

Initial Release

6

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

6 Device Comparison

Table 6-1 lists the features supported across different CC3x3x devices.

Table 6-1. Comparison of Device Features

DEVICE

FEATURE

CC3130

CC3135

CC3230S

CC3230SF

CC3235S

CC3235SF

Wireless

microcontroller

802.11a/b/g/n

IPv4, IPv6

16

Wireless

microcontroller

Classification

Network Processor

Wireless microcontroller

Standard

802.11b/g/n

IPv4, IPv6

16

802.11a/b/g/n

IPv4, IPv6

16

802.11b/g/n

IPv4, IPv6

16

802.11b/g/n

IPv4, IPv6

16

802.11a/b/g/n

IPv4, IPv6

16

TCP/IP stack

Sockets

9-mm × 9-mm

VQFN

9-mm × 9-mm

VQFN

Package

9-mm × 9-mm VQFN 9-mm × 9-mm VQFN

9-mm × 9-mm VQFN

ON-CHIP APPLICATION MEMORY

Flash

RAM

—

1MB

—

1MB

256KB

RF FEATURES

2.4 GHz

Frequency

2.4 GHz

Yes

2.4 GHz, 5 GHz

Yes

2.4 GHz

Yes

2.4 GHz, 5 GHz 2.4 GHz, 5 GHz

Coexistence with

BLE Radio

Yes

SECURITY FEATURES

Secure boot

—

Yes

No

Yes

FIPS 140-2

Level 1

No

Yes

No

Certification⁽¹⁾

File system

security

File system

security

File system security

Secure key storage

Software tamper

File system security

Secure key storage

File system security

Secure key storage

File system security

Secure key storage

Secure key

storage

Secure key

storage

Enhanced

Software tamper

detection

Software tamper

detection

Software tamper

detection

Software tamper Software tamper

detection

application level detection

security

detection

Cloning protection

Cloning

Initial secure

programming

Initial secure

programming

Initial secure

programming

Initial secure

programming

protection

Initial secure

programming

Initial secure

programming

Wi-Fi level of

security

WEP, WPS, WPA / WPA2 PSK, WPA2 (802.1x), WPA3

Unique device identity

Trusted root-certificate catalog

TI Root-of-trust public key

Additional

networking

security

Online certificate status protocol (OCSP)

Certificate signing request (CSR)

Unique per-device key pair

Hardware

acceleration

Hardware crypto engines

(1) For exact status of FIPS certification for a specific part number, please refer to https://csrc.nist.gov/publications/fips.

Submit Document Feedback

7

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

6.1 Related Products

For information about other devices in this family of products or related products, see the links that follow.

The SimpleLink™ MCU This portfolio offers a single development environment that delivers flexible

Portfolio

hardware, software, and tool options for customers developing wired and wireless

applications. With 100 percent code reuse across host MCUs, Wi-Fi^®, Bluetooth^®low

energy, Sub-1 GHz devices and more, choose the MCU or connectivity standard that

fits your design. A one-time investment with the SimpleLink™ software development

kit (SDK) allows you to reuse often, opening the door to create unlimited applications.

SimpleLink™ Wi-Fi^®

Family

This device platform offers several Internet-on-a chip^™solutions, which address the

need of battery-operated, security-enabled products. Texas Instruments offers a

single-chip wireless microcontroller and a wireless network processor that can be

paired with any MCU, allowing developers to design new Wi-Fi^®products or upgrade

existing products with Wi-Fi^®capabilities.

BoosterPack™ Plug-in Extend the functionality of the TI LaunchPad^™Development Kit with the

Module

BoosterPack^™Plug-in Module. The application-specific BoosterPack Plug-in Module

allows you to explore a broad range of applications, including capacitive touch,

wireless sensing, LED Lighting control, and more. Stack multiple BoosterPack Plug-

in Modules onto a single LaunchPad Development Kit to further enhance the

functionality of your design.

Reference Designs

Find reference designs leveraging the best in TI technology – from analog and power

management to embedded processors.

The SimpleLink™ Wi- The SDK contains drivers for the CC3230 programmable MCU, sample applications,

Fi^®SDK

and documentation required to start development with CC3230x solutions.

8

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

7 Terminal Configuration and Functions

7.1 Pin Diagram

Figure 7-1 shows pin assignments for the 64-pin VQFN package.

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

nRESET

VDD_RAM

GPIO0

RF_BG

RTC_XTAL_P

ANTSEL2

RTC_XTAL_N

GPIO30

ANTSEL1

NC

VIN_IO2

NC

GPIO1

NC

VDD_DIG2

LDO_IN2

VDD_PLL

WLAN_XTAL_P

WLAN_XTAL_N

SOP2

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

TMS

TCK

GPIO28

TDO

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

16

NC = No internal connection

Figure 7-1. Top View Pin Assignment for 64-Pin VQFN

Submit Document Feedback

9

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

7.2 Pin Attributes

The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in

the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of

hardware configuration (at device reset) and register control.

Note

TI highly recommends using SysConfig to obtain the desired pinout. In addition refer to the user guide

within the SimpleLink™ CC32XX Software Development Kit (SDK)

The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does

not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used.

Section 7.2.1 and Table 7-1 list the pin descriptions and attributes. Section 7.3.1 lists the signal descriptions.

Table 7-2 presents an overall view of pin multiplexing. All pin multiplexing options are configurable using the pin

mux registers.

The following special considerations apply:

•

All I/Os support drive strengths of 2, 4, and 6 mA. The drive strength is individually configurable for each pin.

All I/Os support 10-µA pullup and pulldown resistors.

The V_IOand V_BATsupplies must be tied together at all times.

By default, all I/Os float in the Hibernate state. However, the default state can be changed by software.

All digital I/Os are nonfail-safe.

Note

If an external device drives a positive voltage to the signal pads and the CC3230x device is not

powered, DC is drawn from the other device. If the drive strength of the external device is adequate,

an unintentional wakeup and boot of the CC3230x device can occur. To prevent current draw, TI

recommends any one of the following conditions:

•

All devices interfaced to the CC3230x device must be powered from the same power rail as the

chip.

•

Use level shifters between the device and any external devices fed from other independent rails.

The nRESET pin of the CC3230x device must be held low until the V_BATsupply to the device is

driven and stable.

•

All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the

TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.

The ADC inputs are tolerant up to 1.8 V (see Section 8.16.6.6.1 for more details about the usable

range of the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to

prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the

digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter

disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For

more information, see Section 7.5.

10

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

7.2.1 Pin Descriptions

PINS

SELECT AS

WAKEUP

SOURCE

CONFIGURE

ADDITIONAL

ANALOG MUX

MUXED

WITH JTAG

TYPE

DESCRIPTION

NO.

NAME

1

2

3

4

5

6

7

8

9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

I/O

General-purpose input or output

Internal digital core voltage

No

Yes

No

N/A

No

N/A

I/O

Yes

No

I/O

No

I/O

No

I/O

Yes

N/A

VDD_DIG1

Power

I/O power supply (same as

battery voltage)

10

11

12

13

14

15

16

VIN_IO1

Power

N/A

No

N/A

No

N/A

No

FLASH_SPI_CLK

FLASH_SPI_DOUT

FLASH_SPI_DIN

FLASH_SPI_CS

GPIO22

O

Serial flash interface: SPI clock

Serial flash interface: SPI data

out

I

Serial flash interface: SPI data in

Serial flash interface: SPI chip

select

O

I/O

General-purpose input or output

JTAG interface: data input

Muxed with

JTAG TDI

TDI

No

Muxed with

JTAG TDO

17

18

TDO

I/O

JTAG interface: data output

Yes

No

GPIO28

General-purpose input or output

No

Muxed with

JTAG/

SWD-TCK

19

TCK

TMS

I/O

JTAG / SWD interface: clock

No

Muxed with

JTAG/

SWD-TMSC

JTAG / SWD interface: mode

select or SWDIO

20

21⁽²⁾

22

SOP2

O

Configuration sense-on-power

40-MHz XTAL

No

WLAN_XTAL_N

Analog

N/A

40-MHz XTAL or TCXO clock

input

23

24

25

WLAN_XTAL_P

VDD_PLL

Analog

Power

N/A

Internal analog voltage

Analog RF supply from analog

DCDC output

LDO_IN2

26

NC

—

O

No Connect

N/A

No

N/A

No

N/A

No

27

NC

No Connect

28

NC

No Connect

29⁽¹⁾

30⁽¹⁾

31

ANTSEL1

ANTSEL2

RF_BG

Antenna selection control

RF BG band: 2.4 GHz TX, RX

O

No

RF

N/A

Master chip reset input. Active

low input.

32

33

nRESET

I

N/A

RF power amplifier (PA) input

from PA DC-DC output

VDD_PA_IN

Power

34

35

SOP1

SOP0

I

Configuration sense-on-power 1

Configuration sense-on-power 0

N/A

Submit Document Feedback

11

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

PINS

SELECT AS

WAKEUP

SOURCE

CONFIGURE

ADDITIONAL

ANALOG MUX

MUXED

WITH JTAG

TYPE

DESCRIPTION

NO.

36

NAME

Analog RF supply from analog

DCDC output

LDO_IN1

Power

N/A

Analog DC-DC supply input

(same as battery voltage)

37

38

39

40

VIN_DCDC_ANA

DCDC_ANA_SW

VIN_DCDC_PA

DCDC_PA_SW_P

Analog DC/DC converter

switching node

PA DC/DC converter input supply

(same as battery voltage)

PA DC/DC converter +ve

switching node

PA DC/DC converter –ve

switching node

41

42

43

DCDC_PA_SW_N

DCDC_PA_OUT

DCDC_DIG_SW

Power

N/A

PA DC/DC converter output.

Digital DC/DC converter switching

node

Digital DC/DC converter supply

input (same as battery voltage)

44

VIN_DCDC_DIG

Power

I/O

N/A

No

N/A

No

Analog2 DCDC converter +ve

switching node

User configuration

not required ⁽³⁾

45⁽⁴⁾

DCDC_ANA2_SW_P

Analog2 DC-DC converter -ve

switching node

46

47

48

49

50

DCDC_ANA2_SW_N

VDD_ANA2

VDD_ANA1

VDD_RAM

Power

Analog

I/O

N/A

No

N/A

No

Analog2 DC-DC output

Analog1 power supply fed by

ANA2 DC-DC output

SRAM LDO output

User configuration

not required ⁽³⁾

GPIO0

General-purpose input or output

32.768-kHz XTAL_P or external

CMOS level clock input

51

RTC_XTAL_P

RTC_XTAL_N

GPIO30

Analog

I/O

N/A

No

N/A

No

User configuration

not required ^{(3) (7)}

52⁽⁵⁾

53

32.768-kHz XTAL_N

User configuration

not required ⁽³⁾

General-purpose input or output

No

54

55

56

VIN_IO2

GPIO1

Analog

I/O

Chip supply voltage (VBAT)

General-purpose input or output

Internal digital core voltage

N/A

No

N/A

No

N/A

No

VDD_DIG2

Analog

N/A

Analog input (1.5V max) or

general-purpose input or output

57⁽⁶⁾

58⁽⁶⁾

59⁽⁶⁾

60⁽⁶⁾

GPIO2

GPIO3

GPIO4

GPIO5

I/O

Wake-up source

See ⁽⁸⁾

No

Analog input (1.5V max) or

general-purpose input or output

No

Wake-up source

No

Analog input (1.5V max) or

general-purpose input or output

Analog input (1.5V max) or

general-purpose input or output

61

62

63

64

GPIO6

GPIO7

GPIO8

GPIO9

I/O

General-purpose input or output

No

12

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

PINS

NAME

SELECT AS

WAKEUP

SOURCE

CONFIGURE

ADDITIONAL

ANALOG MUX

MUXED

WITH JTAG

TYPE

DESCRIPTION

NO.

Thermal pad and electrical

ground

GND_TAB

—

N/A

(1) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3230x device

between two antennas. These pins must not be used for other functionalities.

(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(3) Device firmware automatically enables the digital path during ROM boot.

(4) Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the

CC3230SF device. For the CC3230S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.

(5) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level

configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some

applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,

the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to

automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent

false detection, TI recommends using pin 52 for output-only functions.

(6) This pin is shared by the ADC inputs and digital I/O pad cells.

(7) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor.

(8) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always

connected and must be made Hi-Z before enabling the ADC switch.

Table 7-1. Pin Attributes

PAD STATES

Hib⁽⁴⁾

NO.

SIGNAL

TYPE⁽²⁾

PIN MUX

ENCODING

SIGNAL

DIRECTION

SIGNAL NAME⁽¹⁾

LPDS⁽³⁾

Hi-Z, Pull, Drive

1

nRESET = 0

GPIO10 (PN)

I2C_SCL

0

1

I/O

I/O (open drain)

GT_PWM06

UART1_TX

SDCARD_CLK

GT_CCP01

GPIO11 (PN)

I2C_SDA

3

O

Hi-Z, Pull,

Drive

1

I/O

Hi-Z

7

O

6

O

0

12

0

I

Hi-Z, Pull, Drive

0

I/O

1

I/O (open drain)

GT_PWM07

pXCLK(XVCLK)

SDCARD_CMD

UART1_RX

GT_CCP02

MCAFSX

3

O

4

O

Hi-Z, Pull,

Drive

2

I/O

Hi-Z

6

I/O (open drain)

Hi-Z, Pull, Drive

1

7

I

12

13

0

I

O

GPIO12 (PN)

McACLK

I/O

3

O

pVS(VSYNC)

I2C_SCL

4

I

Hi-Z, Pull,

Drive

3

4

I/O

Hi-Z

5

I/O (open drain)

UART0_TX

GT_CCP03

GPIO13 (PN)

I2C_SDA

7

O

12

0

I

Hi-Z, Pull, Drive

I/O

5

I/O (open drain)

Hi-Z, Pull,

Drive

pHS(HSYNC)

UART0_RX

GT_CCP04

4

I

Hi-Z, Pull, Drive

7

12

Submit Document Feedback

13

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Table 7-1. Pin Attributes (continued)

PAD STATES

Hib⁽⁴⁾

SIGNAL

TYPE⁽²⁾

PIN MUX

ENCODING

SIGNAL

DIRECTION

SIGNAL NAME⁽¹⁾

NO.

LPDS⁽³⁾

nRESET = 0

GPIO14 (PN)

I2C_SCL

0

5

I/O

I/O (open drain)

Hi-Z, Pull,

Drive

5

6

GSPI_CLK

I/O

7

I/O

Hi-Z, Pull, Drive

Hi-Z

pDATA8(CAM_D4)

GT_CCP05

4

I

12

0

I

GPIO15 (PN)

I2C_SDA

I/O

5

I/O (open drain)

GSPI_MISO

7

I/O

I

Hi-Z, Pull,

Drive

Hi-Z, Pull, Drive

Hi-Z

pDATA9(CAM_D5)

GT_CCP06

4

13

8

I

SDCARD_ DATA0

GPIO16 (PN)

GSPI_MOSI

I/O

I

0

Hi-Z, Pull, Drive

1

7

pDATA10(CAM_D6)

UART1_TX

4

Hi-Z, Pull,

Drive

7

8

I/O

Hi-Z

5

O

GT_CCP07

13

8

I

Hi-Z, Pull, Drive

0

SDCARD_CLK

GPIO17 (PN)

UART1_RX

O

0

I/O

I

5

Hi-Z, Pull,

Drive

GSPI_CS

7

I/O

I

Hi-Z, Pull, Drive

pDATA11 (CAM_D7)

SDCARD_ CMD

VDD_DIG1 (PN)

VIN_IO1

4

8

I/O

N/A

9

—

N/A

10

Hi-Z, Pull,

Drive⁽⁵⁾

Hi-Z, Pull,

Drive

11

12

13

14

FLASH_SPI_CLK

FLASH_SPI_DOUT

FLASH_SPI_DIN

FLASH_SPI_CS

O

I

N/A

O

I

Hi-Z

Hi-Z, Pull,

Drive⁽⁵⁾

Hi-Z, Pull,

Drive

Hi-Z, Pull,

Drive⁽⁵⁾

Hi-Z

Hi-Z, Pull,

Drive

O

1

GPIO22 (PN)

McAFSX

0

7

5

1

0

2

9

1

0

5

2

9

4

6

I/O

Hi-Z, Pull,

Drive

15

16

I/O

O

Hi-Z, Pull, Drive

Hi-Z

GT_CCP04

TDI (PN)

I

Hi-Z, Pull, Drive

GPIO23

I/O

Hi-Z, Pull,

Drive

UART1_TX

I2C_SCL

TDO (PN)

GPIO24

O

1

I/O (open drain)

Hi-Z, Pull, Drive

O

I/O

Driven high

in SWD;

driven low in

4-wire JTAG

PWM0

O

17

UART1_RX

I2C_SDA

GT_CCP06

McAFSX

I/O

I

Hi-Z, Pull, Drive

Hi-Z

I/O (open drain)

I

O

14

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

www.ti.com

SWRS226 – FEBRUARY 2020

Table 7-1. Pin Attributes (continued)

PAD STATES

SIGNAL

TYPE⁽²⁾

PIN MUX

ENCODING

SIGNAL

DIRECTION

SIGNAL NAME⁽¹⁾

LPDS⁽³⁾

Hib⁽⁴⁾

nRESET = 0

NO.

Hi-Z, Pull,

Drive

18

GPIO28 (PN)

I/O

0

I/O

Hi-Z, Pull, Drive

Hi-Z

TCK (PN)

GT_PWM03

TMS (PN)

GPIO29

1

8

I

Hi-Z, Pull,

Drive

19

20

Hi-Z, Pull, Drive

Hi-Z

O

1

I/O

O

Hi-Z, Pull,

Drive

I/O

0

GPIO25

0

Hi-Z, Pull, Drive

GT_PWM02

9

O

Hi-Z, Pull, Drive

21⁽⁶⁾McAFSX

O

2

O

Hi-Z, Pull, Drive

Driven low

Hi-Z

TCXO_EN

N/A

See ⁽⁹⁾

N/A

O

0

SOP2 (PN)

I

Hi-Z, Pull, Drive

22

23

24

25

26

27

28

WLAN_XTAL_N

—

N/A

WLAN_XTAL_P

VDD_PLL

LDO_IN2

NC

Hi-Z, Pull,

Drive

29⁽¹²⁾ANTSEL1

30⁽¹²⁾ANTSEL2

O

0

O

Hi-Z, Pull, Drive

Hi-Z

Hi-Z, Pull,

Drive

31

32

33

34

35

36

37

38

39

40

41

42

43

44

RF_BG

—

N/A

0

N/A

I/O

I

N/A

nRESET

VDD_PA_IN

SOP1

SOP0

LDO_IN1

VIN_DCDC_ANA

DCDC_ANA_SW

VIN_DCDC_PA

DCDC_PA_SW_P

DCDC_PA_SW_N

DCDC_PA_OUT

DCDC_DIG_SW

VIN_DCDC_DIG

GPIO31

UART0_RX

McAFSX

9

12

O

I/O

Hi-Z

UART1_RX

McAXR0

2

I

45⁽⁷⁾

6

I/O

GSPI_CLK

7

DCDC_ANA2_SW_P

(PN)

—

See ⁽⁸⁾

N/A

46

47

DCDC_ANA2_SW_N

VDD_ANA2

—

N/A

Submit Document Feedback

15

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Table 7-1. Pin Attributes (continued)

PAD STATES

Hib⁽⁴⁾

SIGNAL

TYPE⁽²⁾

PIN MUX

ENCODING

SIGNAL

DIRECTION

SIGNAL NAME⁽¹⁾

NO.

LPDS⁽³⁾

nRESET = 0

48

49

VDD_ANA1

VDD_RAM

GPIO0 (PN)

UART0_CTS

McAXR1

—

N/A

I/O

I

N/A

0

Hi-Z, Pull, Drive

1

12

6

I/O

I

GT_CCP00

GSPI_CS

7

Hi-Z, Pull,

Drive

50

I/O

Hi-Z

9

I/O

O

UART1_RTS

UART0_RTS

McAXR0

10

3

O

1

4

I/O

N/A

O

Hi-Z, Pull, Drive

N/A

51

RTC_XTAL_P

RTC_XTAL_N (PN)

GPIO32

—

O

N/A

0

McACLK

2

O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

52⁽¹⁰⁾

Hi-Z

McAXR0

4

O

UART0_RTS

GSPI_MOSI

GPIO30 (PN)

UART0_TX

McACLK

6

O

1

8

O

Hi-Z, Pull, Drive

1

0

I/O

O

9

2

O

Hi-Z, Pull,

Drive

53

I/O

Hi-Z

McAFSX

3

O

Hi-Z, Pull, Drive

GT_CCP05

GSPI_MISO

VIN_IO2

4

I

7

I/O

N/A

I/O

O

54

55

56

—

I/O

—

N/A

Hi-Z

N/A

Hi-Z

GPIO1 (PN)

UART0_TX

pCLK (PIXCLK)

UART1_TX

GT_CCP01

VDD_DIG2

ADC_CH0

GPIO2 (PN)

0

Hi-Z, Pull, Drive

3

1

Hi-Z, Pull,

Drive

4

I

Hi-Z, Pull, Drive

6

O

1

Hi-Z, Pull, Drive

N/A

7

I

N/A

I

N/A

See ⁽⁸⁾

0

I/O

I

Analog input

(up to 1.5 V)

or digital I/O

Hi-Z, Pull,

Drive

57⁽¹¹⁾UART0_RX

3

Hi-Z, Pull, Drive

UART1_RX

6

I

GT_CCP02

7

I

ADC_CH1

See ⁽⁸⁾

I

Hi-Z, Pull, Drive

Analog input

(up to 1.5 V)

or digital I/O

GPIO3 (PN)

58⁽¹¹⁾

0

I/O

O

Hi-Z, Pull,

Drive

Hi-Z

UART1_TX

6

1

pDATA7 (CAM_D3)

4

I

Hi-Z, Pull, Drive

ADC_CH2

See ⁽⁸⁾

I

Analog input

(up to 1.5 V)

or digital I/O

GPIO4 (PN)

0

6

4

I/O

I

Hi-Z, Pull,

Drive

59⁽¹¹⁾

Hi-Z, Pull, Drive

UART1_RX

pDATA6 (CAM_D2)

I

16

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

www.ti.com

SWRS226 – FEBRUARY 2020

Table 7-1. Pin Attributes (continued)

PAD STATES

SIGNAL

TYPE⁽²⁾

PIN MUX

ENCODING

SIGNAL

DIRECTION

SIGNAL NAME⁽¹⁾

LPDS⁽³⁾

Hib⁽⁴⁾

nRESET = 0

NO.

ADC_CH3

See ⁽⁸⁾

I

I/O

I

GPIO5 (PN)

0

4

Analog input

(up to 1.5 V)

or digital I/O

Hi-Z, Pull,

Drive

60⁽¹¹⁾pDATA5 (CAM_D1)

Hi-Z, Pull, Drive

Hi-Z

McAXR1

6

I/O

I

GT_CCP05

7

GPIO6 (PN)

0

I/O

O

I

Hi-Z, Pull, Drive

1

UART0_RTS

5

pDATA4 (CAM_D0)

4

Hi-Z, Pull,

Drive

61

I/O

Hi-Z

UART1_CTS

3

I

Hi-Z, Pull, Drive

UART0_CTS

GT_CCP06

GPIO7 (PN)

McACLKX

6

I

7

I

0

I/O

O

I/O

I

Hi-Z, Pull, Drive

1

13

3

Hi-Z, Pull,

Drive

62

63

64

UART1_RTS

UART0_RTS

UART0_TX

GPIO8 (PN)

SDCARD_IRQ

McAFSX

I/O

Hi-Z

10

11

0

6

Hi-Z, Pull,

Drive

Hi-Z, Pull, Drive

7

O

I

GT_CCP06

GPIO9 (PN)

GT_PWM05

SDCARD_DATA0

McAXR0

12

0

I/O

O

I/O

I

3

Hi-Z, Pull,

Drive

I/O

—

6

Hi-Z, Pull, Drive

N/A

Hi-Z

N/A

7

GT_CCP00

12

N/A

GND_TAB

N/A

(1) Signals names with (PN) denote the default pin name.

(2) Signal Types: I = Input, O = Output, I/O = Input or Output.

(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin

configuration), according to the need.

(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin

configuration), according to the need.

(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak

pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.

(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(7) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For the CC3230S device, pin 45 can be used as GPIO_31 if a supply is provided

on pin 47.

(8) For details on proper use, see Section 7.5.

(9) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode.

For this reason, the pin must be output only when used for digital functions.

(10) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level

configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some

applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,

the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to

automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent

false detection, TI recommends using pin 52 for output-only functions.

(11) This pin is shared by the ADC inputs and digital I/O pad cells.

Submit Document Feedback

17

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

(12) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3230x device

between two antennas. These pins must not be used for other functionalities.

18

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

7.3 Signal Descriptions

7.3.1 Signal Descriptions

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

ADC_CH0

ADC_CH1

ADC_CH2

ADC_CH3

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO22

GPIO28

GPIO25

ANTSEL1

ANTSEL2

GPIO31

GPIO0

57

58

59

60

1

I/O

I

ADC channel 0 input (maximum of 1.5 V)

ADC channel 1 input (maximum of 1.5 V)

ADC channel 2 input (maximum of 1.5 V)

ADC channel 3 input (maximum of 1.5 V)

I

ADC

I

I/O

O

2

3

4

5

6

7

8

15

18⁽²⁾

21

29

30

45^{(2) (1)}

50

52⁽²⁾

53⁽²⁾

58

59

60

61

63

64

Antenna

selection

O

Antenna selection control

O

I/O

GPIO32

GPIO30

GPIO3

GPIO4

GPIO5

GPIO6

GPIO8

GPIO9

Submit Document Feedback

19

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO22

GPIO28

GPIO25

GPIO31

GPIO0

1

2

I/O

O

I/O

O

3

I/O

O

4

5

6

7

8

15

18⁽²⁾

21

45^{(2) (1)}

50

52⁽²⁾

53⁽²⁾

58

59

60

61

63

64

22

23

I/O

O

BLE/2.4 GHz

radio

coexistence

Coexistence inputs and outputs

I/O

—

I/O

O

GPIO32

GPIO30

GPIO3

GPIO4

O

GPIO5

I/O

—

GPIO6

GPIO8

GPIO9

WLAN_XTAL_N

WLAN_XTAL_P

40-MHz crystal; pull down if external TCXO is used

40-MHz crystal or TCXO clock input

—

Connect 32.768-kHz crystal or force external CMOS

level clock

Clock

RTC_XTAL_P

RTC_XTAL_N

51

52

—

Connect 32.768-kHz crystal or connect 100-kΩ resistor

to supply voltage

20

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

www.ti.com

FUNCTION

SWRS226 – FEBRUARY 2020

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

HM_IO

DESCRIPTION

1

2

I/O

O

I/O

O

3

I/O

O

4

5

6

7

8

15

18⁽²⁾

21

45^{(2) (1)}

50

52⁽²⁾

53⁽²⁾

58

59

60

61

63

64

16

17

19

20

1

I/O

O

Hostless mode

Hostless mode inputs and outputs

I/O

O

I/O

O

I/O

I

TDI

JTAG TDI. Reset default pinout.

TDO

TCK

TMS

O

JTAG TDO. Reset default pinout.

JTAG/SWD TCK. Reset default pinout.

JTAG/SWD TMS. Reset default pinout.

JTAG / SWD

I

I/O

3

I2C_SCL

I2C_SDA

I/O

I/O (open drain) I²C clock data

5

16

2

I²C

4

I/O (open drain) I²C data

6

17

Submit Document Feedback

21

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

Pulse-width modulated O/P

GT_PWM06

GT_CCP01

GT_PWM07

GT_CCP02

GT_CCP03

1

I/O

O

I

Timer capture port

2

O

I

Pulse-width modulated O/P

2

3

I

4

I

GT_CCP04

GT_CCP05

15

5

I

Timer capture ports

6

I

17

61

63

7

I

GT_CCP06

I

Timers

I

GT_CCP07

PWM0

I

17

19

21

50

64

53

55

57

60

64

O

I

GT_PWM03

GT_PWM02

Pulse-width modulated outputs

Timer capture ports

I/O

I

GT_CCP00

I

GT_CCP05

GT_CCP01

GT_CCP02

GT_CCP05

GT_PWM05

I

Timer capture port Input

I/O

O

Pulse-width modulated output

22

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

www.ti.com

FUNCTION

SWRS226 – FEBRUARY 2020

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

GPIO10

DESCRIPTION

1

2

I/O

O

I/O

O

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO22

GPIO23

GPIO24

GPIO28

GPIO29

GPIO25

GPIO31

GPIO0

3

4

5

6

7

8

15

16

17

18

20

21

45⁽¹⁾

50

52

53

55

57

58

59

60

61

62

63

64

2

GPIO

General-purpose inputs or outputs

I/O

O

GPIO32

GPIO30

GPIO1

I/O

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

15

17

21

45⁽¹⁾

53

63

3

MCAFSX

I/O

O

I²S audio port frame sync

I/O

O

McASP

McACLK

McAXR1

52

53

50

60

45⁽¹⁾

50

I²S audio port clock outputs

I²S or PCM

I/O

I

O

I/O

I²S audio port data 1 (RX/TX)

I²S audio port data 1 (RX and TX)

I/O

I²S audio port data 0 (RX and TX)

I²S audio port data (only output mode is supported on

pin 52)

McAXR0

52

O

64

62

I/O

O

I²S audio port data (RX and TX)

I²S audio port clock

McACLKX

Submit Document Feedback

23

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

1

7

SDCARD_CLK

SDCARD_CMD

SDCARD_DATA0

I/O

O

SD card clock data

2

I/O

I/O (open drain)

I/O

SD card command line

Multimedia card

(MMC or SD)

8

6

I/O

SD card data

64

63

2

SDCARD_IRQ

pXCLK (XVCLK)

pVS (VSYNC)

pHS (HSYNC)

pDATA8 (CAM_D4)

pDATA9 (CAM_D5)

pDATA10 (CAM_D6)

pDATA11 (CAM_D7)

pCLK (PIXCLK)

pDATA7 (CAM_D3)

pDATA6 (CAM_D2)

pDATA5 (CAM_D1)

pDATA4 (CAM_D0)

VDD_DIG1

I/O

I

O

I

Interrupt from SD card⁽³⁾

Free clock to parallel camera

Parallel camera vertical sync

Parallel camera horizontal sync

Parallel camera data bit 4

Parallel camera data bit 5

Parallel camera data bit 6

Parallel camera data bit 7

Pixel clock from parallel camera sensor

Parallel camera data bit 3

Parallel camera data bit 2

Parallel camera data bit 1

Parallel camera data bit 0

Internal digital core voltage

3

4

I

5

I

6

I

7

I

Parallel interface

(8-bit π)

8

I

55

58

59

60

61

9

I

I/O

—

I

—

VIN_IO1

10

24

25

33

36

—

Device supply voltage (V_BAT

Internal analog voltage

)

VDD_PLL

—

LDO_IN2

—

Internal analog RF supply from analog DC/DC output

Internal PA supply voltage from PA DC/DC output

Internal analog RF supply from analog DC/DC output

VDD_PA_IN

—

LDO_IN1

—

Analog DC/DC input (connected to device input supply

[V_BAT])

VIN_DCDC_ANA

DCDC_ANA_SW

VIN_DCDC_PA

37

38

39

—

Internal analog DC/DC switching node

PA DC/DC input (connected to device input supply

[V_BAT])

DCDC_PA_SW_P

DCDC_PA_SW_N

DCDC_PA_OUT

DCDC_DIG_SW

40

41

42

43

—

Internal PA DC/DC switching node

Internal PA buck converter output

Internal digital DC/DC switching node

Power

Digital DC/DC input (connected to device input supply

[V_BAT])

VIN_DCDC_DIG

44

—

DCDC_ANA2_SW_P

DCDC_ANA2_SW_N

VDD_ANA2

VDD_ANA1

VDD_RAM

45⁽¹⁾

46

47

48

49

54

56

32

31

—

I

—

I

Analog to DC/DC converter +ve switching node

Internal analog to DC/DC converter –ve switching node

Internal analog to DC/DC output

Internal analog supply fed by ANA2 DC/DC output

Internal SRAM LDO output

VIN_IO2

Device supply voltage (V_BAT

Internal digital core voltage

)

VDD_DIG2

Reset

RF

nRESET

Global master device reset (active low)

WLAN analog RF 802.11 b/g/n bands

RF_BG

I/O

24

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

www.ti.com

FUNCTION

SWRS226 – FEBRUARY 2020

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

DESCRIPTION

5

45⁽¹⁾

6

I/O

O

I/O

O

I

GSPI_CLK

General SPI clock

General SPI MISO

GSPI_MISO

GSPI_CS

53

8

SPI

General SPI device select

General SPI MOSI

50

7

GSPI_MOSI

52

11

12

13

14

1

FLASH_SPI_CLK

FLASH_SPI_DOUT

FLASH_SPI_DIN

FLASH_SPI_CS

O

Clock to SPI serial flash (fixed default)

Data to SPI serial flash (fixed default)

Data from SPI serial flash (fixed default)

Device select to SPI serial flash (fixed default)

O

FLASH SPI

I

O

I

I/O

7

UART TX data

UART1 TX data

UART RX data

UART1_TX

16

55

58

2

8

I

17

45⁽¹⁾

57

59

50

62

61

3

I

UART1_RX

I

UART1 RX data

I

O

I

UART1_RTS

UART1_CTS

UART1 request-to-send (active low)

UART1 clear-to-send (active low)

UART

O

I

53

55

62

4

UART0_TX

UART0 TX data

UART0 RX data

UART0_RX

45⁽¹⁾

57

50

61

50

52

61

62

21⁽⁴⁾

34

35

I

UART0 RX data

UART0_CTS

I/O

I

UART0 clear-to-send input (active low)

I/O

O

I

UART0_RTS

SOP2

UART0 request-to-send (active low)

I/O

O

Sense-on-power 2

Sense-On-Power SOP1

SOP0

I

Configuration sense-on-power 1

Configuration sense-on-power 0

I

(1) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For the CC3230S device, pin 45 can be used as GPIO_31 if a supply is provided

on pin 47.

(2) LPDS retention unavailable.

(3) Future support.

Submit Document Feedback

25

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

26

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins

Table 7-3 describes the use, drive strength, and default state of analog and digital multiplexed pins at first-time

power up and reset (nRESET pulled low).

Table 7-3. Drive Strength and Reset States for Analog and Digital Multiplexed Pins

State After Configuration of Analog

Switches (ACTIVE, LPDS, and HIB Effective Drive

Maximum

Board-Level Configuration and

Use

Default State at First Power Up

or Forced Reset

29

Power Modes)

Strength (mA)

Connected to the enable pin of the

RF switch (ANTSEL1). Other use is

not recommended.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

4

Connected to the enable pin of the

RF switch (ANTSEL2). Other use is

not recommended.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

30

4

VDD_ANA2 (pin 47) must be

shorted to the input supply rail.

Otherwise, the pin is driven by the is also isolated.

ANA2 DC/DC.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

45

50

52

4

other digital I/Os.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

Generic I/O

The pin must have an external

pullup of 100 kΩ to the supply rail

and must be used in output signals is also isolated.

only.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

other digital I/Os.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

53

57

58

59

60

Generic I/O

4

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

7.6 Pad State After Application of Power to Device, Before Reset Release

When a stable power is applied to the CC3230x device for the first time or when supply voltage is restored to the

proper value following a period with supply voltage less than 1.5 V, the level of each digital pad is undefined in

the period starting from the release of nRESET and until DIG_DCDC powers up. This period is less than

approximately 10 ms. During this period, pads can be internally pulled weakly in either direction. If a certain set

of pins is required to have a definite value during this pre-reset period, an appropriate pullup or pulldown resistor

must be used at the board level. The recommended value of this external pull is 2.7 kΩ.

Submit Document Feedback

29

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

7.7 Connections for Unused Pins

All unused pin should be configured as stated in Table 7-4.

Table 7-4. Connections for Unused Pins

NUMBER

FUNCTION

SIGNAL DESCRIPTION

ACCEPTABLE PRACTICE

PREFERRED PRACTICE

Wake up I/O source should not be

floating during hibernate.

All the I/O pins will float while in

Hibernate and Reset states. Ensure

pullup and pulldown resistors are

available on board to maintain the

state of the I/O.

General-purpose input or

output

GPIO

Leave unused GPIOs as NC

No Connect

SOP

NC

26, 27, 28 Unused pin, leave as NC.

Unused pin, leave as NC

100-kΩ Pull down resistor

on SOP0 and SOP1. 2.7-

kΩ pull down on SOP2

Configuration sense-on-

power

Ensure pulldown resistors are

available on unused SOP pins

Reset

RESET input for the device

RTC_XTAL_N

Never leave the reset pin floating

When using an external oscillator,

add a 100-kΩ pullup resistor to VIO

Clock

JTAG

When using an external oscillator,

connect to ground if unused

WLAN_XTAL_N

JTAG interface

Leave as NC if unused

30

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8 Specifications

All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over

process and voltage, unless otherwise indicated.

8.1 Absolute Maximum Ratings

All measurements are referenced at the device pins unless otherwise indicated. All specifications are over

process and overvoltage unless otherwise indicated.

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX UNIT

V_BATand V_IO

Pins: 37, 39, 44

Pins: 10, 54

–0.5

3.8

V

Supply voltage

V_BATand V_IOshould be tied

together

V_IO– V_BAT(differential)

Digital inputs

RF pins

–0.5

–40

–55

V_IO+ 0.5

V

2.1

85

Analog pins, Crystal

Pins: 22, 23, 51, 52

V

Operating temperature, T_A

Storage temperature, T_stg

°C

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

V_ESD

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Power-On Hours (POH)

This information is provided solely for your convenience and does not extend or modify the warranty provided

under TI's standard terms and conditions for TI semiconductor products.

POWER-ON HOURS [POH]

OPERATING CONDITION

(hours)

T_Aup to 85°C⁽¹⁾

87,600

(1) The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device

can be in any other state.

8.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

2.1⁽⁴⁾

–20

TYP

MAX

UNIT

V_BAT, V_IO

(shorted to V_BAT

Direct battery

connection⁽³⁾

Supply voltage

Pins: 10, 37, 39, 44, 54

3.3

3.6

V

)

Ambient thermal slew

20 °C/minute

(1) Operating temperature is limited by crystal frequency variation.

(2) When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect

feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the

transmission.

(3) To ensure WLAN performance, ripple on the supply must be less than ±300 mV.

(4) The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also

2.1 V, and care must be taken when operating at the minimum specified voltage.

Submit Document Feedback

31

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.5 Current Consumption Summary (CC3230S)

Table 8-1. Current Consumption Summary (CC3230S)

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (5)}

TX power level = 0

MIN

TYP⁽⁶⁾

272

190

248

182

223

160

59

MAX UNIT

1 DSSS

6 OFDM

54 OFDM

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX

RX

NWP ACTIVE

MCU ACTIVE

mA

1 DSSS

54 OFDM

59

NWP idle connected⁽³⁾

15.3

269

187

245

179

220

157

56

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

TX

NWP ACTIVE

MCU SLEEP

mA

1 DSSS

RX

54 OFDM

56

NWP idle connected⁽³⁾

12.2

266

184

242

176

217

154

53

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

TX

NWP ACTIVE

mA

MCU LPDS

1 DSSS

RX

54 OFDM

53

120 µA at 64KB

135 µA at 256KB

NWP LPDS⁽²⁾

135

µA

NWP idle connected⁽³⁾

MCU SHUTDOWN MCU shutdown

MCU HIBERNATE MCU hibernate

710

1

µA

4.5

420

450

670

V_BAT= 3.6 V

V_BAT= 3.3 V

V_BAT= 2.1 V

Peak calibration current⁽⁴⁾

mA

(1) TX power level = 0 implies maximum power (see Figure 8-1, Figure 8-2, and Figure 8-3). TX power level = 4 implies output power

backed off approximately 4 dB.

(2) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The

CC3230x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU

retained SRAM increases LPDS current by 4 µA.

(3) DTIM = 1

(4) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is

performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.

There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further

details, see CC31xx, CC32xx SimpleLink™ Wi-Fi^®and IoT Network Processor Programmer's Guide.

(5) The CC3230x system is a constant power-source system. The active current numbers scale based on the V_BATvoltage supplied.

32

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

(6) Typical numbers assume a VSWR of 1.5:1.

Submit Document Feedback

33

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.6 Current Consumption Summary (CC3230SF)

Table 8-2. Current Consumption Summary (CC3230SF)

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (5)}

TX power level = 0

MIN

TYP⁽⁵⁾

286

202

255

192

232

174

74

MAX UNIT

1 DSSS

6 OFDM

54 OFDM

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX

RX

NWP ACTIVE

MCU ACTIVE

mA

1 DSSS

54 OFDM

74

NWP idle connected⁽³⁾

25.2

282

198

251

188

228

170

70

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

TX

NWP ACTIVE

MCU SLEEP

mA

1 DSSS

RX

54 OFDM

70

NWP idle connected⁽³⁾

21.2

266

184

242

176

217

154

53

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

TX

RX

NWP active

MCU LPDS

mA

1 DSSS

54 OFDM

53

120 µA at 64KB

135 µA at 256KB

NWP LPDS⁽²⁾

135

710

1

µA

NWP idle connected⁽³⁾

MCU

SHUTDOWN

MCU shutdown

MCU hibernate

µA

MCU

HIBERNATE

4.5

V_BAT= 3.6 V

V_BAT= 3.3 V

V_BAT= 2.1 V

420

450

670

Peak calibration current⁽⁴⁾

mA

(1) TX power level = 0 implies maximum power (see Figure 8-1, Figure 8-2, and Figure 8-3). TX power level = 4 implies output power

backed off approximately 4 dB.

(2) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The

CC3230x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU

retained SRAM increases LPDS current by 4 µA.

(3) DTIM = 1

(4) The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly,

typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be

controlled by a configuration file in the serial flash.

34

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

(5) Typical numbers assume a VSWR of 1.5:1.

8.7 TX Power Control

The CC3230x has several options for modifying the output power of the device when required. It is possible to

lower the overall output power at a global level using the global TX power level setting. In addition, the 2.4 GHz

band allows the user to enter additional back-offs ¹, per channel, region ²and modulation rates ³, via Image

creator (see the UniFlash CC3x20, CC3x35 SimpleLink™ Wi-Fi® and Internet-on-a chip™ Solution

ImageCreator and Programming Tool User's Guide for more details).

Figure 8-1, Figure 8-2, and Figure 8-3 show TX power and IBAT versus TX power level settings for the CC3230S

device at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the CC3230SF device, the IBAT

current has an increase of approximately 10 mA to 15 mA depending on the transmitted rate. The TX power

level will remain the same.

In Figure 8-1, the area enclosed in the circle represents a significant reduction in current during transition from

TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends

using TX power level 4 to reduce the current.

1 DSSS

19.00

17.00

280.00

264.40

249.00

233.30

218.00

202.00

186.70

171.00

Color by

TX Power (dBm)

15.00

13.00

IBAT (VBAT @ 3.6 V)

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

TX power level setting

Figure 8-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)

1

2

3

The back-off range is between -6 dB to +6 dB in 0.25dB increments.

FCC/ISED, ETSI (Europe), and Japan are supported.

Back-off rates are grouped into 11b rates, high modulation rates (MCS7, 54 OFDM and 48 OFDM), and

lower modulation rates (all other rates).

Submit Document Feedback

35

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

6 OFDM

19.00

17.00

280.00

264.40

249.00

233.30

218.00

202.00

186.70

171.00

Color by

TX Power (dBm)

15.00

13.00

IBAT (VBAT @ 3.6 V)

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

TX power level setting

Figure 8-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)

54 OFDM

19.00

17.00

280.00

264.40

249.00

233.30

218.00

202.00

186.70

171.00

Color by

TX Power (dBm)

15.00

13.00

IBAT (VBAT @ 3.6 V)

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

TX power level setting

Figure 8-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)

36

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.8 Brownout and Blackout Conditions

The device enters a brownout condition when the input voltage drops below V_brownout(see Figure 8-4 and Figure

8-5). This condition must be considered during design of the power supply routing, especially when operating

from a battery. High-current operations, such as a TX packet or any external activity (not necessarily related

directly to networking) can cause a drop in the supply voltage, potentially triggering a brownout condition. The

resistance includes the internal resistance of the battery, the contact resistance of the battery holder (four

contacts for 2× AA batteries), and the wiring and PCB routing resistance.

Note

When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect during

HIBERNATE state.

Figure 8-4. Brownout and Blackout Levels (1 of 2)

Figure 8-5. Brownout and Blackout Levels (2 of 2)

Submit Document Feedback

37

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the

Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The blackout

condition is equivalent to a hardware reset event in which all states within the device are lost.

Table 8-3 lists the brownout and blackout voltage levels.

Table 8-3. Brownout and Blackout Voltage Levels

CONDITION

VOLTAGE LEVEL

UNIT

V

V_brownout

V_blackout

2.1

1.67

V

8.9 Electrical Characteristics for GPIO Pins

8.9.1 Electrical Characteristics: GPIO Pins Except 29, 30, 50, 52, and 53

T_A= 25°C, V_BAT= 2.1 V to 3.3 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

C_IN

V_IH

V_IL

I_IH

Pin capacitance

4

pF

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

0.65 × V_DD

–0.5

V_DD+ 0.5 V

0.35 × V_DD

V

5

nA

I_IL

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.4 V ≤ V_DD< 3.6 V

V_DD× 0.8

V_DD× 0.7

V_DD× 0.75

IL = 4 mA; configured I/O drive

strength = 4 mA;

2.4 V ≤ V_DD< 3.6 V

V_OH

High-level output voltage

V

IL = 6 mA; configured I/O drive

strength = 6 mA;

2.4 V ≤ V_DD< 3.6 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.1 V ≤ V_DD< 2.4 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.4 V ≤ V_DD< 3.6 V

V_DD× 0.2

V_DD× 0.25

IL = 4 mA; configured I/O drive

strength = 4 mA;

2.4 V ≤ V_DD< 3.6 V

V_OL

Low-level output voltage

V

IL = 6 mA; configured I/O drive

strength = 6 mA;

2.4 V ≤ V_DD< 3.6 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.1 V ≤ V_DD< 2.4 V

2-mA drive

High-level

2

4

6

2

4

6

I_OH

source

current

4-mA drive

6-mA drive

2-mA drive

4-mA drive

6-mA drive

mA

Low-level

I_OL

sink current

(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk

of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength

setting is 6 mA.

38

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.9.2 Electrical Characteristics: GPIO Pins 29, 30, 50, 52, and 53

T_A= 25°C, V_BAT= 2.1 V to 3.6 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

pF

V

C_IN

V_IH

V_IL

I_IH

Pin capacitance

7

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

0.65 × V_DD

–0.5

V_DD+ 0.5 V

0.35 × V_DD

V

50

nA

I_IL

IL = 2 mA; configured I/O

drive strength = 2 mA;

2.4 V ≤ V_DD< 3.6 V

V_DD× 0.8

V_DD× 0.7

V_DD× 0.75

IL = 4 mA; configured I/O

drive strength = 4 mA;

2.4 V ≤ V_DD< 3.6 V

V_OH

High-level output voltage

V

IL = 6 mA; configured I/O

drive strength = 6 mA;

2.4 V ≤ V_DD< 3.6 V

IL = 2 mA; configured I/O

drive strength = 2 mA;

2.1 V ≤ V_DD< 2.4 V

IL = 2 mA; configured I/O

drive strength = 2 mA;

2.4 V ≤ V_DD< 3.6 V

V_DD× 0.2

V_DD× 0.25

IL = 4 mA; configured I/O

drive strength = 4 mA;

2.4 V ≤ V_DD< 3.6 V

V_OL

Low-level output voltage

V

IL = 6 mA; configured I/O

drive strength = 6 mA;

2.4 V ≤ V_DD< 3.6 V

IL = 2 mA; configured I/O

drive strength = 2 mA;

2.1 V ≤ V_DD< 2.4 V

2-mA

drive

1.5

2.5

3.5

1.5

2.5

3.5

High-level

4-mA

I_OH

source current,

drive

mA

V_OH= 2.4

6-mA

drive

2-mA

drive

Low-level sink

current

4-mA

drive

I_OL

mA

V

6-mA

drive

V_IL

nRESET

0.6

(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk

of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength

setting is 6 mA.

8.10 Electrical Characteristics for Pin Internal Pullup and Pulldown

Table 8-4. Electrical Characteristics for Pin Internal Pullup and Pulldown

T_A= 25°C, V_BAT= 3.0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_OH

Pullup current, V_OH= 2.4 (V_DD= 3.0 V)

5

10

µA

Submit Document Feedback

39

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Table 8-4. Electrical Characteristics for Pin Internal Pullup and Pulldown (continued)

T_A= 25°C, V_BAT= 3.0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Pulldown current, V_OL= 0.4 (V_DD= 3.0

V)

I_OL

5

µA

8.11 WLAN Receiver Characteristics

Table 8-5. WLAN Receiver Characteristics

T_A= 25°C, V_BAT= 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).

PARAMETER

TEST CONDITIONS (Mbps)

MIN

TYP

–96.0

–94.0

–88.0

–90.5

–90.0

–86.5

–80.5

–74.5

–71.5

–4.0

MAX

UNIT

1 DSSS

2 DSSS

11 CCK

6 OFDM

Sensitivity

(8% PER for 11b rates, 10% PER for 11g/11n

9 OFDM

dBm

rates)⁽²⁾

18 OFDM

36 OFDM

54 OFDM

MCS7 (GF)⁽¹⁾

802.11b

Maximum input level

(10% PER)

dBm

802.11g

–10.0

(1) Sensitivity for mixed mode is 1-dB worse.

(2) Sensitivity is 1-dB worse on channel 13 (2472 MHz).

40

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.12 WLAN Transmitter Characteristics

Table 8-6. WLAN Transmitter Characteristics

T_A= 25°C, V_BAT= 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 6 (2437 MHz).^{(1) (2)}

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Operating frequency range^{(3) (4)}

2412

2472

MHz

1 DSSS

2 DSSS

11 CCK

18.0

18.3

17.3

17.0

16.0

14.5

13.0

6 OFDM

9 OFDM

18 OFDM

36 OFDM

54 OFDM

MCS7

Maximum RMS output power measured at 1

dB from IEEE spectral mask or EVM

dBm

ppm

Transmit center frequency accuracy

–25

25

(1) The OFDM and MCS7 edge channels (2412 and 2462 MHz) have reduced TX power to meet FCC emission limits.

(2) Power of 802.11b rates are reduced to meet ETSI requirements in Europe.

(3) Channels 1 (2142 MHz) through 11 (2462 MHz) are supported for FCC.

(4) Channels 1 (2142 MHz) through 13 (2472MHz) are supported for Europe and Japan. Note that channel 14 is not supported for Japan.

Submit Document Feedback

41

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.13 WLAN Transmitter Out-of-Band Emissions

The device requires an external band-pass filter to meet the various emission standards, including FCC. Section

8.13.1 presents the minimum attenuation requirements for the band-pass filter. TI recommends using the same

filter used in the reference design to ease the process of certification.

8.13.1 WLAN Filter Requirements

PARAMETER

FREQUENCY (MHz)

2412 to 2484

804 to 828

MIN

TYP

MAX

UNIT

dB

Return loss

Insertion loss⁽¹⁾

10

1

42

23

49

52

30

27

42

44

30

50

1.5

dB

30

20

30

40

20

35

20

1608 to 1656

3216 to 3312

4020 to 4140

4824 to 4968

5628 to 5796

6432 to 6624

7200 to 7500

7500 to 10000

2412 to 2484

Bandpass

Attenuation

dB

Reference impendence

Filter type

Ω

(1) Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation

requirements.

42

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.14 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements

For proper BLE/2.4 GHz radio coexistence, the following requirements needs to met:

Table 8-7. COEX Isolation Requirement

PARAMETER

Band

MIN

20⁽¹⁾

20⁽²⁾

TYP

MAX

UNIT

Single antenna

Port-to-port isolation

dB

Dual antenna Configuration

(1) WLAN/BLE switch used must provide a minimum of 20 dB isolation between ports.

(2) For dual antenna configuration antenna placement must be such that isolation between the BLE and WLAN ports is at least 20 dB.

8.15 Thermal Resistance Characteristics for RGK Package

THERMAL METRICS⁽¹⁾

°C/W^{(2) (3)}

6.3

AIR FLOW (m/s)⁽⁴⁾

0.0051

0.765

RΘ_JC

RΘ_JB

RΘ_JA

Junction-to-case

Junction-to-board

Junction-to-free air

2.4

23

14.6

12.4

10.8

0.2

RΘ_JMA

Junction-to-moving air

1.275

2.55

0.0051

0.765

0.2

Psi_JT

Junction-to-package top

0.3

1.275

0.1

2.55

2.3

0.0051

0.765

2.3

Psi_JB

Junction-to-board

2.2

1.275

2.4

2.55

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

Power dissipation of 2 W and an ambient temperature of 70°C is assumed.

(4) m/s = meters per second.

8.16 Timing and Switching Characteristics

8.16.1 Power Supply Sequencing

For proper operation of the CC3230x device, perform the recommended power-up sequencing as follows:

1. Tie the following pins together on the board:

•

V_BAT(pins 37, 39, and 44)

V_IO(pins 54 and 10)

2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100 K

||, 0.01 µF, RC = 1 ms).

3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).

For timing diagrams, see Section 8.16.3.

Submit Document Feedback

43

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.2 Device Reset

When a device restart is required, the user may issue a negative pulse to the nRESET pin. The user must follow

one of the following alternatives to ensure the reset is properly applied:

•

A negative reset pulse (on pin 32) of at least 200-ms duration

If the 200-ms pulse duration cannot be ensured, a pulldown resistor of 2 MΩ must be connected to pin 52

(RTC_XTAL_N). If implemented, a shorter pulse of at least 100 µs can be used.

To ensure a proper reset sequence, the user must call the sl_stop function prior to toggling the reset. When a

reset is required, it is preferable to use the software reset instead of an external trigger.

8.16.3 Reset Timing

8.16.3.1 nRESET (32-kHz Crystal)

Figure 8-6 shows the reset timing diagram for the 32-kHz crystal first-time power-up and reset removal.

T1

T2

T3

T4

VBAT

VIO

nRESET

APP CODE

LOAD

APP CODE

EXECUTION

POWER

OFF

RESET

HW INIT

FW INIT

STATE

32-kHz

RTC CLK

Figure 8-6. First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal)

Section 8.16.3.2 describes the timing requirements for the 32-kHz clock crystal first-time power-up and reset

removal.

8.16.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)

ITEM

NAME

nReset timing

DESCRIPTION

MIN

NOM

1

MAX

UNIT

ms

nReset timing after VBAT and VIO

supply are stable

T1

T2

Hardware wake-up time

25

ms

Time taken by ROM

firmware to initialize

hardware

Includes 32.768-kHz XOSC settling

time

T3

1.1

s

App code load time for

CC3230S

Image size (KB) × 1.7 ms

Image size (KB) × 0.06 ms

T4

App code integrity check

time for CC3230SF

CC3230SF

44

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.3.3 nRESET (External 32-kHz Clock)

Figure 8-7 shows the reset timing diagram for the external 32-kHz clock first-time power-up and reset removal.

T1

T2

T3

T4

VBAT

VIO

nRESET

STATE

APP CODE

EXECUTION

POWER

OFF

APP CODE

LOAD

RESET

HW INIT

FW INIT

32-kHz

RTC CLK

Figure 8-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32-kHz Clock)

Section 8.16.3.3.1 describes the timing requirements for the external 32-kHz clock first-time power-up and reset

removal.

8.16.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz Clock)

ITEM

NAME

DESCRIPTION

MIN

NOM

MAX

UNIT

ms

nReset timing after VBAT and

VIO supply are stable

T1

T2

nReset time

1

Hardware wake-up time

25

10.3

17.3

ms

CC3230S

CC3230SF

CC3230S

CC3230SF

Time taken by ROM firmware to

initialize hardware

T3

T4

ms

App code load time

Image size (KB) × 1.7 ms

Image size (KB) × 0.06 ms

App code integrity check time

Submit Document Feedback

45

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.4 Wakeup From HIBERNATE Mode

Note

The 32.768-kHz crystal is enabled by default when the chip goes into HIBERNATE mode.

Table 8-8 lists the software hibernate timing requirements.

Table 8-8. Software Hibernate Timing Requirements

ITEM

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

T_{HIB_MIN}

Minimum hibernate time

10

ms

Hardware wakeup time plus

firmware initialization time

(1)

T_{wake_from_hib}

50⁽²⁾

ms

CC3230S

Image size (KB) × 1.7 ms

Image size (KB) × 0.06 ms

T_APP_CODE_LOAD

App code load time

CC3230SF

(1) T_{wake_from_hib}can be 200 ms on rare occasions when calibration is performed. Calibration is performed sparingly, typically when exiting

Hibernate and only if temperature has changed by more than 20°C or more than 24 hours have elapsed since a prior calibration.

(2) Wake-up time can extend to 75 ms if a patch is downloaded from the serial Flash.

Figure 8-8 shows the timing diagram for wakeup from HIBERNATE mode.

Application software requests

entry to hibernate moade

T_{wake_from_hib}

T_{APP_CODE_LOAD}

T_{HIB_MIN}

VBAT

nRESET

STATE

APP CODE

LOAD

ACTIVE

Hibernate

HW WAKEUP

FW INIT

EXECUTION

32-kHz

RTC CLK

Figure 8-8. Wakeup From HIBERNATE Timing Diagram

46

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.5 Clock Specifications

The CC3230x device requires two separate clocks for operation:

•

A slow clock running at 32.768 kHz is used for the RTC.

A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.

The device features internal oscillators that enable the use of less-expensive crystals rather than dedicated

TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system

and to reduce overall cost.

8.16.5.1 Slow Clock Using Internal Oscillator

The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock

frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P

(pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm requirement.

Figure 8-9 shows the crystal connections for the slow clock.

51

RTC_XTAL_P

10 pF

GND

32.768 kHz

52

RTC_XTAL_N

10 pF

GND

Figure 8-9. RTC Crystal Connections

Table 8-9 lists the RTC crystal requirements.

Table 8-9. RTC Crystal Requirements

CHARACTERISTICS

Frequency

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kHz

ppm

kΩ

32.768

Frequency accuracy

Crystal ESR

Initial plus temperature plus aging

32.768 kHz

±150

70

Submit Document Feedback

47

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.5.2 Slow Clock Using an External Clock

When an RTC oscillator is present in the system, the CC3230x device can accept this clock directly as an input.

The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to V_IO. The clock must be a CMOS-

level clock compatible with V_IOfed to the device.

Figure 8-10 shows the external RTC input connection.

32.768 kHz

RTC_XTAL_P

Host system

VIO

100 kΩ

RTC_XTAL_N

Figure 8-10. External RTC Input

Section 8.16.5.2.1 lists the external RTC digital clock requirements.

8.16.5.2.1 External RTC Digital Clock Requirements

CHARACTERISTICS

Frequency

TEST CONDITIONS

MIN

TYP

MAX

UNIT

32768

Hz

Frequency accuracy

(initial plus temperature plus aging)

±150

ppm

ns

t_r, t_f

Input transition time t_r, t_f(10% to 90%)

Frequency input duty cycle

100

80%

20%

50%

V_ih

V_il

0.65 × V_IO

V_IO

V

Slow clock input voltage limits

Input impedance

Square wave, DC coupled

0

1

0.35 × V_IO

V_peak

MΩ

pF

5

48

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.5.3 Fast Clock (F_ref) Using an External Crystal

The CC3230x device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The

crystal is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading

capacitors.

Figure 8-11 shows the crystal connections for the fast clock.

23

WLAN_XTAL_P

6.2 pF

GND

40 MHz

22

WLAN_XTAL_N

6.2 pF

GND

SWAS031-030

A. The crystal capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency Tuning for

information on frequency tuning.

Figure 8-11. Fast Clock Crystal Connections

Section 8.16.5.3.1 lists the WLAN fast-clock crystal requirements.

8.16.5.3.1 WLAN Fast-Clock Crystal Requirements

CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

ppm

Ω

Frequency

40

Frequency accuracy

Crystal ESR

Initial plus temperature plus aging

40 MHz

±20

60

Submit Document Feedback

49

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.5.4 Fast Clock (F_ref) Using an External Oscillator

The CC3230x device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the

clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external

TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the

system.

If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the

LDO improves noise on the TCXO power supply.

Figure 8-12 shows the connection.

V_CC

XO (40 MHz)

EN

CC3230x

TCXO_EN

82 pF

WLAN_XTAL_P

WLAN_XTAL_N

OUT

Figure 8-12. External TCXO Input

Section 8.16.5.4.1 lists the external F_refclock requirements.

8.16.5.4.1 External F_refClock Requirements (–40°C to +85°C)

CHARACTERISTICS

Frequency

TEST CONDITIONS

MIN

TYP

MAX UNIT

40.00

MHz

Frequency accuracy (initial plus temperature

plus aging)

±20 ppm

55%

Frequency input duty cycle

Clock voltage limits

45%

0.7

50%

V_pp

Sine or clipped sine wave, AC coupled

1.2

V_pp

at 1 kHz

–125

Phase noise at 40 MHz

at 10 kHz

at 100 kHz

–138.5 dBc/Hz

–143

kΩ

Resistance

Input impedance

12

Capacitance

7

pF

8.16.6 Peripherals Timing

This section describes the peripherals that are supported by the CC3230x device:

•

SPI

I²S

GPIOs

I²C

IEEE 1149.1 JTAG

ADC

Camera Parallel Port

UART

SD Host

Timers

50

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.1 SPI

8.16.6.1.1 SPI Master

The CC3230x microcontroller includes one SPI module that can be configured as a master or slave device. The

SPI includes a serial clock with programmable frequency, polarity, and phase; a programmable timing control

between chip select and external clock generation; and a programmable delay before the first SPI word is

transmitted. Slave mode does not include a dead cycle between two successive words.

Figure 8-13 shows the timing diagram for the SPI master.

T2

CLK

T6

T7

MISO

MOSI

T9

T8

Figure 8-13. SPI Master Timing Diagram

Section 8.16.6.1.1.1 lists the timing parameters for the SPI master.

8.16.6.1.1.1 SPI Master Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

F⁽¹⁾

T_clk

D⁽¹⁾

Clock frequency

Clock period

30

MHz

ns

(1)

T2

33.3

45%

1

Duty cycle

55%

(1)

T6

T7

T8

T9

t_IS

RX data setup time

RX data hold time

TX data output delay

TX data hold time

ns

(1)

t_IH

2

(1)

t_OD

t_OH

8.5

8

(1) Timing parameter assumes a maximum load of 20 pF.

Submit Document Feedback

51

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.1.2 SPI Slave

Figure 8-14 shows the timing diagram for the SPI slave.

T2

CLK

T6

T7

MISO

T9

T8

MOSI

Figure 8-14. SPI Slave Timing Diagram

Section 8.16.6.1.2.1 lists the timing parameters for the SPI slave.

8.16.6.1.2.1 SPI Slave Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

Clock frequency at V_BAT= 3.3 V

20

12

F⁽¹⁾

MHz

ns

Clock frequency at V_BAT≤ 2.1 V

Clock period

(1)

T2

T_clk

D⁽¹⁾

50

45%

4

Duty cycle

55%

(1)

T6

T7

T8

T9

t_IS

RX data setup time

RX data hold time

TX data output delay

TX data hold time

ns

(1)

t_IH

4

(1)

t_OD

t_OH

20

24

(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.

52

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.2 I²S

The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio

applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit

and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A

fractional divider is available for bit-clock generation.

8.16.6.2.1 I²S Transmit Mode

Figure 8-15 shows the timing diagram for the I²S transmit mode.

T2

T1

T3

McACLKX

T4

McAFSX

McAXR0/1

Figure 8-15. I²S Transmit Mode Timing Diagram

Section 8.16.6.2.1.1 lists the timing parameters for the I²S transmit mode.

8.16.6.2.1.1 I²S Transmit Mode Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

(1)

T1

T2

T3

T4

f_clk

Clock frequency

Clock low period

Clock high period

TX data hold time

9.216

1/2 fclk

22

MHz

ns

t^{LP (1)}

(1)

t_HT

ns

(1)

t_OH

ns

(1) Timing parameter assumes a maximum load of 20 pF.

Submit Document Feedback

53

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.2.2 I²S Receive Mode

Figure 8-16 shows the timing diagram for the I²S receive mode.

T2

T1

T3

McACLKX

T5

T4

McAFSX

McAXR0/1

Figure 8-16. I²S Receive Mode Timing Diagram

Section 8.16.6.2.2.1 lists the timing parameters for the I²S receive mode.

8.16.6.2.2.1 I²S Receive Mode Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

(1)

T1

T2

T3

T4

T5

f_clk

Clock frequency

Clock low period

Clock high period

RX data hold time

RX data setup time

9.216

1/2 f_clk

0

MHz

ns

t^{LP (1)}

(1)

t_HT

ns

(1)

t_OH

ns

(1)

t_OS

15

ns

(1) Timing parameter assumes a maximum load of 20 pF.

54

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.3 GPIOs

All digital pins of the device can be used as general-purpose input/output (GPIO) pins. The GPIO module

consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24

programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown

strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.

Note

Unless otherwise stated, GPIO specifications also applies to pins configured as COEX IOs and

network scripter interface

Figure 8-17 shows the GPIO timing diagram.

V_DD

80%

20%

t_GPIOF

t_GPIOR

SWAS031-067

Figure 8-17. GPIO Timing Diagram

8.16.6.3.1 GPIO Output Transition Time Parameters (V_supply= 3.3 V)

Section 8.16.6.3.1.1 lists the GPIO output transition times for V_supply= 3.3 V.

8.16.6.3.1.1 GPIO Output Transition Times (V_supply= 3.3 V) ^{(1) (2)}

t_r

t_f

DRIVE

STRENGTH (mA)

DRIVE STRENGTH

CONTROL BITS

UNIT

ns

MIN

NOM

MAX

MIN

NOM

MAX

2MA_EN=1

4MA_EN=0

2MA_EN=0

4MA_EN=1

2MA_EN=1

4MA_EN=1

2⁽³⁾

4⁽³⁾

6

8.0

9.3

10.7

8.2

9.5

5.2

2.6

11.0

6.6

3.2

7.1

3.5

7.6

3.7

4.7

2.3

5.8

2.9

ns

(1) V_supply= 3.3 V, T = 25°C, total pin load = 30 pF

(2) The transition data applies to the pins except the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.

(3) The 2-mA and 4-mA drive strength does not apply to the COEX I/O pins. Pins configured as COEX lines are invariably driven at 6 mA.

8.16.6.3.2 GPIO Input Transition Time Parameters

Section 8.16.6.3.2.1 lists the input transition time parameters.

8.16.6.3.2.1 GPIO Input Transition Time Parameters

MIN

1

MAX

UNIT

ns

t_r

t_f

3

Input transition time (t_r, t_f), 10% to 90%

1

ns

Submit Document Feedback

55

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.4 I²C

The CC3230x microcontroller includes one I²C module operating with standard (100 kbps) or fast

(400 kbps) transmission speeds.

Figure 8-18 shows the I²C timing diagram.

T2

T6

T5

I2CSCL

I2CSDA

T1

T7

T4

T8

T3

T9

Figure 8-18. I²C Timing Diagram

Section 8.16.6.4.1 lists the I²C timing parameters.

8.16.6.4.1 I²C Timing Parameters ⁽³⁾

PARAMETER

NUMBER

MIN

MAX

UNIT

T2

T3

T4

T5

T6

T7

T8

T9

t_LP

Clock low period

See ⁽¹⁾

System clock

ns

t_SRT

t_DH

t_SFT

t_HT

SCL/SDA rise time

Data hold time

See ⁽²⁾

N/A

3

SCL/SDA fall time

Clock high time

ns

See ⁽¹⁾

tLP/2

36

System clock

t_DS

Data setup time

t_SCSR

t_SCS

Start condition setup time

Stop condition setup time

24

(1) This value depends on the value programmed in the clock period register of I²C. Maximum output frequency is the result of the minimal

value programmed in this register.

(2) Because I²C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of an external pullup resistor. Rise time

depends on the value of the external signal capacitance and external pullup register.

(3) All timing is with 6-mA drive and 20-pF load.

56

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.5 IEEE 1149.1 JTAG

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and boundary

scan architecture for digital integrated circuits and provides a standardized serial interface to control the

associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the

IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.

Figure 8-19 shows the JTAG timing diagram.

T2

T3

T4

TCK

TMS

TDI

T7

TMS Input Valid

T9 T10

TDI Input Valid

T8

TMS Input Valid

T7

T9

T10

TDI Input Valid

T1

T11

TDO Output Valid

TDO

TDO Output Valid

Figure 8-19. JTAG Timing Diagram

Section 8.16.6.5.1 lists the JTAG timing parameters.

8.16.6.5.1 JTAG Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

T1

T2

T3

T4

T7

T8

T9

T10

T11

f_TCK

Clock frequency

Clock period

15

1 / f_TCK

t_TCK/ 2

MHz

ns

t_TCK

t_CL

Clock low period

Clock high period

TMS setup time

TMS hold time

TDI setup time

TDI hold time

ns

t_CH

ns

t_{TMS_SU}

t_{TMS_HO}

t_{TDI_SU}

t_{TDI_HO}

t_{TDO_HO}

1

16

1

ns

16

ns

TDO hold time

15

ns

Submit Document Feedback

57

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.6 ADC

Figure 8-20 shows the ADC clock timing diagram.

Repeats Every 16 µs

Internal Ch

2 µs

ADC CLOCK

= 10 MHz

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

EXT CHANNEL 0

EXT CHANNEL 1

INTERNAL CHANNEL

Figure 8-20. ADC Clock Timing Diagram

Section 8.16.6.6.1 lists the ADC electrical specifications. See the CC32xx ADC Appnote wiki for further

information on using the ADC and for application-specific examples.

8.16.6.6.1 ADC Electrical Specifications

TEST CONDITIONS and

PARAMETER

Nbits

DESCRIPTION

Number of bits

MIN

TYP

MAX

UNIT

ASSUMPTIONS

12

Bits

Worst-case deviation from

histogram method over full scale

(not including first and last three

LSB levels)

INL

Integral nonlinearity

–2.5

2.5

LSB

Worst-case deviation of any step

from ideal

DNL

Differential nonlinearity

–1

0

4

1.4

LSB

V

Input range

Driving source

impedance

100

Ω

Successive approximation input

clock rate

FCLK

Clock rate

10

MHz

pF

Input capacitance

12

2.15

0.7

ADC Pin 57

ADC Pin 58

ADC Pin 59

ADC Pin 60

Input impedance

kΩ

2.12

1.17

4

Number of channels

F_sample

Sampling rate of each pin

62.5

ksps

kHz

F_input_max

Maximum input signal frequency

31

Input frequency DC to 300 Hz

and 1.4 V_ppsine wave input

SINAD

Signal-to-noise and distortion

Active supply current

55

60

dB

Average for analog-to-digital

during conversion without

reference current

I_active

1.5

mA

Total for analog-to-digital when

not active (this must be the SoC

level test)

Power-down supply current for

core supply

I_PD

1

µA

Absolute offset error

Gain error

FCLK = 10 MHz

±2

mV

±2%

58

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

www.ti.com

PARAMETER

SWRS226 – FEBRUARY 2020

TEST CONDITIONS and

ASSUMPTIONS

DESCRIPTION

MIN

TYP

MAX

UNIT

V_ref

ADC reference voltage

1.467

V

8.16.6.7 Camera Parallel Port

The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a

FIFO, and generates DMA requests. The camera parallel port supports 8 bits.

Figure 8-21 shows the timing diagram for the camera parallel port.

T3

T2

T4

pCLK

T6

T7

pVS, pHS

pDATA

Figure 8-21. Camera Parallel Port Timing Diagram

Section 8.16.6.7.1 lists the timing parameters for the camera parallel port.

8.16.6.7.1 Camera Parallel Port Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

pCLK

T_clk

t_LP

Clock frequency

Clock period

2

1/pCLK

T_clk/2

2

MHz

ns

T2

T3

T4

T6

T7

Clock low period

Clock high period

RX data setup time

RX data hold time

Duty cycle

ns

t_HT

t_IS

ns

t_IH

2

ns

D

45%

55%

8.16.6.8 UART

The CC3230x device includes two UARTs with the following features:

•

Programmable baud-rate generator allows speeds up to 3 Mbps

Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading

Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered

interface

•

FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

Standard asynchronous communication bits for start, stop, and parity

Generation and detection of line-breaks

Fully programmable serial interface characteristics:

– 5, 6, 7, or 8 data bits

– Generation and detection of even, odd, stick, or no-parity bits

– Generation of 1 or 2 stop-bits

•

RTS and CTS hardware flow support

Standard FIFO-level and End-of-Transmission interrupts

Efficient transfers using µDMA:

Submit Document Feedback

59

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO

level

– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed

FIFO level

•

System clock is used to generate the baud clock.

8.16.6.9 SD Host

The CC3230x device provides an interface between a local host (LH), such as an MCU and an SD memory card,

and handles SD transactions with minimal LH intervention.

The SD host does the following:

•

Provides SD card access in 1-bit mode

Deals with SD protocol at the transmission level

Handles data packing

Adds cyclic redundancy checks (CRC)

Start and end bit

Checks for syntactical correctness

The application interface sends every SD command and either polls for the status of the adapter or waits for an

interrupt request. The result is then sent back to the application interface in case of exceptions or to warn of end-

of-operation. The controller can be configured to generate DMA requests and work with minimum CPU

intervention. Given the nature of integration of this peripheral on the CC3230x platform, TI recommends that

developers use peripheral library APIs to control and operate the block. This section emphasizes understanding

the SD host APIs provided in the peripheral library of the CC3230x Software Development Kit (SDK).

The SD Host features are as follows:

•

Full compliance with SD command and response sets, as defined in the SD memory card

– Specifications, v2.0

– Includes high-capacity (size >2 GB) HC and SD cards

Flexible architecture allows support for new command structure

1-bit transfer mode specifications for SD cards

•

Built-in 1024-byte buffer for read or write

– 512-byte buffer for both transmit and receive

– Each buffer is 32-bits wide by 128-words deep

•

32-bit-wide access bus to maximize bus throughput

Single interrupt line for multiple interrupt source events

Two slave DMA channels (1 for TX, 1 for RX)

Programmable clock generation

Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver

Supports configurable busy and response timeout

Support for a wide range of card clock frequency with odd and even clock ratio

Maximum frequency supported is 24 MHz

60

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

8.16.6.10 Timers

Programmable timers can be used to count or time external events that drive the timer input pins. The CC3230x

general-purpose timer module (GPTM) contains 16- or 32-bit GPTM blocks. Each 16- or 32-bit GPTM block

provides two 16-bit timers or counters (referred to as Timer A and Timer B) that can be configured to operate

independently as timers or event counters, or they can be concatenated to operate as one 32-bit timer. Timers

can also be used to trigger µDMA transfers.

The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:

•

Operating modes:

– 16- or 32-bit programmable one-shot timer

– 16- or 32-bit programmable periodic timer

– 16-bit general-purpose timer with an 8-bit prescaler

– 16-bit input-edge count or time-capture modes with an 8-bit prescaler

– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal

Counts up or counts down

Sixteen 16- or 32-bit capture compare pins (CCP)

User-enabled stalling when the microcontroller asserts CPU Halt flag during debug

Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt

service routine

•

Efficient transfers using micro direct memory access controller (µDMA):

– Dedicated channel for each timer

– Burst request generated on timer interrupt

•

Runs from system clock (80 MHz)

Submit Document Feedback

61

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

9 Detailed Description

9.1 Overview

The CC3230x wireless MCU family has a rich set of peripherals for diverse application requirements. This

section briefly highlights the internal details of the CC3230x devices and offers suggestions for application

configurations.

9.2 Arm^®Cortex^®-M4 Processor Core Subsystem

The high-performance Arm^®Cortex^®-M4 processor provides a cost-conscious platform that meets the needs of

minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding

computational performance and exceptional system response to interrupts.

•

The Arm Cortex-M4 core has low-latency interrupt processing with the following features:

– A 32-bit Arm^®Thumb^®instruction set optimized for embedded applications

– Handler and thread modes

– Low-latency interrupt handling by automatic processor state saving and restoration during entry and exit

– Support for Armv6 unaligned accesses

•

Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-latency

interrupt processing. The NVIC includes the following features:

– Bits of priority configurable from 3 to 8

– Dynamic reprioritization of interrupts

– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt levels

– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt processing

without the overhead of state saving and restoration between interrupts

– Processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction

overhead

– Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support

Bus interfaces:

– Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces

– Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations

Cost-conscious debug solution featuring:

•

– Debug access to all memory and registers in the system, including access to memory-mapped devices,

access to internal core registers when the core is halted, and access to debug control registers even while

SYSRESETn is asserted

– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access

– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches

62

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

9.3 Wi-Fi^®Network Processor Subsystem

The Wi-Fi network processor subsystem includes a dedicated Arm MCU to completely offload the host MCU

along with an 802.11b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN and

Internet connections with 256-bit encryption. The CC3230x devices support station, AP, and Wi-Fi Direct modes.

The device also supports WPA2 personal and enterprise security, WPS 2.0, and WPA3 personal ⁴. The Wi-Fi

network processor includes an embedded IPv6, IPv4 TCP/IP stack, TLS stack and network applications such as

HTTPS server.

9.3.1 WLAN

The WLAN features are as follows:

•

802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP, Wi-

Fi Direct client, and group owner with CCK and OFDM rates in the 2.4 GHz band (channels 1 through 13).

Note

802.11n is supported only in Wi-Fi^®station and Wi-Fi Direct^®.

•

The automatically calibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna

without requiring expertise in radio circuit design.

Advanced connection manager with multiple user-configurable profiles stored in serial flash allows automatic

fast connection to an access point without user or host intervention.

Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security

accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x), WPA3 Personal .

Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end

solution. With elaborate events notification to the host, enabling the application to control the provisioning

decision flow. The wide variety of Wi-Fi provisioning methods include:

– Access Point with HTTP server

– WPS - Wi-Fi Protected Setup, supporting both push button and pin code options.

– SmartConfig^™Technology: TI proprietary, easy to use, one-step, one-time process used to connect a

CC3230x-enabled device to the home wireless network.

•

802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket The 802.11

transceiver mode provides the option to select the working channel, rate, and transmitted power. The receiver

mode works with the filtering options.

•

Antenna selection for best connection

BLE/2.4 GHz radio coexistence mechanism to avoid interference

4

See CC3230 SDK v3.40 or later for details.

Submit Document Feedback

63

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

9.3.2 Network Stack

The Network Stack features are as follows:

•

Integrated IPv4, IPv6 TCP/IP stack with BSD socket APIs for simple Internet connectivity with any MCU,

microprocessor, or ASIC

Note

Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.

•

Support of 16 simultaneous TCP, UDP, RAW, SSL\TLS sockets

Built-in network protocols:

– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration

– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND

– DNS client for easy connection to the local network and the Internet

Built-in network applications and utilities:

•

– HTTP/HTTPS

•

Web page content stored on serial flash

RESTful APIs for setting and configuring application content

Dynamic user callbacks

– Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized

server. After connecting to the access point, the CC3230x device provides critical information, such as

device name, IP, vendor, and port number.

– DHCP server

– Ping

Table 9-1 describes the NWP features.

Table 9-1. NWP Features

FEATURE

DESCRIPTION

802.11b/g/n station

Wi-Fi standards

802.11b/g AP supporting up to four stations

Wi-Fi Direct client and group owner

Wi-Fi channels

Channel Bandwidth

Wi-Fi security

Wi-Fi provisioning

IP protocols

2.4 GHz ISM

20 MHz

WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x), WPA3 personal⁽¹⁾

SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server

IPv4/IPv6

IP addressing

Cross layer

Static IP, LLA, DHCPv4, DHCPv6 with DAD

ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP

UDP, TCP

Transport

SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2

RAW

Ping

HTTP/HTTPS web server

mDNS

Network applications and

utilities

DNS-SD

DHCP server

UART/SPI

Host interface

64

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Table 9-1. NWP Features (continued)

FEATURE

DESCRIPTION

Device identity

Trusted root-certificate catalog

TI root-of-trust public key

The CC3230S and CC3230SF variants also support:

•

Secure key storage

Online certificate status protocol (OCSP)

Certificate signing request (CSR)

Unique per device Key-Pair

File system security

Security

Software tamper detection

Cloning protection

Secure boot

Validate the integrity and authenticity of the run-time binary during boot

Initial secure programming

Debug security

JTAG and debug

Power management

Other

Enhanced power policy management uses 802.11 power save and deep-sleep power modes

Transceiver

Programmable RX filters with event-trigger mechanism

Rx Metrics for tracking the surrounding RF environment

(1) See CC3230 SDK v3.40 or newer for details

9.4 Security

The SimpleLink™ Wi-Fi^®CC3230x Internet-on-a chip device enhances the security capabilities available for

development of IoT devices, while completely offloading these activities from the MCU to the networking

subsystem. The security capabilities include the following key features:

Wi-Fi and Internet Security:

•

Personal and enterprise Wi-Fi security

– Personal standards

•

AES (WPA2-PSK)

TKIP (WPA-PSK)

WEP

– Enterprise standards

•

EAP Fast

EAP PEAPv0/1

EAP PEAPv0 TLS

EAP PEAPv1 TLS EAP LS

EAP TLS

EAP TTLS TLS

EAP TTLS MSCHAPv2

•

Secure sockets

– Protocol versions: OCSP, SSL v3, TLS 1.0, TLS 1.1, TLS 1.2

– Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption for TLS

and SSL connections

– Ciphers suites

•

SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA

SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5

Submit Document Feedback

65

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

•

SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA

SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA

SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA

SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA

SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256

SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256

SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256

SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256

SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA

SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA

SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256

SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384

SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256

SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384

SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256

SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384

SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256

SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384

SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256

SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256

SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256

– Server authentication

– Client authentication

– Domain name verification

– Runtime socket upgrade to secure socket – STARTTLS

Secure HTTP server (HTTPS)

Trusted root-certificate catalog – Verifies that the CA used by the application is trusted and known secure

•

content delivery

•

TI root-of-trust public key – Hardware-based mechanism that allows authenticating TI as the genuine origin of

a given content using asymmetric keys

Secure content delivery – Allows encrypted file transfer to the system using asymmetric keys created by the

device

66

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Code and Data Security:

•

Network passwords and certificates are encrypted and signed.

Cloning protection – Application and data files are encrypted by a unique key per device.

Access control – Access to application and data files only by using a token provided in file creation time. If an

unauthorized access is detected, a tamper protection lock down mechanism takes effect.

Secured boot – Authentication of the application image on every boot

Code and data encryption – User application and data files can be encrypted in the serial flash

Code and data authentication – User Application and data files are authenticated with a public key certificate

Offloaded crypto library for asymmetric keys, including the ability to create key-pair, sign and verify data

buffer

•

Recovery mechanism

Device Security:

•

Separate execution environments – Application processor and network processor run on separate Arm cores

Initial secure programming – Allows for keeping the content confidential on the production line

Debug security

– JTAG lock

– Debug ports lock

True random number generator

•

Figure 9-1 shows the high-level structure of the CC3230S and CC3230SF devices. The application image, user

data, and network information files (passwords, certificates) are encrypted using a device-specific key.

CC3230S and CC3230SF

Network Processor + MCU

MCU

Network Processor

Peripherals

ARM^®Cortex^®-M4

Processor

SPI and I2C

GPIO

Internet

Wi-Fi^®

MAC

Internet

256KB RAM /

UART

HTTPS

TLS/SSL

TCP/IP

1MB Flash (CC3230SF)

PWM

ADC

Baseband

Radio

OEM

Application

•

Serial Flash

OEM

Application

Data Files

Network Information

Figure 9-1. CC3230S and CC3230SF High-Level Structure

9.5 Power-Management Subsystem

The CC3230x power-management subsystem contains DC/DC converters to accommodate the different voltage

or current requirements of the system.

•

Digital DC/DC (Pin 44)

– Input: V_BATwide voltage (2.1 to 3.6 V)

ANA1 DC/DC (Pin 37)

– Input: V_BATwide voltage (2.1 to 3.6 V)

PA DC/DC (Pin 39)

– Input: V_BATwide voltage (2.1 to 3.6 V)

ANA2 DC/DC (Pin 47, CC3230SF only)

Submit Document Feedback

67

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

– Input: V_BATwide voltage (2.1 to 3.6 V)

The CC3230x device is a single-chip WLAN radio solution used on an embedded system with a wide-voltage

supply range. The internal power management, including DC/DC converters and LDOs, generates all of the

voltages required for the device to operate from a wide variety of input sources.

9.6 Low-Power Operating Mode

From a power-management perspective, the CC3230x device comprises the following two independent

subsystems:

•

Arm^®Cortex^®-M4 application processor subsystem

Networking subsystem

Each subsystem operates in one of several power states.

The Arm^®Cortex^®-M4 application processor runs the user application loaded from an external serial flash, or

internal flash (in CC3230SF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer

functions.

68

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

The user program controls the power state of the application processor subsystem. The application processor

can be in one of the five modes described in Table 9-2.

Table 9-2. User Program Modes

APPLICATION PROCESSOR

DESCRIPTION

(MCU) MODE⁽¹⁾

MCU active mode

MCU executing code at a state rate of 80 MHz

The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode

offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity

from any GPIO line or peripheral.

MCU sleep mode

State information is lost and only certain MCU-specific register configurations are retained. The MCU

can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.)

Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory

retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU

can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the

wake-up source.

MCU LPDS mode

The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly

powered by the input supply is retained. The RTC continues running and the MCU supports wakeup

from an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about

15 ms plus the time to load the application from serial flash, which varies according to code size. In this

mode, the MCU can be configured to wake up using the RTC timer or external event on a GPIO.

MCU hibernate mode

MCU shutdown mode

The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in

this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the

nRESET line is changed (low to shut down, high to turn on).

(1) Modes are listed in order of power consumption, with highest power modes listed first.

The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network

activity, the NWP sleeps most of the time and wakes up only for beacon reception (see

Table 9-3).

Table 9-3. Networking Subsystem Modes

NETWORK PROCESSOR

DESCRIPTION

MODE

Network active mode

Transmitting or receiving IP protocol packets

(processing layer 3, 2, and 1)

Network active mode

Transmitting or receiving MAC management frames; IP processing is not required

(processing layer 2 and 1)

Network active listen mode

Network connected Idle

Special power-optimized active mode for receiving beacon frames (no other frames are supported)

A composite mode that implements 802.11 infrastructure power-save operation. The CC3230x NWP

automatically enters LPDS mode between beacons and then wakes into active listen mode to receive a

beacon and determine if there is pending traffic at the AP. If not, the NWP returns to LPDS mode and

the cycle repeats.

Advanced features of long sleep interval and IoT low power for extending LPDS time for up to 22

seconds while maintaining Wi-Fi connection is supported in this mode.

Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid wake

up

Network LPDS mode

Network disabled

The network is disabled

Submit Document Feedback

69

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

The operation of the application and network processor ensures that the device remains in the lowest power

mode most of the time to preserve battery life.

The following examples show the use of the power modes in applications:

•

A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but

sends and receives little data spends most of the time in connected idle, which is a composite of receiving a

beacon frame and waiting for the next beacon.

A product that is not continuously connected to the network but instead wakes up periodically (for example,

every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to

transmit data.

9.7 Memory

9.7.1 External Memory Requirements

The CC3230x device maintains a proprietary file system on the serial flash. The CC3230x file system stores the

MCU binary, service pack file, system files, configuration files, certificate files, web page files, and user files. By

using a format command through the API, users can provide the total size allocated for the file system. The

starting address of the file system cannot be set and is always at the beginning of the serial flash. The

applications microcontroller must access the serial flash memory area allocated to the file system directly

through the CC3230x file system. The applications microcontroller must not access the serial flash memory area

directly.

The file system manages the allocation of serial flash blocks for stored files according to download order, which

means that the location of a specific file is not fixed in all systems. Files are stored on serial flash using human-

readable filenames rather than file IDs. The file system API works using plain text, and file encryption and

decryption is invisible to the user. Encrypted files can be accessed only through the file system.

All file types can have a maximum of 100 supported files in the file system. All files are stored in 4-KB blocks and

thus use a minimum of 4KB of flash space. Fail-safe files require twice the original size and use a minimum of

8KB. Encrypted files are counted as fail-safe in terms of space. The maximum file size is 1MB.

Table 9-4 lists the minimum required memory consumption under the following assumptions:

•

System files in use consume 64 blocks (256KB).

Vendor files are not taken into account.

MCU code is taken as the maximal possible size for the CC3230 with fail-safe enabled to account for future

updates, such as through OTA.

•

Gang image:

– Storage for the gang image is rounded up to 32 blocks (meaning 128-KB resolution).

– Gang image size depends on the actual content size of all components. Additionally, the image should be

128KB aligned so unaligned memory is considered lost. Service pack, system files, and the 128KB

aligned memory are assumed to occupy 256KB.

•

All calculations consider that the restore-to-default is enabled.

Table 9-4. Recommended Flash Size

ITEM

CC3230S (KB)

CC3230SF (KB)

20

File system allocation table

20

System and configuration files⁽¹⁾

Service pack⁽¹⁾

256

264

MCU Code⁽¹⁾

512

2048

Gang image size

256 + MCU

1308 + MCU

16 MBit

256 + MCU

2844 + MCU

32 MBit

Total

Minimal flash size⁽²⁾

Recommended flash size⁽²⁾

(1) Including fail-safe

(2) For maximum MCU size

70

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Note

The maximum supported serial flash size is 32MB (256Mb) (see the Using Serial Flash on CC3135

and CC3235x SimpleLink™ Wi-Fi® and Internet-of-Things Devices application report).

9.7.2 Internal Memory

The CC3230x device includes on-chip SRAM to which application programs are downloaded and executed. The

application developer must share the SRAM for code and data. The micro direct memory access (μDMA)

controller can transfer data to and from SRAM and various peripherals. The CC3230x ROM holds the rich set of

peripheral drivers, which saves SRAM space. For more information on drivers, see the CC3230x API list.

9.7.2.1 SRAM

The CC3230x family provides 256KB of on-chip SRAM. Internal RAM is capable of selective retention during

LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory map.

Use the µDMA controller to transfer data to and from the SRAM.

When the device enters low-power mode, the application developer can choose to retain a section of memory

based on need. Retaining the memory during low-power mode provides a faster wakeup. The application

developer can choose the amount of memory to retain in multiples of 64KB. For more information, see the API

guide.

9.7.2.2 ROM

The internal zero-wait-state ROM of the CC3230x device is at address 0x0000 0000 of the device memory and

is programmed with the following components:

•

Bootloader

Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces

The bootloader is used as an initial program loader (when the serial flash memory is empty). The CC3230x

DriverLib software library controls on-chip peripherals with a bootloader capability. The library performs

peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. The

DriverLib APIs in ROM can be called by applications to reduce flash memory requirements and free the flash

memory for other purposes.

9.7.2.3 Flash Memory

The CC3230SF device comes with an on-chip flash memory of 1MB that allows application code to execute in

place while freeing SRAM exclusively for read-write data. The flash memory is used for code and constant data

sections and is directly attached to the icode/dcode bus of the Arm Cortex-M4 core. A 128-bit-wide instruction

prefetch buffer allows maintenance of maximum performance for linear code or loops that fit inside the buffer.

The flash memory is organized as 2KB sectors that can be independently erased. Reads and writes can be

performed at word (32-bit) level.

Submit Document Feedback

71

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

9.7.2.4 Memory Map

Table 9-5 describes the various MCU peripherals and how they are mapped to the processor memory. For more

information on peripherals, see the API document.

Table 9-5. Memory Map

START ADDRESS

0x0000 0000

0x0100 0000

0x2000 0000

0x2200 0000

0x4000 0000

0x4000 4000

0x4000 5000

0x4000 6000

0x4000 7000

0x4000 C000

0x4000 D000

0x4002 0000

0x4002 0800

0x4002 4000

0x4003 0000

0x4003 1000

0x4003 2000

0x4003 3000

0x400F 7000

0x400F E000

0x400F F000

0x4200 0000

0x4401 0000

0x4401 8000

0x4401 C000

0x4402 0000

0x4402 1000

0x4402 5000

0x4402 6000

0x4402 D000

0x4402 E000

0x4402 F000

END ADDRESS

0x0007 FFFF

0x010F FFFF

0x2003 FFFF

0x23FF FFFF

0x4000 0FFF

0x4000 4FFF

0x4000 5FFF

0x4000 6FFF

0x4000 7FFF

0x4000 CFFF

0x4000 DFFF

0x4000 07FF

0x4002 0FFF

0x4002 4FFF

0x4003 0FFF

0x4003 1FFF

0x4003 2FFF

0x4003 3FFF

0x400F 7FFF

0x400F EFFF

0x400F FFFF

0x43FF FFFF

0x4401 0FFF

0x4401 8FFF

0x4401 DFFF

0x4402 1FFF

0x4402 2FFF

0x4402 5FFF

0x4402 6FFF

0x4402 DFFF

0x4402 EFFF

0x4402 FFFF

DESCRIPTION

On-chip ROM (bootloader + DriverLib)

On-chip flash (for user application code)

Bit-banded on-chip SRAM

Bit-band alias of 0x2000 0000 to 0x200F FFFF

Watchdog timer A0

COMMENT

CC3230SF device only

GPIO port A0

GPIO port A1

GPIO port A2

GPIO port A3

UART A0

UART A1

I²C A0 (master)

I²C A0 (slave)

GPIO group 4

General-purpose timer A0

General-purpose timer A1

General-purpose timer A2

General-purpose timer A3

Configuration registers

System control

µDMA

Bit band alias of 0x4000 0000 to 0x400F FFFF

SDIO master

Camera Interface

McASP

SSPI

Used for external serial flash

Used by application processor

GSPI

MCU reset clock manager

MCU configuration space

Global power, reset, and clock manager (GPRCM)

MCU shared configuration

Hibernate configuration

Crypto range (includes apertures for all crypto-related

blocks as follows)

0x4403 0000

0x4403 FFFF

0x4403 0000

0x4403 5000

0x4403 7000

0x4403 9000

0xE000 0000

0xE000 1000

0xE000 2000

0xE000 E000

0x4403 0FFF

0x4403 5FFF

0x4403 7FFF

0x4403 9FFF

0xE000 0FFF

0xE000 1FFF

0xE000 2FFF

0xE000 EFFF

DTHE registers and TCP checksum

MD5/SHA

AES

DES

Instrumentation trace Macrocell^™

Data watchpoint and trace (DWT)

Flash patch and breakpoint (FPB)

NVIC

72

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Table 9-5. Memory Map (continued)

START ADDRESS

END ADDRESS

0xE004 0FFF

0xE004 1FFF

0xE00F FFFF

DESCRIPTION

COMMENT

0xE004 0000

0xE004 1000

0xE004 2000

Trace port interface unit (TPIU)

Reserved for embedded trace macrocell (ETM)

Reserved

9.8 Restoring Factory Default Configuration

The device has an internal recovery mechanism that allows rolling back the file system to its predefined factory

image or restoring the factory default parameters of the device. The factory image is kept in a separate sector on

the serial flash in a secure manner and cannot be accessed from the host processor. The following restore

modes are supported:

•

None – no factory restore settings

Enable restore of factory default parameters

Enable restore of factory image and factory default parameters

The restore process is performed by calling software APIs, or by pulling or forcing SOP[2:0] = 110 pins and

toggling the nRESET pin from low to high.

The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The

restore process typically takes about 8 seconds, depending on the attributes of the serial flash vendor.

Submit Document Feedback

73

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

9.9 Boot Modes

9.9.1 Boot Mode List

The CC3230x device implements a sense-on-power (SOP) scheme to determine the device operation mode.

SOP values are sensed from the device pin during power up. This encoding determines the boot flow. Before the

device is taken out of reset, the SOP values are copied to a register and used to determine the device operation

mode while powering up. These values determine the boot flow as well as the default mapping (to JTAG, SWD,

UART0) for some of the pins. Table 9-6 lists the pull configurations.

Table 9-6. CC3230x Functional Configurations

BOOT MODE NAME

SOP[2]

SOP[1]

SOP[0]

SOP MODE

COMMENT

Factory, lab flash, and SRAM loads

through the UART. The device waits

indefinitely for the UART to load code.

The SOP bits then must be toggled to

configure the device in functional mode.

Also puts JTAG in 4-wire mode.

UARTLOAD

Pullup

Pulldown

Pulldown LDfrUART

Functional development mode. In this

mode, 2-pin SWD is available to the

developer. TMS and TCK are available

for debugger connection.

FUNCTIONAL_2WJ

FUNCTIONAL_4WJ

Pulldown Pulldown

Pullup

Fn2WJ

Functional development mode. In this

mode, 4-pin JTAG is available to the

developer. TDI, TMS, TCK, and TDO are

available for debugger connection.

Pulldown Fn4WJ

Supports flash and SRAM load through

UART and functional mode. The MCU

bootloader tries to detect a UART break

on UART receive line. If the break signal

UARTLOAD_FUNCTIONAL_4WJ

RET_FACTORY_IMAGE

Pulldown Pullup

Pulldown LDfrUART_Fn4WJ is present, the device enters the

UARTLOAD mode, otherwise, the device

enters the functional mode. TDI, TMS,

TCK, and TDO are available for debugger

connection.

When device reset is toggled, the MCU

Pullup

RetFactDef

bootloader kick-starts the procedure to

restore factory default images.

The recommended values of pull down resistors are 100-kΩ for SOP0 and SOP1 and 2.7-kΩ for SOP2. The

application can use SOP2 for other functions after the device has powered up. However, to avoid spurious SOP

values from being sensed at power up, TI strongly recommends using the SOP2 pin only for output signals. The

SOP0 and SOP1 pins are multiplexed with the WLAN analog test pins and are not available for other functions.

74

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

9.10 Hostless Mode

The SimpleLink Wi-Fi CC3230 device incorporates a scripting ability that enables offloading of simple tasks from

the host processor. Using simple and conditional scripts, repetitive tasks can be handled internally, which allows

the host processor to remain in a low-power state. In some cases where the scripter is being used to send

packets, it reduces code footprint and memory consumption. The if-this-then-that style conditioning can include

anything from GPIO toggling to transmitting packets.

The conditional scripting abilities can be divided into conditions and actions. The conditions define when to

trigger actions. Only one action can be defined per condition, but multiple instances of the same condition may

be used, so in effect multiple actions can be defined for a single condition. In total, 16 condition and action pairs

can be defined. The conditions can be simple, or complex using sub-conditions (using a combinatorial AND

condition between them). The actions are divided into two types, those that can occur during runtime and those

that can occur only during the initialization phase.

The following actions can only be performed when triggered by the pre-initialization condition:

•

Set roles AP, station, P2P, and Tag modes

Delete all stored profiles

Set connection policy

Hardware GPIO indication allows an I/O to be driven directly from the WLAN core hardware to indicate

internal signaling

The following actions may be activated during runtime:

•

Send transceiver packet

Send UDP packet

Send TCP packet

Increment counter increments one of the user counters by 1

Set counter allows setting a specific value to a counter

Timer control

Set GPIO allows GPIO output from the device using the internal networking core

Enter Hibernate state

Note

Consider the following limitations:

•

Timing cannot be ensured when using the network scripter because some variable latency will

apply depending on the utilization of the networking core.

•

The scripter is limited to 16 pairs of conditions and reactions.

Both timers and counters are limited to 8 instances each. Timers are limited to a resolution of 1

second. Counters are 32 bits wide.

•

Packet length is limited to the size of one packet and the number of possible packet tokens is

limited to 8.

Submit Document Feedback

75

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

10 Applications, Implementation, and Layout

Note

Information in the following Applications section is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

10.1.1 BLE/2.4 GHz Radio Coexistence

The CC3230x device is designed to support BLE/2.4 GHz radio coexistence. Because WLAN is inherently more

tolerant to time-domain disturbances, the coexistence mechanism gives priority to the Bluetooth^®low energy

entity over the WLAN.

The following coexistence modes can be configured by the user:

•

Off mode or intrinsic mode

– No BLE/2.4 GHz radio coexistence, or no synchronization between WLAN and Bluetooth^®low energy—in

case Bluetooth^®low energy exists in this mode, collisions can randomly occur.

Time division multiplexing (TDM, single antenna)

– In this mode, (see Figure 10-1) the two entities share the antenna through an RF switch using two GPIOs

(one input and one output from the WLAN perspective).

•

Time division multiplexing (TDM, dual antenna)

– in this mode, (see Figure 10-2) the two entities have separate antennas, No RF switch is required and

only a single GPIO (on input from the WLAN persective).

Figure 10-1 shows the single antenna implementation of a complete Bluetooth^®low energy and WLAN

coexistence network. The Coex switch is controlled by a GPIO signal from the BLE device and a GPIO signal

from the CC3230x device.

BLE / 2.4-GHz

Wi-Fi Antenna

SPDT RF

Switch

and BPF

RF

RF_BG

WLAN

BLE

CCxxxx

CC3230x

CC_COEX_SW_OUT

CC_COEX_BLE_IN

Coex IO

Figure 10-1. Single-Antenna Coexistence Mode Block Diagram

76

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Figure 10-2 shows the dual antenna implementation of a complete Bluetooth low energy and WLAN coexistence

network. Note in this implementation no Coex switch is required and only a single GPIO from the BLE device to

the CC3230x device is required.

2.4-GHz Wi-Fi

Antenna

BLE

Antenna

2.4-GHz

BPF

2.4-GHz

BPF

RF

RF_BG

WLAN

BLE

CCxxxx

CC3230x

CC_COEX_BLE_IN

Coex IO

Figure 10-2. Dual-Antenna Coexistence Mode Block Diagram

Submit Document Feedback

77

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

10.1.2 Antenna Selection

The CC3230x device is designed to also support antenna selection and is controlled from Image Creator. When

enabled, there are 3 options possible options:

•

ANT 1: When selected, the GPIOs that are defined for antenna selection with set the RF path for antenna 1.

ANT 2: When selected, the GPIOs that are defined for antenna selection will set the RF path for antenna 2.

Autoselect: When selected, during a scan and prior to connecting to an AP, CC3230x device will determine

the best RF path and select the appropriate antenna ^{5 6}. The result is the saved as port of the profile.

Figure 10-3 shows the implementation of a complete Bluetooth^®low energy and WLAN coexistence network

with WLAN and antenna selection. The Coex switch is controlled by a GPIO signal from the BLE device and a

GPIO signal from the CC3230x device. The antenna switch is controlled by 2 GPIO lines from the CC3230x

device.

BLE / 2.4-GHz Wi-Fi

Antenna

RF_BG

Antenna

CC_COEX_SW_OUT

Selection

SPDT RF

Switch

Coex SPDT

RF Switch

2.4-GHz

BPF

WLAN

CC3230x

BLE

CCxxxx

Coex IO

RF

CC_COEX_BLE_IN

ANTSEL1 ANTSEL2

BLE / 2.4-GHz Wi-Fi

Antenna

Figure 10-3. Antenna Selection Solution with Coexistence

5

When selecting Autoselect via the API, a reset is required in order for the CC3230x device to determine the

best antenna for use.

Refer to the UniFlash CC3x20, CC3x35 SimpleLink™ Wi-Fi® and Internet-on-a chip™ Solution

ImageCreator and Programming Tool User's Guide for more information.

6

78

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Figure 10-4 shows the antenna selection implementation for Wi-Fi, with BLE operating on it's own antenna. Note

in this implementation no Coex switch is required and only a single GPIO from the BLE device to the CC3230x

device is required. The antenna switch is controlled by 2 GPIO lines from the CC3230x device.

2.4-GHz Wi-Fi

Antenna

2.4-GHz

BPF

Selection

SPDT RF

Switch

RF_BG

CC_COEX_SW_OUT

WLAN

CC3230x

BLE

CCxxxx

Coex IO

RF

CC_COEX_BLE_IN

2.4-GHz Wi-Fi

Antenna

ANTSEL1 ANTSEL2

BLE Antenna

Figure 10-4. Coexistence Solution with Wi-Fi Antenna Selection and Dedicated BLE Antenna

Submit Document Feedback

79

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

10.2 PCB Layout Guidelines

This section details the PCB guidelines to speed up the PCB design using the CC3230x VQFN device. Follow

these guidelines ensures that the design will minimize the risk with regulatory certifications including FCC, ETSI,

and CE. For more information, see CC3120 and CC3220 SimpleLink™ Wi-Fi^®and IoT Solution Layout

Guidelines.

10.2.1 General PCB Guidelines

Use the following PCB guidelines:

•

Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended layers for

signals and ground.

•

Ensure that the VQFN PCB footprint follows the information in .

Ensure that the VQFN PCB GND and solder paste follow the recommendations provided in CC3120 and

CC3220 SimpleLink™ Wi-Fi^®and IoT Solution Layout Guidelines.

Decoupling capacitors must be as close as possible to the VQFN device.

•

10.2.2 Power Layout and Routing

Three critical DC/DC converters must be considered for the CC3230x device.

•

Analog DC/DC converter

PA DC/DC converter

Digital DC/DC converter

Each converter requires an external inductor and capacitor that must be laid out with care. DC current loops are

formed when laying out the power components.

10.2.2.1 Design Considerations

The following design guidelines must be followed when laying out the CC3230x device:

•

Ground returns of the input decoupling capacitors (C11, C13, and C19) should be routed on Layer 2 using

thick traces to isolate the RF ground from the noisy supply ground. This step is also required to meet the

IEEE spectral mask specifications.

Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power

amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44).

Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).

Place all decoupling capacitors as close to the respective pins as possible.

Power budget—the CC3230x device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, for

24 ms during the calibration cycle.

•

Ensure the power supply is designed to source this current without any issues. The complete calibration (TX

and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.

The CC3230x device contains many high-current input pins. Ensure the trace feeding these pins can handle

the following currents:

– VIN_DCDC_PA input (pin 39) maximum 1 A

– VIN_DCDC_ANA input (pin 37) maximum 600 mA

– VIN_DCDC_DIG input (pin 44) maximum 500 mA

– DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum 1 A

– DCDC_PA_OUT output node (pin 42) maximum 1 A

– DCDC_ANA_SW switching node (pin 38) maximum 600 mA

– DCDC_DIG_SW switching node (pin 43) maximum 500 mA

– VDD_PA_IN supply (pin 33) maximum 500 mA

84

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

Figure 10-6. Ground Returns for Input Capacitors

Submit Document Feedback

85

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

10.2.3 Clock Interface Guidelines

The following guidelines are for the slow clock:

•

The 32.768-kHz crystal must be placed close to the VQFN package.

Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance within

±150 ppm.

•

The ground plane on layer two is solid below the trace lanes, and there is ground around these traces on the

top layer.

The following guidelines are for the fast clock:

•

The 40-MHz crystal must be placed close to the VQFN package.

Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance within

±10 ppm at room temperature. The total frequency across parts, temperature, and with aging must be ±25

ppm to meet the WLAN specification.

•

To avoid noise degradation, ensure that no high-frequency lines are routed close to the routing of the crystal

pins.

•

Ensure that crystal tuning capacitors are close to the crystal pads.

Both traces (XTAL_N and XTAL_P) should be as close as possible to parallel and approximately the same

length.

•

The ground plane on layer two is solid below the trace lines, and there should be ground around these traces

on the top layer.

For frequency tuning, see CC31xx & CC32xx Frequency Tuning.

10.2.4 Digital Input and Output Guidelines

The following guidelines are for the digital I/Os:

•

Route SPI and UART lines away from any RF traces.

Keep the length of the high-speed lines as short as possible to avoid transmission line effects.

Keep the line lower than 1/10 of the rise time of the signal to ignore transmission line effects (required if the

traces cannot be kept short). Place the resistor at the source end closer to the device that is driving the

signal.

•

Add a series-terminating resistor for each high-speed line (for example, SPI_CLK or SPI_DATA) to match the

driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a 50-Ω line

impedance.

•

Route high-speed lines with a continuous ground reference plane below it to offer good impedance

throughout. This routing also helps shield the trace against EMI.

Avoid stubs on high-speed lines to minimize the reflections. If the line must be routed to multiple locations,

use a separate line driver for each line.

If the lines are longer compared to the rise time, add series-terminating resistors near the driver for each

high-speed line to match the driver impedance to the line. Typical terminating-resistor values range from 27 to

36 Ω for a 50-Ω line impedance.

86

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

10.2.5 RF Interface Guidelines

The following guidelines are for the RF interface. Follow guidelines specified in the vendor-specific antenna

design guides (including placement of the antenna). Also see CC3120 and CC3220 SimpleLink™ Wi-Fi^®and IoT

Solution Layout Guidelines for general antenna guidelines.

•

Ensure that the antenna is matched for 50-Ω. A π-matching network is recommended. Ensure that the π pad

is available for tuning the matching network after PCB manufacture.

•

Ensure that the area underneath the BPFs pads have a solid plane on layer 2 and that the minimum filter

requirements are met.

•

Verify that the Wi-Fi RF trace is a 50-Ω, impedance-controlled trace with a reference to solid ground.

The RF trace bends must be made with gradual curves. Avoid 90-degree bends.

The RF traces must not have sharp corners.

There must be no traces or ground under the antenna section.

The RF traces must have via stitching on the ground plane beside the RF trace on both sides.

For optimal antenna performance, ensure adequate ground plane around the antenna on all layers.

Ensure RF connectors for conducted testing are isolated from the top layer ground using vias.

Maintain a controlled pad to trace shapes using filleted edges if necessary to avoid mismatch.

Submit Document Feedback

87

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

11 Device and Documentation Support

11.1 Tools and Software

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed in this section.

For the most up-to-date list of development tools and software, see the CC3230S Design & development page.

Users can also click the "Alert Me" button on the top right corner of the CC3230S Design & development page to

stay informed about updates related to the CC3230x device.

Development Tools

Pin Mux Tool

The supported devices are: CC3200, CC3220x, CC3230x, and CC3235x.

The Pin Mux Tool is a software tool that provides a graphical user interface (GUI) for

configuring pin multiplexing settings, resolving conflicts and specifying I/O cell

characteristics for MPUs from TI. Results are output as C header/code files that can

be imported into software development kits (SDKs) or used to configure customers'

custom software. Version 3 of the Pin Mux Tool adds the capability of automatically

selecting a mux configuration that satisfies the entered requirements.

SimpleLink™ Wi-Fi^®

Starter Pro

The supported devices are: CC3100, CC3200, CC3120R, CC3220x, CC3130,

CC3135, CC3230x and CC3235x.

The SimpleLink™ Wi-Fi^®Starter Pro mobile App is a new mobile application for

SimpleLink™ provisioning. The app goes along with the embedded provisioning

library and example that runs on the device side (see SimpleLink™ Wi-Fi^®SDK

plugin and TI SimpleLink™ CC32XX Software Development Kit (SDK)). The new

provisioning release is a TI recommendation for Wi-Fi^®provisioning using

SimpleLink™ Wi-Fi^®products. The provisioning release implements advanced AP

mode and SmartConfig™ technology provisioning with feedback and fallback options

to ensure successful process has been accomplished. Customers can use both

embedded library and the mobile library for integration to their end products.

SimpleLink™ CC32XX

The CC3230x devices are supported.

Software Development

Kit (SDK)

The SimpleLink™ CC32XX SDK contains drivers for the CC3230 programmable

MCU, more than 30 sample applications, and documentation needed to use the

solution. It also contains the flash programmer, a command line tool for flashing

software, configuring network and software parameters (SSID, access point channel,

network profile, BS NIEW), system files, and user files (certificates, web pages, and

more). This SDK can be used with TI’s SimpleLink™ Wi-Fi^®CC3230 LaunchPad™

development kits.

Uniflash Standalone

Flash Tool for TI

Microcontrollers (MCU),

Sitara Processors &

SimpleLink Devices

The supported devices are: CC3120R, CC3220x, CC3130, CC3135, CC3230x and

CC3235x.

CCS Uniflash is a standalone tool used to program on-chip flash memory on TI

MCUs and on-board flash memory for Sitara™ processors. Uniflash has a GUI,

command line, and scripting interface. CCS Uniflash is available free of charge.

SimpleLink™ Wi-Fi^®

Radio Testing Tool

The supported devices are: CC3100, CC3200, CC3120R, CC3220, CC3130,

CC3135, CC3230x and CC3235x.

The SimpleLink™ Wi-Fi^®Radio Testing Tool is a Windows-based software tool for

RF evaluation and testing of SimpleLink™ Wi-Fi^®CC3x20 and CC3x3x designs

during development and certification. The tool enables low-level radio testing

88

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

capabilities by manually setting the radio into transmit or receive modes. Using the

tool requires familiarity and knowledge of radio circuit theory and radio test methods.

Created for the internet-of-things (IoT), the SimpleLink™ Wi-Fi^®CC31xx and

CC32xx family of devices include on-chip Wi-Fi^®, Internet, and robust security

protocols with no prior Wi-Fi^®experience needed for faster development. For more

information on these devices, visit SimpleLink™ Wi-Fi^®family, Internet-on-a chip™

solutions.

UniFlash Standalone

Flash Tool for TI

Microcontrollers (MCU),

Sitara™ Processors

and SimpleLink™

Devices

CCS UniFlash is a standalone tool used to program on-chip flash memory on TI

MCUs and on-board flash memory for Sitara^™processors. UniFlash has a GUI,

command line, and scripting interface. CCS UniFlash is available free of charge.

TI Reference Designs

Find reference designs leveraging the best in TI technology – from analog and power management to embedded

processors. All designs include a schematic, test data and design files.

11.2 Firmware Updates

TI updates features in the service pack for this module with no published schedule. Due to the ongoing changes,

TI recommends that the user has the latest service pack in their module for production.

To stay informed, click the SDK “Alert me” button the top right corner of the product page, or visit SimpleLink™

CC32XX SDK.

11.3 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the

CC3230x device and support tools (see Figure 11-1).

X

CC

3

2

3

0

x

xx

xxx

x

PREFIX

X = Preproduction device

Null = Production device

PACKAGING

R = large reel

DEVICE FAMILY

CC = Wireless Connectivity

PACKAGE

RGK = 9-mm × 9-mm VQFN

SERIES NUMBER

3 = Wi-Fi Centric

MEMORY SIZE

M2 = 256KB RAM

12 = 1MB Flash and 256KB RAM

MCU / HOST

1 = No MCU

2 = MCU

DEVICE VARIANTS

S = Secured

SF = Secured Flash

DEVICE GENERATION

0 = Gen 1

2 = Gen 2

DUAL BAND

0 = 2.4-GHz only

5 = 2.4-GHz and 5-GHz supported

3 = Gen 3

Figure 11-1. CC3230x Device Nomenclature

Submit Document Feedback

89

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

11.4 Documentation Support

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com (for example, CC3230S). In the upper right corner, click the "Alert me" button. This registers you

to receive a weekly digest of product information that has changed (if any). For change details, check the

revision history of any revised document. The current documentation that describes the processor, related

peripherals, and other technical collateral follows.

The following documents provide support for the CC3230 device.

Application Reports

CC3135 and CC3235 SimpleLink™ CC3135 and CC3235 SimpleLink Wi-Fi Embedded Programming User

Wi-Fi^®Embedded Programming

User Guide

Guide

SimpleLink™ CC3135, CC3235 Wi- This application report describes the best practices for power

Fi^®Internet-on-a chip™ Networking management and extended battery life for embedded low-power Wi-Fi

Sub-System Power Management

devices such as the SimpleLink Wi-Fi Internet-on-a chip solution from

Texas Instruments.

SimpleLink™ CC31xx, CC32xx Wi- The SimpleLink Wi-Fi CC31xx and CC32xx Internet-on-a chip family of

Fi^®Internet-on-a chip™ Solution

Built-In Security Features

devices from Texas Instruments offer a wide range of built-in security

features to help developers address a variety of security needs, which is

achieved without any processing burden on the main microcontroller

(MCU). This document describes these security-related features and

provides recommendations for leveraging each in the context of

practical system implementation.

SimpleLink™ CC3135, CC3235 Wi- This document describes the OTA library for the SimpleLink Wi-Fi

Fi^®and Internet-of-Things Over-

the-Air Update

CC3x35 family of devices from Texas Instruments and explains how to

prepare a new cloud-ready update to be downloaded by the OTA library.

SimpleLink™ CC3135, CC3235 Wi- This guide describes the provisioning process, which provides the

Fi^®Internet-on-a chip™ Solution

Device Provisioning

SimpleLink Wi-Fi device with the information (network name, password,

and so forth) needed to connect to a wireless network.

Transfer of TI's Wi-Fi^®Alliance

Certifications to Products Based

on SimpleLink™

This document explains how to employ the Wi-Fi® Alliance (WFA)

derivative certification transfer policy to transfer a WFA certification,

already obtained by Texas Instruments, to a system you have

developed.

Using Serial Flash on SimpleLink™ This application note is divided into two parts. The first part provides

CC3135 and CC3235 Wi-Fi^®and

Internet-of-Things Devices

important guidelines and best- practice design techniques to consider

when choosing and embedding a serial Flash paired with the CC3135

and CC3235 (CC3x35) devices. The second part describes the file

system, along with guidelines and considerations for system designers

working with the CC3x35 devices.

90

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

User's Guides

SimpleLink™ Wi-Fi^®and This document provides software (SW) programmers with all of the required

Internet-of-Things

CC31xx and CC32xx

Network Processor

knowledge for working with the networking subsystem of the SimpleLink Wi-Fi

devices. This guide provides basic guidelines for writing robust, optimized

networking host applications, and describes the capabilities of the networking

subsystem. The guide contains some example code snapshots, to give users an

idea of how to work with the host driver. More comprehensive code examples can

be found in the formal software development kit (SDK). This guide does not

provide a detailed description of the host driver APIs.

SimpleLink™ Wi-Fi^®

This document provides the design guidelines of the 4-layer PCB used for the

CC3135 and CC3235 and CC3135 and CC3235 SimpleLink Wi-Fi family of devices from Texas Instruments.

IoT Solution Layout

Guidelines

The CC3135 and CC3235 devices are easy to lay out and are available in quad

flat no-leads (QFNS) packages. When designing the board, follow the suggestions

in this document to optimize performance of the board.

SimpleLink™ CC3235 Wi- The CC3235 SimpleLink LaunchPad Development Kit (LAUNCHXL-CC3235) is a

Fi^®LaunchPad™

Development Kit

Hardware

cost-conscious evaluation platform for Arm Cortex-M4-based MCUs. The

LaunchPad design highlights the CC3230 Internet-on-a chip solution and Wi-Fi

capabilities. The CC3235 LaunchPad also features temperature and

accelerometer sensors, programmable user buttons, three LEDs for custom

applications, and onboard emulation for debugging. The stackable headers of the

CC3235 LaunchPad XL interface demonstrate how easy it is to expand the

functionality of the LaunchPad when interfacing with other peripherals on many

existing BoosterPack^™Plug-in Module add-on boards, such as graphical displays,

audio codecs, antenna selection, environmental sensing, and more.

SimpleLink™ Wi-Fi^®and The Radio Tool serves as a control panel for direct access to the radio, and can be

Internet-on-a chip™

CC3135 and CC3235

Solution Radio Tool

used for both the radio frequency (RF) evaluation and for certification purposes.

This guide describes how to have the tool work seamlessly on Texas Instruments

evaluation platforms such as the BoosterPack™ plus FTDI emulation board for

CC3230 devices, and the LaunchPad™ for CC3230 devices.

SimpleLink™ Wi-Fi^®

CC3135 and CC3235

Provisioning for Mobile

Applications

This guide describes TI’s SimpleLink Wi-Fi provisioning solution for mobile

applications, specifically on the usage of the Android^™and IOS^®building blocks

for UI requirements, networking, and provisioning APIs required for building the

mobile application.

Submit Document Feedback

91

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

More Literature

CC3235 SimpleLink™ Wi-Fi^®and

This technical reference manual details the modules and

Internet of Things Technical Reference peripherals of the CC3230 SimpleLink™ Wi-Fi^®MCU. Each

Manual

description presents the module or peripheral in a general sense.

Not all features and functions of all modules or peripherals may be

present on all devices. Pin functions, internal signal connections,

and operational parameters differ from device to device. The user

should consult the device-specific data sheet for these details.

CC3x35 SimpleLink™ Wi-Fi^®Hardware

Design Checklist

CC3235S/CC3235SF SimpleLink™ Wi-

Fi^®LaunchPad™ Design Files

11.5 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 11-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

CC3230S

Click here

CC3230SF

11.6 Trademarks

WPA^™, WPA2^™, and WPA3^™are trademarks of Wi-Fi Alliance.

Internet-on-a chip^™, LaunchPad^™, BoosterPack^™, SmartConfig^™, Sitara^™, and are trademarks of Texas

Instruments.

Macrocell^™is a trademark of Kappa Global Inc.

Android^™is a trademark of Google LLC.

Wi-Fi CERTIFIED^®, Wi-Fi Alliance^®, Wi-Fi^®, and Wi-Fi Direct^®are registered trademarks of Wi-Fi Alliance.

Arm^®, Cortex^®, and Thumb^®are registered trademarks of Arm Limited.

is a registered trademark of Bluetooth SIG Inc.

Zigbee^®is a registered trademark of Zigbee Alliance.

IOS^®is a registered trademark of Cisco.

All other trademarks are the property of their respective owners.

92

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

93

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

12.1.1 Packaging Information

Orderable

Device

Package Package

Package

Qty

Lead/Ball

Finish⁽³⁾

Device

Status ⁽¹⁾

Pins

Eco Plan ⁽²⁾

MSL Peak Temp ⁽⁴⁾

Op Temp (°C)

Type

Drawing

Marking^{(5) (6)}

Green

(RoHS & no

Sb/Br)

CU NIPDAU |

CU

NIPDAUAG

CC3230SM2RGK

R

Level-3-260C-168

HR

PREVIEW

VQFN

RGK

64

2500

–40 to 85

CC3230SM2

Green

(RoHS & no

Sb/Br)

CU NIPDAU |

CU

NIPDAUAG

CC3230SF12RG

KR

Level-3-260C-168

HR

PREVIEW

VQFN

RGK

64

CC3230SF12

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using

this part in a new design.

PRE_PROD: Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please

check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS

requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where

designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the

die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free

(RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb)

based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).

space

(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.

Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

space

(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

space

(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

space

(6) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will

appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device

Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI

bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.

Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and

accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers

consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to

Customer on an annual basis.

Submit Document Feedback

95

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

12.1.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

W

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

CC3230SM2RGKR

CC3230SF12RGKR

VQFN

RGK

64

2500

330.0

16.4

9.3

1.1

12.0

16.0

Q2

96

Submit Document Feedback

Product Folder Links: CC3230S CC3230SF

CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

www.ti.com

TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

Package Drawing

Pins

64

SPQ

2500

Length (mm)

367.0

Width (mm)

Height (mm)

38.0

CC3230SM2RGKR

CC3230SF12RGKR

VQFN

RGK

367.0

64

367.0

38.0

Submit Document Feedback

97

Product Folder Links: CC3230S CC3230SF

PACKAGE OUTLINE

RGK0064B

VQFN - 1 mm max height

S

C

A

L

E

1

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

9.1

8.9

A

B

PIN 1 INDEX AREA

9.1

8.9

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 7.5

6.3 0.1

SYMM

(0.2) TYP

17

32

16

33

EXPOSED

THERMAL PAD

SYMM

65

2X 7.5

0.30

64X

1

48

60X 0.5

PIN 1 ID

0.18

64

49

0.1

C A B

0.5

0.3

0.05

64X

4222201/B 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGK0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

6.3)

SEE SOLDER MASK

DETAIL

SYMM

64X (0.6)

64

49

64X (0.24)

1

48

60X (0.5)

8X (1.1)

(R0.05) TYP

18X (1.2)

(0.6) TYP

SYMM

65

(8.8)

(

0.2) TYP

VIA

16

33

17

32

(0.6) TYP

18X (1.2)

8X

(1.1)

(8.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222201/B 03/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGK0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

25X ( 1)

64

(1.2) TYP

49

64X (0.6)

64X (0.24)

1

48

60X (0.5)

(R0.05) TYP

(1.2) TYP

65

SYMM

(8.8)

16

33

METAL

TYP

17

32

SYMM

(8.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 65

63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4222201/B 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CC3230SF12RGKR
厂家：	TEXAS INSTRUMENTS
描述：	CC3230S and CC3230SF SimpleLinkâ¢ Wi-FiÂ® 2.4GHz Wireless MCU with Coexistence 无线
文件：	总104页 (文件大小：3597K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC3230SF12RGKR [TI]

相关型号：

CC3230SM2RGKR

CC3235MODAS

CC3235MODASF

CC3235MODASF12MONR

CC3235MODASM2MONR

CC3235MODS

CC3235MODSF

CC3235MODSF12MOBR

CC3235MODSM2MOBR

CC3235S

CC3235SF

CC3235SF12RGKR