CC3235MODSF [TI]

具有 1MB 闪存的 SimpleLink™ 32 位 Arm Cortex-M4 双频带 Wi-Fi CERTIFIED™ 无线模块;


型号：	CC3235MODSF
厂家：	TEXAS INSTRUMENTS
描述：	具有 1MB 闪存的 SimpleLink™ 32 位 Arm Cortex-M4 双频带 Wi-Fi CERTIFIED™ 无线模块无线无线模块闪存
文件：	总117页 (文件大小：4348K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC3235MODS, CC3235MODSF, CC3235MODAS, CC3235MODASF

ZHCSKT8B –FEBRUARY 2020 –REVISED MAY 2021

CC3235MODx 和CC3235MODAx SimpleLink™ Wi-Fi CERTIFIED™ 双频带无线天线

MCU 模块

• 安全性：

1 特性

– WEP

– WPA^™/ WPA2^™PSK

– WPA2 企业

• 完全集成的绿色RoHS 模块，包括所有必需的时

钟、SPI 闪存和无源器件

– WPA3^™个人版

– WPA3^™企业版

– 互联网和应用协议：

• 802.11a/b/g/n：2.4GHz 和5GHz

• 经FCC、IC/ISED、ETSI/CE、MIC 和SRRC 认

证¹

• 经FIPS 140-2 1 级验证的内部IC

• 多层安全特性可帮助开发人员保护身份信息、数据

和软件IP

• 低功耗模式适用于电池供电应用

• 与2.4GHz 无线电共存

• 工业温度：–40°C 至+85°C

• CC3235MODx 多内核架构、片上系统(SoC)

• CC3235MODAx 模块包含集成PCB 天线，可轻松

集成到主机系统中

• 1.27mm 间距QFM 封装，实现轻松组装和低成本

PCB 设计

• HTTP 服务器、mDNS、DNS-SD 和DHCP

• IPv4 和IPv6 TCP/IP 堆栈

• 16 BSD 套接字（完全安全的TLS v1.2 和

SSL 3.0）

– 内置的电源管理子系统：

• 可配置的低功耗配置（始终开启、间歇性连

接、标签）

• 高级低功耗模式

• 集成式直流/直流稳压器

• 多层安全特性：

– 独立执行环境

• 可转让的Wi-Fi 联盟^®认证

• 应用微控制器子系统：

– 网络安全

– 设备身份和密钥

– 硬件加速器加密引擎（AES、DES、SHA/MD5

和CRC）

– 文件系统安全（加密、身份验证、访问控制）

– 初始安全编程

– 软件篡改检测

– ^®运行频率为80MHz 的Arm^®Cortex^®-M4 内核

– 用户专用存储器

• 256KB RAM

• 可选的1MB 可执行文件闪存

– 多种外设和计时器

• McASP 支持两个I2S 通道

• SD、SPI、I²C、UART

• 8 位同步成像仪接口

– 安全引导

– 证书注册请求(CSR)

– 每个设备具有唯一密钥对

• 应用吞吐量

• 4 通道12 位ADC

– UDP：16Mbps

– TCP：13Mbps

• 电源管理子系统：

• 4 个具有16 位PWM 模式的通用计时器

(GPT)

• 看门狗计时器

• 多达27 个GPIO 引脚

• 调试接口：JTAG、cJTAG、SWD

• Wi-Fi 网络处理器子系统：

– 集成式直流/直流转换器支持宽电源电压范围：

• 单电源电压，VBAT：2.3V 至3.6V

– 高级低功耗模式：

– Wi-Fi^®内核：

• 关断：1µA，休眠：5.5µA

• 802.11 a/b/g/n 2.4GHz 和5GHz

• 模式：

• 低功耗深度睡眠(LPDS)：120µA

• 空闲连接（MCU 处于LPDS 状态）：710µA

• RX 流量（MCU 处于活动模式）：59 mA

• TX 流量（MCU 处于活动模式）：223 mA

– 接入点(AP)

– 基站(STA)

– Wi-Fi Direct^®（仅在2.4GHz 受支持）

有关使用SRRC ID 认证的更多信息，请联系TI：www.ti.com.cn/tool/cn/SIMPLELINK-CC3XXX-CERTIFICATION

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWRS243

CC3235MODS, CC3235MODSF, CC3235MODAS, CC3235MODASF

ZHCSKT8B –FEBRUARY 2020 –REVISED MAY 2021

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– Wi-Fi TX 功率

2 应用

• 2.4 GHz：1 DSSS 时为16dBm

• 5 GHz：6 OFDM 时为15.1dBm

– Wi-Fi RX 灵敏度

• 对于物联网应用，例如：

– 医疗和保健

• 多参数患者监护仪

• 心电图(ECG)

• 电子病床和床控制器

• 远程保健系统

• 2.4 GHz：1 DSSS 时为-94.5dBm

• 5 GHz：6 OFDM 时为-89dBm

• 其他集成元件

– 40.0MHz 晶体

– 32.768kHz 晶体(RTC)

– 32Mb SPI 串行闪存

– 楼宇和住宅自动化：

• HVAC 系统和恒温器

• 视频监控、可视门铃和低功耗摄像头

• 楼宇安全系统和电子锁

– 射频滤波器、双工器和无源器件

• 尺寸兼容的QFM 封装

– 电器

– 资产跟踪

– 工厂自动化

– 电网基础设施

– CC3235MODx：1.27mm 间距、

63 引脚、20.5mm × 17.5mm

– CC3235MODAx：1.27mm 间距、

63 引脚、20.5mm × 25.0mm

• 模块支持SimpleLink 开发人员生态系统

3 描述

使用此完全可编程的无线微控制器 (MCU) 模块开始您的设计，它经过 FCC、IC/ISED、ETSI/CE、MIC 和SRRC

认证，且具有内置双带 Wi-Fi 连接。该模块集成有 40MHz 晶体、32.768kHz RTC 时钟、32Mb SPI 串行闪存、射

频滤波器、双工器和无源器件。

SimpleLink^™CC3235MODx 模块提供两种型号：

• CC3235MODS 包括256KB RAM、IoT 网络安全性、器件身份和密钥以及MCU 级安全特性，例如文件系统加

密、用户IP（MCU 图像）加密、安全启动和调试安全性。

• CC3235MODSF 基于CC3235MODS 而构建，除了256KB RAM 以外，还集成了一个用户专用的1MB 可执

行文件闪存。

SimpleLink^™CC3235MODAx 模块提供两种型号：

• CC3235MODAS 包括256KB RAM、IoT 网络安全性、器件身份和密钥以及MCU 级安全特性，例如文件系统

加密、用户IP（MCU 图像）加密、安全启动和调试安全性。

• CC3235MODASF 基于CC3235MODAS 而构建，除了256KB RAM 以外，还集成了一个用户专用的1MB 可

执行文件闪存。

德州仪器 (TI) 的 SimpleLink™ Wi-Fi^®CC3235MODx 和 CC3235MODAx 模块系列专为物联网而设计，是集成了

两个物理隔离片上MCU 的无线模块。

• 应用处理器- Arm^®Cortex^®-M4 MCU，具有用户专用的256KB RAM 和可选的1MB 可执行闪存。

• 用以运行所有Wi-Fi 和互联网逻辑层的网络处理器此基于ROM 的子系统完全减轻了主机MCU 的负载，包括

一个802.11 a/b/g/n 双频带2.4GHz 和5GHz 无线电、基带和带有强大硬件加密引擎的MAC。

这一代引进了可进一步简化物联网连接的新功能。主要新特性包括：

• 802.11a/b/g/n：2.4GHz 和5GHz 支持

• 2.4GHz 与低功耗Bluetooth ^®无线电共存

• 天线分集

• 经FIPS 140-2 1 级验证的内部IC 增强了安全性：认证。

• 可同时打开更多安全套接字（多达16 个）

• 证书注册请求(CSR)

• 在线证书状态协议(OCSP)

• 针对具有低功耗功能以及其他功能的IoT 应用经过Wi-Fi 联盟^®认证

• 降低模板包传输负载的无主机模式

• 改善了快速扫描

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CC3235MODx 和 CC3235MODAx 器件系列是 SimpleLink MCU 平台的一部分，该平台是一个常见、易用的开发

环境，基于单核软件开发套件 (SDK)，具有丰富的工具集和参考设计。E2E^™支持论坛支持 Wi-Fi、低功耗蓝牙、

低于1GHz 和主机MCU。关于更多信息，请访问www.ti.com.cn/simplelink 或www.ti.com.cn/simplelinkwifi。

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

CC3235MODSM2MOB

封装

QFM (63)

20.5mm × 17.5mm

20.5 mm × 25 mm

CC3235MODSF12MOB

CC3235MODASM2MON

CC3235MODASF12MON

(1) 如需更多信息，请参阅节13。

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4 功能方框图

图4-1 显示了CC3235MODx 模块的功能方框图。

CC3235

40 MHz

RF_ABG

32.768 kHz

BGN

UART

SPI

WRF_BGN

5 GHz

SPDT

nReset

Aband

WRF_A

2.3 V to 3.6 V

VBAT

32-Mbit

SFlash

External SPI

Programming

User GPIOx

图4-1. CC3235MODx 功能方框图

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图4-2 显示了CC3235MODAx 模块的功能方框图。

CC3235

40 MHz

RF_ABG

32.768 kHz

BGN

UART

SPI

WRF_BGN

5 GHz

SPDT

nReset

Aband

WRF_A

2.3 V to 3.6 V

VBAT

32-Mbit

SFlash

External SPI

Programming

User GPIOx

图4-2. CC3235MODAx 功能方框图

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图4-3 显示了CC3235x 硬件概述。

CC32xx œ Single-Chip Wireless MCU

1-MB Flash (optional)

256-KB RAM

ROM

ARM

Cortex-M4

80 MHz

1x SPI

2x UART

DMA

Timers

1x I²C

1x I2S/PCM

1x SD/MMC

GPIOs

COEX I/Os

Antenna Selection

8-bit Camera

4x ADC

Network Processor

Application

Power

Management

Protocols

Wi-Fi Driver

TCP/IP Stack

Oscillators

DC-DC

RTC

RAM

ROM

(ARM Cortex)

Dual Band

Wi-Fi

Synthesizer

图4-3. CC3235x 硬件概览

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图4-4 显示了CC3235x 嵌入式软件的概述。

Applications MCU

Customer Application

BSD

Socket

NetApp

Wi-Fi

Peripherals

Driver

SimpleLink Driver APIs

Host Interface

Network Applications

TCP/IP Stack

WLAN Security

and

Management

WLAN MAC and PHY

Network Processor

图4-4. CC3235x 嵌入式软件概览

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Table of Contents

9.4 Wi-Fi Network Processor Subsystem....................... 66

9.5 Security.....................................................................68

9.6 FIPS 140-2 Level 1 Certification............................... 70

9.7 Power-Management Subsystem...............................70

9.8 Low-Power Operating Mode..................................... 70

9.9 Memory.....................................................................73

9.10 Restoring Factory Default Configuration.................75

9.11 Boot Modes.............................................................75

9.12 Hostless Mode........................................................ 76

9.13 Device Certification and Qualification..................... 77

9.14 Module Markings.....................................................79

9.15 End Product Labeling..............................................80

9.16 Manual Information to the End User....................... 80

10 Applications, Implementation, and Layout............... 81

10.1 Typical Application.................................................. 81

10.2 Device Connection and Layout Fundamentals....... 88

10.3 PCB Layout Guidelines...........................................88

11 Environmental Requirements and SMT

Specifications................................................................95

11.1 PCB Bending...........................................................95

11.2 Handling Environment.............................................95

11.3 Storage Condition................................................... 95

11.4 PCB Assembly Guide..............................................95

11.5 Baking Conditions................................................... 96

11.6 Soldering and Reflow Condition..............................97

12 Device and Documentation Support..........................98

12.1 Development Tools and Software........................... 98

12.2 Firmware Updates...................................................99

12.3 Device Nomenclature..............................................99

12.4 Documentation Support........................................ 100

12.5 Related Links........................................................ 102

12.6 支持资源................................................................102

12.7 Trademarks...........................................................103

12.8 Electrostatic Discharge Caution............................103

12.9 Glossary................................................................103

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 2

3 描述................................................................................... 2

4 功能方框图.........................................................................4

5 Revision History.............................................................. 8

6 Device Comparison.........................................................9

6.1 Related Products...................................................... 12

7 Terminal Configuration and Functions........................13

7.1 CC3235MODx and CC3235MODAx Pin Diagram....13

7.2 Pin Attributes and Pin Multiplexing........................... 14

7.3 Signal Descriptions................................................... 31

7.4 Drive Strength and Reset States for Analog-

Digital Multiplexed Pins............................................... 36

7.5 Pad State After Application of Power to Chip, but

Before Reset Release................................................. 36

7.6 Connections for Unused Pins................................... 36

8 Specifications................................................................ 37

8.1 Absolute Maximum Ratings...................................... 37

8.2 ESD Ratings............................................................. 37

8.3 Recommended Operating Conditions.......................37

8.4 Current Consumption (CC3235MODS and

CC3235MODAS).........................................................38

8.5 Current Consumption (CC3235MODSF and

CC3235MODASF).......................................................40

8.6 TX Power Control for 2.4 GHz Band.........................42

8.7 TX Power Control for 5 GHz..................................... 44

8.8 Brownout and Blackout Conditions...........................44

8.9 Electrical Characteristics for GPIO Pins................... 46

8.10 CC3235MODAx Antenna Characteristics...............48

8.11 WLAN Receiver Characteristics..............................48

8.12 WLAN Transmitter Characteristics..........................49

8.13 BLE and WLAN Coexistence Requirements...........50

8.14 Reset Requirement.................................................50

8.15 Thermal Resistance Characteristics for MOB

and MON Packages.................................................... 50

8.16 Timing and Switching Characteristics..................... 51

9 Detailed Description......................................................64

9.1 Overview...................................................................64

9.2 Functional Block Diagram.........................................64

9.3 Arm Cortex-M4 Processor Core Subsystem.............65

Information.................................................................. 104

13.1 Mechanical, Land, and Solder Paste Drawings.... 104

13.2 Package Option Addendum..................................104

5 Revision History

Changes from August 20, 2020 to May 13, 2021 (from Revision A (Aug 2020) to Revision B

(May 2021))

Page

• 向节1“安全”中的Wi-Fi 网络处理器子系统添加了WPA3 企业版................................................................... 1

• 更改了图4-1 ...................................................................................................................................................... 4

• Added WPA3 enterprise to 节9.4 ....................................................................................................................66

• Added WPA3 Enterprise to 节9.4.1 .................................................................................................................66

• Added WPA3 enterprise to Wi-Fi security Feature in 表9-1 ............................................................................66

• Changed 图12-1 ............................................................................................................................................. 99

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6 Device Comparison

表6-2 shows the features supported across different CC3x35 modules.

表6-1. Device Features Comparison

DEVICE

FEATURE

CC3135MOD

CC3235MODS

CC3235S

CC3235MODSF

CC3235SF

On-board chip

On-board ANT

sFlash

CC3135

32-Mbit

Regulatory certifications

Wi-Fi Alliance^®Certification

Input voltage

FCC, IC/ISED, ETSI/CE, MIC

Yes

FCC, IC/ISED, ETSI/CE, MIC

Yes

FCC, IC/ISED, ETSI/CE, MIC

Yes

2.3 V to 3.6 V

17.5 mm × 20.5 mm QFM

–40°C to +85°C

Wi-Fi Network Processor

802.11 a/b/g/n

2.4 GHz, 5 GHz

IPv4, IPv6

2.3 V to 3.6 V

17.5 mm × 20.5 mm QFM

–40°C to +85°C

Wireless Microcontroller

802.11 a/b/g/n

2.4 GHz, 5 GHz

IPv4, IPv6

Package

17.5 mm × 20.5 mm QFM

–40°C to +85°C

Wireless Microcontroller

802.11 a/b/g/n

Operating temperature range

Classification

Standard

Frequency

2.4 GHz, 5 GHz

IPv4, IPv6

TCP/IP Stack

Secured sockets

Integrated MCU

Arm Cortex-M4 at 80 MHz

–

ON-CHIP APPLICATION MEMORY

RAM

256KB

1MB

–

Flash

–

PERIPHERALS AND INTERFACES

Universal Asynchronous

Receiver/Transmitter (UART)

Serial Port Interface (SPI)

Multichannel Audio Serial Port (McASP)- I2S or PCM

Inter-Integrated Circuit (I²C)

2-ch

–

Analog-to-digital converter (ADC)

Parallel interface (8-bit PI)

4-ch, 12-bit

General-purpose timers

Multimedia card (MMC / SD)

SECURITY FEATURES

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表6-1. Device Features Comparison (continued)

DEVICE

FEATURE

CC3135MOD

CC3235MODS

CC3235MODSF

Unique Device Identity

Additional networking security

Trusted Root-Certificate Catalog

TI Root-of-Trust Public key

Trusted Root-Certificate Catalog

TI Root-of-Trust Public key

Trusted Root-Certificate Catalog

TI Root-of-Trust Public key

Hardware acceleration

Secure boot

Hardware Crypto Engines

Yes

Hardware Crypto Engines

Yes

–

File system security

Secure key storage

Enhanced Application Level Security

FIPS 140-2 Level 1 Certification

Software tamper detection

Cloning protection

Initial secure programming

Software tamper detection

Cloning protection

Initial secure programming

–

Yes

表6-2. Device Features Comparison

DEVICE

FEATURE

CC3135MOD

CC3135

CC3235MODS

CC3235S

CC3235MODSF

CC3235MODAS

CC3235S

Yes

CC3235MODASF

CC3235SF

Yes

On-board chip

On-board ANT

sFlash

CC3235SF

32-Mbit

FCC, IC/ISED, ETSI/CE, MIC,

SRRC⁽¹⁾

FCC, IC/ISED, ETSI/CE, MIC,

Regulatory certifications

FCC, IC/ISED, ETSI/CE, MIC

SRRC⁽¹⁾

Wi-Fi Alliance^®Certification

Input voltage

Yes

2.3 V to 3.6 V

17.5 mm × 20.5 mm QFM

–40°C to +85°C

Wi-Fi Network Processor

802.11 a/b/g/n

2.4 GHz, 5 GHz

IPv4, IPv6

2.3 V to 3.6 V

25.0 mm × 20.5 mm QFM

–40°C to +85°C

Wireless Microcontroller

802.11 a/b/g/n

2.4 GHz, 5 GHz

IPv4, IPv6

Package

17.5 mm × 20.5 mm QFM

–40°C to +85°C

Wireless Microcontroller

802.11 a/b/g/n

2.4 GHz, 5 GHz

IPv4, IPv6

17.5 mm × 20.5 mm QFM

–40°C to +85°C

Wireless Microcontroller

802.11 a/b/g/n

2.4 GHz, 5 GHz

IPv4, IPv6

25.0 mm × 20.5 mm QFM

–40°C to +85°C

Wireless Microcontroller

802.11 a/b/g/n

2.4 GHz, 5 GHz

IPv4, IPv6

Operating temperature range

Classification

Standard

Frequency

TCP/IP Stack

Secured Sockets

Integrated MCU

Arm Cortex-M4 at 80 MHz

–

ON-CHIP APPLICATION MEMORY

RAM

256KB

1MB

256KB

1MB

–

Flash

–

PERIPHERALS AND INTERFACES

Universal Asynchronous

Receiver/Transmitter (UART)

Serial Port Interface (SPI)

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FEATURE

ZHCSKT8B –FEBRUARY 2020 –REVISED MAY 2021

表6-2. Device Features Comparison (continued)

DEVICE

CC3135MOD

CC3235MODS

CC3235MODSF

CC3235MODAS

CC3235MODASF

Multichannel Audio Serial Port

(McASP)- I2S or PCM

2-ch

–

Inter-Integrated Circuit (I²C)

Analog-to-digital converter (ADC)

Parallel interface (8-bit PI)

General-purpose timers

–

4-ch, 12-bit

Multimedia card (MMC / SD)

SECURITY FEATURES

Unique Device Identity

Additional networking security

Trusted Root-Certificate Catalog

TI Root-of-Trust Public key

Trusted Root-Certificate Catalog

TI Root-of-Trust Public key

Trusted Root-Certificate Catalog

TI Root-of-Trust Public key

Trusted Root-Certificate Catalog

TI Root-of-Trust Public key

Trusted Root-Certificate Catalog

TI Root-of-Trust Public key

Hardware acceleration

Secure boot

Hardware Crypto Engines

Yes

Hardware Crypto Engines

Yes

Hardware Crypto Engines

Yes

Hardware Crypto Engines

Yes

–

File system security

Secure key storage

Software tamper detection

Cloning protection

Secure key storage

Software tamper detection

Cloning protection

Secure key storage

Software tamper detection

Cloning protection

Secure key storage

Software tamper detection

Cloning protection

Enhanced Application Level

Security

–

Initial secure programming

FIPS 140-2 Level 1 Certification

Yes

(1) Contact TI for more information on using SRRC ID Certification: www.ti.com/tool/SIMPLELINK-CC3XXX-CERTIFICATION

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6.1 Related Products

For information about other devices in this family of products or related products see the links below.

The SimpleLink™ MCU offers a single development environment that delivers flexible hardware, software and

Portfolio

tool options for customers developing wired and wireless applications. With 100

percent code reuse across host MCUs, Wi-Fi^®, Bluetooth^®low energy, Sub-1GHz

devices and more, choose the MCU or connectivity standard that fits your design. A

one-time investment with the SimpleLink software development kit (SDK) allows you

to reuse often, opening the door to create unlimited applications.

SimpleLink™ Wi-Fi^®

Family

The SimpleLink Wi-Fi Family offers several Internet-on-a chip solutions, which

address the need of battery operated, security enabled products. Texas instruments

offers a single chip wireless microcontroller and a wireless network processor which

can be paired with any MCU, to allow developers to design new wi-fi products, or

upgrade existing products with wi-fi capabilities.

BoosterPack™ Plug-In BoosterPack^™Plug-In Modules extend the functionality of TI LaunchPad Kit.

Modules

Application specific BoosterPack Plug in modules allow you to explore a broad range

of applications, including capacitive touch, wireless sensing, LED Lighting control, and

more. Stack multiple BoosterPack modules onto a single LaunchPad kit to further

enhance the functionality of your design.

Reference Designs for TI Designs Reference Design Library is a robust reference design library spanning

CC3200, CC3220, and analog, embedded processor and connectivity. Created by TI experts to help you jump

CC3235 Modules

start your system design, all TI Designs include schematic or block diagrams, BOMs

and design files to speed your time to market.

SimpleLink™ Wi-Fi^®

CC3235 SDK

The SDK contains drivers for the CC3235 programmable MCU, sample applications,

and documentation required to start development with CC3235x solutions.

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7 Terminal Configuration and Functions

7.1 CC3235MODx and CC3235MODAx Pin Diagram

图7-1 shows the pin diagram for the CC3235MODx module.

GND

FLASH_SPI_CLK

FLASH_SPI_nCS_IN

FLASH_SPI_MISO

JTAG_TDI

CC3235MODx

GPIO22

GPIO13

GPIO12

GPIO17

GPIO16

GPIO15

GPIO14

GPIO11

GPIO10

GND

图7-1 shows the approximate location of pins on the module.

图7-1. CC3235MODx Pin Diagram Bottom View

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图7-2 shows the pin diagram for the CC3235MODAx module.

GND

FLASH_SPI_CLK

FLASH_SPI_nCS_IN

FLASH_SPI_MISO

JTAG_TDI

GPIO22

CC3235MODAx

GPIO13

GPIO12

GPIO17

GPIO16

GPIO15

GPIO14

GPIO11

GPIO10

GND

图7-2. CC3235MODAx Pin Diagram Bottom View

7.2 Pin Attributes and Pin Multiplexing

节7.2.1 lists the pin descriptions of the CC3235MODx and CC3235MODAx module.

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7.2.1 Module Pin Descriptions

MODULE PIN

CC3235 DEVICE PIN

NO.

TYPE⁽¹⁾

MODULE PIN DESCRIPTION

NO.

NAME

GND

Ground

GPIO⁽²⁾

–

I/O

–

GND

GPIO10

GPIO11

GPIO14

GPIO15

GPIO16

GPIO17

GPIO12

GPIO13

GPIO22

JTAG_TDI

FLASH_SPI_MISO

FLASH_SPI_nCS_IN

FLASH_SPI_CLK

GND

JTAG TDI input. Leave unconnected if not used on product⁽²⁾

External serial flash programming: SPI data in

External serial flash programming: SPI chip select (active low)

External serial flash programming: SPI clock

Ground

–

FLASH_SPI_MOSI

JTAG_TDO

GPIO28

External serial flash programming: SPI data out

JTAG TDO output. Leave unconnected if not used on product⁽¹⁾

GPIO⁽²⁾

I/O

No Connect

–

I/O

–

JTAG TCK input. Leave unconnected if not used on product.⁽²⁾An internal 100-kΩ

pulldown resistor is tied to this pin.

JTAG TMS input. Leave unconnected if not used on product.⁽²⁾

JTAG_TCK

JTAG_TMS

SOP2

An internal 100-kΩpulldown resistor is tied to this SOP pin. An external 10-kΩresistor

is required to pull this pin high. See 节9.11.1 for SOP[2:0] configuration modes.

–

An internal 100-kΩpulldown resistor is tied to this SOP pin. An external 10-kΩresistor

is required to pull this pin high. See 节9.11.1 for SOP[2:0] configuration modes.

SOP1

GND

Ground

–

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MODULE PIN

TYPE⁽¹⁾

CC3235 DEVICE PIN

NO.

MODULE PIN DESCRIPTION

NO.

NAME

GND

Ground

–

GND

CC3235MODx: RF ABG band

CC3235MODAx: NC

I/O

2.4 GHz and 5 GHz RF input/output

GND

Ground

–

No Connect

An internal 100-kΩpulldown resistor is tied to this SOP pin. An external 10-kΩresistor

is required to pull this pin high. See 节9.11.1 for SOP[2:0] configuration modes.

SOP0

–

nRESET

There is an internal, 100-kΩpullup resistor option from the nRESET pin to

VBAT_RESET. Note: VBAT_RESET is not connected to VBAT1 or VBAT2 within the

module. The following connection schemes are recommended:

•

Connect nRESET to a switch, external controller, or host, only if nRESET will be in a

defined state under all operating conditions. Leave VBAT_RESET unconnected to

save power.

VBAT_RESET

–

•

If nRESET cannot be in a defined state under all operating conditions, connect

VBAT_RESET to the main module power supply (VBAT1 and VBAT2). Due to the

internal pullup resistor a leakage current of 3.3 V / 100 kΩis expected.

VBAT1

GND

Power

Power supply for the module, must be connected to battery (2.3 V to 3.6 V)

Ground

–

No Connect

VBAT2

Power

10, 44, 54

Power supply for the module, must be connected to battery (2.3 V to 3.6 V)

No Connect

GPIO⁽²⁾

–

GPIO30

GND

I/O

Ground

GPIO⁽²⁾

–

GPIO0

I/O

No Connect

GPIO⁽²⁾

–

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

I/O

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MODULE PIN

NAME

GPIO9

GND

CC3235 DEVICE PIN

NO.

TYPE⁽¹⁾

MODULE PIN DESCRIPTION

NO.

I/O

–

GPIO⁽²⁾

Thermal ground

GND

(1) I = input; O = output; I/O = bidirectional

(2) For pin multiplexing details, see 表7-1.

The module makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To

achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at module reset) and register control.

The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does not ensure that the proper pin

multiplexing options are selected for the peripherals or interface mode used. 表 7-1 describes the general pin attributes and presents an overview of pin

multiplexing. All pin multiplexing options are configurable using the pin MUX registers. The following special considerations apply:

• All I/Os support drive strengths of 2, 4, and 6 mA. Drive strength is individually configurable for each pin.

• All I/Os support 10-µA pullup and pulldown resistors.

• By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.

• All digital I/Os are non fail-safe.

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Note

If an external device drives a positive voltage to the signal pads and the CC3235MODx or CC3235MODAx module is not powered, DC is

drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3235MODx or

CC3235MODAx module can occur. To prevent current draw, TI recommends any one of the following conditions:

• All devices interfaced to the CC3235MODx and CC3235MODAx module must be powered from the same power rail as the chip.

• Use level shifters between the device and any external devices fed from other independent rails.

• The nRESET pin of the CC3235MODx and CC3235MODAx module must be held low until the VBAT supply to the module is driven and

stable.

• All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the TDI, TDO, TCK, TMS, and Flash_SPI

pins to mode 1. All the other pins are left in the Hi-Z state.

The ADC inputs are tolerant up to 1.8 V (see 表 8-24 for more details about the usable range of the ADC). On the other hand, the digital pads

can tolerate up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of

the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass

switches (S7 [Pin 47], S8 [Pin 48], S9 [Pin 49], and S10 [Pin 50]). For more information, see 表7-3.

表7-1. Pin Attributes and Pin Multiplexing

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

GND

N/A

GND

N/A

Hi-Z,

Pull,

Drive

GPIO10

GPIO

I/O

(open

drain)

Hi-Z,

Pull,

Drive

I2C_SCL

I²C clock

GPIO_PAD_

CONFIG_10

Hi-Z,

Pull,

Hi-Z,

Pull,

Drive

Pulse-width

modulated O/P

GPIO10

I/O

Hi-Z

GT_PWM06

UART1_TX

(0x4402 E0C8)

Drive

UART TX data

SDCARD_CLK SD card clock

Hi-Z,

Pull,

GT_CCP01 Timer capture port

Drive

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表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

Hi-Z,

GPIO11

GPIO

I/O

Pull,

Drive

I/O

(open

drain)

Hi-Z,

Pull,

Drive

I2C_SDA

I²C data

Hi-Z,

Pull,

Drive

Pulse-width

modulated O/P

GT_PWM07

pXCLK (XVCLK)

SDCARD_CMD

Free clock to

parallel camera

GPIO_PAD_

CONFIG_11

Hi-Z,

Pull,

GPIO11

I/O

Yes

Hi-Z

I/O

(open

drain)

Hi-Z,

Pull,

Drive

SD card command

line

(0x4402 E0CC)

Drive

Hi-Z,

Pull,

Drive

UART1_RX

GT_CCP02

UART RX data

Hi-Z,

Pull,

Timer capture port

Drive

Hi-Z,

Pull,

Drive

I2S audio port

frame sync

MCAFSX

GPIO14

GPIO

I/O

(open

drain)

I2C_SCL

GSPI_CLK

I²C clock

GPIO_PAD_

CONFIG_14

(0x4402 E0D8)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

GPIO14

I/O

Hi-Z

General SPI clock

I/O

pDATA8

(CAM_D4)

Parallel camera

data bit 4

GT_CCP05

Timer capture port

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nRESET = 0

表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

Value

GPIO15

I2C_SDA

GPIO

I/O

(open

drain)

I²C data

GPIO_PAD_

CONFIG_15

(0x4402 E0DC)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

GSPI_MISO

General SPI MISO

I/O

GPIO15

I/O

Hi-Z

pDATA9

(CAM_D5)

Parallel camera

data bit 5

GT_CCP06

Timer capture port

SD card data

SDCARD_

DATA0

I/O

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

GPIO16

GPIO

I/O

Hi-Z,

Pull,

Drive

GPIO_PAD_

CONFIG_16

Hi-Z,

Pull,

Hi-Z,

Pull,

GPIO16

I/O

Hi-Z

GSPI_MOSI

General SPI MOSI

(0x4402 E0E0)

Drive

Hi-Z,

Pull,

Drive

pDATA10

(CAM_D6)

Parallel camera

data bit 6

UART1_TX

GT_CCP07

UART1 TX data

Hi-Z,

Pull,

Drive

Timer capture port

SDCARD_CLK SD card clock

Zero

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表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

GPIO17

GPIO

I/O

UART1_RX

UART1 RX data

General SPI chip

select

GPIO_PAD_

CONFIG_17

(0x4402 E0E4)

GSPI_CS

I/O

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

GPIO17

GPIO12

GPIO13

I/O

Yes

Hi-Z

pDATA11

(CAM_D7)

Parallel camera

data bit 7

SDCARD_

CMD

SD card command

line

I/O

Hi-Z,

Pull,

Drive

GPIO12

McACLK

GPIO

I/O

Hi-Z,

Pull,

Drive

I2S audio port clock

output

Hi-Z,

Pull,

Drive

Parallel camera

vertical sync

GPIO_PAD_

CONFIG_12

(0x4402 E0D0)

Hi-Z,

Pull,

Drive

pVS (VSYNC)

Hi-Z

I/O

(open

drain)

Hi-Z,

Pull,

Drive

I2C_SCL

UART0_TX

GT_CCP03

GPIO13

I²C clock

UART0 TX data

Timer capture port

GPIO

Hi-Z,

Pull,

Drive

I/O

(open

drain)

I2C_SDA

I²C data

GPIO_PAD_

CONFIG_13

(0x4402 E0D4)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

Yes

Hi-Z

Parallel camera

horizontal sync

pHS (HSYNC)

UART0_RX

GT_CCP04

UART0 RX data

Timer capture port

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表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

GPIO22

McAFSX

GT_CCP04

TDI

GPIO

I/O

GPIO_PAD_

CONFIG_22

(0x4402 E0F8)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

I2S audio port

frame sync

GPIO22

I/O

Hi-Z

Timer capture port

JTAG TDI. Reset

default pinout.

Hi-Z,

Pull,

Drive

GPIO23

GPIO

I/O

Muxed

GPIO_PAD_

with JTAG CONFIG_23

Hi-Z,

Pull,

Drive

JTAG_TDI

Hi-Z

UART1_TX

UART1 TX data

TDI

(0x4402 E0FC)

I/O

(open

drain)

Hi-Z,

Pull,

Drive

I2C_SCL

I2C clock

FLASH_

SPI_

MISO

Data from SPI

FLASH_SPI_MISO serial flash (fixed

default)

N/A

Hi-Z

FLASH_

SPI_

nCS_IN

Chip select to SPI

Hi-Z,

Pull,

Drive

FLASH_SPI_nCS_

serial flash (fixed

default)

Hi-Z,

Pull,

Hi-Z,

Pull,

Drive

FLASH_

SPI_CLK

FLASH_SPI_

CLK

Clock to SPI serial

flash (fixed default)

N/A

GND

N/A

Hi-Z

N/A

Hi-Z

Drive⁽³⁾

GND

N/A

FLASH_

SPI_

MOSI

Hi-Z,

Pull,

Hi-Z,

Pull,

Drive

Data to SPI serial

flash (fixed default)

FLASH_SPI_MOSI

Drive⁽³⁾

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表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

JTAG TDO. Reset

TDO

GPIO24

PWM0

default pinout.

GPIO

I/O

Driven

high in

SWD;

driven

low in 4-

wire

Pulse-width

modulated O/P

Muxed

with JTAG CONFIG_ 24

TDO

GPIO_PAD_

Hi-Z,

Pull,

Drive

UART1_RX

UART1 RX data

JTAG_TDO

I/O

Yes

Hi-Z

I/O

(open

drain)

(0x4402 E100)

I2C_SDA

I²C data

JTAG

GT_CCP06

McAFSX

Timer capture port

I2S audio port

frame sync

GPIO_PAD_

CONFIG_ 40

(0x4402 E140)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

GPIO28

I/O

N/A

GPIO28

GPIO

I/O

N/A

Hi-Z

N/A

WLAN

analog

N/A

Reserved

N/A

JTAG/SWD TCK.

Reset default

pinout.

Muxed

with

JTAG/

SWD-

TCK

GPIO_PAD_

CONFIG_ 28

(0x4402 E110)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

JTAG_TCK

JTAG_TMS

I/O

Hi-Z

Pulse-width

modulated O/P

GT_PWM03

Muxed

with

JTAG/

SWD-

TMSC

JTAG/SWD TMS.

Reset default

pinout.

GPIO_PAD_

CONFIG_ 29

(0x4402 E114)

TMS

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

I/O

GPIO29

GPIO

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nRESET = 0

表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

Value

Hi-Z,

GPIO25

GT_PWM02

McAFSX

GPIO

Pull,

Drive

Hi-Z,

Pull,

Drive

Pulse-width

modulated O/P

GPIO_PAD_

CONFIG_ 25

(0x4402 E104)

Hi-Z,

Pull,

Drive

I2S audio port

frame sync

Driven

Low

23⁽⁴⁾

SOP2

O only

Hi-Z

Enable to optional

external 40-MHz

TCXO

See⁽⁵⁾

TCXO_EN

Hi-Z,

Pull,

Drive

See⁽⁶⁾

N/A

SOP2

SOP1

Sense-on-power 2

Sense-on-power 1

Config

sense

SOP1

N/A

GND

N/A

GND

N/A

WLAN

analog

CC3235MODx:

RF ABG band

RF_ABG

GND

N/A

GND

WLAN

analog

Reserved

Config

sense

SOP0

N/A

SOP0

nRESET

Sense-on-power 0

N/A

Master chip reset.

Active low.

nRESET

Global reset

VBAT_

RESET

VBAT to nRESET

pullup resistor

VBAT_RESET

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表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

Analog DC/DC

Supply

input

input (connected to

chip input supply

[VBAT])

VBAT1

N/A

VBAT1

N/A

GND

N/A

GND

N/A

WLAN

analog

Reserved

Supply

input

Analog input supply

VBAT

VBAT2

N/A

VBAT2

N/A

WLAN

analog

Reserved

Hi-Z,

Pull,

Drive

GPIO30

UART0_TX

McACLK

GPIO

I/O

UART0 TX data

I2S audio port clock

Hi-Z,

Pull,

User

config

not

Drive

GPIO_PAD_

CONFIG_30

(0x4402 E118)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

GPIO30

I/O

Hi-Z

I2S audio port

frame sync

McAFSX

required

(7)

Hi-Z,

Pull,

GT_CCP05

Timer capture port

Drive

Hi-Z,

Pull,

Drive

GSPI_MISO

GND

General SPI MISO

GND

I/O

GND

N/A

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表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

Hi-Z,

Pull,

Hi-Z,

Pull,

GPIO0

UART0_CTS

McAXR1

GPIO

I/O

Hi-Z

Drive

UART0 Clear-to-

Send input (active

low)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

I2S audio port data

1 (RX/TX)

I/O

User

config

not

Hi-Z,

Pull,

Drive

GPIO_PAD_

CONFIG_0

GT_CCP00

GSPI_CS

Timer capture port

GPIO0

I/O

Hi-Z,

Pull,

Drive

required

(0x4402 E0A0)

(7)

Hi-Z,

Pull,

Drive

Hi-Z

General SPI chip

select

I/O

UART1 Request-to-

Send (active low)

UART1_RTS

UART0_RTS

UART0 Request-to-

Send (active low)

Hi-Z,

Pull,

Drive

I2S audio port data

0 (RX/TX)

McAXR0

I/O

WLAN

analog

N/A

Reserved

GPIO

N/A

Hi-Z,

Pull,

Drive

GPIO1

I/O

UART0_TX

UART0 TX data

Pixel clock from

pCLK (PIXCLK) parallel camera

sensor

GPIO_PAD_

CONFIG_1

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

GPIO1

I/O

Hi-Z

(0x4402 E0A4)

Drive

UART1_TX

UART1 TX data

Hi-Z,

Pull,

GT_CCP01

Timer capture port

Drive

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表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

Hi-Z,

Pull,

Drive

ADC channel 0

input (1.5-V max)

See⁽⁵⁾

ADC_CH0

GPIO2

Hi-Z,

Pull,

GPIO

I/O

Drive

Analog

input (up to

1.8 V)/

GPIO_PAD_

CONFIG_2

(0x4402 E0A8)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

47⁽⁹⁾

GPIO2

Yes

See⁽⁸⁾

UART0_RX

UART1_RX

GT_CCP02

ADC_CH1

UART0 RX data

UART1 RX data

Timer capture port

Hi-Z

digital I/O

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

ADC channel 1

input (1.5-V max)

See⁽⁵⁾

Hi-Z,

Pull,

Drive

Analog

input (up to

1.8 V)/

GPIO_PAD_

CONFIG_3

(0x4402 E0AC)

Hi-Z,

Pull,

Drive

GPIO3

GPIO

I/O

48⁽⁹⁾

GPIO3

See⁽⁸⁾

Hi-Z

digital I/O

UART1_TX

UART1 TX data

Hi-Z,

Pull,

Drive

pDATA7

(CAM_D3)

Parallel camera

data bit 3

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nRESET = 0

表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

Value

Hi-Z,

Pull,

Drive

ADC channel 2

input (1.5-V max)

See⁽⁵⁾

ADC_CH2

GPIO4

Hi-Z,

Pull,

GPIO

I/O

Analog

input (up to

1.8 V)/

GPIO_PAD_

CONFIG_4

(0x4402 E0B0)

Hi-Z,

Pull,

Drive

49⁽⁹⁾

GPIO4

Yes

See⁽⁸⁾

Yes

Hi-Z

Hi-Z,

Pull,

digital I/O

UART1_RX

UART1 RX data

Drive

Hi-Z,

Pull,

Drive

pDATA6

(CAM_D2)

Parallel camera

data bit 2

i-Z,

Pull,

Drive

ADC channel 3

input (1.5 V max)

See⁽⁵⁾

ADC_CH3

GPIO5

I/O

Hi-Z,

Pull,

Drive

GPIO

Analog

input up to

1.5 V

GPIO_PAD_

CONFIG_5

(0x4402 E0B4)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

pDATA5

(CAM_D1)

Parallel camera

data bit 1

50⁽⁹⁾

GPIO5

See⁽⁸⁾

Hi-Z

Hi-Z,

Pull,

Drive

I2S audio port data

1 (RX, TX)

McAXR1

I/O

Hi-Z,

Pull,

GT_CCP05

Timer capture port

Drive

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表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

nRESET = 0

Value

Hi-Z,

GPIO6

GPIO

I/O

Pull,

Drive

UART0 Request-to-

Send (active low)

UART0_RTS

Hi-Z,

Pull,

Drive

pDATA4

(CAM_D0)

Parallel camera

data bit 0

GPIO_PAD_

CONFIG_6

(0x4402 E0B8)

Hi-Z,

Pull,

Drive

GPIO6

I/O

Hi-Z

Hi-Z,

Pull,

Drive

UART1 Clear to

send (active low)

UART1_CTS

UART0_CTS

GT_CCP06

GPIO7

Hi-Z,

Pull,

Drive

UART0 Clear to

send (active low)

Hi-Z,

Pull,

Drive

Timer capture port

GPIO

Hi-Z,

Pull,

Drive

I/O

Hi-Z,

Pull,

Drive

McACLK

I2S audio port clock

GPIO_PAD_

CONFIG_7

Hi-Z,

Pull,

GPIO7

I/O

Hi-Z

(0x4402 E0BC)

UART1 Request to

send (active low)

Drive

UART1_RTS

UART0_RTS

UART0 Request to

send (active low)

UART0_TX

GPIO8

UART0 TX data

GPIO

I/O

Interrupt from SD

card (future

support)

SDCARD_IRQ

GPIO_PAD_

CONFIG_8

Hi-Z,

Pull,

Hi-Z,

Pull,

GPIO8

I/O

Hi-Z

(0x4402 E0C0)

Drive

I2S audio port

frame sync

McAFSX

GT_CCP06

Timer capture port

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nRESET = 0

表7-1. Pin Attributes and Pin Multiplexing (continued)

GENERAL PIN ATTRIBUTES

FUNCTION

PAD STATES

Dig. Pin

Mux

Config.

Mode

Config.

Addl.

Analog

Mux

Select as

Wakeup

Source

Muxed

With

JTAG

Signal

Dig. Pin Mux

Config. Reg.

Pkg. Pin Pin Alias

Use

Signal Name

Signal Description Directio LPDS⁽¹⁾

Hib⁽²⁾

Value

GPIO9

GPIO

I/O

Pulse-width

modulated O/P

GT_PWM05

GPIO_PAD_

CONFIG_9

(0x4402 E0C4)

Hi-Z,

Pull,

Drive

Hi-Z,

Pull,

Drive

SDCARD_

DATA0

GPIO9

I/O

SD card data

I/O

Hi-Z

I2S audio port data

(RX, TX)

McAXR0

GT_CCP00

GND

Timer capture port

GND

N/A

GND

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7.3 Signal Descriptions

表7-2. Signal Descriptions

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

ADC_CH0

ADC_CH1

ADC_CH2

ADC_CH3

GPIO10

GPIO14

GPIO15

GPIO16

GPIO17

GPIO12

GPIO22

GPIO28

GPIO0

I/O

ADC channel 0 input (maximum of 1.5 V)

ADC channel 1 input (maximum of 1.5 V)

ADC channel 2 input (maximum of 1.5 V)

ADC channel 3 input (maximum of 1.5 V)

ADC

I/O

BLE/2.4 GHz

radio

19⁽¹⁾

42⁽¹⁾

Coexistence inputs and outputs

coexistence⁽²⁾

GPIO30

GPIO5

GPIO6

GPIO8

GPIO9

I/O

19⁽¹⁾

42⁽¹⁾

I/O

Hostless mode

HM_IO

Hostless mode inputs and outputs

I/O

TDI

JTAG TDI. Reset default pinout.

TDO

TCK

TMS

JTAG TDO. Reset default pinout.

JTAG/SWD TCK. Reset default pinout.

JTAG/SWD TMS. Reset default pinout.

JTAG / SWD

I/O

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表7-2. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

I2C_SCL

I/O

I/O (open drain) I²C clock data

I²C

I2C_SDA

I/O (open drain) I²C data

GT_PWM06

GT_CCP01

GT_PWM07

GT_CCP02

GT_CCP03

I/O

Pulse-width modulated O/P

Timer capture port

Pulse-width modulated O/P

GT_CCP04

GT_CCP05

Timer capture ports

GT_CCP06

Timers

GT_CCP07

PWM0

GT_PWM03

GT_PWM02

Pulse-width modulated outputs

Timer capture ports

I/O

GT_CCP00

GT_CCP05

GT_CCP01

GT_CCP02

GT_CCP05

GT_PWM05

Timer capture port Input

I/O

Pulse-width modulated output

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FUNCTION

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表7-2. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

GPIO10

DESCRIPTION

I/O

GPIO11

GPIO14

GPIO15

GPIO16

GPIO17

GPIO12

GPIO13

GPIO22

GPIO23

GPIO24

GPIO28

GPIO29

GPIO25

GPIO0

GPIO

General-purpose inputs or outputs

I/O

GPIO30

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

MCAFSX

I/O

I²S audio port frame sync

I²S audio port clock outputs

McASP

I/O

I²S or PCM

McACLK

McAXR1

I/O

I²S audio port data 1 (RX/TX)

I²S audio port data 1 (RX and TX)

I²S audio port data 0 (RX and TX)

I²S audio port data (RX and TX)

I²S audio port clock

I/O

McAXR0

McACLKX

SDCARD_CLK

I/O

SD card clock data

I/O

I/O (open drain)

I/O

SDCARD_CMD

SD card command line

Multimedia card

(MMC or SD)

SDCARD_DATA0

SDCARD_IRQ

I/O

SD card data

Interrupt from SD card⁽³⁾

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表7-2. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

Free clock to parallel camera

pXCLK (XVCLK)

pVS (VSYNC)

I/O

Parallel camera vertical sync

Parallel camera horizontal sync

Parallel camera data bit 4

Parallel camera data bit 5

Parallel camera data bit 6

Parallel camera data bit 7

Pixel clock from parallel camera sensor

Parallel camera data bit 3

Parallel camera data bit 2

Parallel camera data bit 1

Parallel camera data bit 0

Power supply for the module

WLAN analog RF 802.11 a/b/g/n bands

General SPI clock

pHS (HSYNC)

pDATA8 (CAM_D4)

pDATA9 (CAM_D5)

pDATA10 (CAM_D6)

pDATA11 (CAM_D7)

pCLK (PIXCLK)

pDATA7 (CAM_D3)

pDATA6 (CAM_D2)

pDATA5 (CAM_D1)

pDATA4 (CAM_D0)

VBAT1

Parallel interface

(8-bit π)

I/O

—

I/O

—

Power

RF⁽⁴⁾

VBAT2

RF_ABG

GSPI_CLK

I/O

GSPI_MISO

GSPI_CS

General SPI MISO

SPI

General SPI device select

GSPI_MOSI

General SPI MOSI

FLASH_SPI_CLK

FLASH_SPI_DOUT

FLASH_SPI_DIN

FLASH_SPI_CS

Clock to SPI serial flash (fixed default)

Data to SPI serial flash (fixed default)

Data from SPI serial flash (fixed default)

FLASH SPI

Device select to SPI serial flash (fixed default)

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FUNCTION

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表7-2. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

DESCRIPTION

I/O

UART TX data

UART1_TX

UART1 TX data

UART RX data

UART1_RX

UART1 RX data

UART1_RTS

UART1_CTS

UART1 request-to-send (active low)

UART1 clear-to-send (active low)

UART

23⁽⁵⁾

UART0_TX

UART0 TX data

UART0 RX data

UART0_RX

UART0_CTS

I/O

UART0 clear-to-send input (active low)

I/O

UART0_RTS

SOP2

UART0 request-to-send (active low)

Sense-on-power 2

Sense-On-Power SOP1

SOP0

Configuration sense-on-power 1

Configuration sense-on-power 0

(1) LPDS retention unavailable.

(2) The CC3235MODx or CC3235MODAx modules are compatible with TI BLE modules using an external RF switch.

(3) Future support.

(4) This pins is not accessible on the CC3235MODAx devices as it is directly tied to the integrated antenna.

(5) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

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7.4 Drive Strength and Reset States for Analog-Digital Multiplexed Pins

表 7-3 describes the use, drive strength, and default state of analog- and digital-multiplexed pins at first-time

power up and reset (nRESET pulled low).

表7-3. Drive Strength and Reset States for Analog-Digital Multiplexed Pins

MAXIMUM

STATE AFTER CONFIGURATION

OF ANALOG SWITCHES (ACTIVE,

LPDS, and HIB POWER MODES)

EFFECTIVE

DRIVE

STRENGTH

(mA)

BOARD LEVEL

CONFIGURATION AND USE

DEFAULT STATE AT FIRST POWER

UP OR FORCED RESET

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

Generic I/O

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

7.5 Pad State After Application of Power to Chip, but Before Reset Release

When a stable power is applied to the CC3235MODx or CC3235MODAx module for the first time or when supply

voltage is restored to the proper value following a prior period with supply voltage below 1.5 V, the level of the

digital pads are undefined in the period starting from the release of nRESET and until the DIG_DCDC of the

CC3235x chip powers up. This period is less than approximately 10 ms. During this period, pads can be

internally pulled weakly in either direction. If a certain set of pins are required to have a definite value during this

pre-reset period, an appropriate pullup or pulldown must be used at the board level. The recommended value of

these external pullup or pulldown resistors is 2.7 kΩ.

7.6 Connections for Unused Pins

All unused pin should be configured as stated in 表7-4.

表7-4. Connections for Unused Pins

FUNCTION

SIGNAL DESCRIPTION

PIN NUMBER

ACCEPTABLE PRACTICE

Wake up I/O source should not be floating during

hibernate.

All the I/O pins will float while in Hibernate and Reset

states. Ensure pullup and pulldown resistors are available

on board to maintain the state of the I/O.

Leave unused GPIOs as NC

GPIO

General-purpose input or output

20, 31⁽¹⁾, 33, 39,

41, 45

No Connect

SOP

Unused pin, leave as NC.

Leave as NC (Modules contain internal 100-kΩpulldown

resistors on the SOP lines). An external 10-kΩpullup

resistor is required to pull these pins high. See 节9.11.1

for SOP[2:0] configuration modes.

Configuration sense-on-power

23, 24, 34

Reset

JTAG

RESET input for the device

JTAG interface

Never leave the reset pin floating

Leave as NC if unused

(1) The CC3235MODAx's RF_ABG pin is a NC as it is directly tied to the integrated PCB antenna.

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8 Specifications

8.1 Absolute Maximum Ratings

All measurements are referenced at the module pins unless otherwise indicated. All specifications are over process and

voltage unless otherwise indicated.

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.5

–40

MAX

UNIT

V_BAT

3.8

Digital I/O

V_BAT+ 0.5

RF pin

2.1

Analog pins

Operating temperature (T_A)

°C

Storage temperature (T_stg

)

Junction temperature (T_j)⁽³⁾

120

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) Junction temperature is for the CC3235x device that is contained within the module.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾

±2000

V_ESD

Electrostatic discharge

Charged device model (CDM),

All pins

±500

per JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)^{(2) (1) (3)}

MIN

2.3

TYP

3.3

MAX

3.6

UNIT

V_BAT

°C

Operating temperature

Ambient thermal slew

–40

–20

°C/minute

(1) When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect

feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the

transmission.

(2) To ensure WLAN performance, the ripple on the power supply must be less than ±300 mV. The ripple should not cause the supply to

fall below the brownout voltage.

(3) The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1

V, and care must be taken when operating at the minimum specified voltage.

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8.4 Current Consumption (CC3235MODS and CC3235MODAS)

表8-1. Current Consumption Summary (CC3235MODS and CC3235MODAS) 2.4 GHz RF Band

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (5)}

TX power level = 0

MIN

TYP⁽⁶⁾

272

190

248

182

223

160

MAX UNIT

1 DSSS

6 OFDM

54 OFDM

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

NWP ACTIVE

MCU ACTIVE

1 DSSS

54 OFDM

NWP idle connected⁽³⁾

15.3

269

187

245

179

220

157

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

NWP ACTIVE

MCU SLEEP

1 DSSS

54 OFDM

NWP idle connected⁽³⁾

12.2

266

184

242

176

217

154

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

NWP ACTIVE

MCU LPDS

1 DSSS

54 OFDM

64 KB

120

135

710

NWP LPDS⁽²⁾

SRAM Retention

256 KB

µA

NWP idle connected⁽³⁾

MCU SHUTDOWN MCU shutdown

MCU HIBERNATE MCU hibernate

µA

5.5

V_BAT= 3.6 V

V_BAT= 3.3 V

V_BAT= 2.3 V

420

450

610

Peak calibration current⁽⁴⁾

(1) TX power level = 0 implies maximum power (see 图8-1, 图8-2, and 图8-3). TX power level = 4 implies output power backed off

approximately 4 dB.

(2) LPDS current does not include the external serial flash. The CC3235MODS and CC3235MODAS device can be configured to retain

0 KB, 64 KB, 128 KB, 192 KB, or 256 KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases LPDS current by 4

µA.

(3) DTIM = 1

(4) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is

performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.

There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further

details, see CC31xx, CC32xx SimpleLink™ Wi-Fi^®and IoT Network Processor Programmer's Guide.

(5) The CC3235MODS and CC3235MODAS system is a constant power-source system. The active current numbers scale based on the

V_BATvoltage supplied.

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(6) Typical numbers assume a VSWR of 1.5:1.

表8-2. Current Consumption Summary (CC3235MODS and CC3235MODAS) 5 GHz RF Band

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (4)}

6 OFDM

MIN

TYP⁽⁵⁾

318

293

MAX UNIT

NWP ACTIVE

54 OFDM

MCU ACTIVE

MCU SLEEP

54 OFDM

NWP idle connected⁽³⁾

15.3

315

290

6 OFDM

54 OFDM

NWP ACTIVE

NWP idle connected⁽³⁾

SRAM Retention

12.2

312

287

6 OFDM

54 OFDM

64 KB

NWP ACTIVE

NWP LPDS⁽²⁾

µA

MCU LPDS

120

135

710

256 KB

NWP idle connected⁽³⁾

MCU SHUTDOWN MCU shutdown

MCU HIBERNATE MCU hibernate

µA

5.5

V_BAT= 3.6 V

V_BAT= 3.3 V

V_BAT= 2.7 V

V_BAT= 2.3 V

290

310

365

Peak calibration current⁽⁶⁾

(1) Measurements taken at maximum TX power

(2) LPDS current does not include the external serial flash. The CC3235MODx and CC3235MODAx can be configured to retain 0 KB,

64 KB, 128 KB, 192 KB, or 256 KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases LPDS current by 4 µA.

(3) DTIM = 1

(4) The CC3235MODx and CC3235MODAx system is a constant power-source system. The active current numbers scale based on the

V_BATvoltage supplied.

(5) Typical numbers assume a VSWR of 1.5:1.

(6) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is

performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.

There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further

details, see CC31xx, CC32xx SimpleLink™ Wi-Fi^®and IoT Network Processor Programmer's Guide.

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8.5 Current Consumption (CC3235MODSF and CC3235MODASF)

表8-3. Current Consumption Summary (CC3235MODSF and CC3235MODASF) 2.4 GHz RF Band

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (5)}

TX power level = 0

MIN

TYP⁽⁵⁾

286

202

255

192

232

174

MAX UNIT

1 DSSS

6 OFDM

54 OFDM

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

NWP ACTIVE

MCU ACTIVE

1 DSSS

54 OFDM

NWP idle connected⁽³⁾

25.2

282

198

251

188

228

170

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

NWP ACTIVE

MCU SLEEP

1 DSSS

NWP idle connected⁽³⁾

54 OFDM

21.2

266

184

242

176

217

154

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

NWP active

MCU LPDS

1 DSSS

54 OFDM

64 KB

120

135

710

SRAM

Retention

NWP LPDS⁽²⁾

256 KB

µA

NWP idle connected⁽³⁾

MCU shutdown

MCU

SHUTDOWN

µA

MCU

HIBERNATE

MCU hibernate

5.5

V_BAT= 3.6 V

V_BAT= 3.3 V

V_BAT= 2.3 V

420

450

610

Peak calibration current⁽⁴⁾

(1) TX power level = 0 implies maximum power (see 图8-2, 图8-2, and 图8-3). TX power level = 4 implies output power backed off

approximately 4 dB.

(2) LPDS current does not include the external serial flash. The CC3235MODx and CC3235MODAx can be configured to retain 0 KB,

64 KB, 128 KB, 192 KB, or 256 KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases LPDS current by 4 µA.

(3) DTIM = 1

(4) The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly,

typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be

controlled by a configuration file in the serial flash.

(5) Typical numbers assume a VSWR of 1.5:1.

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表8-4. Current Consumption Summary (CC3235MODS and CC3235MODAS) 5 GHz RF Band

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (4)}

6 OFDM

MIN TYP⁽⁴⁾MAX UNIT

329

NWP ACTIVE

54 OFDM

306

MCU ACTIVE

MCU SLEEP

NWP idle connected⁽³⁾

25.2

325

6 OFDM

54 OFDM

NWP ACTIVE

302

NWP idle connected⁽³⁾

21.2

312

6 OFDM

54 OFDM

64 KB

NWP active

289

µA

MCU LPDS

120

135

710

SRAM

Retention

NWP LPDS⁽²⁾

256 KB

NWP idle connected⁽³⁾

MCU shutdown

MCU

SHUTDOWN

µA

MCU

HIBERNATE

MCU hibernate

5.5

V_BAT= 3.6 V

290

310

333

V_BAT= 3.3 V

V_BAT= 2.7 V

V_BAT= 2.3 V

Peak calibration current⁽⁵⁾

(1) Measurements taken at maximum TX power

(2) LPDS current does not include the external serial flash. The CC3235MODS and CC3235MODAS can be configured to retain 0 KB,

64 KB, 128 KB, 192 KB, or 256 KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases LPDS current by 4 µA.

(3) DTIM = 1

(4) Typical numbers assume a VSWR of 1.5:1.

(5) The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly,

typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be

controlled by a configuration file in the serial flash.

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8.6 TX Power Control for 2.4 GHz Band

The CC3235MODS and CC3235MODAS has several options for modifying the output power of the device when

required. For the 2.4 GHz band it is possible to lower the overall output power at a global level using the global

TX power level setting. In addition, the 2.4 GHz band allows the user to enter additional back-offs ², per channel,

region and modulation rates ^{4 5}, through Image creator (see the Uniflash with Image Creator User Guide for

more details).

图 8-1, 图 8-2, and 图 8-3 show TX power and IBAT versus TX power level settings for the CC3235MODS

module at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the CC3235MODSF module, the

IBAT current has an increase of approximately 10 mA to 15 mA depending on the transmitted rate. The TX

power level remains the same.⁵

In 图 8-1, the area enclosed in the circle represents a significant reduction in current during transition from TX

power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends using

TX power level 4 to reduce the current.

1 DSSS

19.00

17.00

280.00

264.40

249.00

233.30

218.00

202.00

186.70

171.00

Color by

TX Power (dBm)

15.00

13.00

IBAT (VBAT @ 3.6 V)

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

TX power level setting

图8-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)

The back-off range is between –6 dB to +6 dB in 0.25-dB increments.

FCC, IC/ISED, ETSI/CE, MIC, and SRRC are supported.

Back-off rates are grouped into 11b rates, high modulation rates (MCS7, 54 OFDM and 48 OFDM), and lower modulation rates (all

other rates).

There will be a difference between the CC3135MOD and CC3135 IC TX power levels.

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6 OFDM

19.00

17.00

280.00

Color by

264.40

TX Power (dBm)

249.00

15.00

13.00

IBAT (VBAT @ 3.6 V)

233.30

218.00

202.00

186.70

171.00

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

TX power level setting

图8-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)

54 OFDM

19.00

17.00

280.00

264.40

249.00

233.30

218.00

202.00

186.70

171.00

Color by

TX Power (dBm)

15.00

13.00

IBAT (VBAT @ 3.6 V)

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

TX power level setting

图8-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)

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8.7 TX Power Control for 5 GHz

5-GHz power control is done via Image Creator where the maximum transmit power is provided ⁶. Within Image

Creator, power control is possible per channel, region ⁷, and modulation rate ⁸. In addition, it is possible to enter

an additional back-off ⁹factor per channel and modulation rate for further margin to regulatory requirements.

It is also possible to set the TX and RX trace losses to the antenna per band ¹⁰. The peak antenna gain ¹¹can

also be provided, thus allowing further control. For a full description of options and capabilities see Uniflash with

Image Creator User Guide.

8.8 Brownout and Blackout Conditions

The module enters a brownout condition whenever the input voltage dips below V_BROWNOUT(see 图 8-4 and 图

8-5). This condition must be considered during design of the power supply routing, especially if operating from a

battery. High-current operations, such as a TX packet or any external activity (not necessarily related directly to

networking) can cause a drop in the supply voltage, potentially triggering a brownout. The resistance includes

the internal resistance of the battery, contact resistance of the battery holder (four contacts for a 2× AA battery),

and the wiring and PCB routing resistance.

Note

When the module is in HIBERNATE state, brownout is not detected. Only blackout is in effect during

HIBERNATE state.

The maximum transmit power range is 18 dBm to 0.125 dBm in 0.125-dBm decrements.

FCC, IC/ISED, ETSI/CE, MIC, and SRRC are supported.

Rates are grouped into high modulation rates (MCS7, 54 OFDM and 48 OFDM) and lower modulation rates (all other rates).

The back-off range is 0 dBm to 18 dBm in 0.125-dBm increments, with the maximum back-off not exceed that of the maximum

transmit power.

The range of losses if from 0 dBm to 7.75 dBm in 0.125-dBm increments.

The antenna gain has a range of -2 dBi to 5.75 dBi in 0.125-dBi increments.

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图8-4. Brownout and Blackout Levels (1 of 2)

图8-5. Brownout and Blackout Levels (2 of 2)

In the brownout condition, all sections of the device shut down within the module except for the Hibernate block

(including the 32-kHz RTC clock), which remains on. The current in this state can reach approximately 400 µA.

The blackout condition is equivalent to a hardware reset event in which all states within the module are lost.

V_brownout= 2.1 V and V_blackout= 1.67 V

表8-5 lists the brownout and blackout voltage levels.

表8-5. Brownout and Blackout Voltage Levels

CONDITION

V_brownout

VOLTAGE LEVEL

UNIT

2.1

V_blackout

1.67

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8.9 Electrical Characteristics for GPIO Pins

表8-6. GPIO Pins Except 25, 26, 42, and 44 (25°C)⁽¹⁾

T_A= 25°C, V_BAT= 3.3 V

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

C_IN

V_IH

V_IL

I_IH

Pin capacitance

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

0.65 × V_DD

V_DD+ 0.5 V

0.35 × V_DD

–0.5

I_IL

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.4 V ≤V_DD< 3.6 V

V_DD× 0.8

V_DD× 0.7

V_DD× 0.75

IL = 4 mA; configured I/O drive

strength = 4 mA;

2.4 V ≤V_DD< 3.6 V

V_OH

High-level output voltage

IL = 6 mA; configured I/O drive

strength = 6 mA;

2.4 V ≤V_DD< 3.6 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.3 V ≤V_DD< 2.4 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.4 V ≤V_DD< 3.6 V

V_DD× 0.2

V_DD× 0.25

IL = 4 mA; configured I/O drive

strength = 4 mA;

2.4 V ≤V_DD< 3.6 V

V_OL

Low-level output voltage

IL = 6 mA; configured I/O drive

strength = 6 mA;

2.4 V ≤V_DD< 3.6 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.3 V ≤V_DD< 2.4 V

2-mA drive

High-level

source current,

I_OH

4-mA drive

6-mA drive

2-mA drive

Low-level sink

4-mA drive

current,

I_OL

6-mA drive

(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk

of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength

setting is 6 mA.

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表8-7. GPIO Pins 25, 26, 42, and 44 (25°C)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

C_IN

V_IH

V_IL

I_IH

Pin capacitance

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

0.65 × V_DD

V_DD+ 0.5 V

0.35 × V_DD

–0.5

I_IL

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.4 V ≤V_DD< 3.6 V

V_DD× 0.8

V_DD× 0.7

V_DD× 0.75

IL = 4 mA; configured I/O drive

strength = 4 mA;

2.4 V ≤V_DD< 3.6 V

V_OHHigh-level output voltage

IL = 6 mA; configured I/O drive

strength = 6 mA;

2.4 V ≤V_DD< 3.6 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.3 V ≤V_DD< 2.4 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.4 V ≤V_DD< 3.6 V

V_DD× 0.2

V_DD× 0.25

IL = 4 mA; configured I/O drive

strength = 4 mA;

2.4 V ≤V_DD< 3.6 V

V_OLLow-level output voltage

IL = 6 mA; configured I/O drive

strength = 6 mA;

2.4 V ≤V_DD< 3.6 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.3 V ≤V_DD< 2.4 V

2-mA drive

1.5

2.5

3.5

1.5

2.5

3.5

High-level source

current, V_OH= 2.4

I_OH

4-mA drive

6-mA drive

2-mA drive

4-mA drive

6-mA drive

Low-level sink

current,

I_OL

V_IL

nRESET

0.6

(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk

of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength

setting is 6 mA.

8.9.1 Electrical Characteristics for Pin Internal Pullup and Pulldown (25°C)

PARAMETER

Pullup current

TEST CONDITIONS

MIN

NOM

MAX

UNIT

I_OH

I_OL

µA

(V_DD= 3.0 V)

Pulldown current

(V_DD= 3.0 V)

µA

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8.10 CC3235MODAx Antenna Characteristics

T_A= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Polarization

Peak Gain

Linear

2.4 GHz Band

5 GHz Band

2.4 GHz Band

5 GHz Band

3.5

4.5

dBi

70%

65%

Efficiency

8.11 WLAN Receiver Characteristics

表8-8. WLAN Receiver Characteristics: 2.4 GHz Band

T_A= 25°C, V_BAT= 2.3 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).

PARAMETER

TEST CONDITIONS (Mbps)

MIN

TYP

–94.5

–92.5

–86.5

–89

MAX

UNIT

1 DSSS

2 DSSS

11 CCK

6 OFDM

Sensitivity

(8% PER for 11b rates, 10% PER for 11g/11n

9 OFDM

dBm

–88.5

–85

rates)⁽¹⁾

18 OFDM

36 OFDM

54 OFDM

MCS7 (GF)⁽²⁾

802.11b

–79

–73

–70

–2.5

–8.5

Maximum input level

(10% PER)

dBm

802.11g

(1) Sensitivity is 1-dB worse on channel 13 (2472 MHz).

(2) Sensitivity for mixed mode is 1-dB worse.

表8-9. WLAN Receiver Characteristics: 5 GHz Band

T_A= 25°C, V_BAT= 2.3 V to 3.6 V.

PARAMETER

TEST CONDITIONS (Mbps)

6 OFDM

MIN

TYP

-89

MAX

UNIT

dBm

9 OFDM

-88

18 OFDM

-85

Sensitivity

(10% PER for 11g/11n rates)

36 OFDM

-78.5

-72

54 OFDM

MCS7 (GF)⁽¹⁾

-68

Maximum input level

802.11a

-17

(1) Sensitivity for mixed mode is 1-dB worse.

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8.12 WLAN Transmitter Characteristics

表8-10. WLAN Transmitter Characteristics: 2.4 GHz Band

T_A= 25°C, V_BAT= 2.3 V to 3.6 V.⁽¹⁾Parameters measured at SoC pin on channel 6 (2437 MHz).^{(2) (3)}

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Operating frequency range^{(4) (5)}

2412

2472

MHz

1 DSSS

2 DSSS

11 CCK

16.3

15.3

6 OFDM

9 OFDM

18 OFDM

36 OFDM

54 OFDM

MCS7

Maximum RMS output power measured at 1

dB from IEEE spectral mask or EVM

dBm

ppm

12.5

Transmit center frequency accuracy

–25

(1) Transmit power will be reduced by 1.5dB for V_BAT< 2.8V

(2) The 11g/n low rates on edge channels (2412 and 2462 MHz) have reduced TX power to meet FCC emission limits.

(3) Power of 802.11b rates are reduced to meet ETSI requirements in Europe.

(4) Channels 1 (2142 MHz) through 11 (2462 MHz) are supported for FCC.

(5) Channels 1 (2142 MHz) through 13 (2472MHz) are supported for Europe and Japan. Note that channel 14 is not supported for Japan.

表8-11. WLAN Transmitter Characteristics: 5 GHz Band

T_A= 25°C, V_BAT= 2.3 V to 3.6 V.⁽¹⁾Parameters measured at SoC pin are the average of channels 40, 56, 120, and 157 .^{(5) (6)}

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Operating frequency range^{(2) (3) (4)}

5180

5825

MHz

6 OFDM

9 OFDM

18 OFDM

36 OFDM

54 OFDM

MCS7

15.1

13.6

Maximum RMS output power measured at 1

dB from IEEE spectral mask or EVM

dBm

ppm

Transmit center frequency accuracy

-20

(1) Transmit power will be reduced by 1.5dB for V_BAT< 2.8V

(2) FCC band covers U-NII-1, U-NII-2A, U-NII-2C, and U-NII-3 20-MHz BW modulations.

(3) Europe bands 1, 2 and 3, 20-MHz BW modulations are supported.

(4) For Japan, W52, W53 and W56, 20-MHz BW modulations are supported.

(5) FCC channels 36, 60, 64, 100, and 140, where harmonics/sub-harmonics of fall in the FCC restricted band, have reduced output

power to meet the FCC RSE requirement.

(6) The edge channels (100 and 140) have reduced TX power to meet FCC emissions limits.

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8.13 BLE and WLAN Coexistence Requirements

For proper BLE and WLAN 2.4 GHz radio coexistence, the following requirements must be met:

表8-12. BLE/WLAN Coex⁽¹⁾Isolation Requirement

PARAMETER

Band

MIN

TYP

MAX

UNIT

Port-to-port isolation

Dual antenna configuration⁽²⁾

20⁽³⁾

(1) The CC3235MODS and CC3235MODAS modules are compatible with TI BLE modules using an external RF switch.

(2) A single antenna configuration is possible using the CC3x35 devices.

(3) For dual antenna configuration, the antenna placement must be such that isolation between the BLE and WLAN ports is at least 20 dB.

8.14 Reset Requirement

PARAMETER

Operation mode level

MIN

TYP

0.65 × V_BAT

0.6

MAX UNIT

V_IH

V_IL

Shutdown mode level⁽¹⁾

Minimum time for nReset low for resetting the module

Rise and fall times

µs

T_rand T_f

(1) The nRESET pin must be held below 0.6 V for the module to register a reset.

8.15 Thermal Resistance Characteristics for MOB and MON Packages

NO.

PARAMETER

RΘ_JC

DESCRIPTION

°C/W^{(1) (2)}

AIR FLOW (m/s)⁽³⁾

11.4

8.0

N/A

Junction-to-case

Junction-to-board

Junction-to-free air

RΘ_JB

19.1

14.7

13.4

12.5

5.4

RΘ_JA

Junction-to-moving air

Junction-to-free air

Junction-to-package top

Junction-to-free air

Junction-to-board

5.8

Ψ_JT

6.1

T10

T11

T12

T13

T14

6.5

6.8

6.6

Ψ_JB

6.6

6.5

(1) °C/W = degrees Celsius per watt.

(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

Power dissipation of 2 W and an ambient temperature of 70°C is assumed.

(3) m/s = meters per second.

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8.16 Timing and Switching Characteristics

8.16.1 Power-Up Sequencing

For proper start-up of the CC3235MODx and CC3235MODAx module, perform the recommended power-up

sequencing as follows:

1. Tie V_BAT1(pin 37) and V_BAT2(pin 40) together on the board.

2. Hold the nRESET pin low while the supplies are ramping up.

图8-6 shows the reset timing diagram for the first-time power-up and reset removal.

VBAT

nRESET

APP CODE

EXECUTION

POWER

APP CODE

LOAD

RESET

HW INIT

FW INIT

STATE

OFF

32-kHz

RTC CLK

图8-6. First-Time Power-Up and Reset Removal Timing Diagram

表8-13 lists the timing requirements for the first-time power-up and reset removal.

表8-13. First-Time Power-Up and Reset Removal Timing Requirements

ITEM

NAME

DESCRIPTION

MIN

TYP

MAX UNIT

T1 nReset time

nReset timing after VBAT supplies are stable

T2 Hardware wake-up time

Time taken by ROM

T3 firmware to initialize

hardware

Includes internal 32-kHz XOSC settling time

CC3235MODS and CC3235MODAS

CC3235MODSF and CC3235MODASF

1.1

App code load time for

CC3235MODS and

Image size (KB) × 1.7 ms

Image size (KB) × 0.06 ms

CC3235MODAS

App code load time for

CC3235MODSF and

CC3235MODASF

8.16.2 Power-Down Sequencing

For proper power down of the CC3235MODx and CC3235MODAx module, ensure that the nRESET (pin 35) and

nHIB (pin 4) pins have remained in a known state for a minimum of 200 ms before removing power from the

module.

8.16.3 Device Reset

When a device restart is required, issue a negative pulse to the nRESET pin. Ensure the reset is properly

applied: A negative reset pulse (on pin 35) of at least 200-mS duration.

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8.16.4 Wake Up From Hibernate Timing

表8-14 lists the software hibernate timing requirements.

Note

The internal 32.768-kHz crystal is kept enabled by default when the module goes to hibernate.

表8-14. Software Hibernate Timing Requirements

ITEM

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

T_{HIB_MIN}

Minimum hibernate time

Hardware wakeup time plus

firmware initialization time

(1)

T_{wake_from_hib}

50⁽²⁾

App code load time for

CC3235MODS and

CC3235MODAS

CC3235MODS and CC3235MODAS

Image size (KB) × 1.7 ms

Image size (KB) × 0.06 ms

T_APP_CODE_LOAD

App code load time for

CC3235MODSF and

CC3235MODASF

CC3235MODSF and

CC3235MODASF

(1) T_{wake_from_hib}can be 200 ms on rare occasions when calibration is performed. Calibration is performed sparingly, typically when exiting

Hibernate and only if temperature has changed by more than 20°C or more than 24 hours have elapsed since a prior calibration.

(2) Wake-up time can extend to 75 ms if a patch is downloaded from the serial flash.

图8-7 shows the timing diagram for wake up from the hibernate state.

Application software requests

entry to hibernate moade

T_{wake_from_hib}

T_{APP_CODE_LOAD}

T_{HIB_MIN}

VBAT

nRESET

STATE

APP CODE

LOAD

ACTIVE

Hibernate

HW WAKEUP

FW INIT

EXECUTION

32-kHz

RTC CLK

图8-7. Wake Up From Hibernate Timing Diagram

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8.16.5 Peripherals Timing

This section describes the peripherals that are supported by the CC3235MODx and CC3235MODAx module, as

follows:

• SPI

• I2S

• GPIOs

• I²C

• IEEE 1149.1 JTAG

• ADC

• Camera parallel port

• External flash

• UART

• SD Host

• Timers

8.16.5.1 SPI

8.16.5.1.1 SPI Master

The CC3235MODx and CC3235MODAx MCU includes one SPI module, which can be configured as a master or

slave device. The SPI includes a serial clock with programmable frequency, polarity, and phase; a programmable

timing control between chip select and external clock generation; and a programmable delay before the first SPI

word is transmitted. Slave mode does not include a dead cycle between two successive words.

图8-8 shows the timing diagram for the SPI master.

CLK

MISO

MOSI

图8-8. SPI Master Timing Diagram

表8-15 lists the timing parameters for the SPI master.

表8-15. SPI Master Timing Parameters

ITEM

NAME

DESCRIPTION

MIN

MAX

UNIT

MHz

F⁽¹⁾

T_clk

D⁽¹⁾

Clock frequency

Clock period

(1)

45%

Duty cycle

55%

(1)

t_IS

RX data setup time

RX data hold time

TX data output delay

TX data hold time

(1)

t_IH

(1)

t_OD

t_OH

8.5

(1) Timing parameter assumes a maximum load of 20 pF.

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8.16.5.1.2 SPI Slave

图8-9 shows the timing diagram for the SPI slave.

CLK

MISO

MOSI

图8-9. SPI Slave Timing Diagram

表8-16 lists the timing parameters for the SPI slave.

表8-16. SPI Slave Timing Parameters

ITEM

NAME

DESCRIPTION

MIN

MAX

UNIT

MHz

Clock frequency @ VBAT = 3.3 V

F⁽¹⁾

Clock frequency @ VBAT ≤2.3 V

Clock period

(1)

T_clk

D⁽¹⁾

45%

Duty cycle

55%

(1)

t_IS

RX data setup time

RX data hold time

TX data output delay

TX data hold time

(1)

t_IH

(1)

t_OD

t_OH

(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.

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8.16.5.2 I2S

The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio

applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit

and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A

fractional divider is available for bit-clock generation.

8.16.5.2.1 I2S Transmit Mode

图8-10 shows the timing diagram for the I2S transmit mode.

McACLKX

McAFSX

McAXR0/1

图8-10. I2S Transmit Mode Timing Diagram

表8-17 lists the timing parameters for the I2S transmit mode.

表8-17. I2S Transmit Mode Timing Parameters

ITEM

NAME

DESCRIPTION

MIN

MAX

9.216

1/2 fclk

UNIT

MHz

(1)

f_clk

Clock frequency

t^{LP (1)}

Clock low period

(1)

t_HT

Clock high period

(1)

t_OH

TX data hold time

(1) Timing parameter assumes a maximum load of 20 pF.

8.16.5.2.2 I2S Receive Mode

图8-11 shows the timing diagram for the I2S receive mode.

McACLKX

McAFSX

McAXR0/1

图8-11. I2S Receive Mode Timing Diagram

表8-18 lists the timing parameters for the I2S receive mode.

表8-18. I2S Receive Mode Timing Parameters

ITEM

NAME

DESCRIPTION

MIN

MAX

9.216

1/2 f_clk

UNIT

MHz

(1)

f_clk

Clock frequency

t^{LP (1)}

Clock low period

(1)

t_HT

Clock high period

(1)

t_OH

RX data hold time

(1)

t_OS

RX data setup time

(1) Timing parameter assumes a maximum load of 20 pF.

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8.16.5.3 GPIOs

All digital pins of the module can be used as general-purpose input/output (GPIO) pins. The GPIO module

consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24

programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown

strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.

图8-12 shows the GPIO timing diagram.

V_DD

80%

20%

t_GPIOF

t_GPIOR

SWAS031-067

图8-12. GPIO Timing Diagram

表8-19 lists the GPIO output transition times for V_BAT= 2.3 V.

表8-19. GPIO Output Transition Times (V_BAT= 2.3 V)^{(1) (2)}

T_r

T_f

DRIVE

STRENGTH (mA)

DRIVE STRENGTH

CONTROL BITS

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

2MA_EN=1

4MA_EN=0

2MA_EN=0

4MA_EN=1

2MA_EN=1

4MA_EN=1

11.7

13.9

15.6

6.4

16.3

11.5

13.9

11.6

4.7

16.7

13.7

5.5

18.0

7.4

9.9

3.8

13.6

5.8

(1) V_BAT= 2.3 V, T = 25°C, total pin load = 30 pF

(2) The transition data applies to the pins other than the multiplexed analog-digital pins 25, 26, 42, and 44.

表8-20 lists the GPIO output transition times for V_BAT= 3.3 V.

表8-20. GPIO Output Transition Times (V_BAT= 3.3 V)^{(1) (2)}

T_r

T_f

DRIVE

STRENGTH (mA)

DRIVE STRENGTH

CONTROL BITS

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

2MA_EN=1

4MA_EN=0

2MA_EN=0

4MA_EN=1

2MA_EN=1

4MA_EN=1

8.0

9.3

7.1

3.5

10.7

8.2

9.5

11.0

6.6

3.2

7.6

3.7

4.7

2.3

5.2

2.6

5.8

2.9

(1) V_BAT= 3.3 V, T = 25°C, total pin load = 30 pF

(2) The transition data applies to the pins except the multiplexed analog-digital pins 29, 30, 45, 50, 52 and 53.

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8.16.5.3.1 GPIO Input Transition Time Parameters

表8-21 lists the input transition time parameters.

表8-21. GPIO Input Transition Time Parameters

MIN

MAX

UNIT

t_r

t_f

Input transition time (t_r, t_f), 10% to 90%

8.16.5.4 I²C

The CC3235MODx and CC3235MODAx MCU includes one I2C module operating with standard (100 kbps) or

fast (400 kbps) transmission speeds.

图8-13 shows the I²C timing diagram.

I2CSCL

I2CSDA

图8-13. I²C Timing Diagram

表8-22 lists the I²C timing parameters.

表8-22. I²C Timing Parameters⁽³⁾

ITEM

NAME

DESCRIPTION

MIN

MAX

UNIT

System clock

t_LP

Clock low period

See ⁽¹⁾

t_SRT

t_DH

t_SFT

t_HT

SCL/SDA rise time

Data hold time

See ⁽²⁾

SCL/SDA fall time

Clock high time

See ⁽¹⁾

tLP/2

System clock

t_DS

Data setup time

t_SCSR

t_SCS

Start condition setup time

Stop condition setup time

(1) This value depends on the value programmed in the clock period register of I²C. Maximum output frequency is the result of the minimal

value programmed in this register.

(2) Because I²C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on

the value of the external signal capacitance and external pullup register.

(3) All timing is with 6-mA drive and 20-pF load.

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8.16.5.5 IEEE 1149.1 JTAG

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and boundary

scan architecture for digital integrated circuits and provides a standardized serial interface to control the

associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the

IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.

图8-14 shows the JTAG timing diagram.

TCK

TMS

TDI

TMS Input Valid

T9 T10

TDI Input Valid

TMS Input Valid

T10

TDI Input Valid

T11

TDO Output Valid

TDO

TDO Output Valid

图8-14. JTAG Timing Diagram

表8-23 lists the JTAG timing parameters.

表8-23. JTAG Timing Parameters

ITEM

NAME

DESCRIPTION

MIN

MAX

UNIT

MHz

f_TCK

t_TCK

t_CL

Clock frequency

Clock period

1 / f_TCK

t_TCK/ 2

Clock low period

Clock high period

TMS setup time

TMS hold time

TDI setup time

TDI hold time

t_CH

t_{TMS_SU}

t_{TMS_HO}

t_{TDI_SU}

t_{TDI_HO}

t_{TDO_HO}

T10

T11

TDO hold time

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8.16.5.6 ADC

表 8-24 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on using the

ADC and for application-specific examples.

Repeats Every 16 µs

Internal Ch

2 µs

ADC CLOCK

= 10 MHz

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

EXT CHANNEL 0

EXT CHANNEL 1

INTERNAL CHANNEL

图8-15. ADC Clock Timing Diagram

图8-15 shows the ADC clock timing diagram.

表8-24. ADC Electrical Specifications

TEST CONDITIONS /

ASSUMPTIONS

PARAMETER

Nbits

DESCRIPTION

Number of bits

MIN

TYP

MAX

UNIT

Bits

Worst-case deviation from

histogram method over full scale

(not including first and last three

LSB levels)

INL

Integral nonlinearity

2.5

LSB

–2.5

Worst-case deviation of any step

from ideal

DNL

Differential nonlinearity

1.4

LSB

–1

Input range

Driving source

impedance

100

Successive approximation input

clock rate

FCLK

Clock rate

MHz

Input capacitance

2.15

0.7

ADC Pin 57

ADC Pin 58

ADC Pin 59

ADC Pin 60

Input impedance

kΩ

2.12

1.17

Number of channels

F_sample

Sampling rate of each pin

62.5

KSPS

kHz

F_input_max

Maximum input signal frequency

Input frequency DC to 300 Hz

and 1.4 V_ppsine wave input

SINAD

Signal-to-noise and distortion

Active supply current

Average for analog-to-digital

during conversion without

reference current

I_active

1.5

Total for analog-to-digital when

not active (this must be the SoC

level test)

Power-down supply current for

core supply

I_PD

µA

Absolute offset error

Gain error

FCLK = 10 MHz

±2

±2%

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表8-24. ADC Electrical Specifications (continued)

TEST CONDITIONS /

ASSUMPTIONS

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

V_ref

ADC reference voltage

1.467

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8.16.5.7 Camera Parallel Port

The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a

FIFO, and generates DMA requests. The camera parallel port supports 8 bits.

图8-16 shows the timing diagram for the camera parallel port.

pCLK

pVS, pHS

pDATA

图8-16. Camera Parallel Port Timing Diagram

表8-25 lists the timing parameters for the camera parallel port.

表8-25. Camera Parallel Port Timing Parameters

ITEM

NAME

DESCRIPTION

MIN

MAX

UNIT

MHz

pCLK

T_clk

t_LP

Clock frequency

Clock period

1/pCLK

T_clk/2

Clock low period

Clock high period

RX data setup time

RX data hold time

t_HT

t_IS

t_IH

8.16.5.8 UART

The CC3235MODx and CC3235MODAx MCU includes two UARTs with the following features:

• Programmable baud-rate generator allowing speeds up to 3 Mbps

• Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading

• Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered

interface

• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

• Standard asynchronous communication bits for start, stop, and parity

• Generation and detection of line-breaks

• Fully programmable serial interface characteristics:

– 5, 6, 7, or 8 data bits

– Generation and detection of even, odd, stick, or no-parity bits

– Generation of 1 or 2 stop-bits

• RTS and CTS hardware flow support

• Standard FIFO-level and end-of-transmission interrupts

• Efficient transfers using µDMA:

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO

level

– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed

FIFO level

• System clock is used to generate the baud clock.

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8.16.5.9 External Flash Interface

The CC3235MODx and CC3235MODAx MCU includes the Macronix^™32-Mbit serial flash. The serial flash can

be programmed directly using the external flash interface (pins 13, 14, 15, and 17). During normal operation, the

external flash interface should remain unconnected.

For timing details, see the MX25R3235F data sheet.

8.16.5.10 SD Host

The CC3235MODx and CC3235MODAx MCU provides an interface between a local host (LH), such as an MCU

and an SD memory card, and handles SD transactions with minimal LH intervention.

The SD host does the following:

• Provides SD card access in 1-bit mode

• Deals with SD protocol at the transmission level

• Handles data packing

• Adds cyclic redundancy checks (CRC)

• Start and end bit

• Checks for syntactical correctness

The application interface sends every SD command and either polls for the status of the adapter or waits for an

interrupt request. The result is then sent back to the application interface in case of exceptions or to warn of end-

of-operation. The controller can be configured to generate DMA requests and work with minimum CPU

intervention. Given the nature of integration of this peripheral on the CC3235x platform, TI recommends that

developers use peripheral library APIs to control and operate the block. This section emphasizes understanding

the SD host APIs provided in the peripheral library of the CC3235x Software Development Kit (SDK).

The SD host features are as follows:

• Full compliance with SD command and response sets, as defined in the SD memory card

– Specifications, v2.0

– Includes high-capacity (size >2 GB) cards HC SD

• Flexible architecture, allowing support for new command structure.

• 1-bit transfer mode specifications for SD cards

• Built-in 1024-byte buffer for read or write

– 512-byte buffer for both transmit and receive

– Each buffer is 32-bits wide by 128-words deep

• 32-bit-wide access bus to maximize bus throughput

• Single interrupt line for multiple interrupt source events

• Two slave DMA channels (1 for TX, 1 for RX)

• Programmable clock generation

• Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver

• Supports configurable busy and response timeout

• Support for a wide range of card clock frequency with odd and even clock ratio

• Maximum frequency supported is 24 MHz

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8.16.5.11 Timers

Programmable timers can be used to count or time external events that drive the timer input pins. The general-

purpose timer module (GPTM) of the CC3235MODx and CC3235MODAx MCU contains 16- or 32-bit GPTM

blocks. Each 16- or 32-bit GPTM block provides two 16-bit timers or counters (referred to as Timer A and Timer

B) that can be configured to operate independently as timers or event counters, or they can be concatenated to

operate as one 32-bit timer. Timers can also be used to trigger µDMA transfers.

The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:

• Operating modes:

– 16- or 32-bit programmable one-shot timer

– 16- or 32-bit programmable periodic timer

– 16-bit general-purpose timer with an 8-bit prescaler

– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler

– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal

• Counts up or counts down

• Sixteen 16- or 32-bit capture compare pins (CCP)

• User-enabled stalling when the microcontroller asserts CPU Halt flag during debug

• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt

service routine

• Efficient transfers using micro direct memory access controller (µDMA):

– Dedicated channel for each timer

– Burst request generated on timer interrupt

• Runs from system clock (80 MHz)

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9 Detailed Description

9.1 Overview

The CC3235MODx and CC3235MODAx MCU is a Dual-Band Wi-Fi internet-on-a chip module that consists of an

Arm Cortex-M4 processor with a rich set of peripherals for diverse application requirements, a Wi-Fi network

processor, and power-management subsystems.

9.2 Functional Block Diagram

图 9-1 shows the functional block diagram of the CC3235MODx and CC3235MODAx SimpleLink™ Wi-Fi^®

solution.

BLE/WLAN

COEX

I²C

Peripheral

SPI

Peripheral

GSPI

I²C

Dual-Band Wi-Fi

V_CC

(2.3 V to 3.6 V)

CC3235MODx

CC3235MODAx

Parallel

Camera Port

GPIO/PWM

I2S

Miscellaneous

Peripheral

Camera

Sensor

Audio

Codec

图9-1. Functional Block Diagram

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9.3 Arm Cortex-M4 Processor Core Subsystem

The high-performance Arm Cortex-M4 processor provides a low-cost platform that meets the needs of minimal

memory implementation, reduced pin count, and low power consumption, while delivering outstanding

computational performance and exceptional system response to interrupts.

• The Cortex-M4 core has low-latency interrupt processing with the following features:

– A 32-bit Arm Thumb^®instruction set optimized for embedded applications

– Handler and thread modes

– Low-latency interrupt handling by automatic processor state saving and restoration during entry and exit

– Support for ARMv6 unaligned accesses

• Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-latency

interrupt processing. The NVIC includes the following features:

– Bits of priority configurable from 3 to 8

– Dynamic reprioritization of interrupts

– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt levels

– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt processing

without the overhead of state saving and restoration between interrupts

– Processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction

overhead

– Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support

• Bus interfaces:

– Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces

– Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations

• Low-cost debug solution featuring:

– Debug access to all memory and registers in the system, including access to memory-mapped devices,

access to internal core registers when the core is halted, and access to debug control registers even while

SYSRESETn is asserted

– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access

– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches

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9.4 Wi-Fi Network Processor Subsystem

The Wi-Fi network processor subsystem includes a dedicated Arm MCU to completely offload the host MCU

along with an 802.11 a/b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN

and Internet connections with 256-bit encryption. The CC3235MODx and CC3235MODAx MCU supports station,

AP, and Wi-Fi Direct modes. The module also supports WPA2 personal and enterprise security, WPS 2.0, and

WPA3 personal and enterprise ¹². The Wi-Fi network processor includes an embedded IPv6, IPv4 TCP/IP stack,

TLS stack, and network applications such as HTTPS server.

9.4.1 WLAN

The WLAN features are as follows:

• 802.11 a/b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP,

Wi-Fi Direct client and group owner with CCK and OFDM rates in the 2.4 GHz ISM band, channels 1 to 13,

and 5 GHz U-NII band.

Note

802.11n is supported only in Wi-Fi station, Wi-Fi Direct, and P2P client modes.

• Autocalibrated radio with a single-ended 50-Ωinterface enables easy connection to the antenna without

requiring expertise in radio circuit design.

• Advanced connection manager with multiple user-configurable profiles stored in serial-flash allows automatic

fast connection to an access point without user or host intervention.

• Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security

accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x), WPA3 Personal and WPA3

Enterpise.

• Smart provisioning options deeply integrated within the module providing a comprehensive end-to-end

solution. With elaborate events notification to the host, enabling the application to control the provisioning

decision flow. The wide variety of Wi-Fi provisioning methods include:

– Access Point using HTTPS

– SmartConfig Technology: a 1-step, 1-time process to connect a CC3235MODx or CC3235MODAx-

enabled module to the home wireless network, removing dependency on the I/O capabilities of the host

MCU; thus, it is usable by deeply embedded applications

• 802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket without

adding MAC or PHY headers. The 802.11 transceiver mode provides the option to select the working

channel, rate, and transmitted power. The receiver mode works with the filtering options.

9.4.2 Network Stack

The Network Stack features are as follows:

• Integrated IPv4, IPv6 TCP/IP stack with BSD socket APIs for simple Internet connectivity with any MCU,

microprocessor, or ASIC

Note

Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.

• Support of 16 simultaneous TCP, UDP, RAW, SSL\TLS sockets

• Built-in network protocols:

– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration

– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND

– DNS client for easy connection to the local network and the Internet

• Built-in network application and utilities:

– HTTP/HTTPS

See CC3x35 SDK v3.40 or newer for details. Limited to STA mode only.

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• Web page content stored on serial flash

• RESTful APIs for setting and configuring application content

• Dynamic user callbacks

– Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized

server. After connecting to the access point, the CC3235MODx or CC3235MODAx MCU provides critical

information, such as device name, IP, vendor, and port number.

– DHCP server

– Ping

表9-1 describes the NWP features.

表9-1. NWP Features

Feature

Description

802.11a/b/g/n station

Wi-Fi standards

802.11a/b/g AP supporting up to four stations

Wi-Fi Direct client and group owner

2.4 GHz ISM and 5 GHz U-NII Channels

20 MHz

Wi-Fi channels

Channel Bandwidth

Wi-Fi security

Wi-Fi provisioning

IP protocols

WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x), WPA3 personal and enterprise ⁽¹⁾

SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server

IPv4/IPv6

IP addressing

Cross layer

Static IP, LLA, DHCPv4, DHCPv6 with DAD

ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP

UDP, TCP

Transport

SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2

RAW

Ping

HTTP/HTTPS web server

Network applications and

utilities

mDNS

DNS-SD

DHCP server

Host interface

UART/SPI

Device identity

Trusted root-certificate catalog

TI root-of-trust public key

The CC3235S and CC3235SF variants also support:

•

Secure key storage

Online certificate status protocol (OCSP)

Certificate signing request (CSR)

Unique per device Key-Pair

File system security

Security

Software tamper detection

Cloning protection

Secure boot

Validate the integrity and authenticity of the run-time binary during boot

Initial secure programming

Debug security

JTAG and debug

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表9-1. NWP Features (continued)

Feature

Description

Enhanced power policy management uses 802.11 power save and deep-sleep power modes

Transceiver

Power management

Other

Programmable RX filters with event-trigger mechanism

Rx Metrics for tracking the surrounding RF environment

(1) See CC3x35 SDK v3.40 or newer for details. Limited to STA mode only.

9.5 Security

The SimpleLink Wi-Fi CC3235MODx and CC3235MODAx internet-on-a chip module enhances the security

capabilities available for development of IoT devices, while completely offloading these activities from the MCU

to the networking subsystem. The security capabilities include the following key features:

Wi-Fi and Internet Security:

• Personal and enterprise Wi-Fi security

– Personal standards

• AES (WPA2-PSK)

• TKIP (WPA-PSK)

• WEP

– Enterprise standards

• EAP Fast

• EAP PEAPv0/1

• EAP PEAPv0 TLS

• EAP PEAPv1 TLS EAP LS

• EAP TLS

• EAP TTLS TLS

• EAP TTLS MSCHAPv2

• Secure sockets

– Protocol versions: SSL v3, TLS 1.0, TLS 1.1, TLS 1.2

– Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption for TLS

and SSL connections

– Ciphers suites

• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA

• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5

• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA

• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA

• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256

• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA

• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256

• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384

• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256

• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384

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• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256

• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256

– Server authentication

– Client authentication

– Domain name verification

– Runtime socket upgrade to secure socket –STARTTLS

• Secure HTTP server (HTTPS)

• Trusted root-certificate catalog –Verifies that the CA used by the application is trusted and known secure

content delivery

• TI root-of-trust public key –Hardware-based mechanism that allows authenticating TI as the genuine origin

of a given content using asymmetric keys

• Secure content delivery –Allows encrypted file transfer to the system using asymmetric keys created by the

device

Code and Data Security:

• Network passwords and certificates are encrypted and signed

• Cloning protection –Application and data files are encrypted by a unique key per device

• Access control –Access to application and data files only by using a token provided in file creation time. If

an unauthorized access is detected, a tamper protection lockdown mechanism takes effect

• Encrypted and authenticated file system

• Secured boot –Authentication of the application image on every boot

• Code and data encryption –User application and data files are encrypted in sFlash

• Code and data authentication –User Application and data files are authenticated with a public key certificate

• Offloaded crypto library for asymmetric keys, including the ability to create key-pair, sign and verify data

buffer

• Recovery mechanism

Device Security:

• Separate execution environments –Application processor and network processor run on separate Arm

cores

• Initial secure programming –Allows for keeping the content confidential on the production line

• Debug security

– JTAG lock

– Debug ports lock

• True random number generator

图 9-2 shows the high-level structure of the CC3235S and CC3235SF devices that are contained within the

CC3235MODS and CC3235MODSF modules, respectively. The application image, user data, and network

information files (passwords, certificates) are encrypted using a device-specific key.

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CC3235S and CC3235SF

Network Processor + MCU

MCU

Network Processor

Peripherals

ARM^®Cortex^®-M4

Processor

SPI and I2C

GPIO

Internet

Wi-Fi^®

MAC

Internet

256KB RAM /

UART

HTTPS

TLS/SSL

TCP/IP

1MB Flash (CC3235SF)

PWM

ADC

Baseband

OEM

Application

Dual-Band Radio

•

Serial Flash

OEM

Application

Data Files

Network Information

图9-2. CC3235S and CC3235SF High-Level Structure

9.6 FIPS 140-2 Level 1 Certification

The Federal Information Processing Standard (FIPS) Publication 140-2 is a U.S. government computer security

standard. It is commonly referred to as FIPS 140-2, and is used to accredit the design and implementation of

cryptographic functions, for example within a chip. A cryptographic function within a chip security system is

necessary to maintain the confidentiality and integrity of the information that is being processed.

The security functions of the CC3235x chip that is inside the CC3235MODx or CC3235MODAx module, are

FIPS certified to FIPS 140-2 level 1. This certification covers topics such as: cryptographic specifications, ports

and interfaces, a finite state model for the cryptographic functions, the operational environment of the function,

and how cryptographic keys are managed. The certification provides the assurance that the implementation

meets FIPS 140-2 level 1 standards.

9.7 Power-Management Subsystem

The CC3235MODx and CC3235MODAx power-management subsystems contain DC/DC converters to

accommodate the differing voltage or current requirements of the system.

The CC3235MODx and CC3235MODAx MCU is a fully integrated module-based WLAN radio solution used on

an embedded system with a wide-voltage supply range. The internal power management, including DC/DC

converters and LDOs, generates all of the voltages required for the module to operate from a wide variety of

input sources. For maximum flexibility, the module can operate in the modes described in the following sections.

9.7.1 VBAT Wide-Voltage Connection

In the wide-voltage battery connection, the module can be directly connected to two AA alkaline batteries. All

other voltages required to operate the module are generated internally by the DC/DC converters. This scheme is

the most common mode for the module because it supports wide-voltage operation from 2.3 to 3.6 V.

9.8 Low-Power Operating Mode

From a power-management perspective, the CC3235MODx and CC3235MODAx MCU comprises the following

two independent subsystems:

• Arm Cortex-M4 application processor subsystem

• Networking subsystem

Each subsystem operates in one of several power states.

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The Arm Cortex-M4 application processor runs the user application loaded from an internal serial flash, or on-

module XIP flash (in CC3235MODSF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data

link layer functions.

The user program controls the power state of the application processor subsystem and can be in one of the five

modes described in 表9-2.

表9-2. User Program Modes

APPLICATION PROCESSOR

DESCRIPTION

(MCU) MODE⁽¹⁾

MCU active mode

MCU executing code at 80-MHz state rate.

The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode

offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity

from any GPIO line or peripheral.

MCU sleep mode

State information is lost and only certain MCU-specific register configurations are retained. The MCU

can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.)

Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory

retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU

can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the

wake-up source.

MCU LPDS mode

The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly

external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about 15 ms

plus the time to load the application from serial flash, which varies according to code size. In this mode,

the MCU can be configured to wake up using the RTC timer or external event on a GPIO.

MCU hibernate mode

MCU shutdown mode

The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in

this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the

nRESET line is changed (low to shut down, high to turn on).

(1) Modes are listed in order of power consumption, with highest power modes listed first.

The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network

activity, the NWP sleeps most of the time and wakes up only for beacon reception (see

表9-3).

表9-3. Networking Subsystem Modes

NETWORK PROCESSOR

DESCRIPTION

MODE

Network active mode

Transmitting or receiving IP protocol packets

(processing layer 3, 2, and 1)

Network active mode

Transmitting or receiving MAC management frames; IP processing not required.

(processing layer 2 and 1)

Network active listen mode

Network connected Idle

Special power optimized active mode for receiving beacon frames (no other frames supported)

A composite mode that implements 802.11 infrastructure power save operation. The CC3235MODx and

CC3235MODAx NWPs automatically go into LPDS mode between beacons and then wakes to active

listen mode to receive a beacon and determine if there is pending traffic at the AP. If not, the NWP

returns to LPDS mode and the cycle repeats.

Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid wake

up.

Network LPDS mode

Network disabled

The network is disabled

The operation of the application and network processor ensures that the module remains in the lowest power

mode most of the time to preserve battery life.

The following examples show the use of the power modes in applications:

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• A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but

sends and receives little data spends most of the time in connected idle, which is a composite of receiving a

beacon frame and waiting for the next beacon.

• A product that is not continuously connected to the network but instead wakes up periodically (for example,

every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to

transmit data.

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9.9 Memory

9.9.1 Internal Memory

The CC3235x device within the CC3235MODx and CC3235MODAx modules includes on-chip SRAM to which

application programs are downloaded and executed. The application developer must share the SRAM for code

and data. The micro direct memory access (µDMA) controller can transfer data to and from SRAM and various

peripherals. The CC3235x device ROM holds the rich set of peripheral drivers, which saves SRAM space. For

more information on drivers, see the CC3235x API list.

9.9.1.1 SRAM

The CC3235MODx and CC3235MODAx MCU family provides 256KB of on-chip SRAM. Internal RAM is capable

of selective retention during LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory

map.

Use the µDMA controller to transfer data to and from the SRAM.

When the device enters low-power mode, the application developer can choose to retain a section of memory

based on need. Retaining the memory during low-power mode provides a faster wakeup. The application

developer can choose the amount of memory to retain in multiples of 64KB. For more information, see the API

guide.

9.9.1.2 ROM

The internal zero-wait-state ROM of the CC3235MODx and CC3235MODAx module is at address 0x0000 0000

of the device memory and is programmed with the following components:

• Bootloader

• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces

The bootloader is used as an initial program loader (when the serial flash memory is empty). The DriverLib

software library of the CC3235MODx and CC3235MODAx MCU controls on-chip peripherals with a bootloader

capability. The library performs peripheral initialization and control functions, with a choice of polled or interrupt-

driven peripheral support. The DriverLib APIs in ROM can be called by applications to reduce flash memory

requirements and free the flash memory to be used for other purposes.

9.9.1.3 Flash Memory

The CC3235SF device within the CC3235MODSF and CC3235MODASF modules comes with an on-chip flash

memory of 1MB that allows application code to execute in place while freeing SRAM exclusively for read-write

data. The flash memory is used for code and constant data sections and is directly attached to the ICODE/

DCODE bus of the Arm Cortex-M4 core. A 128-bit-wide instruction prefetch buffer allows maintenance of

maximum performance for linear code or loops that fit inside the buffer.

The flash memory is organized as 2-KB sectors that can be independently erased. Reads and writes can be

performed at word (32-bit) level.

9.9.1.4 Memory Map

表 9-4 describes the various MCU peripherals and how they are mapped to the processor memory. For more

information on peripherals, see the API document.

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表9-4. Memory Map

START ADDRESS

0x0000 0000

0x0100 0000

0x2000 0000

0x2200 0000

0x4000 0000

0x4000 4000

0x4000 5000

0x4000 6000

0x4000 7000

0x4000 C000

0x4000 D000

0x4002 0000

0x4002 4000

0x4002 0800

0x4003 0000

0x4003 1000

0x4003 2000

0x4003 3000

0x400F7000

0x400F E000

0x400F F000

0x4200 0000

0x4401 0000

0x4401 8000

0x4401 C000

0x4402 0000

0x4402 1000

0x4402 5000

0x4402 6000

0x4402 D000

0x4402 E000

0x4402 F000

END ADDRESS

0x0007 FFFF

0x010F FFFF

0x2003 FFFF

0x23FF FFFF

0x4000 0FFF

0x4000 4FFF

0x4000 5FFF

0x4000 6FFF

0x4000 7FFF

0x4000 CFFF

0x4000 DFFF

0x4000 07FF

0x4002 4FFF

0x4002 0FFF

0x4003 0FFF

0x4003 1FFF

0x4003 2FFF

0x4003 3FFF

0x400F 7FFF

0x400F EFFF

0x400F FFFF

0x43FF FFFF

0x4401 0FFF

0x4401 8FFF

0x4401 DFFF

0x4402 0FFF

0x4402 1FFF

0x4402 5FFF

0x4402 6FFF

0x4402 DFFF

0x4402 EFFF

0x4402 FFFF

DESCRIPTION

On-chip ROM (bootloader + DriverLib)

On-chip flash (for user application code)

Bit-banded on-chip SRAM

Bit-band alias of 0x2000 0000 to 0x200F FFFF

Watchdog timer A0

COMMENT

SF devices only

GPIO port A0

GPIO port A1

GPIO port A2

GPIO port A3

UART A0

UART A1

I²C A0 (master)

GPIO group 4

I²C A0 (slave)

General-purpose timer A0

General-purpose timer A1

General-purpose timer A2

General-purpose timer A3

Configuration registers

System control

µDMA

Bit band alias of 0x4000 0000 to 0x400F FFFF

SDIO master

Camera Interface

McASP

SSPI

Used for external serial flash

Used by application processor

GSPI

MCU reset clock manager

MCU configuration space

Global power, reset, and clock manager (GPRCM)

MCU shared configuration

Hibernate configuration

Crypto range (includes apertures for all crypto-related

blocks as follows)

0x4403 0000

0x4403 FFFF

0x4403 0000

0x4403 5000

0x4403 7000

0x4403 9000

0xE000 0000

0xE000 1000

0xE000 2000

0xE000 E000

0xE004 0000

0xE004 1000

0xE004 2000

0x4403 0FFF

0x4403 5FFF

0x4403 7FFF

0x4403 9FFF

0xE000 0FFF

0xE000 1FFF

0xE000 2FFF

0xE000 EFFF

0xE004 0FFF

0xE004 1FFF

0xE00F FFFF

DTHE registers and TCP checksum

MD5/SHA

AES

DES

Instrumentation trace Macrocell^™

Data watchpoint and trace (DWT)

Flash patch and breakpoint (FPB)

NVIC

Trace port interface unit (TPIU)

Reserved for embedded trace macrocell (ETM)

Reserved

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9.10 Restoring Factory Default Configuration

The module has an internal recovery mechanism that rolls back the file system to its predefined factory image or

restoring the factory default parameters of the device. The factory image is kept in a separate sector on the

sFLASH in a secure manner and cannot be accessed from the host processor. The following restore modes are

supported:

• None—no factory restore settings

• Enable restore of factory default parameters

• Enable restore of factory image and factory default parameters

The restore process is performed by calling software APIs, or by pulling or forcing SOP[2:0] = 011 pins and

toggling the nRESET pin from low to high.

The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The

restore process typically takes about 8 seconds, depending on the attributes of the serial flash vendor.

9.11 Boot Modes

9.11.1 Boot Mode List

The CC3235MODx and CC3235MODAx MCU implements a sense-on-power (SoP) scheme to determine the

device operation mode.

SoP values are sensed from the module pin during power up. This encoding determines the boot flow. Before

the device is taken out of reset, the SoP values are copied to a register and used to determine the device

operation mode while powering up. These values determine the boot flow as well as the default mapping for

some of the pins (JTAG, SWD, UART0). 表9-5 lists the pull configurations.

All CC3235MODx and CC3235MODAx MCUs contain internal pulldown resistors on the SOP[2:0] lines. The

application can use SOP2 for other functions after chip has powered up. However, to avoid spurious SOP values

from being sensed at power up, TI strongly recommends using the SOP2 pin only for output signals. The SOP0

and SOP1 pins are multiplexed with the WLAN analog test pins and are not available for other functions.

表9-5. CC3235MODx and CC3235MODAx Functional Configurations

NAME

SOP[2]

SOP[1]

SOP[0]

SoP MODE

COMMENT

Factory, lab flash, and SRAM loads

through the UART. The device waits

indefinitely for the UART to load code.

The SOP bits then must be toggled to

configure the device in functional mode.

Also puts JTAG in 4-wire mode.

UARTLOAD

Pullup

Pulldown Pulldown LDfrUART

Functional development mode. In this

mode, 2-pin SWD is available to the

developer. TMS and TCK are available for

debugger connection.

FUNCTIONAL_2WJ

FUNCTIONAL_4WJ

Pulldown Pulldown Pullup

Fn2WJ

Functional development mode. In this

mode, 4-pin JTAG is available to the

developer. TDI, TMS, TCK, and TDO are

available for debugger connection. The

default configuration for CC3235MODx

and CC3235MODAx MCUs.

Pulldown Pulldown Pulldown Fn4WJ

Supports flash and SRAM load through

UART and functional mode. The MCU

bootloader tries to detect a UART break

on UART receive line. If the break signal

is present, the device enters the

UARTLOAD_FUNCTIONAL_4WJ

Pulldown Pullup

Pulldown LDfrUART_FnWJ

UARTLOAD mode, otherwise, the device

enters the functional mode. TDI, TMS,

TCK, and TDO are available for debugger

connection.

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表9-5. CC3235MODx and CC3235MODAx Functional Configurations (continued)

NAME

SOP[2]

SOP[1]

SOP[0]

SoP MODE

COMMENT

When module reset is toggled, the MCU

bootloader kickstarts the procedure to

restore factory default images.

RET_FACTORY_IMAGE

Pulldown Pullup

Pullup

RetFactDef

9.12 Hostless Mode

The SimpleLink™ Wi-Fi^®CC3235MODx or CC3235MODAx devices incorporate a scripting ability that enables

offloading of simple tasks from the host processor. Using simple and conditional scripts, repetitive tasks can be

handled internally, which allows the host processor to remain in a low-power state. In some cases where the

scripter is being used to send packets, it reduces code footprint and memory consumption. The if-this-then-that

style conditioning can include anything from GPIO toggling to transmitting packets.

The conditional scripting abilities can be divided into conditions and actions. The conditions define when to

trigger actions. Only one action can be defined per condition, but multiple instances of the same condition may

be used, so in effect multiple actions can be defined for a single condition. In total, 16 condition and action pairs

can be defined. The conditions can be simple, or complex using sub-conditions (using a combinatorial AND

condition between them). The actions are divided into two types, those that can occur during runtime and those

that can occur only during the initialization phase.

The following actions can only be performed when triggered by the pre-initialization condition:

• Set roles AP, station, P2P, and Tag modes

• Delete all stored profiles

• Set connection policy

• Hardware GPIO indication allows an I/O to be driven directly from the WLAN core hardware to indicate

internal signaling

The following actions may be activated during runtime:

• Send transceiver packet

• Send UDP packet

• Send TCP packet

• Increment counter increments one of the user counters by 1

• Set counter allows setting a specific value to a counter

• Timer control

• Set GPIO allows GPIO output from the device using the internal networking core

• Enter Hibernate state

Note

Consider the following limitations:

• Timing cannot be ensured when using the network scripter because some variable latency will

apply depending on the utilization of the networking core.

• The scripter is limited to 16 pairs of conditions and reactions.

• Both timers and counters are limited to 8 instances each. Timers are limited to a resolution of 1

second. Counters are 32 bits wide.

• Packet length is limited to the size of one packet and the number of possible packet tokens is

limited to 8.

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9.13 Device Certification and Qualification

The CC3235MODx and CC3235MODAx MCU from TI is certified for FCC, IC/ISED, ETSI/CE, Japan MIC, and

SRRC. Moreover, the module is also Wi-Fi CERTIFIED^™with the ability to request a certificate transfer for Wi-Fi

Alliance^®members. TI customers that build products based on the CC3235MODx or CC3235MODAx MCU from

TI can save in testing cost and time per product family.

表9-6. CC3235MODx and CC3235MODAx List of Certifications

Regulatory Body

FCC (USA)

Specification

ID (IF APPLICABLE)

Part 15C + MPE FCC RF Exposure

RSS-102 (MPE) and RSS-247 (Wi-Fi)

EN300328 v2.2.1 (2.4GHz Wi-Fi)

EN301893 v2.1.1 (5GHz Wi-Fi)

EN62311:2008 (MPE)

Z64-CC3235MOD

IC/ISED (Canada)

451I-CC3235MOD

—

ETSI/CE (Europe)

EN301489-1 v2.2.1 (General EMC)

EN301489-17 v3.2.0 (EMC)

EN60950-1:2006/A11:2009/A1:2010/

A12:2011/A2:2013

—

MIC (Japan)

Article 49-20 of ORRE

201-190033

Please contact TI for more information on

using SRRC ID Certification: www.ti.com/tool/

SIMPLELINK-CC3XXX-CERTIFICATION

SRRC (China)

—

9.13.1 FCC Certification and Statement

FCC RF Radiation Exposure Statement:

CAUTION

This equipment complies with FCC radiation exposure limits set forth for an uncontrolled

environment. End users must follow the specific operating instructions for satisfying RF exposure

limits. This transmitter must not be co-located or operating with any other antenna or transmitter.

The CC3235MODx and CC3235MODAx modules from TI are certified for the FCC as a single-modular

transmitter. The modules are FCC-certified radio modules that carries a modular grant.

You are cautioned that changes or modifications not expressly approved by the party responsible for compliance

could void the user’s authority to operate the equipment.

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

• This device may not cause harmful interference.

• This device must accept any interference received, including interference that may cause undesired

operation of the device.

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9.13.2 IC/ISED Certification and Statement

CAUTION

IC RF Radiation Exposure Statement:

To comply with IC RF exposure requirements, this device and its antenna must not be co-located or

operating in conjunction with any other antenna or transmitter.

Pour se conformer aux exigences de conformité RF canadienne l'exposition, cet appareil et son

antenne ne doivent pas étre co-localisés ou fonctionnant en conjonction avec une autre antenne ou

transmetteur.

The CC3235MODx and CC3235MODAx modules from TI are certified for IC as a single-modular transmitter. The

CC3235MODx and CC3235MODAx modules from TI meet IC modular approval and labeling requirements. The

IC follows the same testing and rules as the FCC regarding certified modules in authorized equipment.

This device complies with Industry Canada licence-exempt RSS standards.

Operation is subject to the following two conditions:

• This device may not cause interference.

• This device must accept any interference, including interference that may cause undesired operation of the

device.

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de

licence.

L'exploitation est autorisée aux deux conditions suivantes:

• L'appareil ne doit pas produire de brouillage

• L'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est

susceptible d'en compromettre le fonctionnement.

9.13.3 ETSI/CE Certification

The CC3235MODx and CC3235MODAx modules from TI are CE certified with certifications to the appropriate

EU radio and EMC directives summarized in the Declaration of Conformity and evidenced by the CE mark. The

modules are tested against the new Radio Equipment Directive (RE-D). See the full text of the EU Declaration of

Conformity for the CC3235MODSM2MOB and CC3235MODSF12MOB devices.

9.13.4 MIC Certification

The CC3235MODx and CC3235MODAx modules from TI are MIC certified against article 49-20 and the relevant

articles of the Ordinance Regulating Radio Equipment.

Operation is subject to the following condition:

• The host system does not contain a wireless wide area network (WWAN) device.

This device operates in the W52 and W53 bands and is for indoor use only (except communication to high power

radio).

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9.14 Module Markings

图9-3 and 图9-4 show the markings for the SimpleLink™ CC3235MODx module.

图9-3. CC3235MODS Module Marking

图9-4. CC3235MODSF Module Marking

图9-5 and 图9-6 show the markings for the SimpleLink™ CC3235MODAx modules.

图9-6. CC3235MODASF Module Marking

图9-5. CC3235MODAS Module Marking

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表9-7 lists the CC3235MODx and CC3235MODAx module markings.

表9-7. Module Descriptions

MARKING

DESCRIPTION

CC3235MODSM2MOB

CC3235MODSF12MOB

CC3235MODASM2MON

CC3235MODASF12MON

Model

LTC (Lot Trace Code):

•

Y = Year

YMWLLLC

M = Month

WLLLC = Reserved for internal use

Z64-CC3235MOD

451I-CC3235MOD

FCC ID: single modular FCC grant ID

IC: single modular IC grant ID

MIC compliance mark

R 201-190033

MIC ID: modular MIC grant ID

CE compliance mark

9.15 End Product Labeling

These modules are designed to comply with the FCC single modular FCC grant, FCC ID: Z64-CC3235MOD.

The host system using this module must display a visible label indicating the following text:

Contains FCC ID: Z64-CC3235MOD

These modules are designed to comply with the IC single modular FCC grant, IC: 451I-CC3235MOD. The host

system using this module must display a visible label indicating the following text:

Contains IC: 451I-CC3235MOD

This module is designed to comply with the JP statement, 201-190033. The host system using this module must

display a visible label indicating the following text:

Contains transmitter module with certificate number: 201-190033

9.16 Manual Information to the End User

The OEM integrator must be aware not to provide information to the end user regarding how to install or remove

this RF module in the user’s manual of the end product which integrates this module.

The end user manual must include all required regulatory information and warnings as shown in this manual.

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10 Applications, Implementation, and Layout

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Typical Application

10.1.1 BLE/2.4 GHz Radio Coexistence

The CC3235MODx and CC3235MODAx devices are designed to support BLE/2.4 GHz radio coexistence.

Because WLAN is inherently more tolerant to time-domain disturbances, the coexistence mechanism gives

priority to the Bluetooth^®low energy entity over the WLAN. Bluetooth^®low energy operates in the 2.4 GHz band,

therefore the coexistence mechanism does not affect the 5 GHz band. The CC3235MODx and CC3235MODAx

device can operate normally on the 5 GHz band, while the Bluetooth^®low energy works on the 2.4 GHz band

without mutual interference.

The following coexistence modes can be configured by the user:

• Off mode or intrinsic mode

– No BLE/2.4 GHz radio coexistence, or no synchronization between WLAN and Bluetooth^®low energy—in

case Bluetooth^®low energy exists in this mode, collisions can randomly occur.

• Time Division Multiplexing (TDM, Dual Antenna)

– Dual-band Wi-Fi (see 图10-1)

In this mode, the WLAN can operate on either a 2.4 or 5 GHz band and Bluetooth^®low energy operates

on the 2.4 GHz band.

图 10-1 shows the dual antenna implementation of a complete Bluetooth^®low energy and WLAN coexistence

network with the WLAN operating on either a 2.4- or a 5 GHz band. Note in this implementation a Coex switch is

not required and only a single GPIO from the BLE device to the CC3235MOD device is needed. In addition, the

CC3235MODx's antenna is external while the CC3235MODAx's antenna is integrated.

Dual-band Antenna

BLE Ant.

RF_ABG

WLAN

CC3235MODx

BLE

CCxxxx

Coex IO

CC_COEX_BLE_IN

图10-1. Dual-Antenna Coexistence Mode Block Diagram

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10.1.2 Antenna Selection (CC3235MODx only)

The CC3235MODx device is designed to also support antenna selection and is controlled from Image Creator.

When enabled, there are 3 options possible options:

• ANT 1: When selected, the GPIOs that are defined for antenna selection with set the RF path for antenna 1.

• ANT 2: When selected, the GPIOs that are defined for antenna selection will set the RF path for antenna 2.

• Autoselect: When selected, during a scan and prior to connecting to an AP, CC3235MODx device will

determine the best RF path and select the appropriate antenna ^{13 14}. The result is the saved as port of the

profile.

图 10-2 shows the antenna selection implementation for Wi-Fi, with BLE operating on it's own antenna. Note in

this implementation, only a single GPIO from the BLE device to the CC3235MODx device is required. The

Antenna switch ¹⁵is controlled by 2 GPIO lines from the CC3235MODx device. 节 7.3 lists which GPIOs can be

used for Antenna Selection.

Dual Band Ant. 1

Antenna Selection

SPDT RF Switch

RF_ABG

ANT_SEL_1

Dual Band Ant. 2

ANT_SEL_2

WLAN

CC3235MODx

BLE Ant.

BLE

CCxxxx

CC_COEX_BLE_IN

Coex IO

图10-2. Coexistence Solution with Wi-Fi Antenna Selection and Dedicated BLE Antenna

When selecting Autoselect via the API, a reset is required in order for the CC3235MODx device to determine the best antenna for use.

Refer to the Uniflash with Image Creator User Guidefor more information.

The recommended Antenna switch is the Richwave RTC6608OSP.

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10.1.3 Typical Application Schematic (CC3235MODx)

图10-3 shows the typical application schematic using the CC3235MODx module. See the full reference schematic for CC3235MODx.

Note that the CC3235MODx and CC3235MODAx modules share the same reference schematic. The difference between the two references is the

antenna and its matching circuitry. The CC3235MODAx's pin 31 is not accessible to the designer because it is directly tied to the integrated antenna.

Note

The following guidelines are recommended for implementation of the RF design:

• Ensure an RF path is designed with an impedance of 50 Ω

• Tuning of the antenna impedance πmatching network is recommended after manufacturing of the PCB to account for PCB parasitics

• πor L matching and tuning may be required between cascaded passive components on the RF path

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Optional:

Consider adding extra decoupling

capaci tors itfhe battery cannot source

the peak cu rrenst.

VBAT_CC

0.1uF

100uF

GND

CC1

0.1uF

VBAT1

VBAT2

GPIO0

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO22

GPIO28

GPIO30

P50_GPIO_00

P55_GPIO_01

P57_GPIO_02

GND

At a minimum, pull thesepins out

P58_GPIO_03

P59_GPIO_04

P60_GPIO_05

to test pointsto aid in debug:

Pin 48: RS232_TX

Pin 49: RS232_RX

Pin 50: WLAN_LOG

Pin 52: NWP_LOG

VBAT_RESET

RESET

P61_GPIO_06

P62_GPIO_07

P63_GPIO_08

SEE TABLE 4-1 FOR

VBAT_RESET and nRESET

CONNECTION OPTIONS

P64_GPIO_09

P01_GPIO_10

P02_GPIO_11

P03_GPIO_12

P04_GPIO_13

P05_GPIO_14

P06_GPIO_15

P07_GPIO_16

P08_GPIO_17

P15_GPIO_22

P18_GPIO_28

P53_GPIO_30

Matching circuit shown belowis for

the antenna. The module is matched

may require antennamatching

optimization with a pi-network.

JTAG_TDI

JTAG_TDO

JTAG_TCK

JTAG_TMS

RF_ABG

JTAG/DEBUG

1pF

4.7nH

GND

VBAT_CC

RF_ABG

GNDGND

SOP[2:0] USED TO CONFIGURBEOOT MODES (TABLE 5-5)

10k

GND

SOP0

SOP1

SOP2

FLASH_SPI_MISO

FLASH_SPI_CS_IN

FLASH_SPI_CLK

FLASH_SPI_MOSI

EXTERNAL

PROGRAMMING

CC3235MODSF12MOBR

GND

图10-3. CC3235MODx Typical Application Schematic

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表10-1 provides the bill of materials for a typical application using the CC3235MODx module in 图10-3.

For full operation reference design, see the CC3235MODAx SimpleLink™ and Internet of Things Hardware Design Files.

表10-1. Bill of Materials

QTY

PART REFERENCE VALUE

MANUFACTURER

PART NUMBER

DESCRIPTION

C1, C2

0.1 µF

1 pF

Murata

GRM155R61A104KA01D

GRM1555C1H1R0CA01D

LMK325ABJ107MMHT

Capacitor, ceramic, 0.1 µF, 10 V, ±10%, X5R, 0402

Capacitor, ceramic, 1 pF, 50 V, ±5%, C0G/NP0, 0402

Murata

C4, C5

100 µF

Murata

Capacitor, ceramic, 100 µF, 10 V, ±20%, X5R, AEC-

Q200 Grade 3, 1210

2.4 GHz, 5 GHz Ant

4.7 nH

Ethertronics

Murata

M830520

Antenna Bluetooth WLAN Zigbee^®

LQG15HS4N7C02D

Inductor, Multilayer, Air Core, 4.7nH, 0.7 A, 0.16 Ω,

SMD

10k

Vishay-Dale

CRCW040210K0JNED

RES, 10k, 5%, 0.063 W, AEC-Q200 Grade 0, 0402

CC1

CC3235MODx

Texas Instruments

CC3235MODSM2MOB/

CC3235MODSF12MOB

SimpleLink™ Wi-Fi^®and Internet-of-Things Module

Solution, a Single-Chip Wireless Dual-Band MCU,

MOB0063A

10.1.4 Typical Application Schematic (CC3235MODAx)

图10-4 shows the typical application schematic using the CC3235MODAx module. See the full reference schematic for CC3235MODAx.

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Optional:

Consider adding extra decoupling

capacitors if the battery cannot source

the peak currents.

VBAT_CC

0.1uF

100uF

GND

CC?

0.1uF

VBAT1

VBAT2

GPIO_0

GPIO_01

GPIO_02

GPIO_03

GPIO_04

GPIO_05

GPIO_06

GPIO_07

GPIO_08

GPIO_09

GPIO_10

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_17

GPIO_22

GPIO_28

GPIO_30

P50_GPIO_00

P55_GPIO_01

P57_GPIO_02

GND

At a minimum, pull these pins out

P58_GPIO_03

to test points to aid in debug:

Pin 48: RS232_TX

Pin 49: RS232_RX

Pin 50: WLAN_LOG

Pin 52: NWP_LOG

P59_GPIO_04

P60_GPIO_05

P61_GPIO_06

P62_GPIO_07

VBAT_RESET

RESET

SEE TABLE 4-1 FOR

VBAT_RESET and nRESET

CONNECTION OPTIONS

P63_GPIO_08

P64_GPIO_09

P01_GPIO_10

P02_GPIO_11

P03_GPIO_12

P04_GPIO_13

P05_GPIO_14

P06_GPIO_15

P07_GPIO_16

P08_GPIO_17

P15_GPIO_22

P18_GPIO_28

P53_GPIO_30

JTAG_TDI

JTAG_TDO

JTAG_TCK

JTAG_TMS

JTAG/DEBUG

RF_ABG

VBAT_CC

GND

SOP[2:0] USED TO CONFIGURE BOOT MODES (TABLE 5-5)

10k

GND

SOP0

SOP1

SOP2

FLASH_SPI_CLK

FLASH_SPI_CS_IN

FLASH_SPI_MOSI

FLASH_SPI_MISO

EXTERNAL

PROGRAMMING

GND

CC3235MODASM2MONR

GND

图10-4. CC3235MODAx Typical Application Schematic

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表10-2 provides the bill of materials for a typical application using the CC3235MODAx module in 图10-4.

For full operation reference design, see the CC3235MODAx SimpleLink™ and Internet of Things Hardware Design Files.

表10-2. Bill of Materials

QTY

PART REFERENCE VALUE

MANUFACTURER

PART NUMBER

DESCRIPTION

C1, C2

C4, C5

0.1 µF

100 µF

Murata

GRM155R61A104KA01D

LMK325ABJ107MMHT

Capacitor, ceramic, 0.1 µF, 10 V, ±10%, X5R, 0402

Murata

Capacitor, ceramic, 100 µF, 10 V, ±20%, X5R, AEC-

Q200 Grade 3, 1210

10k

Vishay-Dale

CRCW040210K0JNED

RES, 10k, 5%, 0.063 W, AEC-Q200 Grade 0, 0402

CC1

CC3235MODAx

Texas Instruments

CC3235MODASM2MON/

CC3235MODASF12MON

SimpleLink™ Wi-Fi^®and Internet-of-Things Module

Solution, a Single-Chip Wireless Dual-Band MCU,

MON0063A

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10.2 Device Connection and Layout Fundamentals

10.2.1 Power Supply Decoupling and Bulk Capacitors

Depending upon routing resistors and battery type, TI recommends adding two 100-µF ceramic capacitors to

help provide the peak current drawn by the CC3235MODx and CC3235MODAx modules.

Note

The module enters a brown-out condition whenever the input voltage dips below V_BROWN(see 图 8-4

and 图8-5). This condition must be considered during design of the power supply routing specifically if

operating from a battery. For more details on brown-out consideration, see 节8.8.

10.2.2 Reset

The module features an internal RC circuit to reset the device during power ON. The nRESET pin must be held

below 0.6 V for at least 5 ms for the device to successfully reset.

10.2.3 Unused Pins

All unused pins can be left unconnected without the concern of having leakage current.

10.3 PCB Layout Guidelines

This section details the PCB guidelines to speed up the PCB design using the CC3235MODx and

CC3235MODAx. The integrator of theCC3235MODxandCC3235MODAx modules must comply with the PCB

layout recommendations described in the following subsections to minimize the risk with regulatory certifications

for the FCC, IC/ISED, ETSI/CE, MIC, and SRRC. Moreover, TI recommends customers follow the guidelines

described in this section to achieve similar performance to that obtained with the TI reference design.

10.3.1 General Layout Recommendations

Ensure that the following general layout recommendations are followed:

• Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.

• Do not run signal traces underneath the module on a layer where the module is mounted.

10.3.2 CC3235MODx RF Layout Recommendations

The RF section of this wireless module gets top priority in terms of layout. It is very important for the RF section

to be laid out correctly to ensure optimum performance from the module. A poor layout can cause low-output

power, EVM degradation, sensitivity degradation, and mask violations.

图10-5 shows the RF placement and routing of the CC3235MODx module with external antenna.

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图10-5. RF Section Layout

Follow these RF layout recommendations for the CC3235MODx device:

• RF traces must have 50-Ωimpedance.

• RF trace bends must be made with gradual curves, and 90° bends must be avoided.

• RF traces must not have sharp corners.

• There must be no traces or ground under the antenna section.

• RF traces must have via stitching on the ground plane beside the RF trace on both sides.

• RF traces must be as short as possible. The antenna, RF traces, and the module must be on the edge of the

PCB product in consideration of the product enclosure material and proximity.

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For optimal RF performance, ensure the copper cut out on the top layer under the RF-BG pin (pin 31) is as

shown in 图10-6.

图10-6. Top Layer Copper Pullback on RF Pads

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10.3.2.1 Antenna Placement and Routing

The antenna is the element used to convert the guided waves on the PCB traces to the free space

electromagnetic radiation. The placement and layout of the antenna are the keys to increased range and data

rates. 表10-3 provides a summary of the recommended antennas to use with the CC3235MODx module.

表10-3. Antenna Guidelines

SR NO.

GUIDELINES

Place the antenna on an edge or corner of the PCB.

Ensure that no signals are routed across the antenna elements on all the layers of the

PCB.

Most antennas, including the chip antenna used on the LaunchPad^™, require ground

clearance on all the layers of the PCB. Ensure that the ground is cleared on inner layers

as well.

Ensure that there is provision to place matching components for the antenna. These must

be tuned for best return loss when the complete board is assembled. Any plastics or

casing must also be mounted while tuning the antenna because this can impact the

impedance.

Ensure that the antenna impedance is 50 Ωbecause the module is rated to work only

with a 50-Ωsystem.

In case of printed antenna, ensure that the simulation is performed with the solder mask in

consideration.

Ensure that the antenna has a near omnidirectional pattern.

The feed point of the antenna is required to be grounded. This is only for the antenna type

used on the CC3235MODx Launchpad. See the specific antenna data sheets for the

recommendations.

表 10-4 lists the recommended antennas to use with the CC3235MODx module. Other antennas may be

available for use with the CC3235MODx modules.

表10-4. Recommended Components

CHOICE

PART NUMBER

MANUFACTURER

NOTES

Can be placed on edge of the PCB and uses much less PCB

space

M830520

Ethertronics

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10.3.2.2 Transmission Line Considerations

The RF signal from the module is routed to the antenna using a Coplanar Waveguide with ground (CPW-G)

structure. CPW-G structure offers the maximum amount of isolation and the best possible shielding to the RF

lines. In addition to the ground on the L1 layer, placing GND vias along the line also provides additional

shielding.

图10-7 shows a cross section of the coplanar waveguide with the critical dimensions.

图10-8 shows the top view of the coplanar waveguide with GND and via stitching.

图10-7. Coplanar Waveguide (Cross Section)

图10-8. CPW With GND and Via Stitching (Top View)

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The recommended values for the PCB are provided for 2-layer boards in 表10-5 and 4-layer boards in 表10-6.

表10-5. Recommended PCB Values for 2-Layer

Board (L1 to L2 = 42.1 mils)

PARAMETER

VALUE

UNIT

mils

F/m

5.5

42.1

4.2

Er (FR-4 substrate)

表10-6. Recommended PCB Values for 4-Layer

Board (L1 to L2 = 16 mils)

PARAMETER

VALUE

UNITS

mils

Er (FR-4 substrate)

4.5

F/m

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10.3.3 CC3235MODAx RF Layout Recommendations

Use the following guidelines to lay out the CC3235MODAx module with an integrated antenna, as shown in 图

10-9.

• The module must have an overhang of 1 mm from the PCB edge.

• The module must have a 6-mm clearance on all layers (no copper) to the left and right of the module

placement.

• There must be at least one ground-reference plane under the module on the main PCB.

图10-9. CC3235MODAx Layout Guidelines

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11 Environmental Requirements and SMT Specifications

11.1 PCB Bending

The PCB follows IPC-A-600J for PCB twist and warpage < 0.75% or 7.5 mil per inch.

11.2 Handling Environment

11.2.1 Terminals

The product is mounted with motherboard through land-grid array (LGA). To prevent poor soldering, do not make

skin contact with the LGA portion.

11.2.2 Falling

The mounted components will be damaged if the product falls or is dropped. Such damage may cause the

product to malfunction.

11.3 Storage Condition

11.3.1 Moisture Barrier Bag Before Opened

A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH. The

calculated shelf life for the dry-packed product will be 24 months from the date the bag is sealed.

11.3.2 Moisture Barrier Bag Open

Humidity indicator cards must be blue, < 30%.

11.4 PCB Assembly Guide

The wireless MCU modules are packaged in a substrate base Leadless Quad Flatpack (QFM) package.

Components were mounted onto the substrate with standard SMT process with the additional of a metal lid

covering the top of the module. The module are designed with pull back leads for easy PCB layout and board

mounting.

11.4.1 PCB Land Pattern & Thermal Vias

We recommended a solder mask defined land pattern to provide a consistent soldering pad dimension in order

to obtain better solder balancing and solder joint reliability. PCB land pattern are 1:1 to module soldering pad

dimension. Thermal vias on PCB connected to other metal plane are for thermal dissipation purpose. It is critical

to have sufficient thermal vias to avoid device thermal shutdown. Recommended vias size are 0.2mm and

position not directly under solder paste to avoid solder dripping into the vias.

11.4.2 SMT Assembly Recommendations

The module surface mount assembly operations include:

• Screen printing the solder paste on the PCB

• Monitor the solder paste volume (uniformity)

• Package placement using standard SMT placement equipment

• X-ray pre-reflow check - paste bridging

• Reflow

• X-ray post-reflow check - solder bridging and voids

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11.4.3 PCB Surface Finish Requirements

A uniform PCB plating thickness is key for high assembly yield. For an electroless nickel immersion gold finish,

the gold thickness should range from 0.05 µm to 0.20 µm to avoid solder joint embrittlement. Using a PCB with

Organic Solderability Preservative (OSP) coating finish is also recommended as an alternative to Ni-Au.

11.4.4 Solder Stencil

Solder paste deposition using a stencil-printing process involves the transfer of the solder paste through pre-

defined apertures with the application of pressure. Stencil parameters such as aperture area ratio and the

fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of

package is highly recommended to improve board assembly yields.

11.4.5 Package Placement

Packages can be placed using standard pick and place equipment with an accuracy of ±0.05 mm. Component

pick and place systems are composed of a vision system that recognizes and positions the component and a

mechanical system that physically performs the pick and place operation. Two commonly used types of vision

systems are:

• A vision system that locates a package silhouette

• A vision system that locates individual pads on the interconnect pattern

The second type renders more accurate placements but tends to be more expensive and time consuming. Both

methods are acceptable since the parts align due to a self-centering features fo the solder joint during solder

reflow. It is recommended to release the package to 1 to 2 mils into the solder paste or with minimum force to

avoid causing any possible damage to the thinner packages.

11.4.6 Solder Joint Inspection

After surface mount assembly, transmission X-ray should be used for sample monitoring of the solder

attachment process. This identifies defects such as solder bridging, shorts, opens, and voids. It is also

recommended to use side view inspection in addition to X-rays to determine if there are "Hour Glass" shaped

solder and package tilting existing. The "Hour Glass" solder shape is not a reliable joint. 90° mirror projection can

be used for side view inspection.

11.4.7 Rework and Replacement

TI recommends removal of modules by rework station applying a profile similar to the mounting process. Using a

heat gun can sometimes cause damage to the module by overheating.

11.4.8 Solder Joint Voiding

TI recommends to control solder joint voiding to be less than 30% (per IPC-7093). Solder joint voids could be

reduced by baking of components and PCB, minimized solder paste exposure duration, and reflow profile

optimization.

11.5 Baking Conditions

Products require baking before mounting if:

• Humidity indicator cards read > 30%

• Temp < 30°C, humidity < 70% RH, over 96 hours

Baking condition: 90°C, 12 to 24 hours

Baking times: 1 time

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11.6 Soldering and Reflow Condition

• Heating method: Conventional convection or IR convection

• Temperature measurement: Thermocouple d = 0.1 mm to 0.2 mm CA (K) or CC (T) at soldering portion or

equivalent method

• Solder paste composition: SAC305

• Allowable reflow soldering times: 2 times based on the reflow soldering profile (see 图11-1)

• Temperature profile: Reflow soldering will be done according to the temperature profile (see

图11-1)

• Peak temperature: 260°C

图11-1. Temperature Profile for Evaluation of Solder Heat Resistance of a Component (at Solder Joint)

表11-1. Temperature Profile

Profile Elements

Convection or IR⁽¹⁾

Peak temperature range

235 to 240°C typical (260°C maximum)

Pre-heat / soaking (150 to 200°C)

Time above melting point

Time with 5°C to peak

Ramp up

60 to 120 seconds

60 to 90 seconds

30 seconds maximum

< 3°C / second

Ramp down

< -6°C / second

(1) For details, refer to the solder paste manufacturer's recommendation.

Note

TI does not recommend the use of conformal coating or similar material on the SimpleLink™ module.

This coating can lead to localized stress on the solder connections inside the module and impact the

module reliability. Use caution during the module assembly process to the final PCB to avoid the

presence of foreign material inside the module.

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12 Device and Documentation Support

TI offers and extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed in this section.

12.1 Development Tools and Software

For the most up to date list of Development Tools and Software, visit the CC3235MOD tools and software page.

Or, click on the Alert me button in the top-right corner of the page, to stay informed of updates related to the

CC3235MOD.

Pin Mux Tool

The supported devices are: CC3200, CC3220x, and CC3235x.

The Pin Mux Tool is a software tool that provides a graphical user interface (GUI) for

configuring pin multiplexing settings, resolving conflicts and specifying I/O cell

characteristics for MPUs from TI. Results are output as C header/code files that can

be imported into software development kits (SDKs) or used to configure customers'

custom software. Version 3 of the Pin Mux Tool adds the capability of automatically

selecting a mux configuration that satisfies the entered requirements.

SimpleLink™ Wi-Fi^®

Starter Pro

The supported devices are: CC3100, CC3200, CC3120R, CC3220x, CC3135, and

CC3235x.

The SimpleLink™ Wi-Fi^®Starter Pro mobile App is a new mobile application for

SimpleLink™ provisioning. The app goes along with the embedded provisioning

library and example that runs on the device side (see SimpleLink™ Wi-Fi^®SDK plugin

and TI SimpleLink ™ CC32XX Software Development Kit (SDK)). The new

provisioning release is a TI recommendation for Wi-Fi^®provisioning using SimpleLink

™ Wi-Fi^®products. The provisioning release implements advanced AP mode and

SmartConfig™ technology provisioning with feedback and fallback options to ensure

successful process has been accomplished. Customers can use both embedded

library and the mobile library for integration to their end products.

SimpleLink™ CC32XX

The CC3235x devices are supported.

Software Development

Kit (SDK)

The SimpleLink™ CC32XX SDK contains drivers for the CC3235 programmable

MCU, more than 30 sample applications, and documentation needed to use the

solution. It also contains the flash programmer, a command line tool for flashing

software, configuring network and software parameters (SSID, access point channel,

network profile, BS NIEW), system files, and user files (certificates, web pages, and

more). This SDK can be used with TI’s SimpleLink™ Wi-Fi^®CC3235 LaunchPad™

development kits.

Uniflash Standalone

Flash Tool for TI

The supported devices are: CC3120R, CC3220x, CC3135, and CC3235x.

Microcontrollers (MCU), CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs

Sitara Processors &

SimpleLink Devices

and on-board flash memory for Sitara™ processors. Uniflash has a GUI, command

line, and scripting interface. CCS Uniflash is available free of charge.

SimpleLink™ Wi-Fi^®

Radio Testing Tool

The supported devices are: CC3100, CC3200, CC3120R, CC3220, CC3135, and

CC3235x.

The SimpleLink™ Wi-Fi^®Radio Testing Tool is a Windows-based software tool for RF

evaluation and testing of SimpleLink™ Wi-Fi^®CC3x20 and CC3x35 designs during

development and certification. The tool enables low-level radio testing capabilities by

manually setting the radio into transmit or receive modes. Using the tool requires

familiarity and knowledge of radio circuit theory and radio test methods.

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Created for the internet-of-things (IoT), the SimpleLink™ Wi-Fi^®CC31xx and CC32xx

family of devices include on-chip Wi-Fi^®, Internet, and robust security protocols with

no prior Wi-Fi^®experience needed for faster development. For more information on

these devices, visit SimpleLink™ Wi-Fi^®family, Internet-on-a chip™ solutions.

UniFlash Standalone

Flash Tool for TI

Microcontrollers (MCU),

Sitara™ Processors and

SimpleLink™ Devices

CCS UniFlash is a standalone tool used to program on-chip flash memory on TI

MCUs and on-board flash memory for Sitara^™processors. UniFlash has a GUI,

command line, and scripting interface. CCS UniFlash is available free of charge.

12.2 Firmware Updates

TI updates features in the service pack for this module with no published schedule. Due to the ongoing changes,

TI recommends users have the latest service pack in their module for production.

To stay informed, sign up for updates using the SDK Alert me button in the top-right corner of the product page,

or visit http://www.ti.com/tool/download/SIMPLELINK-CC32XX-SDK.

12.3 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the

CC3235MODx and CC3235MODAx and support tools (see 图12-1).

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, CC3235MODxandCC3235MODAx). Texas Instruments recommends two of three possible prefix

designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product

development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

CC 3235 MOD

XXXX XXX

PACKAGING

R = tape/reel

PREFIX

X = preproduction device

no prefix = production device

PACKAGE DESIGNATOR

MON = LGA package

DEVICE FAMILY

CC = wireless connectivity

SERIES NUMBER

3 = Wi-Fi Centric

SM2 = S module

SF12 = SF module

MODULE

MOD = module

A = integral antenna

No prefix = no antenna

图12-1. CC3235MODx and CC3235MODAx Module Nomenclature

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For orderable part numbers of the CC3235MODx and CC3235MODAx devices in the QFM package type, see 节

13.2, see ti.com, or contact your TI sales representative.

12.4 Documentation Support

To receive notification of documentation updates — including silicon errata — go to the CC3235MOD product

folder on ti.com. In the upper-right corner, click on Alert me to receive a weekly digest of any product information

that has changed. For change details, check the revision history of any revised document.

The current documentation that describes the processor, related peripherals, and other technical collateral is as

follows.

Application Reports

CC3135 and CC3235 SimpleLink™

CC3135 and CC3235 SimpleLink Wi-Fi Embedded Programming User

Wi-Fi^®Embedded Programming User Guide

Guide

SimpleLink™ CC3135, CC3235 Wi-Fi^®This application report describes the best practices for power

Internet-on-a chip™ Networking Sub- management and extended battery life for embedded low-power Wi-Fi

System Power Management

devices such as the SimpleLink Wi-Fi Internet-on-a chip solution from

Texas Instruments.

SimpleLink™ CC31xx, CC32xx Wi-Fi^®The SimpleLink Wi-Fi CC31xx and CC32xx Internet-on-a chip family of

Internet-on-a chip™ Solution Built-In

Security Features

devices from Texas Instruments offer a wide range of built-in security

features to help developers address a variety of security needs, which

is achieved without any processing burden on the main microcontroller

(MCU). This document describes these security-related features and

provides recommendations for leveraging each in the context of

practical system implementation.

SimpleLink™ CC3135, CC3235 Wi-Fi^®This document describes the OTA library for the SimpleLink Wi-Fi

and Internet-of-Things Over-the-Air

Update

CC3x35 family of devices from Texas Instruments and explains how to

prepare a new cloud-ready update to be downloaded by the OTA

library.

SimpleLink™ CC3135, CC3235 Wi-Fi^®This guide describes the provisioning process, which provides the

Internet-on-a chip™ Solution Device

Provisioning

SimpleLink Wi-Fi device with the information (network name, password,

and so forth) needed to connect to a wireless network.

Transfer of TI's Wi-Fi^®Alliance

Certifications to Products Based on

SimpleLink™

This document explains how to employ the Wi-Fi® Alliance (WFA)

derivative certification transfer policy to transfer a WFA certification,

already obtained by Texas Instruments, to a system you have

developed.

Using Serial Flash on SimpleLink™

CC3135 and CC3235 Wi-Fi^®and

Internet-of-Things Devices

This application note is divided into two parts. The first part provides

important guidelines and best- practice design techniques to consider

when choosing and embedding a serial Flash paired with the CC3135

and CC3235 (CC3x35) devices. The second part describes the file

system, along with guidelines and considerations for system designers

working with the CC3x35 devices.

More Literature

CC3235MODx SimpleLink™ Wi-Fi^®and Internet-of-Things Hardware Design Files

CC3220MODAx SimpleLink™ Wi-Fi^®and Internet-of-Things Hardware Design Files

CC3x35x SimpleLink™ Wi-Fi^®and Internet-of-Things Design Checklist

User's Guides

CC3135 and CC3235

SimpleLink™ Wi-Fi^®

CC3135 and CC3235 SimpleLink Wi-Fi Embedded Programming User Guide

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Embedded Programming

User Guide

UniFlash SimpleLink™

This document describes the installation, operation, and usage of the SimpleLink

CC31xx/32xx Wi-Fi^®and IoC ImageCreator tool as part of the UniFlash.

™ Solution ImageCreator

and Pro

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SimpleLink™ Wi-Fi^®and

Internet-of-Things CC31xx

and CC32xx Network

Processor

This document provides software (SW) programmers with all of the required

knowledge for working with the networking subsystem of the SimpleLink Wi-Fi

devices. This guide provides basic guidelines for writing robust, optimized

networking host applications, and describes the capabilities of the networking

subsystem. The guide contains some example code snapshots, to give users an

idea of how to work with the host driver. More comprehensive code examples can

be found in the formal software development kit (SDK). This guide does not

provide a detailed description of the host driver APIs.

SimpleLink™ Wi-Fi^®CC3135

and CC3235 Provisioning for

Mobile Applications

This guide describes TI’s SimpleLink Wi-Fi provisioning solution for mobile

applications, specifically on the usage of the Android^™and IOS^®building blocks

for UI requirements, networking, and provisioning APIs required for building the

mobile application.

CC3235 SimpleLink™ Wi-Fi^®This technical reference manual details the modules and peripherals of the

and Internet of Things

CC3235 SimpleLink™ Wi-Fi^®MCU. Each description presents the module or

Technical Reference Manual peripheral in a general sense. Not all features and functions of all modules or

peripherals may be present on all devices. Pin functions, internal signal

connections, and operational parameters differ from device to device. The user

should consult the device-specific data sheet for these details.

SimpleLink™ Wi-Fi^®and

The Radio Tool serves as a control panel for direct access to the radio, and can

Internet-on-a chip™ CC3135 be used for both the radio frequency (RF) evaluation and for certification

and CC3235 Solution Radio purposes. This guide describes how to have the tool work seamlessly on Texas

Tool

Instruments evaluation platforms such as the BoosterPack™ plus FTDI emulation

board for CC3235 devices, and the LaunchPad™ for CC3235 devices.

CC3235MOD SimpleLink™ The CC3235MOD SimpleLink LaunchPad™ Development Kit

Wi-Fi^®LaunchPad™

Development Kit

(LAUNCHCC3235MOD) is a low-cost evaluation platform for Arm^®Cortex^®-M4-

based MCUs. The LaunchPad design highlights the CC3235MOD Internet-on-a

chip™ solution and Dual-Band Wi-Fi capabilities. The CC3235MOD LaunchPad

also features temperature and accelerometer sensors, programmable user

buttons, an RGB LED for custom applications, and onboard emulation for

debugging. The stackable headers of the CC3235MOD LaunchPad XL interface

demonstrate how easy it is to expand the functionality of the LaunchPad when

interfacing with other peripherals on many existing BoosterPack™ Plug-in

Module add-on boards, such as graphical displays, audio codecs, antenna

selection, environmental sensing, and more.

12.5 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

表12-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

CC3235MODS

CC3235MODSF

CC3235MODAS

CC3235MODASF

Click here

12.6 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

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12.7 Trademarks

WPA^™, WPA2^™, WPA3^™, Wi-Fi CERTIFIED^™are trademarks of Wi-Fi Alliance.

SimpleLink^™, E2E^™, BoosterPack^™, LaunchPad^™, Sitara^™, and TI E2E^™are trademarks of Texas Instruments.

Macronix^™is a trademark of Macronix International Co..

Macrocell^™is a trademark of Kappa Global Inc.

Android^™is a trademark of Google LLC.

Wi-Fi 联盟^®, Wi-Fi^®, Wi-Fi Direct^®, and are registered trademarks of Wi-Fi Alliance.

^®, Arm^®, Cortex^®, Thumb^®are registered trademarks of Arm Limited.

Zigbee^®is a registered trademark of Zigbee Alliance Inc.

IOS^®is a registered trademark of Cisco.

所有商标均为其各自所有者的财产。

12.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.9 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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ZHCSKT8B –FEBRUARY 2020 –REVISED MAY 2021

www.ti.com.cn

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document.

13.1 Mechanical, Land, and Solder Paste Drawings

Note

The total height of the module is 2.4 mm.

The weight of the CC3235MODx module is 1.8 g typical.

The weight of the CC3235MODAx module is 1.8 g typical.

Note

1. All dimensions are in mm.

2. Solder mask should be the same or 5% larger than the dimension of the pad.

3. Solder paste must be the same as the pin for all peripheral pads. For ground pins, make the

solder paste 20% smaller than the pad.

13.2 Package Option Addendum

The CC3235MODx is only offered in a 750-unit reel. The CC3235MODAx is only offered in a 700-unit reel.

104 Submit Document Feedback

Product Folder Links: CC3235MODS CC3235MODSF CC3235MODAS CC3235MODASF

CC3235MODS, CC3235MODSF, CC3235MODAS, CC3235MODASF

www.ti.com.cn

ZHCSKT8B –FEBRUARY 2020 –REVISED MAY 2021

13.2.1 Packaging Information

Package

Type

Package

Drawing

Package

Qty

Lead/Ball

Finish

Orderable Device

Status ⁽¹⁾

ACTIVE

Pins

Eco Plan ⁽²⁾

MSL, Peak Temp ⁽³⁾

3, 260°C

Op Temp (°C)

–40 to 85

Device Marking^{(4) (5)}

CC3235MODSF12MOB

CC3235MODSM2MOB

CC3235MODASF12MON

CC3235MODASM2MON

Green (RoHS

and no Sb/Br)

CC3235MODSF12MOBR

CC3235MODSM2MOBR

CC3235MODASF12MONR

CC3235MODASM2MONR

QFM

MOB

MON

750

700

ENIG

Green (RoHS

and no Sb/Br)

ACTIVE

3, 260°C

Green (RoHS

and no Sb/Br)

PREVIEW

3, 260°C

Green (RoHS

and no Sb/Br)

3, 260°C

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%

by weight in homogeneous material)

space

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by

third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable

steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain

information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Submit Document Feedback

105

Product Folder Links: CC3235MODS CC3235MODSF CC3235MODAS CC3235MODASF

CC3235MODS, CC3235MODSF, CC3235MODAS, CC3235MODASF

ZHCSKT8B –FEBRUARY 2020 –REVISED MAY 2021

www.ti.com.cn

13.2.2 Tape and Reel Information

330.0 max

101±1.0

W1 44±±.0

W± 45.8 max

106 Submit Document Feedback

Product Folder Links: CC3235MODS CC3235MODSF CC3235MODAS CC3235MODASF

CC3235MODS, CC3235MODSF, CC3235MODAS, CC3235MODASF

www.ti.com.cn

ZHCSKT8B –FEBRUARY 2020 –REVISED MAY 2021

13.2.3 CC3235MODx Tape Specifications

1. 10 sprocket hole pitch cumulative tolerance 0.20.

2. Material: Polystyrene

3. All dimensions meet EIA-481-E requirements.

4. Thickness: 0.2 0.05mm

13.2.4 CC3235MODAx Tape Specifications

1. 10 sprocket hole pitch cumulative tolerance 0.ꢀ0.

ꢀ. Material: Polystyrene

3. All dimensions meet EIA-481-E requirements.

4. Thickness: 0.ꢀ 0.0ꢁmm

Submit Document Feedback 107

Product Folder Links: CC3235MODS CC3235MODSF CC3235MODAS CC3235MODASF

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

22-Jul-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

CC3235MODASF12MONR

ACTIVE

QFM

MON

700

RoHS (In

Work) & Green

(In Work)

NIAU

Level-3-260C-168 HR

-40 to 85

CC3235MODASF12MON

Z64-CC3235MOD

451I-CC3235MOD

201-190033

Samples

XXXXXXXXXX(M)

CC3235MODASM2MONR

CC3235MODSF12MOBR

CC3235MODSM2MOBR

ACTIVE

QFM

MON

MOB

700

750

RoHS (In

Work) & Green

(In Work)

NIAU

Level-3-260C-168 HR

-40 to 85

CC3235MODASM2MON

Z64-CC3235MOD

451I-CC3235MOD

201-190033

Samples

RoHS & Green

CC3235MODSF12MOB

Z64-CC3235MOD

451I-CC3235MOD

201-190033

RoHS (In

Work) & Green

(In Work)

CC3235MODSM2MOB

Z64-CC3235MOD

451I-CC3235MOD

201-190033

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-Jul-2023

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

MOB0063A

QFM - 2.4 mm max height

SCALE 0.650

QUAD FLAT MODULE

17.75

17.25

PIN 1 INDEX

AREA

20.75

20.25

2X (0.45)

2X (0.38)

2.40

2.03

0.1

0.88

0.72

2X 12.7

20X 1.27

(0.3) TYP

30X 1.27

(0.32)

PADS 1,16,28 & 43

(0.3)

TYP

0.05

1.5

19.05

6X 3

54X 0.81 0.08

0.15

0.05

C A B

44 43

PIN 1 ID

(45 X1)

1.5

6X 3

4221462/D 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

MOB0063A

QFM - 2.4 mm max height

QUAD FLAT MODULE

PKG

SEE DETAIL

54X ( 0.81)

(

8.1)

9X ( 2)

0.05 MIN TYP

(45 X 1)

(

0.2) TYP

VIA

METAL UNDER

SOLDER MASK

OPENING

PKG

6X (3)

(1.5)

2X (19.1)

(0.65)

TYP

(1.5)

(0.65)

TYP

6X (3)

(1.27) TYP

(R0.05)

ALL PADS

2X (16.1)

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE:6X

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

SIGNAL PADS DETAIL

4221462/D 06/2019

NOTES: (continued)

3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

MOB0063A

QFM - 2.4 mm max height

QUAD FLAT MODULE

PKG

54X ( 0.81)

(R0.05)

TYP

SOLDER MASK

EDGE, TYP

SOLDER MASK EDGE

SEE DETAILS

PKG

(3) TYP

2X (19.1)

(1.5) TYP

(3) TYP

(1.27) TYP

2X (16.1)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PADS PRINTED SOLDER COVERAGE BY AREA

PAD 55: 77.5 %, PADS 56 - 63: 79%

SCALE:6X

(1.54)

(0.55) TYP

(0.45)

(

0.89) TYP

2X ( 0.89)

(0.55 TYP)

METAL

TYP

(R0.05) TYP

(R0.05)

TYP

PADS 56 - 63 DETAIL

PAD 55 DETAIL

SCALE:10X

4221462/D 06/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

MON0063A

QFM - 2.4 mm max height

SCALE 0.600

QUAD FLAT MODULE

25.25

24.75

PIN 1 ID

20.75

20.25

19.61 0.1

PICK & PLACE

NOZZLE AREA

16.74 0.1

2.40

2.03

SEATING PLANE

0.08 C

0.88

0.72

2X 12.7

PKG

20X 1.27

30X 1.27

0.05

1.5

19.05

PADS 1-16

& 28-43

PKG

19.038

PADS 17-27

& 44-54

6X 3

PIN 1 ID

(45 X1)

(0.326) TYP

54X 0.81 0.08

6X 3

11.769

2.224

0.15

0.05

C A B

4.321

4223415/D 11/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

MON0063A

QFM - 2.4 mm max height

QUAD FLAT MODULE

SEE DETAIL

PATTERN

PKG

54X ( 0.81)

(

8.1)

9X ( 2)

(

0.2) TYP

0.05 MIN TYP

VIA

(45 X 1)

METAL UNDER

SOLDER MASK

OPENING

(19.048)

PKG

6X (3)

(20.5)

(1.5)

(0.65)

TYP

(1.5)

(0.65)

TYP

6X (3)

(1.27) TYP

(R0.05)

ALL PADS

(8.05)

(3.724)

(25)

(4.326)

NO TRACES, VIAS, GND PLANE

OR SILK SCREEN SHOULD BE

LOCATED WITHIN THIS AREA

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE:5X

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

SIGNAL PADS DETAIL

4223415/D 11/2021

NOTES: (continued)

3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

MON0063A

QFM - 2.4 mm max height

QUAD FLAT MODULE

PATTERN

PKG

54X ( 0.81)

SOLDER MASK

EDGE, TYP

SOLDER MASK EDGE

SEE DETAILS

(3) TYP

(19.048)

PKG

(1.5) TYP

(3) TYP

(1.27) TYP

(R0.05)

TYP

(8.05)

(3.724)

(16.1)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PADS PRINTED SOLDER COVERAGE BY AREA

PAD 55: 77.5 %, PADS 56 - 63: 79%

SCALE:6X

(1.54)

(0.55) TYP

(0.45)

2X ( 0.89)

(

0.89) TYP

(0.55 TYP)

EXPOSED METAL

TYP

(R0.05) TYP

(R0.05)

TYP

PAD 55 DETAIL

PADS 56 - 63 DETAIL

SCALE:10X

4223415/D 11/2021

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CC3235MODSF [TI]

相关型号：

CC3235MODSF12MOBR

CC3235MODSM2MOBR

CC3235S

CC3235SF

CC3235SF12RGKR

CC3235SM2RGKR

CC327

CC327-16

CC327-25

CC327-40

CC327A

CC327APNP