CD74ACT245SM96G4 [TI]
Octal-Bus Transceiver Three-State, Non-Inverting; 八路总线收发器三态，非反相
| 型号： | CD74ACT245SM96G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal-Bus Transceiver Three-State, Non-Inverting |
| 文件： | 总16页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74AC245,
CD54/74ACT245
Data sheet acquired from Harris Semiconductor
SCHS245B
Octal-Bus Transceiver,
Three-State, Non-Inverting
September 1998 - Revised October 2000
Features
Description
• Buffered Inputs
The ’AC245 and ’ACT245 are octal-bus transceivers that
utilize Advanced CMOS Logic technology. They are non-
• Typical Propagation Delay
o
inverting
three-state
bidirectional
transceiver-buffers
- 4ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
intended for two-way transmission from “A” bus to “B” bus or
“B” bus to “A”. The logic level present on the direction input
(DIR) determines the data direction. When the output enable
input (OE) is HIGH, the outputs are in the high-impedance
state.
• Exceeds 2kV ESD Protection per MIL-STD-883,
Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
[ /Title
(CD74
AC245
,
CD74
ACT24
5)
/Sub-
ject
(Octal-
Bus
Trans-
ceiver,
Three-
State,
Non-
Invert-
ing)
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
TEMP.
o
NUMBER
RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld PDIP
• Balanced Propagation Delays
CD54AC245F3A
CD74AC245E
CD74AC245M
CD74AC245SM
CD54ACT245F3A
CD74ACT245E
CD74ACT245M
CD74ACT245SM
NOTES:
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
20 Ld SOIC
20 Ld SSOP
20 Ld CERDIP
20 Ld PDIP
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
20 Ld SOIC
20 Ld SSOP
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
/Autho
r ()
/Key-
words
(Har-
ris
Pinout
CD54AC245, CD54ACT245
(CERDIP)
CD74AC245, CD74ACT245
(PDIP, SOIC, SSOP)
TOP VIEW
Semi-
con-
ductor,
Advan
ced
CMOS
,Harris
Semi-
con-
1
2
3
4
5
6
7
8
9
V
DIR
A0
A1
A2
A3
A4
A5
A6
A7
20
19
CC
OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12
B6
GND 10
11 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated
CD54/74AC245, CD54/74ACT245
Functional Diagram
2
18
A0
B0
3
17
A1
B1
4
16
A2
B2
5
15
A3
B3
6
14
A4
B4
7
13
A5
B5
8
12
A6
B6
9
11
A7
B7
1
DIR
19
OE
TRUTH TABLE
CONTROL INPUTS
OE
L
DIR
OPERATION
L
H
X
B Data to A Bus
L
A Data to B Bus
Isolation
H
H = High Level, L = Low Level, X = Irrelevant
To prevent excess currents in the High-Z (isolation) modes, all I/O
terminals should be terminated with 10kΩ to 1MΩ resistors.
2
CD54/74AC245, CD54/74ACT245
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
E Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SM Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
58
70
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
DC Output Source or Sink Current per Output Pin, I
O
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD54/74AC245, CD54/74ACT245
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
GND
or
0
5.5
-
8
-
80
-
160
µA
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State or Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
or
0
-
5.5
-
-
8
-
-
80
-
-
160
3
µA
CC
CC
GND
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
2.8
mA
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
4
CD54/74AC245, CD54/74ACT245
ACT Input Load Table
INPUT
An, Bn
OE
UNIT LOAD
0.83
0.64
DIR
0.25
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay,
Data to Output
t
, t
1.5
3.3
-
-
-
96
-
-
-
106
ns
ns
PLH PHL
3.2
10.8
3
11.9
(Note 9)
5
2.2
-
7.7
2.1
-
8.5
ns
(Note 10)
Propagation Delay,
Output Disable to Output
t
, t
PLZ PHZ
1.5
3.3
5
-
-
159
15.9
12.7
159
19
-
-
175
17.5
14
ns
ns
ns
ns
ns
ns
V
4.7
3.7
-
-
4.4
3.5
-
-
-
-
Propagation Delay,
Output Enable to Output
t , t
PZL PZH
1.5
3.3
5
-
-
175
21
5.6
3.7
-
-
-
5.3
3.5
-
-
-
12.7
-
14
Minimum (Valley) V
OH
Switching of Other Outputs
During
V
5
4 at
4 at
-
OHV
See Figure 1
o
o
25 C
25 C
(Output Under Test Not Switching)
Maximum (Peak) V During
OL
Switching of Other Outputs
V
5
-
1 at
25 C
-
-
1 at
25 C
-
V
OLP
See Figure 1
o
o
(Output Under Test Not Switching)
Three-State Output Capacitance
Input Capacitance
C
-
-
-
-
-
-
15
-
-
10
-
-
-
-
15
-
-
10
-
pF
pF
pF
O
C
I
Power Dissipation Capacitance
C
57
57
PD
(Note 11)
ACT TYPES
Propagation Delay,
Data to Output
t
, t
5
2.7
3.7
3.8
-
-
9.1
12.7
13.1
-
2.5
3.5
3.6
-
-
10
14
ns
ns
ns
V
PLH PHL
(Note 10)
Propagation Delay,
Output Disable to Output
t
, t
PLZ PHZ
5
5
5
Propagation Delay,
Output Enable to Output
t
, t
PZL PZH
14.4
-
Minimum (Valley) V
OH
Switching of Other Outputs
During
V
4 at
4 at
OHV
See Figure 1
o
o
25 C
25 C
(Output Under Test Not Switching)
Maximum (Peak) V During
OL
Switching of Other Outputs
V
5
-
1 at
25 C
-
-
1 at
25 C
-
V
OLP
See Figure 1
o
o
(Output Under Test Not Switching)
5
CD54/74AC245, CD54/74ACT245
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Three-State Output Capacitance
Input Capacitance
SYMBOL
V
(V)
MIN
TYP
15
-
MAX
MIN
TYP
15
-
MAX
UNITS
pF
CC
C
-
-
-
-
-
10
-
-
-
-
-
10
-
O
C
-
-
pF
I
Power Dissipation Capacitance
C
57
57
pF
PD
(Note 11)
NOTES:
8. Limits tested 100%
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C
is used to determine the dynamic power consumption per channel.
PD
AC: P = V
2
f (C
+ C )
D
CC
i
PD
L
2
ACT: P = V
f (C
PD
+ C ) + V
∆I
where f = input frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
CC CC
i
L
V
OH
OTHER
OUTPUTS
V
OL
V
OH
V
OUTPUT
UNDER
TEST
OHV
V
OLP
V
OL
NOTES:
12. Input pulses have the following characteristics: PRR ≤ 1MHz, t = 3ns, SKEW 1ns.
r
13. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 1. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
6
CD54/74AC245, CD54/74ACT245
t = 3ns
t = 3ns
INPUT LEVEL
90%
f
r
OUTPUTS
DISABLED
V
S
10%
GND
t
t
t
PLZ
PZL
PZH
OUTPUT:
LOW TO OFF
TO LOW
V
S
0.2 V
CC
CC
V
(≠ V
)
CC
OL
t
PHZ
0.8 V
V
S
OUTPUT:
HIGH TO OFF
TO HIGH
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
GND (t )
, t
PHZ PZH
OPEN (t
, t
)
PHL PLH
, t
OTHER
INPUTS
TIED HIGH
OR LOW
2 V
(t )
CC PLZ PZL
R
500Ω
L
(OPEN DRAIN)
DUT WITH
THREE-
STATE
OUT
L
500Ω
(NOTE 14)
R
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE:
14. For AC Series only: When V
= 1.5V, R = 1kΩ.
L
CC
FIGURE 2. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT
t = 3ns
t = 3ns
f
r
INPUT
LEVEL
90%
An
V
S
10%
GND
t
t
PHL
PLH
V
S
Bn
FIGURE 3. PROPAGATION DELAY TIMES
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
L
CC
AC
ACT
3V
Input Level
V
CC
Input Switching Voltage, V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
0.5 V
CC
S
FIGURE 4. PROPAGATION DELAY TIMES
7
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
PDIP
Drawing
CD54AC245F3A
CD54ACT245F3A
CD74AC245E
ACTIVE
ACTIVE
ACTIVE
J
J
20
20
20
1
1
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74AC245EE4
CD74AC245M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SSOP
SSOP
SSOP
SSOP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SSOP
SSOP
SSOP
SSOP
N
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
DW
DW
DW
DW
DW
DW
DB
DB
DB
DB
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74AC245M96
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74AC245M96E4
CD74AC245M96G4
CD74AC245ME4
CD74AC245MG4
CD74AC245SM
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74AC245SM96
CD74AC245SM96E4
CD74AC245SM96G4
CD74ACT245E
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74ACT245EE4
CD74ACT245M
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
DW
DW
DW
DW
DW
DW
DB
DB
DB
DB
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74ACT245M96
CD74ACT245M96E4
CD74ACT245M96G4
CD74ACT245ME4
CD74ACT245MG4
CD74ACT245SM
CD74ACT245SM96
CD74ACT245SM96E4
CD74ACT245SM96G4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package Package
Type Drawing
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
(mm)
24
CD74AC245M96
CD74AC245SM96
CD74ACT245M96
CD74ACT245SM96
DW
DB
DW
DB
20
20
20
20
SITE 41
SITE 41
SITE 41
SITE 41
10.8
8.2
13.0
7.5
2.7
2.5
2.7
2.5
12
12
12
12
24
16
24
16
Q1
Q1
Q1
Q1
16
24
10.8
8.2
13.0
7.5
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
CD74AC245M96
CD74AC245SM96
CD74ACT245M96
CD74ACT245SM96
DW
DB
DW
DB
20
20
20
20
SITE 41
SITE 41
SITE 41
SITE 41
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
41.0
33.0
41.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Wireless
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Copyright © 2007, Texas Instruments Incorporated
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