CD74ACT245SM [TI]
Octal-Bus Transceiver, Three-State, Non-Inverting; 八路总线收发器，三态，非反相
| 型号： | CD74ACT245SM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal-Bus Transceiver, Three-State, Non-Inverting |
| 文件： | 总8页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74AC245,
CD74ACT245
Data sheet acquired from Harris Semiconductor
SCHS245
Octal-Bus Transceiver,
September 1998
Three-State, Non-Inverting
Features
Description
• Buffered Inputs
The CD74AC245 and CD74ACT245 are octal-bus transceiv-
ers that utilize the Harris Advanced CMOS Logic technology.
They are non-inverting three-state bidirectional transceiver-
buffers intended for two-way transmission from “A” bus to “B”
bus or “B” bus to “A”. The logic level present on the direction
input (DIR) determines the data direction. When the output
enable input (OE) is HIGH, the outputs are in the high-
impedance state.
• Typical Propagation Delay
o
- 4ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
[ /Title
(CD74
AC245
,
CD74
ACT24
5)
/Sub-
ject
(Octal-
Bus
Trans-
ceiver,
Three-
State,
Non-
Invert-
ing)
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
TEMP.
PKG.
NO.
o
NUMBER
RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
• Balanced Propagation Delays
CD74AC245E
CD74ACT245E
CD74AC245M
CD74ACT245M
CD74AC245SM
CD74ACT245SM
NOTES:
E20.3
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
E20.3
M20.3
M20.3
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
20 Ld SSOP M20.15
20 Ld SSOP M20.15
- Drives 50Ω Transmission Lines
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74AC245, CD74ACT245
/Autho
r ()
(PDIP, SSOP, SOIC)
TOP VIEW
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Advan
ced
1
2
3
4
5
6
7
8
9
V
DIR
A0
A1
A2
A3
A4
A5
A6
A7
20
19
CC
OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12
B6
CMOS
,Harris
Semi-
con-
GND 10
11 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
File Number 1907.1
1
CD74AC245, CD74ACT245
Functional Diagram
2
18
17
16
15
14
13
12
11
A0
B0
B1
B2
B3
B4
B5
B6
B7
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
1
DIR
19
OE
TRUTH TABLE
CONTROL INPUTS
OE
L
DIR
OPERATION
B Data to A Bus
L
H
X
L
A Data to B Bus
Isolation
H
H = High Level, L = Low Level, X = Irrelevant
To prevent excess currents in the High-Z (isolation) modes, all I/O
terminals should be terminated with 10kΩ to 1MΩ resistors.
2
CD74AC245, CD74ACT245
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
120
130
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
DC Output Source or Sink Current per Output Pin, I
O
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD74AC245, CD74ACT245
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
GND
or
0
5.5
-
8
-
80
-
160
µA
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State or Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
or
0
-
5.5
-
-
8
-
-
80
-
-
160
3
µA
CC
CC
GND
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
V
4.5 to
5.5
2.4
2.8
mA
CC
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
4
CD74AC245, CD74ACT245
ACT Input Load Table
INPUT
An, Bn
OE
UNIT LOAD
0.83
0.64
0.15
DIR
NOTE: Unit load is ∆I
CC
Table, e.g., 2.4mA max at 25 C.
limit specified in DC Electrical Specifications
o
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay,
Data to Output
t
, t
PLH PHL
1.5
3.3
-
-
-
96
-
-
-
106
ns
ns
3.2
10.8
3
11.9
(Note 9)
5
2.2
-
7.7
2.1
-
8.5
ns
(Note 10)
Propagation Delay,
Output Disable to Output
t
, t
PLZ PHZ
1.5
3.3
5
-
-
159
15.9
12.7
159
19
-
-
175
17.5
14
ns
ns
ns
ns
ns
ns
V
4.7
3.7
-
-
4.4
3.5
-
-
-
-
Propagation Delay,
Output Enable to Output
t , t
PZL PZH
1.5
3.3
5
-
-
175
21
5.6
3.7
-
-
-
5.3
3.5
-
-
-
12.7
-
14
Minimum (Valley) V
OH
Switching of Other Outputs
During
V
5
4 at
4 at
-
OHV
See Figure 1
o
o
25 C
25 C
(Output Under Test Not Switching)
Maximum (Peak) V During
OL
Switching of Other Outputs
V
5
-
1 at
25 C
-
-
1 at
25 C
-
V
OLP
See Figure 1
o
o
(Output Under Test Not Switching)
Three-State Output Capacitance
Input Capacitance
C
-
-
-
-
-
-
15
-
-
10
-
-
-
-
15
-
-
10
-
pF
pF
pF
O
C
I
Power Dissipation Capacitance
C
57
57
PD
(Note 11)
ACT TYPES
Propagation Delay,
Data to Output
t
, t
5
2.7
3.7
3.8
-
-
9.1
12.7
13.1
-
2.5
3.5
3.6
-
-
10
14
ns
ns
ns
V
PLH PHL
(Note 10)
Propagation Delay,
Output Disable to Output
t
, t
PLZ PHZ
5
5
5
Propagation Delay,
Output Enable to Output
t
, t
PZL PZH
14.4
-
Minimum (Valley) V
OH
Switching of Other Outputs
During
V
4 at
4 at
OHV
See Figure 1
o
o
25 C
25 C
(Output Under Test Not Switching)
Maximum (Peak) V During
OL
Switching of Other Outputs
V
5
-
1 at
25 C
-
-
1 at
25 C
-
V
OLP
See Figure 1
o
o
(Output Under Test Not Switching)
5
CD74AC245, CD74ACT245
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Three-State Output Capacitance
Input Capacitance
SYMBOL
V
(V)
MIN
TYP
15
-
MAX
MIN
TYP
15
-
MAX
UNITS
pF
CC
C
-
-
-
-
-
10
-
-
-
-
-
10
-
O
C
-
-
pF
I
Power Dissipation Capacitance
C
57
57
pF
PD
(Note 11)
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V
11. C
PD
is used to determine the dynamic power consumption per channel.
2
AC: P = V
ACT: P = V
f (C + C )
D
CC
i
PD L
2
f (C
PD
+ C ) + V
∆I
where f = input frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
CC CC
i
L
V
OH
OTHER
OUTPUTS
V
OL
V
OH
V
OUTPUT
UNDER
TEST
OHV
V
OLP
V
OL
NOTES:
12. Input pulses have the following characteristics: PRR ≤ 1MHz, t = 3ns, SKEW 1ns.
r
13. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 1. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
6
CD74AC245, CD74ACT245
t = 3ns
t = 3ns
r
INPUT LEVEL
90%
f
OUTPUTS
DISABLED
V
S
10%
GND
t
t
t
PLZ
PZL
PZH
OUTPUT:
LOW TO OFF
TO LOW
V
S
0.2 V
CC
CC
V
(≠ V
)
CC
OL
t
PHZ
0.8 V
V
S
OUTPUT:
HIGH TO OFF
TO HIGH
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
GND (t )
, t
PHZ PZH
OPEN (t
, t
)
PHL PLH
, t
OTHER
INPUTS
TIED HIGH
OR LOW
2 V
(t )
CC PLZ PZL
R
500Ω
L
(OPEN DRAIN)
DUT WITH
THREE-
STATE
OUT
L
500Ω
(NOTE 14)
R
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE:
14. For AC Series only: When V
= 1.5V, R = 1kΩ.
L
CC
FIGURE 2. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT
t = 3ns
t = 3ns
f
r
INPUT
LEVEL
90%
An
V
S
10%
GND
t
t
PHL
PLH
V
S
Bn
FIGURE 3. PROPAGATION DELAY TIMES
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
Input Level
= 1.5V, R = 1kΩ.
CC
L
CD74AC
CD74ACT
3V
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 4. PROPAGATION DELAY TIMES
7
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Copyright 1999, Texas Instruments Incorporated
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