CD74HC85PWRG4 [TI]
High-Speed CMOS Logic 4-Bit Magnitude Comparator; 高速CMOS逻辑4位幅度比较型号: | CD74HC85PWRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | High-Speed CMOS Logic 4-Bit Magnitude Comparator |
文件: | 总17页 (文件大小:498K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54HC85, CD74HC85,
CD54HCT85, CD74HCT85
Data sheet acquired from Harris Semiconductor
SCHS136E
High-Speed CMOS Logic
4-Bit Magnitude Comparator
August 1997 - Revised October 2003
Features
Description
• Buffered Inputs and Outputs
The ’HC85 and ’HCT85 are high speed magnitude
comparators that use silicon-gate CMOS technology to
achieve operating speeds similar to LSTTL with the low
power consumption of standard CMOS integrated circuits.
• Typical Propagation Delay: 13ns (Data to Output at
o
[ /Title
(CD74
HC85,
CD74
HCT85
)
V
= 5V, C = 15pF, T = 25 C
L A
CC
• Serial or Parallel Expansion Without External Gating
These 4-bit devices compare two binary, BCD, or other
monotonic codes and present the three possible magnitude
results at the outputs (A > B, A < B, and A = B). The 4-bit
input words are weighted (A0 to A3 and B0 to B3), where A3
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
and B are the most significant bits.
3
o
o
/Sub-
ject
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
The devices are expandable without external gating, in both
serial and parallel fashion. The upper part of the truth table
indicates operation using a single device or devices in a
serially expanded application. The parallel expansion
scheme is described by the last three entries in the truth
table.
(High
Speed
CMOS
Logic
4-Bit
Magni-
tude
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
Ordering Information
- High Noise Immunity: N = 30%, N = 30%of V
IL IH
at
CC
V
= 5V
TEMP. RANGE
o
CC
PART NUMBER
CD54HC85F3A
CD54HCT85F3A
CD74HC85E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
• HCT Types
Com-
para-
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
CD74HC85M
Pinout
CD74HC85MT
CD74HC85M96
CD74HC85NSR
CD74HC85PW
CD74HC85PWR
CD74HC85PWT
CD74HCT85E
CD74HCT85M
CD74HCT85MT
CD74HCT85M96
CD54HC85, CD54HCT85 (CERDIP)
CD74HC85 (PDIP, SOIC, SOP, TSSOP)
CD74HCT85 (PDIP, SOIC)
TOP VIEW
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
B3
(A < B) IN
(A = B) IN
(A > B) IN
(A > B) OUT
(A = B) OUT
(A < B) OUT
GND
1
2
3
4
5
6
7
8
16 V
CC
15 A3
14 B2
13 A2
12 A1
11 B1
10 A0
9
B0
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
PFunctional Diagram
15
13
12
10
A3
A2
A1
A0
7
6
5
2
3
4
(A < B) OUT
(A = B) OUT
(A > B) OUT
(A < B) IN
(A = B) IN
(A > B) IN
1
14
11
9
B3
B2
B1
B0
TRUTH TABLE
CASCADING INPUTS
COMPARING INPUTS
A2, B2 A1, B1
SINGLE DEVICE OR SERIES CASCADING
OUTPUTS
A < B
A3, B3
A0, B0
A > B
A < B
A = B
A > B
A = B
A3 > B3
A3 < B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
X
X
A2 >B2
A2 < B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
X
H
L
X
H
L
A1 > B1
A1 < B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
H
L
H
L
A0 > B0
A0 < B0
A0 = B0
A0 = B0
A0 = B0
H
L
H
L
H
L
H
L
L
H
L
L
H
L
PARALLEL CASCADING
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A1 = B1
A1 = B1
A1 = B1
A0 = B0
A0 = B0
A0 = B0
X
H
L
X
H
L
H
L
L
L
L
L
L
H
L
L
A2 = B2
A2 = B2S
H
H
H = High Voltage Level, L = Low Voltage, Level, X = Don’t Care
2
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Package Thermal Impedance, θ (see Note 1):
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
IK
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
o
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
o
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
1.9
4.4
5.9
-
-
1.9
4.4
5.9
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
4.4
5.9
-
OH
-0.02
-0.02
-
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-4
4.5
6
3.98
5.48
-
-
3.84
5.34
-
-
3.7
5.2
-
-
-5.2
0.02
0.02
0.02
4
-
-
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
0.1
0.1
0.1
0.26
0.1
0.1
0.1
0.33
0.1
0.1
0.1
0.4
OL
4.5
6
-
-
-
-
-
-
Low Level Output
Voltage
4.5
-
-
-
TTL Loads
5.2
-
6
6
-
-
-
-
0.26
-
-
0.33
-
-
0.4
V
Input Leakage
Current
I
V
or
±0.1
±1
±1
µA
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
A0-A3, B0-B3 and (A = B) IN
(A > B) IN, (A < B) IN
1.5
1
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
Propagation Delay,
A , B to (A > B) OUT,
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
t
t
C = 50pF
2
-
-
-
195
39
-
-
-
-
-
-
-
-
-
245
47
-
-
-
-
-
-
-
-
-
295
59
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH, PHL
L
n
n
4.5
5
-
-
-
-
-
-
-
(A < B) OUT
C = 15pF
16
-
L
C = 50pF
6
33
175
35
-
42
240
44
-
50
265
53
-
L
A , B to (A = B) OUT
t
t
C = 50pF
2
-
n
n
PLH, PHL
L
4.5
5
-
C = 15pF
14
-
L
C = 50pF
6
30
37
45
L
4
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
(A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT
t
t
C = 50pF
2
-
-
-
140
28
-
-
-
-
-
-
-
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
210
42
-
ns
ns
ns
ns
ns
ns
ns
ns
pF
PLH, PHL
L
4.5
5
-
-
-
-
-
-
-
-
C = 15pF
11
-
L
C = 50pF
6
24
120
24
-
30
150
30
-
36
180
36
-
L
(A > B) IN to (A = B) OUT
t
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C = 15pF
9
-
L
C = 50pF
L
6
20
-
26
-
31
-
Power Dissipation Capacitance
(Notes 3, 4)
C
-
5
24
PD
Output Transition Times
(Figure 1)
t
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
-
-
75
15
13
10
-
-
-
-
95
19
16
10
-
-
-
-
110
22
ns
ns
ns
pF
19
Input Capacitance
C
-
-
10
IN
HCT TYPES
Propagation Delay,
An, Bn to (A > B) OUT,
(A < B) OUT
t
t
C = 50pF
4.5
5
-
-
-
37
-
-
-
46
-
-
-
56
-
ns
ns
PLH, PHL
L
C = 15pF
15
L
An, Bn to (A = B) OUT
t
t
t
t
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
17
-
40
-
-
-
-
-
-
-
-
50
-
-
-
-
-
-
-
-
60
-
ns
ns
ns
ns
ns
ns
ns
PLH, PHL
L
C = 15pF
L
(A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT
t
C = 50pF
4.5
5
30
-
38
-
45
-
PLH, PHL
L
C = 15pF
12
-
L
(A > B) IN to (A = B) OUT
t
C = 50pF
4.5
5
31
-
39
-
47
-
PLH, PHL
L
C = 15pF
13
-
L
Output Transition Times
(Figure 1)
t
, t
TLH THL
C = 50pF
L
4.5
15
19
22
Power Dissipation Capacitance
(Notes 3, 4)
C
-
5
-
-
-
26
-
-
-
-
-
-
-
-
pF
pF
PD
Input Capacitance
NOTES:
C
-
10
10
10
IN
3. C
is used to determine the dynamic power consumption, per gate/package.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Test Circuits and Waveforms
GND
(A > B) IN
(A = B) IN
(A < B) IN
V
CC
GND
A0
A1
A2
A3
B0
B1
B2
B3
A0
A1
CD74HC85
CD74HCT85
A2
A3
B0
B1
B2
B3
LEAST SIGNIFICANT
4-BITS OF EACH WORD
(A > B) IN
(A = B) IN
(A < B) IN
A4
A5
A6
A7
B4
B5
B6
B7
A4
A5
CD74HC85
A6
A7
B4
B5
B6
B7
CD74HCT85
(A > B) OUT
(A = B) OUT
(A < B) OUT
(A > B) IN
(A = B) IN
(A < B) IN
A0
A1
A2
A3
B0
B1
B2
B3
A0
A1
CD74HC85
A2
A3
B0
B1
B2
B3
CD74HCT85
MOST SIGNIFICANT
4-BITS OF EACH WORD
(A > B) OUT
(A = B) OUT
(A < B) OUT
OUTPUTS
FIGURE 3. SERIES CASCADING - COMPARING 12-BIT WORDS
6
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Test Circuits and Waveforms
CD74HC85
B11
A11
B10
A10
B9
B3
A3
B2
CD74HCT85
A2 (A < B) OUT
B1
NC
(A = B) OUT
A1
A9
(A > B) OUT
B0
B8
A0
A8
B7
(A < B) IN
(A = B) IN
(A > B) IN
GND
A7
CD74HC85
B6
A6
B3
A3
B2
A2
B1
A1
B0
A0
CD74HCT85
B5
(A < B) OUT
(A = B) OUT
(A > B) OUT
A5
CD74HC85
B4
NC
B3
A3
B2
A2
B1
A1
B0
A0
CD74HCT85
A4
B3
A3
(A > B) OUT
(A = B) OUT
(A < B) OUT
(A < B) IN
(A = B) IN
(A > B) IN
B2
OUTPUTS
CD74HC85
GND
A2
B1
A1
B0
A0
B3
A3
B2
CD74HCT85
OUTPUTS
(A < B) IN
(A = B) IN
(A > B) IN
A2 (A < B) OUT
B1
A1
B0
A0
(A = B) OUT
(A > B) OUT
GND
(A < B) IN
(A = B) IN
(A > B) IN
VCC
GND
FIGURE 4. PARALLEL CASCADING - COMPARING 12-BIT WORDS
7
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8867201EA
8601301EA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
16
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
CD54HC85F3A
CD54HCT85F3A
CD74HC85E
J
1
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC85EE4
CD74HC85M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
N
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC85M96
CD74HC85M96E4
CD74HC85M96G4
CD74HC85ME4
CD74HC85MG4
CD74HC85MT
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC85MTE4
CD74HC85MTG4
CD74HC85NSR
CD74HC85NSRE4
CD74HC85NSRG4
CD74HC85PW
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC85PWE4
CD74HC85PWG4
CD74HC85PWR
CD74HC85PWRE4
CD74HC85PWRG4
CD74HC85PWT
CD74HC85PWTE4
CD74HC85PWTG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
CD74HCT85E
CD74HCT85EE4
CD74HCT85M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
N
N
D
D
D
D
D
D
D
D
D
16
16
16
16
16
16
16
16
16
16
16
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
Pb-Free
(RoHS)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT85M96
CD74HCT85M96E4
CD74HCT85M96G4
CD74HCT85ME4
CD74HCT85MG4
CD74HCT85MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT85MTE4
CD74HCT85MTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
(mm)
16
CD74HC85M96
CD74HC85NSR
CD74HC85PWR
CD74HCT85M96
D
NS
PW
D
16
16
16
16
SITE 27
SITE 41
SITE 41
SITE 27
6.5
8.2
7.0
6.5
10.3
10.5
5.6
2.1
2.5
1.6
2.1
8
12
8
16
16
12
16
Q1
Q1
Q1
Q1
16
12
16
10.3
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
CD74HC85M96
CD74HC85NSR
CD74HC85PWR
CD74HCT85M96
D
NS
PW
D
16
16
16
16
SITE 27
SITE 41
SITE 41
SITE 27
342.9
346.0
346.0
342.9
336.6
346.0
346.0
336.6
28.58
33.0
29.0
28.58
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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