CD74HC86M [TI]
High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR Gate; 高速CMOS逻辑四路2输入异或门
| 型号： | CD74HC86M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR Gate |
| 文件： | 总6页 (文件大小：47K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC86,
CD74HCT86
Data sheet acquired from Harris Semiconductor
SCHS137
High Speed CMOS Logic
August 1997
Quad 2-Input EXCLUSIVE OR Gate
Features
Description
• Typical Propagation Delay: 9ns at V
o
= 5V,
The Harris CD74HC86, CD74HCT86 contain four
independent EXCLUSIVE OR gates in one package. They
CC
C = 15pF, T = 25 C
L
A
[ /Title
(CD74
HC86,
CD74
HCT86
)
provide the system designer with
a
means for
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
implementation of the EXCLUSIVE OR function. Logic gates
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power
consumption of standard CMOS integrated circuits. All
devices have the ability to drive 10 LSTTL loads. The 74HCT
logic family is functionally pin compatible with the standard
74LS logic family.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
/Sub-
ject
Ordering Information
• HC Types
(High
Speed
CMOS
Logic
Quad
2-Input
EXCL
USIVE
OR
- 2V to 6V Operation
TEMP. RANGE
PKG.
NO.
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
o
PART NUMBER
CD74HC86E
( C)
PACKAGE
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
Wafer
at V
= 5V
CC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E14.3
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
CD74HCT86E
CD74HC86M
CD74HCT86M
CD54HC86W
CD54HCT86W
CD54HC86H
E14.3
M14.15
M14.15
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Applications
Wafer
• Logical Comparators
Die
• Parity Generators and Checkers
• Adders and Subtractors
NOTE: When ordering, use the entire part number. Add the suffix 96
to obtain the variant in the tape and reel.
Pinout
CD74HC86, CD74HCT86
(PDIP, SOIC)
TOP VIEW
1A
1B
1
2
3
4
5
6
7
14 V
CC
13 4B
12 4A
11 4Y
10 3B
1Y
2A
2B
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1644.1
Copyright © Harris Corporation 1997
1
CD74HC86, CD74HCT86
Functional Diagram
14
13
12
11
10
9
1
2
3
4
5
6
7
V
1A
1B
CC
4B
4A
4Y
3B
3A
3Y
1Y
2A
2B
2Y
8
GND
TRUTH TABLE
INPUTS
OUTPUT
nA
L
nB
L
nY
L
L
H
L
H
H
L
H
H
H
NOTE: H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nB
nY
2
CD74HC86, CD74HCT86
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
180
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO +85 C -55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
2
20
40
CC
CC
GND
3
CD74HC86, CD74HCT86
DC Electrical Specifications (Continued)
TEST
o
o
o
o
o
CONDITIONS
25 C
-40 C TO +85 C -55 C TO 125 C
PARAMETER
HCT TYPES
SYMBOL V (V)
I
(mA)
V (V) MIN TYP MAX
CC
MIN
MAX
MIN
MAX
UNITS
I
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
5.5
5.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
Low Level Output
Voltage
CMOS Loads
V
or
-0.02
-
-
-
0.1
-
-
-
0.1
0.33
±1
-
-
-
0.1
0.4
±1
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
4
0
0.26
±0.1
V
Input Leakage
Current
I
V
µA
I
CC
and
GND
Quiescent Device
Current
I
V
or
0
-
-
-
-
2
-
-
20
-
-
40
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 2)
∆I
CC
V
4.5 to
5.5
100
360
450
490
CC
-2.1
NOTE:
2. For dual-supply systems theorectical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
1
NOTE: Unit Load is ∆I
Specifications table, e.g. 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay,Input to
Output (Figure 1)
t
, t
PLH PHL
C = 50pF
2
4.5
6
-
-
-
-
-
-
120
24
20
-
-
-
-
-
150
30
26
-
-
-
-
-
180
36
31
-
ns
ns
ns
ns
L
-
Propagation Delay, Data Input to
Output Y
t , t
PLH PHL
C = 15pF
5
9
L
Transition Times (Figure 1)
t
, t
TLH THL
C = 50pF
2
4.5
6
-
-
-
-
-
-
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
L
19
4
CD74HC86, CD74HCT86
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
Input Capacitance
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
10
-
MIN
MAX
10
-
UNITS
pF
C
-
-
-
-
-
-
10
-
-
-
-
-
I
Power Dissipation Capacitance
(Notes 3, 4)
C
5
22
pF
PD
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
t
, t
PLH PHL
C = 50pF
4.5
5
-
-
-
32
-
-
-
40
-
-
-
48
-
ns
ns
L
Propagation Delay, Data Input to
Output Y
t , t
PLH PHL
C = 15pF
13
L
Transition Times (Figure 2)
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
-
-
-
-
-
15
10
-
-
-
-
19
10
-
-
-
-
22
10
-
ns
pF
pF
C
-
-
I
Power Dissipation Capacitance
(Notes 3, 4)
C
5
27
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per gate.
2
PD
4. P = V
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V = supply voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
t = 6ns
f
t = 6ns
r
r
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
t
GND
GND
t
t
TLH
t
THL
THL
TLH
90%
50%
10%
90%
1.3V
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
t
t
PHL
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明