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CD74HCT390MTG4 [TI]

High-Speed CMOS Logic Dual Decade Ripple Counter; 高速CMOS逻辑双路十年纹波计数器
CD74HCT390MTG4
型号： CD74HCT390MTG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed CMOS Logic Dual Decade Ripple Counter
高速CMOS逻辑双路十年纹波计数器

计数器
文件： 总15页 (文件大小：424K)
中文：  中文翻译
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CD74HC390,  
CD54HCT390, CD74HCT390  
Data sheet acquired from Harris Semiconductor  
SCHS185C  
High-Speed CMOS Logic  
September 1997 - Revised October 2003  
Dual Decade Ripple Counter  
Features  
Description  
• Two BCD Decade or Bi-Quinary Counters  
The CD74HC390 and ’HCT390 dual 4-bit decade ripple  
counters are high-speed silicon-gate CMOS devices and are  
pin compatible with low-power Schottky TTL (LSTTL). These  
devices are divided into four separately clocked sections.  
The counters have two divide-by-2 sections and two divide-  
by-5 sections. These sections are normally used in a BCD  
decade or bi-quinary configuration, since they share a com-  
mon master reset (nMR). If the two master reset inputs (1MR  
and 2MR) are used to simultaneously clear all 8 bits of the  
counter, a number of counting configurations are possible  
within one package. The separate clock inputs (nCP0 and  
nCP1) of each section allow ripple counter or frequency divi-  
sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100.  
Each section is triggered by the High-to-Low transition of the  
input pulses (nCP0 and nCP1).  
• One Package Can Be Configured to Divide-by-2, 4,  
5,10, 20, 25, 50 or 100  
[ /Title  
(CD74  
HC390  
,
CD74  
HCT39  
0)  
/Sub-  
ject  
(High  
Speed  
CMOS  
• Two Master Reset Inputs to Clear Each Decade  
Counter Individually  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
For BCD decade operation, the nQ0 output is connected to  
the nCP1 input of the divide-by-5 section. For bi-quinary  
decade operation, the nO3 output is connected to the nCP0  
• HC Types  
- 2V to 6V Operation  
input and nQ becomes the decade output.  
0
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
The master reset inputs (1MR and 2MR) are active-High  
asynchronous inputs to each decade counter which oper-  
ates on the portion of the counter identified by the “1” and “2”  
prefixes in the pin configuration. A High level on the nMR  
input overrides the clock and sets the four outputs Low.  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
Ordering Information  
l
OL OH  
TEMP. RANGE  
o
PART NUMBER  
CD54HCT390F3A  
CD74HC390E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
Pinout  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
CD54HCT390  
(CERDIP)  
CD74HC390, CD74HCT390  
(PDIP, SOIC)  
CD74HC390M  
TOP VIEW  
CD74HC390MT  
CD74HC390M96  
CD74HCT390E  
CD74HCT390M  
CD74HCT390MT  
CD74HCT390M96  
1CP0  
1MR  
1
2
3
4
5
6
7
8
16 V  
CC  
15 2CP0  
14 2MR  
13 2Q0  
1Q  
0
1CP1  
1Q  
1Q  
1Q  
12 2CP1  
1
2
3
11 2Q  
10 2Q  
1
2
3
9
2Q  
GND  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD74HC390, CD54HCT390, CD74HCT390  
Functional Diagram  
1 (15)  
2 (14)  
3 (13)  
nCP0  
nMR  
nQ  
0
÷
2
COUNTER  
5 (11)  
nQ  
nQ  
nQ  
1
2
6 (10)  
7 (9)  
÷
5
4 (12)  
COUNTER  
nCP1  
3
GND = 8  
V
= 16  
CC  
TRUTH TABLE  
INPUTS  
CP  
↑
MR  
ACTION  
No Change  
Count  
L
L
↓
X
H
All Qs Low  
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,  
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.  
B-QUINARY COUNT SEQUENCE FOR 1/2 THE 390  
OUTPUTS  
BCD COUNT SEQUENCE FOR 1/2 THE 390  
OUTPUTS  
COUNT  
Q0  
L
Q1  
L
Q2  
L
Q3  
L
COUNT  
Q0  
L
Q1  
L
Q2  
L
Q3  
L
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
L
H
L
L
L
H
L
L
L
L
L
H
H
L
L
H
H
L
L
L
L
H
L
L
H
L
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
H
L
L
H
L
L
L
H
L
H
H
H
L
L
H
H
L
L
L
H
L
L
H
L
L
H
H
H
H
L
L
Output nQ3 connected to nCP0 with counter input on nCP1.  
Output nQ0 connected to nCP1 with counter input on nCP0.  
2
CD74HC390, CD54HCT390, CD74HCT390  
Logic Diagram  
4(12)  
nCP1  
Q
Q
Q
Q
1(15)  
nCP0  
Φ
Φ
Φ
Φ
R
R
R
R
2(14)  
nMR  
V
= 16  
CC  
GND = 8  
3(13)  
0
5(11)  
1
6(10)  
2
7(9)  
3
nQ  
nQ  
nQ  
nQ  
3
CD74HC390, CD54HCT390, CD74HCT390  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
JA  
IK  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .  
67  
73  
For V < -0.5V or V > V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
(SOIC - Lead Tips Only)  
DC V  
or Ground Current, I  
I
. . . . . . . . . . . . . . . . . .±50mA  
CC  
CC or GND  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
2
4.5  
6
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
3.15  
-
-
3.15  
-
-
3.15  
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
2
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
-0.02  
2
1.9  
1.9  
1.9  
OH  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
8
-
80  
-
160  
µA  
CC  
CC  
4
CD74HC390, CD54HCT390, CD74HCT390  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HCT TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
V
or V  
-0.02  
4.5  
4.5  
4.5  
4.5  
4.4  
4.4  
4.4  
OH  
IH  
IH  
IL  
High Level Output  
Voltage  
TTL Loads  
-4  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
or V  
0.02  
4
-
-
0.1  
0.26  
-
-
0.1  
0.33  
-
-
0.1  
0.4  
OL  
IL  
Low Level Output  
Voltage  
TTL Loads  
Input Leakage  
Current  
I
V
and  
0
0
-
5.5  
5.5  
-
-
-
-
-
±0.1  
8
-
-
-
±1  
80  
-
-
-
±1  
µA  
µA  
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
or  
160  
490  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
CC  
-2.1  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
nCP0  
UNIT LOADS  
0.45  
0.6  
nCP1, MR  
NOTE: Unit Load is ∆I  
360µA max at 25 C.  
limit specified in DC Electrical Table, e.g.,  
CC  
o
Prerequisite for Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
CHARACTERISTIC  
HC TYPES  
SYMBOL  
V
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CC  
Maximum Clock  
Frequency  
f
2
6
-
-
-
-
-
-
-
-
-
-
-
-
5
24  
28  
100  
20  
17  
-
-
-
-
-
-
4
20  
24  
120  
24  
20  
-
-
-
-
-
-
MHz  
MHz  
MHz  
ns  
MAX  
4.5  
30  
35  
80  
16  
14  
6
2
Clock Pulse Width,  
nCP0, nCP1  
t
W
4.5  
6
ns  
ns  
5
CD74HC390, CD54HCT390, CD74HCT390  
Prerequisite for Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
CHARACTERISTIC  
SYMBOL  
t
V
(V)  
MIN  
70  
14  
12  
50  
10  
9
TYP  
MAX  
MIN  
90  
18  
15  
65  
13  
11  
MAX  
MIN  
105  
21  
MAX  
UNITS  
ns  
CC  
Reset Removal Time  
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
REM  
4.5  
ns  
6
2
18  
ns  
Reset Pulse Width  
t
75  
ns  
W
4.5  
6
15  
ns  
13  
ns  
HCT TYPES  
Maximum Clock  
Frequency  
f
MAX  
4.5  
4.5  
27  
19  
-
-
-
-
22  
24  
-
-
18  
29  
-
-
MHz  
ns  
Clock Pulse Width,  
nCP0, nCP1  
t
W
Reset Removal Time  
Reset Pulse Width  
t
4.5  
4.5  
15  
13  
-
-
-
-
19  
16  
-
-
22  
20  
-
-
ns  
ns  
REM  
t
W
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
Propagation Delay (Figure 1)  
SYMBOL CONDITIONS  
(V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX UNITS  
t
C = 50pF  
2
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
175  
35  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
220  
44  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
265  
53  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PLH,  
L
t
PHL  
nCP0 to nQ  
nCP1 to nQ  
nCP1 to nQ  
nCP1 to nQ  
0
1
2
3
C =15pF  
14  
-
L
C = 50pF  
6
30  
185  
37  
31  
245  
49  
42  
180  
36  
-
37  
230  
46  
39  
305  
61  
52  
225  
45  
-
45  
280  
56  
48  
370  
74  
63  
270  
54  
-
L
t
t
t
C = 50pF  
2
-
PLH,  
L
t
PHL  
4.5  
6
-
-
C = 50pF  
2
-
PLH,  
L
t
PHL  
4.5  
6
-
-
C = 50pF  
2
-
PLH,  
L
t
PHL  
4.5  
5
-
15  
-
6
31  
365  
73  
62  
190  
38  
-
38  
455  
91  
77  
240  
48  
-
46  
550  
110  
94  
285  
57  
-
nCP0 to nQ3  
(nQ connected to nCP1)  
t
t
C = 50pF  
2
-
PLH,  
L
t
0
PHL  
4.5  
6
-
-
MR to Q  
C = 50pF  
2
-
n
PLH,  
L
t
PHL  
4.5  
5
-
C =15pF  
16  
-
L
C = 50pF  
6
32  
41  
48  
L
6
CD74HC390, CD54HCT390, CD74HCT390  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
(V)  
PARAMETER  
SYMBOL CONDITIONS  
MIN TYP MAX  
MIN  
MAX  
95  
19  
16  
10  
-
MIN  
MAX UNITS  
Output Transition Time  
(Figure 1)  
t
, t  
C = 50pF  
2
4.5  
6
-
-
-
-
-
-
-
75  
15  
13  
10  
-
-
-
-
-
-
-
-
-
-
-
110  
22  
19  
10  
-
ns  
ns  
ns  
pF  
pF  
TLH THL  
L
-
Input Capacitance  
C
C = 50pF  
-
-
IN  
L
Power Dissipation Capacitance  
(Notes 3, 4)  
C
C =15pF  
5
28  
PD  
L
HCT TYPES  
Propagation Delay (Figure 1)  
t
t
C = 50pF  
4.5  
5
-
-
-
-
17  
-
40  
-
-
-
-
50  
-
-
-
-
60  
-
ns  
ns  
ns  
PLH,  
L
PHL  
nCP0 to nQ  
nCP1 to nQ  
C =15pF  
L
0
t
t
t
C = 50pF  
4.5  
43  
51  
65  
1
PLH,  
L
t
PHL  
nCP1 to nQ  
nCP1 to nQ  
C = 50pF  
4.5  
4.5  
-
-
-
-
55  
42  
-
-
69  
53  
-
-
83  
63  
ns  
ns  
2
PLH,  
L
t
PHL  
C = 50pF  
3
PLH,  
L
t
PHL  
C =15pF  
5
-
-
18  
-
-
-
-
-
-
-
-
ns  
ns  
L
nCP0 to nQ2  
(nQ connected to nCP1)  
t
t
C = 50pF  
4.5  
84  
105  
126  
PLH,  
L
t
0
PHL  
MR to Q  
C = 50pF  
4.5  
5
-
-
-
-
-
-
18  
-
42  
-
-
-
-
-
-
53  
-
-
-
-
-
-
63  
-
ns  
ns  
ns  
pF  
pF  
n
PLH,  
L
t
PHL  
C =15pF  
L
Output Transition  
Input Capacitance  
t
, t  
C = 50pF  
4.5  
-
15  
10  
-
19  
10  
-
22  
10  
-
TLH THL  
L
C
C =15pF  
-
IN  
L
Power Dissipation Capacitance  
(Notes 3, 4)  
C
C =15pF  
5
32  
PD  
L
NOTES:  
3. C  
is used to determine the dynamic power consumption, per multiplexer.  
2
PD  
4. P = V  
f (C  
PD  
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.  
CC  
D
CC  
i
L
i
L
Test Circuits and Waveforms  
t = 6ns  
f
t = 6ns  
t = 6ns  
t = 6ns  
r
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
PDIP  
Drawing  
5962-9098401MEA  
CD54HCT390F3A  
CD74HC390E  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
16  
16  
16  
1
1
TBD  
TBD  
A42 SNPB  
A42 SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HC390EE4  
CD74HC390M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
D
D
D
D
D
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC390M96  
CD74HC390M96E4  
CD74HC390M96G4  
CD74HC390ME4  
CD74HC390MG4  
CD74HC390MT  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC390MTE4  
CD74HC390MTG4  
CD74HCT390E  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HCT390EE4  
CD74HCT390M  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HCT390M96  
CD74HCT390M96E4  
CD74HCT390M96G4  
CD74HCT390ME4  
CD74HCT390MG4  
CD74HCT390MT  
CD74HCT390MTE4  
CD74HCT390MTG4  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
(mm)  
16  
CD74HC390M96  
CD74HCT390M96  
D
D
16  
16  
SITE 27  
SITE 27  
6.5  
6.5  
10.3  
10.3  
2.1  
2.1  
8
8
16  
16  
Q1  
Q1  
330  
16  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
CD74HC390M96  
CD74HCT390M96  
D
D
16  
16  
SITE 27  
SITE 27  
342.9  
342.9  
336.6  
336.6  
28.58  
28.58  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,  
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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Military  
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www.ti.com/military  
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logic.ti.com  
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Microcontrollers  
RFID  
power.ti.com  
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Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
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www.ti-rfid.com  
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Wireless  
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Copyright © 2007, Texas Instruments Incorporated  

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