CD74HCT4020E [TI]
High Speed CMOS Logic 14-Stage Binary Counter; 高速CMOS逻辑14级二进制计数器![CD74HCT4020E](http://pdffile.icpdf.com/pdf1/p00088/img/icpdf/CD74HCT4020_465021_icpdf.jpg)
型号: | CD74HCT4020E |
厂家: | ![]() |
描述: | High Speed CMOS Logic 14-Stage Binary Counter |
文件: | 总8页 (文件大小:44K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
CD74HC4020,
CD74HCT4020
Data sheet acquired from Harris Semiconductor
SCHS201
High Speed CMOS Logic
14-Stage Binary Counter
February 1998
at V
= 5V
Features
CC
• HCT Types
• Fully Static Operation
• Buffered Inputs
• Common Reset
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
[ /Title
(CD74
HC402
0,
CD74
HCT40
20)
/Sub-
ject
(High
Speed
CMOS
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
• Negative Edge Clocking
• Typical f
MAX
= 60 MHz at V = 5V, C = 15pF,
CC L
Description
o
T = 25 C
A
The Harris CD74HC4020 and CD74HCT4020 are 14-stage
ripple-carry binary counters. All counter stages are master-
slave flip-flops. The state of the stage advances one count
on the negative clock transition of each input pulse; a high
voltage level on the MR line resets all counters to their zero
state. All inputs and outputs are buffered.
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
PKG.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E16.3
E16.3
• HC Types
CD74HC4020E
CD74HCT4020E
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
Pinout
CD74HC4020, CD74HCT4020
(PDIP, SOIC)
TOP VIEW
Q
Q
Q
1
2
3
4
5
6
7
8
16 V
CC
12
13
14
15 Q
14 Q
13 Q
12 Q
11
10
8
Q6
Q
Q
Q
5
7
4
9
11 MR
10 CP
9
Q ‘
1
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1484.2
Copyright © Harris Corporation 1998
1
CD74HC4020, CD74HCT4020
Functional Diagram
V
CC
16
10
9
Q1’
Q4
INPUT
PULSES
7
5
Q5
4
Q6
6
Q7
13
12
14
15
1
14-STAGE
RIPPLE
COUNTER
Q8
BUFFERED
OUTPUTS
Q9
Q10
Q11
Q12
Q13
Q14
2
11
3
MASTER
RESET
8
GND
TRUTH TABLE
CP COUNT
MR
L
OUTPUT STATE
↑
↓
No Change
L
Advance to Next State
All Outputs Are Low
X
H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
CD74HC4020, CD74HCT4020
Logic Diagram
3
CD74HC4020, CD74HCT4020
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
115
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
4
CD74HC4020, CD74HCT4020
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
MR
CP
0.65
0.5
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Maximum Input Pulse
Frequency
f
2
6
-
-
-
-
-
-
-
-
-
5
25
29
100
20
17
65
13
11
-
-
-
-
-
-
-
-
-
4
20
24
120
24
20
75
15
13
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
4.5
30
35
80
16
14
50
10
9
6
2
Input Pulse Width
t
W
4.5
6
Reset Removal Time
t
2
REM
4.5
6
5
CD74HC4020, CD74HCT4020
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
80
MAX
MIN
100
20
MAX
MIN
120
24
MAX
UNITS
ns
CC
Reset Pulse Width
t
2
-
-
-
-
-
-
-
-
-
W
4.5
16
ns
6
14
17
20
ns
HCT TYPES
Maximum Input Pulse
Frequency
f
t
4.5
25
-
20
-
16
-
MHz
MAX
Input Pulse Width
Reset Recovery Time
Reset Pulse Width
t
4.5
4.5
4.5
20
10
20
-
-
-
25
13
25
-
-
-
30
15
30
-
-
-
ns
ns
ns
W
REC
t
W
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
(V)
PARAMETER
HC TYPES
SYMBOL CONDITIONS
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay Time
(Figure 1)
t
t
C = 50pF
2
-
-
140
-
175
-
210
ns
PLH,
L
PHL
CP to Q1’ Output
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11
-
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
42
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
C =15pF
L
C = 50pF
6
24
75
15
-
30
95
19
-
36
110
22
-
L
Q to Q + 1
t
t
C = 50pF
2
-
n
n
PLH,
L
t
PHL
4.5
5
-
C =15pF
6
-
L
C = 50pF
6
13
170
34
-
16
215
43
-
19
255
51
-
L
MR to Q
C = 50pF
2
-
n
PLH,
L
t
PHL
4.5
5
-
14
-
6
29
75
15
13
10
-
37
95
19
16
10
-
43
110
22
19
10
-
Output Transition Time
(Figure 1)
t
, t
C = 50pF
2
-
TLH THL
L
4.5
6
-
-
Input Capacitance
C
C = 50pF
-
-
IN
L
Power Dissipation Capaci-
tance
C
C =15pF
5
30
PD
L
(Notes 4, 5)
HCT TYPES
Propagation Delay Time
(Figure 2)
t
t
C = 50pF
4.5
-
-
40
-
50
-
60
ns
PLH,
L
PHL
CP to Q1’ Output
C =15pF
5
4.5
5
-
-
-
-
-
17
-
-
15
-
-
-
-
-
-
-
19
-
-
-
-
-
-
-
22
-
ns
ns
ns
ns
ns
L
Q to Q + 1
t
t
C = 50pF
L
n
n
PLH,
t
PHL
C =15pF
6
L
MR to Q
C = 50pF
4.5
5
-
40
-
50
-
60
-
n
PLH,
L
t
PHL
C =15pF
17
L
6
CD74HC4020, CD74HCT4020
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
Output Transition
MIN TYP MAX
MIN
MAX
19
10
-
MIN
MAX
22
10
-
UNITS
ns
t
, t C = 50pF
4.5
-
-
-
-
-
-
15
10
-
-
-
-
-
-
-
TLH THL
L
Input Capacitance
C
C =15pF
pF
IN
L
Power Dissipation Capaci-
tance
C
C =15pF
5
30
pF
PD
L
(Notes 4, 5)
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per package.
2
5. P = V
CC
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
i
L
i
L
Test Circuits and Waveforms
I
t
+ t
WH
=
WL
I
t C = 6ns
fC
L
r
L
t
+ t
=
WL
WH
t C = 6ns
t C
f
L
f
t C
f
L
CL
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
7
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明