CD74HCT4020MG4 [TI]
High Speed CMOS Logic 14-Stage Binary Counter 16-SOIC -55 to 125;
| 型号： | CD74HCT4020MG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 14-Stage Binary Counter 16-SOIC -55 to 125 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总17页 (文件大小：478K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC4020, CD74HC4020,
CD54HCT4020, CD74HCT4020
Data sheet acquired from Harris Semiconductor
SCHS201C
High-Speed CMOS Logic
14-Stage Binary Counter
February 1998 - Revised October 2003
Features
Description
• Fully Static Operation
• Buffered Inputs
The ’HC4020 and ’HCT4020 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flip-
flops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
[ /Title
(CD74
HC402
0,
CD74
HCT40
20)
/Sub-
ject
(High
Speed
CMOS
• Common Reset
• Negative Edge Clocking
• Fanout (Over Temperature Range)
Ordering Information
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
TEMP. RANGE
o
PART NUMBER
CD54HC4020F3A
CD54HCT4020F3A
CD74HC4020E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
CD74HC4020M
- 2V to 6V Operation
CD74HC4020MT
CD74HC4020M96
CD74HCT4020E
CD74HCT4020M
CD74HCT4020MT
CD74HCT4020M96
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC4020, CD54HCT4020
(CERDIP)
CD74HC4020, CD74HCT4020
(PDIP, SOIC)
TOP VIEW
Q
Q
Q
1
2
3
4
5
6
7
8
16 V
CC
12
13
14
15 Q
14 Q
13 Q
12 Q
11
10
8
Q6
Q
Q
Q
5
7
4
9
11 MR
10 CP
9
Q ‘
1
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
Functional Diagram
V
CC
16
10
9
Q1’
Q4
INPUT
PULSES
7
5
Q5
4
Q6
6
Q7
13
12
14
15
1
14-STAGE
RIPPLE
COUNTER
Q8
BUFFERED
OUTPUTS
Q9
Q10
Q11
Q12
Q13
Q14
2
11
3
MASTER
RESET
8
GND
TRUTH TABLE
CP COUNT
MR
L
OUTPUT STATE
↑
↓
No Change
L
Advance to Next State
All Outputs Are Low
X
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
CD54/74HC4020, CD54/74HCT4020
Logic Diagram
3
CD54HC4020, CD74HC4020, CD54HC4020, CD74HCT4020
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
4
CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
MR
CP
0.65
0.5
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Maximum Input Pulse
Frequency
f
2
6
-
-
-
-
-
-
5
25
29
100
20
17
-
-
-
-
-
-
4
20
24
120
24
20
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
30
35
80
16
14
6
2
Input Pulse Width
t
W
4.5
6
ns
ns
5
CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
50
10
9
MAX
MIN
65
MAX
MIN
75
MAX
UNITS
ns
CC
Reset Removal Time
t
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
REM
4.5
13
15
ns
6
2
11
13
ns
Reset Pulse Width
t
80
16
14
100
20
120
24
ns
W
4.5
6
ns
17
20
ns
HCT TYPES
Maximum Input Pulse
Frequency
f
t
4.5
25
-
20
-
16
-
MHz
MAX
Input Pulse Width
Reset Recovery Time
Reset Pulse Width
t
4.5
4.5
4.5
20
10
20
-
-
-
25
13
25
-
-
-
30
15
30
-
-
-
ns
ns
ns
W
REC
t
W
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
(V)
PARAMETER
HC TYPES
SYMBOL CONDITIONS
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay Time
(Figure 1)
t
t
C = 50pF
2
-
-
140
-
175
-
210
ns
PLH,
L
PHL
CP to Q1’ Output
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11
-
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
42
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
C =15pF
L
C = 50pF
6
24
75
15
-
30
95
19
-
36
110
22
-
L
Q to Q + 1
t
t
C = 50pF
2
-
n
n
PLH,
L
t
PHL
4.5
5
-
C =15pF
6
-
L
C = 50pF
6
13
170
34
-
16
215
43
-
19
255
51
-
L
MR to Q
C = 50pF
2
-
n
PLH,
L
t
PHL
4.5
5
-
14
-
6
29
75
15
13
10
-
37
95
19
16
10
-
43
110
22
19
10
-
Output Transition Time
(Figure 1)
t
, t
C = 50pF
2
-
TLH THL
L
4.5
6
-
-
Input Capacitance
C
C = 50pF
-
-
IN
L
Power Dissipation Capaci-
tance
C
C =15pF
5
30
PD
L
(Notes 3, 4)
6
CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
HCT TYPES
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay Time
(Figure 2)
t
t
C = 50pF
4.5
-
-
40
-
50
-
60
ns
PLH,
L
PHL
CP to Q1’ Output
C =15pF
5
4.5
5
-
-
-
-
-
-
-
-
17
-
-
15
-
-
-
-
-
-
-
-
-
-
19
-
-
-
-
-
-
-
-
-
-
22
-
ns
ns
ns
ns
ns
ns
pF
pF
L
Q to Q + 1
t
t
C = 50pF
L
n
n
PLH,
t
PHL
C =15pF
6
L
MR to Q
C = 50pF
4.5
5
-
40
-
50
-
60
-
n
PLH,
L
t
PHL
C =15pF
17
-
L
Output Transition
Input Capacitance
t
, t
C = 50pF
4.5
-
15
10
-
19
10
-
22
10
-
TLH THL
L
C
C =15pF
-
IN
L
Power Dissipation Capaci-
tance
C
C =15pF
5
30
PD
L
(Notes 3, 4)
NOTES:
3. C
is used to determine the dynamic power consumption, per package.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
I
t
+ t
WH
=
WL
I
t C = 6ns
fC
L
r
L
t
+ t
=
WL
WH
t C = 6ns
t C
f
L
f
t C
f
L
CL
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
7
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
5962-8945801EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8945801EA
CD54HCT4020F3A
CD54HC4020F
ACTIVE
ACTIVE
CDIP
CDIP
J
J
16
16
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
CD54HC4020F
CD54HC4020F3A
8500301EA
CD54HC4020F3A
CD54HCT4020F3A
CD74HC4020E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
SOIC
J
16
16
16
16
16
16
16
16
16
16
16
16
16
16
1
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
5962-8945801EA
CD54HCT4020F3A
N
N
D
D
D
D
D
D
N
D
D
D
D
25
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CD74HC4020E
CD74HC4020E
HC4020M
CD74HC4020EE4
CD74HC4020M
25
Pb-Free
(RoHS)
N / A for Pkg Type
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
CD74HC4020M96
CD74HC4020M96E4
CD74HC4020M96G4
CD74HC4020MG4
CD74HC4020MT
CD74HCT4020E
2500
2500
2500
40
Green (RoHS
& no Sb/Br)
HC4020M
Green (RoHS
& no Sb/Br)
HC4020M
Green (RoHS
& no Sb/Br)
HC4020M
Green (RoHS
& no Sb/Br)
HC4020M
250
25
Green (RoHS
& no Sb/Br)
HC4020M
Pb-Free
(RoHS)
CD74HCT4020E
HCT4020M
HCT4020M
HCT4020M
HCT4020M
CD74HCT4020M
CD74HCT4020M96
CD74HCT4020M96G4
CD74HCT4020MG4
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2500
2500
40
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
CD74HCT4020MT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4020M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4020, CD54HCT4020, CD74HC4020, CD74HCT4020 :
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Catalog: CD74HC4020, CD74HCT4020
•
Military: CD54HC4020, CD54HCT4020
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CD74HC4020M96
CD74HCT4020M96
SOIC
SOIC
D
D
16
16
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
10.3
10.3
2.1
2.1
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CD74HC4020M96
CD74HCT4020M96
SOIC
SOIC
D
D
16
16
2500
2500
333.2
333.2
345.9
345.9
28.6
28.6
Pack Materials-Page 2
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