CDC208NSR [TI]

5V 双路 1:4 时钟驱动器 | NS | 20 | -40 to 85;
CDC208NSR
型号: CDC208NSR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

5V 双路 1:4 时钟驱动器 | NS | 20 | -40 to 85

时钟 驱动 时钟驱动器
文件: 总10页 (文件大小:159K)
中文:  中文翻译
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CDC208  
DUAL 1-LINE TO 4-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS109F – APRIL 1990 – REVISED OCTOBER 1998  
DW PACKAGE  
(TOP VIEW)  
Low-Skew Propagation Delay  
Specifications for Clock-Driver  
Applications  
1Y2  
1Y3  
1Y4  
GND  
GND  
GND  
GND  
2Y1  
1Y1  
1A  
1OE1  
1OE2  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
TTL-Compatible Inputs and  
CMOS-Compatible Outputs  
Flow-Through Architecture Optimizes  
PCB Layout  
V
CC  
Center-Pin V  
and GND Pin  
CC  
V
CC  
Configurations Minimize High-Speed  
Switching Noise  
2A  
2OE1  
2OE2  
2Y4  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
2Y2  
2Y3  
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic  
Small-Outline (DW)  
description  
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew  
for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each  
circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level  
independent of the signal on the respective A input.  
Skew parameters are specified for a reduced temperature and voltage range common to many applications.  
The CDC208 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLES  
INPUTS  
OUTPUTS  
1OE1 1OE2  
1A  
L
1Y1  
L
1Y2  
L
1Y3  
L
1Y4  
L
L
L
L
L
H
X
H
H
H
H
L
H
L
L
L
L
L
H
H
X
H
H
H
H
H
X
Z
Z
Z
Z
INPUTS  
OUTPUTS  
2OE1 2OE2  
2A  
L
2Y1  
L
2Y2  
L
2Y3  
L
2Y4  
L
L
L
L
L
H
X
H
H
H
H
L
H
L
L
L
L
L
H
H
X
H
H
H
H
H
X
Z
Z
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CDC208  
DUAL 1-LINE TO 4-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS109F – APRIL 1990 – REVISED OCTOBER 1998  
logic symbol  
X/Y  
1
18  
1
2
3
V4  
1
1OE1  
1OE2  
17  
G5  
EN  
2
20  
1
4, 5  
1Y1  
1Y2  
1Y3  
1Y4  
4, 5  
4, 5  
4, 5  
19  
2
1A  
3
13  
12  
8
9
2Y1  
2Y2  
2Y3  
2Y4  
2OE1  
2OE2  
10  
11  
14  
2A  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
logic diagram (positive logic)  
18  
1OE1  
20  
1
1Y1  
1Y2  
17  
1OE2  
2
3
1Y3  
1Y4  
19  
1A  
13  
2OE1  
8
9
2Y1  
2Y2  
12  
2OE2  
10  
11  
2Y3  
2Y4  
14  
2A  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CDC208  
DUAL 1-LINE TO 4-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS109F – APRIL 1990 – REVISED OCTOBER 1998  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
+ 0.5 V  
+ 0.5 V  
I
CC  
CC  
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
IK  
I
I
CC  
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
Continuous current through V  
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA  
A
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.  
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology  
Data Book, literature number SCBD002B.  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
V
V
V
V
V
Supply voltage  
4.5  
2
5
5.5  
CC  
High-level input voltage  
Low-level input voltage  
Input voltage  
V
IH  
0.8  
V
IL  
0
V
V
I
CC  
I
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Input clock frequency  
Operating free-air temperature  
24  
24  
mA  
mA  
ns/V  
MHz  
°C  
OH  
OL  
t/v  
0
10  
f
60  
clock  
T
40  
85  
A
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CDC208  
DUAL 1-LINE TO 4-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS109F – APRIL 1990 – REVISED OCTOBER 1998  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
PARAMETER  
TEST CONDITIONS  
V
MIN  
MAX  
UNIT  
CC  
MIN  
4.4  
TYP  
MAX  
4.5 V  
5.5 V  
4.5 V  
5.5 V  
5.5 V  
4.5 V  
5.5 V  
4.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
4.4  
5.4  
I
= 50 µA  
OH  
5.4  
V
3.94  
4.94  
3.8  
V
OH  
OL  
I
I
I
= 24 mA  
= 75 mA  
= 50 µA  
OH  
OH  
OL  
4.8  
3.85  
0.1  
0.1  
0.1  
0.1  
V
0.36  
0.36  
0.44  
0.44  
1.65  
±1  
V
I
I
= 24 mA  
OL  
= 75 mA  
OL  
I
I
I
V = V  
or GND  
±0.1  
±0.5  
8
µA  
µA  
µA  
I
I
CC  
V
= V  
or GND  
±5  
OZ  
CC  
O
CC  
V = V  
or GND,  
I
O
= 0  
80  
I
CC  
One input at 3.4 V,  
Other inputs at V  
I  
CC  
5.5 V  
0.9  
1
mA  
or GND  
CC  
or GND  
C
C
V = V  
5 V  
5 V  
4
pF  
pF  
i
I
CC  
= V or GND  
CC  
V
10  
o
O
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.  
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V  
.
CC  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CDC208  
DUAL 1-LINE TO 4-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS109F – APRIL 1990 – REVISED OCTOBER 1998  
switching characteristics over recommended operating free-air temperature range,  
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)  
V
CC  
T
A
= 25°C  
TYP  
8.5  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
MIN  
MAX  
UNIT  
ns  
MIN  
5.3  
3.6  
4.7  
4.4  
4.4  
5
MAX  
10.9  
11  
t
t
t
t
t
t
t
t
5.3  
3.6  
4.7  
4.4  
4.4  
5
11.7  
11.5  
12.8  
12.4  
12.4  
14.9  
10.2  
9.9  
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
1A and 2A  
Any Y  
Any Y  
Any Y  
Any Y  
7.7  
8.5  
11.7  
11.3  
11.3  
13.3  
9.3  
1OE1, 1OE2, and  
2OE1, 2OE2  
ns  
8.4  
1OE2 or 2OE2  
1OE1 or 2OE1  
1OE2 or 2OE2  
1OE1 or 2OE1  
8.1  
ns  
9.6  
4.2  
5.4  
7.4  
4.2  
5.4  
ns  
7.5  
9.2  
switching characteristics, V  
= 5 V ± 0.25 V, T = 25°C to 70°C (see Note 3 and Figures 1 and 2)  
A
CC  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
MIN  
MAX  
UNIT  
t
t
t
6.6  
6.6  
10.2  
9.8  
1
PLH  
PHL  
sk(o)  
1A and 2A  
1A and 2A  
Any Y  
Any Y  
ns  
ns  
NOTE 3: All specifications are valid only for all outputs switching simultaneously and in phase.  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
= 50 pF, f = 1 MHz  
TYP  
96  
UNIT  
Outputs enabled  
Outputs disabled  
C
Power dissipation capacitance per bank  
C
pF  
pd  
L
12  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CDC208  
DUAL 1-LINE TO 4-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS109F – APRIL 1990 – REVISED OCTOBER 1998  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
Open  
GND  
TEST  
S1  
Open  
2 × V  
CC  
GND  
S1  
t
t
t
/t  
500 Ω  
PLH PHL  
From Output  
Under Test  
/t  
PLZ PZL  
/t  
PHZ PZH  
C
= 50 pF  
L
500 Ω  
(see Note A)  
3 V  
0 V  
Output  
Control  
(low-level  
enabling)  
(see Note A)  
LOAD CIRCUIT FOR OUTPUTS  
1.5 V  
1.5 V  
t
PZL  
t
PLZ  
3 V  
0 V  
V  
CC  
Input  
(see Note B)  
Output  
Waveform 1  
1.5 V  
1.5 V  
50% V  
CC  
20% V  
CC  
CC  
S1 at 2 × V  
(see Note C)  
CC  
V
OL  
t
PLH  
t
PHZ  
t
PHL  
t
PZH  
Output  
Waveform 2  
V
OH  
V
OH  
80% V  
Output  
50% V  
50% V  
S1 at 2 × V  
(see Note C)  
50% V  
CC  
CC  
V
CC  
CC  
OL  
0 V  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
NOTES: A.  
C
L
includes probe and jig capacitance.  
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 3 ns, t 3 ns.  
O
r
f
For testing pulse duration: t = t = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.  
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
Figure 1. Load Circuit and Voltage Waveforms  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CDC208  
DUAL 1-LINE TO 4-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS109F – APRIL 1990 – REVISED OCTOBER 1998  
PARAMETER MEASUREMENT INFORMATION  
1A, 2A  
1Y1  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH1  
PLH2  
PLH3  
PLH4  
PLH5  
PLH6  
PLH7  
PLH8  
PHL1  
PHL2  
PHL3  
PHL4  
PHL5  
PHL6  
PHL7  
PHL8  
1Y2  
1Y3  
1Y4  
2Y1  
2Y2  
2Y3  
2Y4  
NOTE A: Output skew, t  
, is calculated as the greater of:  
sk(o)  
– The difference between the fastest and slowest of t  
– The difference between the fastest and slowest of t  
(n = 1, 2, . . . , 8)  
(n = 1, 2, . . . , 8)  
PLHn  
PHLn  
Figure 2. Waveforms for Calculation of t  
sk(o)  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CDC208  
DUAL 1-LINE TO 4-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS109F – APRIL 1990 – REVISED OCTOBER 1998  
MECHANICAL INFORMATION  
DW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
16 PIN SHOWN  
0.050 (1,27)  
16  
0.020 (0,51)  
0.014 (0,35)  
0.010 (0,25)  
M
9
0.419 (10,65)  
0.400 (10,15)  
0.010 (0,25) NOM  
0.299 (7,59)  
0.293 (7,45)  
Gage Plane  
0.010 (0,25)  
1
8
0°8°  
0.050 (1,27)  
0.016 (0,40)  
A
Seating Plane  
0.004 (0,10)  
0.012 (0,30)  
0.004 (0,10)  
0.104 (2,65) MAX  
PINS **  
16  
20  
24  
0.610  
DIM  
0.410  
0.510  
A MAX  
(10,41) (12,95) (15,49)  
0.400  
0.500  
0.600  
A MIN  
(10,16) (12,70) (15,24)  
4040000/D 02/98  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MS-013  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
17-Nov-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SSOP  
SOIC  
Drawing  
CDC208DBLE  
CDC208DW  
OBSOLETE  
ACTIVE  
DB  
20  
20  
TBD  
Call TI  
Call TI  
DW  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CDC208DWG4  
CDC208DWR  
CDC208DWRG4  
CDC208N  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
PDIP  
DW  
DW  
DW  
N
20  
20  
20  
20  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
ACTIVE  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
OBSOLETE  
TBD  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
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information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
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CDC209-7DW

DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS
TI

CDC209-7DWR

DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS
TI

CDC209DBLE

DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS
TI

CDC209DW

DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS
TI

CDC209DWR

DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS
TI

CDC209N

DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS
TI

CDC222PAH

FIFTEEN DISTRIBUTED-OUTPUT CLOCK DRIVER|ECL100|TQFP|52PIN|PLASTIC
ETC

CDC2351

1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
TI

CDC2351-EP

1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
TI

CDC2351-Q1

具有三态输出的汽车类 1 线路至 10 线路时钟驱动器
TI