CDC2510BPWRG4 [TI]

3.3-V Phase-Lock Loop Clock Driver 24-TSSOP;


型号：	CDC2510BPWRG4
厂家：	TEXAS INSTRUMENTS
描述：	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 驱动光电二极管逻辑集成电路
文件：	总14页 (文件大小：638K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ꢕ

SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

PW PACKAGE

(TOP VIEW)

Use CDCVF2510A as a Replacement for

this Device

Designed to Meet PC SDRAM Registered

DIMM Specification

AGND

CLK

Spread Spectrum Clock Compatible

1Y0

1Y1

1Y2

GND

1Y3

Operating Frequency 25 MHz to 125 MHz

1Y9

1Y8

GND

1Y7

1Y6

tPhase Error Minus Jitter at 66 MHz to

100 MHz Is 150 ps

Jitter (pk − pk) at 66 MHz to 100 MHz is

80ps

1Y4

Jitter (cyc − cyc) at 66 MHz to 100 MHz is

|100 ps|

15 1Y5

Available in Plastic 24-Pin TSSOP

FBOUT

FBIN

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to One Bank of

Ten Outputs

Separate Output Enable for Each Output

Bank

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3-V

description

The CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CDC2510B operates at 3.3-V V . It also

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output

enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input

is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510B does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510B requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢕ

SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

description (continued)

The CDC2510B is characterized for operation from 0°C to 70°C.

For application information, see the High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) (literature number SCAA039) application reports.

FUNCTION TABLE

INPUTS

CLK

OUTPUTS

FBOUT

(0:9)

functional block diagram

1Y0

1Y1

1Y2

1Y3

1Y4

1Y5

1Y6

1Y7

1Y8

CLK

PLL

FBIN

1Y9

FBOUT

AVAILABLE OPTIONS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

PACKAGE

SMALL OUTLINE

(PW)

0°C to 70°C

CDC2510BPWR

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

Clock input. CLK provides the clock signal to be distributed by the CDC2510B clock driver. CLK is

used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK

must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is

powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock

the feedback signal to its reference signal.

CLK

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to

FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is

nominally zero phase error between CLK and FBIN.

FBIN

Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are

disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same

frequency as CLK.

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as

CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has

an integrated 25-Ω series-damping resistor.

FBOUT

1Y (0:9)

3, 4, 5, 8, 9

15, 16, 17, 20,

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via

the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.

Each output has an integrated 25-Ω series-damping resistor.

Analog power supply. AV

provides the power reference for the analog circuitry. In addition, AV

Power

can be used to bypass the PLL for test purposes. When AV

and CLK is buffered directly to the device outputs.

is strapped to ground, PLL is bypassed

AGND

Ground Analog ground. AGND provides the ground reference for the analog circuitry.

Power Power supply

Ground Ground

GND

2, 10, 14, 22

6, 7, 18, 19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, AV

Supply voltage range, V , AV

Input voltage range, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

Voltage range applied to any output in the high

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV

< V

+0.7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

or low state, V (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Output clamp current, I

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Continuous current through each V

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Maximum power dissipation at T = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W

stg

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. AV

must not exceed V .

2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This value is limited to 4.6 V maximum.

4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data

Book, literature number SCBD002.

recommended operating conditions (see Note 5)

MIN

MAX

UNIT

Supply voltage, V , AV

CC CC

3.6

High-level input voltage, V

Low-level input voltage, V

0.8

Input voltage, V

High-level output current, I

−12

°C

Low-level output current, I

Operating free-air temperature, T

NOTE 5: Unused inputs must be held high or low to prevent them from floating.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

‡

PARAMETER

TEST CONDITIONS

AV , V

CC CC

MIN TYP

MAX

UNIT

I = −18 mA

3 V

−1.2

= −100 µA

= −12 mA

= −6 mA

= 100 µA

= 12 mA

= 6 mA

MIN to MAX

3 V

−0.2

2.1

3 V

2.4

MIN to MAX

3 V

0.2

0.8

0.55

3 V

V = V

or GND

or GND,

3.6 V

µA

V = V

I = 0, Outputs: low or high

3.6 V

∆I

One input at V

− 0.6 V,

Other inputs at V

or GND

3.3 V to 3.6 V

3.3 V

500

V = V

or GND

= V

O CC

3.3 V

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

For I of AV and I vs Frequency (see Figures 7 and 8).

CC CC CC

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

125

60%

UNIT

Clock frequency

MHz

clk

Input clock duty cycle

40%

†

Stabilization time

†

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,

and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under

SSC application.

switching characteristics over recommended ranges of supply voltage and operating free-air

‡

temperature, C = 30 pF (see Note 6 and Figures 1 and 2)

, AV

= 3.3 V

0.165 V

, AV = 3.3 V

FROM

(INPUT)/CONDITION

(OUTPUT)

0.3 V

PARAMETER

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

t , − jitter

phase error

(see Notes 7 and 8,

Figures 3, 4, and 5)

CLKIN↑ = 66 MHz to 100 MHz

FBIN↑

−150

150

−200

200

Any Y or FBOUT

200

sk(o)

Jitter

(see Figure 6)

−80

(pk-pk)

Clkin = 66 MHz to 100 MHz

F(clkin > 60 MHz)

Jitter

(See Figure 6)

(cycle-cycle)

Any Y or FBOUT

|100|

55%

Duty cycle reference

(see Figure 4)

45%

Any Y or FBOUT

1.3

1.7

1.9

2.5

0.8

1.2

2.1

2.7

‡

These parameters are not production tested.

The t

specification is only valid for equal loading of all outputs.

sk(o)

NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

7. This is considered as static phase error.

8. Phase error does not include jitter. The total phase error is −230 ps to 230 ps for the 5% V

range.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢕ

SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

Input

50% V

From Output

Under Test

2 V

0.4 V

2 V

Output

500 W

50% V

0.4 V

30 pF

LOAD CIRCUIT FOR OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NOTES: A.

includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.

C. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

CLKIN

FBIN

phase error

FBOUT

Any Y

sk(o)

Any Y

sk(o)

Figure 2. Phase Error and Skew Calculations

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

PHASE ADJUSTMENT SLOPE AND PHASE ERROR

LOAD CAPACITANCE

250

= 3.3 V

= 100 MHz

200

150

100

= 30pF

= 25°C

Phase Error

Phase Error Measured

from CLK to Y

−10

−20

−30

−50

−100

−150

Phase Adjustment Slope

−40

−50

−200

−250

45 50

10 15 20 25 30 35 40

CLF − Lumped Feedback Capacitance at FBIN − pF

Figure 3

PHASE ERROR

CLOCK FREQUENCY

400

= 3.3 V

CLY = CLF = 30 pF

= 25°C

300

200

Phase Error Measured

from CLK to FBIN

100

−100

35 45

85 95 105 115 125

− Clock Frequency − MHz

Figure 4

NOTES: A. CLY = Lumped capacitive load at Y

B. CLF = Lumped feedback capacitance at FBIN

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SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

PHASE ERROR

JITTER

CLOCK FREQUENCY

SUPPLY VOLTAGE

400

350

300

250

400

350

300

= 100 MHz

= 3.3 V

= 25°C

CLY = CLF = 30 pF

Phase Error Measured

from CLK to FBIN

= 25°C

250

200

150

200

150

100

Peak to Peak

100

−50

Cycle to Cycle

−100

35 45

65 75

85 95 105 115 125

2.9

3.0

3.1 3.2

3.3

3.4

3.5

3.6 3.7

− Clock Frequency − MHz

− Supply Voltage − V

Figure 5

Figure 6

SUPPLY CURRENT

ANALOG SUPPLY CURRENT

CLOCK FREQUENCY

250

200

150

100

= 3.6 V

= 25°C

= 3.6 V

CLY = CLF = 30 pF

Bias = 0/3 V

CLY = CLF = 30 pF

= 25°C

100

120

140

100

120

140

− Clock Frequency − MHz

clk

− Clock Frequency − MHz

Figure 7

Figure 8

NOTES: A. CLY = Lumped capacitive load at Y

B. CLF = Lumped feedback capacitance at FBIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

16-Jul-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

CDC2510BPWR

NRND

TSSOP

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Samples Not Available

CDC2510BPWRG4

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Samples Not Available

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDC2510BPWR

TSSOP

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 24

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

CDC2510BPWR

2000

Pack Materials-Page 2

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and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

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