CDCE706_10_技术文档

CDCE706

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PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1

FEATURES

TERMINAL ASSIGNMENT

•

High-Performance 3:6 PLL-Based Clock

Synthesizer/Multiplier/Divider

PW Package

(Top View)

•

User-Programmable PLL Frequencies

EEPROM Programming Without the Need to

Apply High Programming Voltage

S0/A0/CLK_SEL

S1/A1

1

2

3

4

5

6

7

8

9

10

Y5

20

19

18

17

16

15

14

13

12

11

Y4

•

Easy In-Circuit Programming via SMBus Data

Interface

V_CC

V_CCOUT2

GND

Y3

CLK_IN0

Wide PLL Divider Ratio Allows 0-ppm Output

Clock Error

CLK_IN1

V_CC

Y2

V_CCOUT1

Clock Inputs Accept a Crystal, a Single-Ended

LVCMOS, or a Differential Input Signal

GND

Y1

SDATA

SCLOCK

Accepts Crystal Frequencies From 8 MHz to

54 MHz

Y0

P0087-01

Accepts LVCMOS or Differential Input

Frequencies up to 200 MHz

DESCRIPTION

Two Programmable Control Inputs [S0/S1,

A0/A1] for User-Defined Control Signals

The CDCE706 is one of the smallest and most

powerful PLL synthesizer/multiplier/dividers available

today. Despite its small physical outline, the

CDCE706 is very flexible. It has the capability to

produce an almost independent output frequency

from a given input frequency.

Six LVCMOS Outputs With Output Frequencies

up to 300 MHz

LVCMOS Outputs Can Be Programmed for

Complementary Signals

Free Selectable Output Frequency via

Programmable Output Switching Matrix [6×6]

Including 7-Bit Post-Divider for Each Output

The input frequency can be derived from an

LVCMOS, differential input clock, or single crystal.

The appropriate input waveform can be selected via

the SMBus data interface controller.

•

PLL Loop Filter Components Integrated

Low Period Jitter (Typically 60 ps)

To achieve an independent output frequency, the

reference divider M and the feedback divider N for

each PLL can be set to values from 1 to 511 for the

M-divider and from 1 to 4095 for the N-divider. The

PLL-VCO (voltage controlled oscillator) frequency

then is routed from the programmable output

switching matrix to any of the six outputs. The

switching matrix includes an additional 7-bit

post-divider (1 to 127) and an inverting logic for each

output.

Features Spread-Spectrum Clocking (SSC) for

Lowering System EMI

•

Programmable Output Slew-Rate Control

(SRC) for Lowering System EMI

•

3.3-V Device Power Supply

Industrial Temperature Range –40°C to 85°C

Development and Programming Kit for Easy

PLL Design and Programming (TI ClockPro

Software)

The deep M/N divider ratio allows the generation of

zero-ppm clocks from any reference input frequency

(e.g., 27 MHz).

•

Packaged in 20-Pin TSSOP

The CDCE706 includes three PLLs; of those, one

supports spread-spectrum clocking (SSC). PLL1,

PLL2, and PLL3 are designed for frequencies up to

300 MHz and optimized for zero-ppm applications

with wide divider factors.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCE706

SCAS815I–OCTOBER 2005–REVISED NOVEMBER 2008........................................................................................................................................... www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

PLL2 also supports center- and down-spread-spectrum clocking (SSC). This is a common technique to reduce

electromagnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically

adjusted to achieve the high stability and optimized jitter transfer characteristic of the PLL.

The device supports nonvolatile EEPROM programming for easily customized application. The device is

preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different

application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different

device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic

control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE706 has three power-supply pins, V_CC, V_CCOUT1, and V_CCOUT2. V_CCis the power supply for the device.

It operates from a single 3.3-V supply voltage. V_CCOUT1and V_CCOUT2are the power supply pins for the outputs.

V_CCOUT1supplies the outputs Y0 and Y1, and V_CCOUT2supplies the outputs Y2, Y3, Y4, and Y5. Both output

supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE706 is characterized for operation from –40°C to 85°C.

2

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FUNCTIONAL BLOCK DIAGRAM

V_CC

V_CCOUT1

GND

PLL Bypass

Output Switch Matrix

VCO1 Bypass

PLL1

MUX

Prg. 9-Bit

Divider M

LV

CMOS

Y0

Y1

PFD

Filter

VCO

Prg. 12-Bit

Divider N

LV

CMOS

CLK_IN0

CLK_IN1

VCO2 Bypass

XO

or

2 LVCMOS

or

Differential

Input

PLL2

w/ SSC

LV

CMOS

Y2

Y3

Prg. 9-Bit

Divider M

PFD

Filter

VCO

MUX

Prg. 12-Bit

Divider N

LV

CMOS

SSC

On/Off

S0/A0/CLK_SEL

LV

CMOS

EEPROM

LOGIC

VCO3 Bypass

Y4

Y5

S1/A1

SDATA

PLL3

MUX

Prg. 9-Bit

Divider M

SMBUS

LOGIC

SCLOCK

PFD

Filter

VCO

LV

CMOS

Factory Prg.

Prg. 12-Bit

Divider N

V_CCOUT2

GND

B0334-01

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OUTPUT SWITCH MATRIX

5 x 6 - Switch A

6 x 6 - Switch B

7-Bit Divider

P0

Y0

Y1

Y2

Y3

Y4

Y5

Input CLK

(PLL Bypass)

P1

P2

P3

P4

PLL1

PLL2

Non-SSC

PLL2

w/ SSC

P5

PLL3

Programming

B0335-01

TERMINAL FUNCTIONS

TERMINAL

TSSOP20

I/O

DESCRIPTION

NAME

NO.

Dependent on SMBus settings, CLK_IN0 is the crystal-oscillator input and can also be used as an

LVCMOS input or as positive differential signal inputs.

CLK_IN0

5

I

Depending on SMBus settings, CLK_IN1 serves as the crystal oscillator output or can be the

second LVCMOS input or the negative differential signal input.

CLK_IN1

GND

6

I/O

4, 8, 13, 17

Ground

User-programmable control input S0 (PLL bypass or power-down mode) or A0 (address bit 0), or

CLK_SEL (selects one of two LVCMOS clock inputs), dependent on the SMBus settings; LVCMOS

inputs; internal pullup 150 kΩ

S0, A0,

CLK_SEL

1

I

User-programmable control input S1 (output enable/disable or all output low), A1 (address bit 1),

dependent on the SMBus settings; LVCMOS inputs; internal pullup 150 kΩ

S1, A1

2

I

SCLOCK

SDATA

V_CC

10

9

I

Serial control clock input for SMBus controller; LVCMOS input

Serial control data input/output for SMBus controller; LVCMOS input

3.3-V power supply for the device

I/O

3, 7

14

18

Power

V_CCOUT1

V_CCOUT2

Power supply for outputs Y0, Y1

Power supply for outputs Y2, Y3, Y4, Y5

11, 12, 15,

16, 19, 20

Y0 to Y5

O

LVCMOS outputs

4

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

–0.5 to 4.6

–0.5 to V_CC+ 0.5

±20

UNIT

V

V_CCSupply voltage range

V_I

Input voltage range⁽²⁾

V

V_O

I_I

Output voltage range⁽²⁾

Input current (V_I< 0, V_I> V_CC

Continuous output current

Storage temperature range

V

)

mA

°C

I_O

±50

T_stg

T_J

–65 to 150

125

Maximum junction temperature

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

PACKAGE THERMAL RESISTANCE

for TSSOP20 (PW) Package⁽¹⁾

PARAMETER

Thermal resistance, junction-to-ambient

Thermal resistance, junction-to-case

AIRFLOW (LFM)

AIRFLOW (m/s)

°C/W

66.3

59.3

56.3

51.9

19.7

0

150

250

500

0.762

1.27

2.54

θ_JA

θ_JC

(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

3

NOM

MAX

3.6

UNIT

V_CC

Device supply voltage

3.3

V

(1)

V_CCOUT1

V_CCOUT2

V_IL

Output Y0, Y1 supply voltage

Output Y2, Y3, Y4, Y5 supply voltage

Low-level input voltage, LVCMOS

High-level input voltage, LVCMOS

Input voltage threshold, LVCMOS

Input voltage range, LVCMOS

Differential input voltage

2.3

3.6

V

0.3 V_CC

V

V_IH

0.7 V_CC

V

V_Ithresh

V_I

0.5 V_CC

V

0

0.1

0.2

3.6

V

|V_ID

|

V

V_IC

Common-mode for differential input voltage

Output current (3.3 V)

V_CC– 0.6

V

I_OH/I_OL

C_L

±6

±4

25

85

mA

pF

°C

Output current (2.5 V)

Output load, LVCMOS

T_A

Operating free-air temperature

–40

(1) The minimum output voltage can be down to 1.8 V. See the CDCx706/x906 Termination and Signal Integrity Guidelines application

report (SCAA080) for more information.

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RECOMMENDED CRYSTAL SPECIFICATIONS

MIN NOM

MAX

54

UNIT

MHz

Ω

f_Xtal

ESR Effective series resistance⁽¹⁾⁽²⁾

C_INInput capacitance CLK_IN0 and CLK_IN1

Crystal input frequency range (fundamental mode)

8

27

15

60

3

pF

(1) For crystal frequencies above 50 MHz, the effective series resistor should not exceed 50 Ω to assure stable start-up condition.

(2) For maximum power handling (drive level), see Figure 15.

EEPROM SPECIFICATION

MIN

100

10

TYP

MAX

UNIT

Cycles

Years

EEcyc

EEret

Programming cycles of EEPROM

Data retention

1000

TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating-free air temperature

MIN NOM MAX UNIT

CLK_IN REQUIREMENTS

PLL mode

1

0

200

4

f_{CLK_IN}

CLK_IN clock input frequency (LVCMOS or differential)

MHz

ns

PLL bypass mode

t_r/t_f

Rise and fall time, CLK_IN signal (20% to 80%)

Duty cycle, CLK_IN at V_CC/2

duty_REF

40%

60%

SMBus TIMING REQUIREMENTS (see Figure 11)

f_SCLK

SCLK frequency

100

50

kHz

µs

t_h(START)

t_w(SCLL)

t_w(SCLH)

t_su(START)

t_h(SDATA)

t_su(SDATA)

START hold time

4

4.7

4

SCLK low-pulse duration

SCLK high-pulse duration

START setup time

SDATA hold time

0.6

0.3

0.25

SDATA setup time

t_r(SDATA)

t_r(SM)

/

SCLK/SDATA input rise time

SCLK/SDATA input fall time

1000

300

ns

t_f(SDATA)

/

t_f(SM)

t_su(STOP)

t_(BUS)

STOP setup time

Bus free time

4

µs

4.7

t_(POR)

Time in which the device must be operational after power-on reset

500

ms

DEVICE CHARACTERISTICS

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

OVERALL PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

All PLLs on, all outputs on,

f_OUT= 80 MHz, f_{CLK_IN}= 27 MHz,

f_VCO= 160 MHz

I_CC

Supply current⁽²⁾

90

115

mA

Every circuit powered down except SMBus,

f_IN= 0 MHz, V_CC= 3.6 V

I_CCPDPower-down current

50

µA

Supply voltage V_CCthreshold for power-up

control circuit

V_PUC

2.1

V

(1) All typical values are at nominal V_CC

.

(2) For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using the high-speed mode of the VCO

reduces the current consumption. See Figure 3.

6

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DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

TEST CONDITIONS

MIN

80

TYP⁽¹⁾

MAX UNIT

All PLLs

200

Normal speed-mode⁽³⁾

VCO frequency of internal PLL (any of three

PLLs)

f_VCO

PLL2 with SSC

80

167

300

250

300

MHz

High-speed mode⁽³⁾

V_CC= 2.5 V

180

LVCMOS output frequency range⁽⁴⁾, See

Figure 4

f_OUT

V_CC= 3.3 V

LVCMOS PARAMETER

V_IK

LVCMOS input voltage

V_CC= 3 V, I_I= –18 mA

–1.2

±5

V

LVCMOS input current (CLK_IN0 and

CLK_IN1)

I_I

V_I= 0 V or V_CC, V_CC= 3.6 V

µA

I_IH

I_IL

LVCMOS input current (S1/S0)

V_I= V_CC, V_CC= 3.6 V

V_I= 0 V, V_CC= 3.6 V

5

µA

–35

–10

Input capacitance at CLK_IN0 and

CLK_IN1

C_I

V_I= 0 V or V_CC

3

pF

LVCMOS PARAMETER FOR V_CCOUT= 3.3-V Mode

V_CCOUT= 3 V, I_OH= –0.1 mA

V_CCOUT= 3 V, I_OH= –4 mA

V_CCOUT= 3 V, I_OH= –6 mA

V_CCOUT= 3 V, I_OL= 0.1 mA

V_CCOUT= 3 V, I_OL= 4 mA

V_CCOUT= 3 V, I_OL= 6 mA

All PLL bypass

2.9

2.4

2.1

V_OH

LVCMOS high-level output voltage

V

0.1

0.5

V_OL

LVCMOS low-level output voltage

Propagation delay

V

0.85

9

11

t_PLH

,

ns

t_PHL

VCO bypass

t_r0/t_f0

t_r1/t_f1

t_r2/t_f2

Rise and fall time for output slew rate 0

Rise and fall time for output slew rate 1

Rise and fall time for output slew rate 2

V_CCOUT= 3.3 V (20%–80%)

1.7

1.5

1.2

3.3

2.5

1.6

4.8

3.2

2.1

ns

Rise and fall time for output slew rate 3

(default configuration)

t_r3/t_f3

V_CCOUT= 3.3 V (20%–80%)

0.4

0.6

1

ns

f_OUT= 50 MHz

55

45

90

80

1 PLL, 1 output

3 PLLs, 3 outputs

1 PLL, 1 output

3 PLLs, 3 outputs

f_OUT= 245.76 MHz

f_OUT= 50 MHz

t_jit(cc)

Cycle-to-cycle jitter⁽⁵⁾⁽⁶⁾

ps

125

60

155

95

f_OUT= 245.76 MHz

f_OUT= 50 MHz

60

90

f_OUT= 245.76 MHz

f_OUT= 50 MHz

55

80

t_jit(per)Peak-to-peak period jitter⁽⁵⁾⁽⁶⁾

ps

145

70

180

105

f_OUT= 245.76 MHz

1.6-ns rise/fall time at f_VCO= 150 MHz,

Pdiv = 3

t_sk(o)

odc

Output skew (see⁽⁷⁾and Table 5)

Output duty cycle⁽⁸⁾

200

f_VCO= 100 MHz, Pdiv = 1

45%

55%

(3) Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in byte 6, bits [7:5]. The minimum f_VCO

can be lower, but impacts jitter performance.

(4) Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow).

(5) 50,000 cycles

(6) Jitter depends on configuration. Jitter data is normal t_r/t_f, input frequency = 3.84 MHz, f_VCO= 245.76 MHz.

(7) The t_sk(o)specification is only valid for equal loading of all outputs.

(8) odc depends on output rise and fall time (t_r/t_f). The data is for normal t_r/t_fand is valid for both SSC on and off.

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DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

LVCMOS PARAMETER FOR V_CCOUT= 2.5-V Mode⁽⁹⁾

V_CCOUT= 2.3 V, I_OH= 0.1 mA

V_CCOUT= 2.3 V, I_OH= –3 mA

V_CCOUT= 2.3 V, I_OH= –4 mA

V_CCOUT= 2.3 V, I_OL= 0.1 mA

V_CCOUT= 2.3 V, I_OL= 3 mA

V_CCOUT= 2.3 V, I_OL= 4 mA

All PLL bypass

2.2

1.7

1.5

V_OH

LVCMOS high-level output voltage

V

0.1

V_OL

LVCMOS low-level output voltage

Propagation delay

0.5

V

0.85

9

11

3.9

2.9

2

t_PLH

,

ns

t_PHL

VCO bypass

t_r0/t_f0

t_r1/t_f1

t_r2/t_f2

Rise and fall time for output slew rate 0

Rise and fall time for output slew rate 1

Rise and fall time for output slew rate 2

V_CCOUT= 2.5 V (20%–80%)

2

1.8

1.3

5.6

4.4

3.2

ns

Rise and fall time for output slew rate 3

(default configuration)

t_r3/t_f3

V_CCOUT= 2.5 V (20%–80%)

0.4

0.8

1.1

ns

f_OUT= 50 MHz

60

50

105

85

1 PLL, 1 output

3 PLLs, 3 outputs

1 PLL, 1 output

3 PLLs, 3 outputs

f_OUT= 245.76 MHz

f_OUT= 50 MHz

t_jit(cc)

Cycle-to-cycle jitter^(10)(11)

ps

130

60

160

95

f_OUT= 245.76 MHz

f_OUT= 50 MHz

65

110

90

f_OUT= 245.76 MHz

f_OUT= 50 MHz

60

t_jit(per)Peak-to-peak period jitter^(10)(11)

ps

145

70

180

105

250

55%

f_OUT= 245.76 MHz

t_sk(o)

odc

Output skew (see⁽¹²⁾and Table 5)

Output duty cycle⁽¹³⁾

2-ns rise/fall time at f_VCO= 150 MHz, Pdiv = 3

f_VCO= 100 MHz, Pdiv = 1

45%

2.1

SMBus PARAMETER

V_IK

I_LK

SCLK and SDATA input clamp voltage

V_CC= 3 V, I_I= –18 mA

–1.2

±5

V

µA

V

SCLK and SDATA input current

SCLK input, high voltage

V_I= 0 V or V_CC, V_CC= 3.6 V

V_IH

V_IL

V_OL

SCLK input, low voltage

0.8

0.4

10

V

SDATA low-level output voltage

Input capacitance at SCLK

Input capacitance at SDATA

I_OL= 4 mA, V_CC= 3 V

V_I= 0 V or V_CC

V

3

pF

C_I

V_I= 0 V or V_CC

10

(9) There is a limited drive capability at output supply voltage of 2.5 V. For proper termination, see the CDCx706/x906 Termination and

Signal Integrity Guidelines application report, SCAA080.

(10) 50,000 cycles

(11) Jitter depends on configuration. Jitter data is normal t_r/t_f, input frequency = 3.84 MHz, f_VCO= 245.76 MHz.

(12) The t_sk(o)specification is only valid for equal loading of all outputs.

(13) odc depends on output rise and fall time (t_r/t_f). The data is for normal t_r/t_fand is valid for both SSC on and off.

8

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PARAMETER MEASUREMENT INFORMATION

CDCE706

1 kW

Yn

LVCMOS

10 pF

1 kW

S0375-01

Figure 1. Test Load

TYPICAL CHARACTERISTICS

120

110

100

90

80

70

60

50

40

30

20

10

0

V

= 3.3 V

CC

M div = 1

N div = 2

P div = 1

VCO Normal-Speed Mode

PLL1 + PLL2 + PLL3

PLL1 + PLL2 SSC + PLL3

PLL1 + PLL2

PLL1

0

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210

− VCO Frequency − MHz

f

VCO

G001

Figure 2. I_CCvs Number of PLLs and VCO Frequency (VCO at Normal-Speed Mode, Byte 6 Bits [7:5])

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TYPICAL CHARACTERISTICS (continued)

120

V

= 3.3 V

CC

110

100

90

80

70

60

50

40

30

20

10

0

M div = 1

N div = 2

P div = 1

VCO High-Speed Mode

PLL1 + PLL2 + PLL3

PLL1 + PLL2

PLL1 + PLL2 SSC + PLL3

PLL1

130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310

f

− VCO Frequency − MHz

VCO

G002

Figure 3. I_CCvs Number of PLLs and VCO Frequency (VCO at High-Speed Mode, Byte 6 Bits [7:5])

90

V

= 3.3 V

CC

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

M div = 1

N div = 2

P div = 1

6 Outputs

5 Outputs

4 Outputs

3 Outputs

2 Outputs

1 Output

0

20

40

60

80

100

120

140

160

180

200

220

240

260

280

300

f

− VCO Frequency − MHz

VCO

G003

Figure 4. I_CCOUTvs Number of Outputs and VCO Frequency

10

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TYPICAL CHARACTERISTICS (continued)

3.6

3.4

3.2

V

= 3.3 V

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

CC

M div = 4

N div = 15

P div = 1

V

OH

at V

= 3.6 V

CCOUT

V

OH

at V

= 2.3 V

CCOUT

V

OL

at V

= 3.6 V

CCOUT

V

OL

at V

= 2.3 V

CCOUT

80

100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420

− Output Frequency − MHz

f

OUT

G004

Figure 5. Output Swing vs Output Frequency

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APPLICATION INFORMATION

SMBus Data Interface

To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It follows

the SMBus specification Version 2.0, which is based on the principles of operation of I²C. More details of the

SMBus specification can be found at http://www.smbus.org.

Through the SMBus, various device functions, such as individual clock output buffers, can be individually

enabled or disabled. The registers associated with the SMBus data interface initialize to their default setting on

power up; therefore, using this interface is optional. The clock device register changes are normally made on

system initialization, if any are required.

Data Protocol

The clock-driver serial protocol accepts byte-write, byte-read, block-write, and block-read operations from the

controller.

For block-write/read operations, the bytes must be accessed in sequential order from lowest to highest byte

(most significant bit first) with the ability to stop after any complete byte has been transferred. For byte-write and

byte-read operations, the system controller can access individually addressed bytes.

Once a byte has been sent, it is written into the internal register and becomes effective immediately after the

rising edge of the ACK bit. This applies to each transferred byte, independently of whether this is a byte-write or

a block-write sequence.

If the EEPROM write cycle is initiated, the data of the internal SMBus register is written into the EEPROM.

During EEPROM write, no data is allowed to be sent to the device via the SMBus until the programming

sequence is completed. Data, however, can be read out during the programming sequence (byte read or block

read). The programming status can be monitored by EEPIP, byte 24 bit 7.

The offset of the indexed byte is encoded in the command code, as described in Table 1.

The block-write and block-read protocol is outlined in Figure 9 and Figure 10, whereas Figure 7 and Figure 8

outline the corresponding byte-write and byte-read protocol.

Slave Receiver Address (7 bits)

A6

A5

A4

A3

1

A2

0

A1⁽¹⁾

0

A0⁽¹⁾

1

R/W

0

1

0

(1) Address bits A0 and A1 are programmable by the configuration inputs S0 and S1 (byte 10 bits [1:0] and bits [3:2]. This allows

addressing up to four devices connected to the same SMBus.

Table 1. Command Code Definition

Bits

Description

7

0 = Block-read or block-write operation

1 = Byte-read or byte-write operation

6–0

Byte offset for read and write operations

12

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1

7

1

8

1

Data Byte

S

Slave Address

Wr

A

P

S

Sr

Rd

Wr

A

Start Condition

Repeated Start Condition

Read (Bit Value = 1)

Write (Bit Value = 0)

Acknowledge (ACK = 0 and NACK = 1)

Stop Condition

P

PE Packet Error

Master-to-Slave Transmission

Slave-to-Master Transmission

M0053-01

Figure 6. Generic Programming Sequence

Byte-Write Programming Sequence

1

7

1

8

1

8

1

S

Slave Address

Wr

A

CommandCode

A

Data Byte

A

P

Figure 7. Byte-Write Protocol

Byte-Read Programming Sequence

1

7

1

8

1

7

1

S

Slave Address

Wr

A

CommandCode

A

S

Slave Address

Rd

A

8

1

Data Byte

A/NA

P

Acknowledge/Not Acknowledge

Figure 8. Byte-Read Protocol

Block-Write Programming Sequence⁽¹⁾

1

7

1

8

1

8

1

S

Slave Address

Wr

A

CommandCode

A

Byte Count N

A

8

1

8

1

8

1

Data Byte 0

A

Data Byte 1

A

- - - - -

Data Byte N – 1

A

P

(1) Data Byte 0 is reserved for revision code and vendor identification. However, this byte is used for internal test. Do not write into it other

than 0000 0001.

Figure 9. Block-Write Protocol

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Block-Read Programming Sequence

1

7

1

8

1

7

1

S

Slave Address

Wr

A

CommandCode

A

Sr

Slave Address

Rd

A

8

1

8

1

8

1

Byte Count N

A

Data Byte 0

A

- - - - -

Data Byte N – 1

NA

P

Figure 10. Block-Read Protocol

P

S

Bit 7 (MSB)

Bit 6

Bit 0 (LSB)

A

P

t_w(SCLL)

t_w(SCLH)

t_r(SM)

t_f(SM)

V_IH(SM)

V_IL(SM)

SCLK

t_h(START)

t_su(START)

t_h(SDATA)

t_su(SDATA)

t_su(STOP)

t_(BUS)

t_r(SDATA)

t_f(SDATA)

V_IH(SM)

V_IL(SM)

SDATA

T0131-01

Figure 11. Timing Diagram, Serial Control Interface

SMBus Hardware Interface

Figure 12 shows how the CDCE706 clock synthesizer is connected to the SMBus. Note that the current through

the pullup resistors (R_p) must meet the SMBus specifications (minimum 100 µA, maximum 350 µA). If the

CDCE706 is not connected to the SMBus, the SDATA and SCLK inputs must be connected with 10-kΩ resistors

to V_CCto avoid floating input conditions.

SMB Host

R_P

CDCE706

SDATA

9

SCLK

10

C_BUS

S0376-01

Figure 12. SMBus Hardware Interface

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Table 2. Register Configuration Command Bitmap

Adr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Byte 0

Byte 1

Byte 2

Byte 3

Revision Code

Vendor Identification

PLL1 Reference Divider M 9-Bit [7:0]

PLL1 Feedback Divider N 12-Bit [7:0]

PLL1 Mux

PLL2 Mux

PLL3 Mux

PLL1 Feedback Divider N 12-Bit [11:8]

PLL1 Ref

Div M [8]

Byte 4

Byte 5

Byte 6

PLL2 Reference Divider M 9-Bit [7:0]

PLL2 Feedback Divider N 12-Bit [7:0]

PLL3 f_VCOPLL2 Feedback Divider N 12-Bit [11:8]

Selection

PLL3 Reference Divider 9-Bit M [7:0]

PLL3 Feedback Divider N [12-Bit 7:0]

PLL3 Feedback Divider N 12-Bit [11:8]

PLL1 f_VCO

Selection

PLL2 f_VCO

Selection

PLL2 Ref

Div M [8]

Byte 7

Byte 8

Byte 9

PLL Selection for P0 (Switch A)

PLL Selection for P1 (Switch A)

Input Signal Source

PLL3 Ref

Div M [8]

Byte 10

Inp. Clock

Selection

Configuration Inputs S1

Configuration Inputs S0

Byte 11

Byte 12

Byte 13

Byte 14

Byte 15

Byte 16

Byte 17

Byte 18

Byte 19

PLL Selection for P3 (Switch A)

PLL Selection for P5 (Switch A)

PLL Selection for P2 (Switch A)

PLL Selection for P4 (Switch A)

Reserved

Power Down

Reserved

7-Bit Divider P0 [6:0]

7-Bit Divider P1 [6:0]

7-Bit Divider P2 [6:0]

7-Bit Divider P3 [6:0]

7-Bit Divider P4 [6:0]

7-Bit Divider P5 [6:0]

Y0 Inv. or Non-Inv

Y1 Inv. or Non-Inv

Y2 Inv. or Non-Inv

Y3 Inv. or Non-Inv

Y4 Inv. or Non-Inv

Y0 Slew-Rate Control

Y0 Enable or

Low

Y0 Divider Selection (Switch B)

Y1 Divider Selection (Switch B)

Y2 Divider Selection (Switch B)

Y3 Divider Selection (Switch B)

Y4 Divider Selection (Switch B)

Y5 Divider Selection (Switch B)

Frequency Selection for SSC

Byte 20

Byte 21

Byte 22

Byte 23

Reserved

Y1 Slew-Rate Control

Y2 Slew-Rate Control

Y3 Slew-Rate Control

Y4 Slew-Rate Control

Y5 Slew-Rate Control

Y1 Enable or

Low

Y2 Enable or

Low

Y3 Enable or

Low

Y4 Enable or

Low

Byte 24 EEPIP [read only] Y5 Inv or Non-Inv

Y5 Enable or

Low

Byte 25

Byte 26

EELOCK

SSC Modulation Selection

EEWRITE

7-Bit Byte Count

Default Device Setting

The internal EEPROM of the CDCE706 is preprogrammed with a factory-default configuration as shown in

Figure 13. This puts the device in an operating mode without the need to program it first. The default setting

appears after power is switched on or after a power-down/up sequence until it is reprogrammed by the user to a

different application configuration. A new register setting is programmed via the serial SMBus Interface.

A different default setting can be programmed on customer request. Contact a Texas Instruments Sales and

Marketing representative for more information.

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f_VCO1= 216 MHz

Output Switch Matrix

PLL1

Divider M

1

Y0

Y1

LV

CMOS

P0-Div

10

27 MHz

PFD

Filter

VCO

MUX

Divider N

8

LV

CMOS

P1-Div

20

f_VCO2= 250 MHz

CLK_IN0

14 pF

XO

or

2 LVCMOS

or

Differential

Input

PLL2

w/ SSC

Y2

Y3

LV

CMOS

P2-Div

8

27 MHz

Divider M

27

PFD

Filter

VCO

CLK_IN1

14 pF

MUX

Divider N

250

LV

CMOS

P3-Div

9

SSC

Off

f_VCO3= 225.792 MHz

S0/CLK_SEL

Y4

Y5

LV

CMOS

P4-Div

32

EEPROM

LOGIC

27 MHz

S1

SDATA

PLL3

MUX

Divider M

375

SMBUS

LOGIC

SCLOCK

PFD

Filter

VCO

LV

CMOS

P5-Div

4

Divider N

3136

B0336-01

NOTE: All outputs are enabled and in noninverting mode. S0, S1, and SSC comply according the default setting described in

byte 10 and byte 25.

Figure 13. Default Device Setting

The output frequency can be calculated:

f ´N

27 MHz ´8

in

f_out

=

,i.e., f_out

=

= 27 MHz

M´P

(1´8)

(1)

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Functional Description of the Logic

All bytes are readable/writeable, unless otherwise expressly mentioned.

Byte 0 (Read-Only): Vendor Identification Bits [3:0]; Revision Code Bit [7:4]⁽¹⁾

Revision Code

Vendor Identification

X

0

1

(1) Byte 0 is only readable by the byte-read instruction (see Figure 8).

Bytes 1 to 9: Reference Divider M of PLL1, PLL2, PLL3⁽¹⁾

M8

0

M7

0

M6

0

M5

0

M4

0

M3

0

M2

0

M1

0

M0

0

Div by

Default^{(2) (3)}

Not allowed

0

1

2

3

0

1

0

1

•

1

0

1

0

1

509

510

511

(1) By selecting the PLL divider factors, M ≤ N and 80 MHz ≤ f_VCO≤ 300 MHz.

(2) Unless customer-specific setting

(3) Default setting of divider M for PLL1 = 1, for PLL2 = 27, and for PLL3 = 375.

Bytes 1 to 9: Feedback Divider N of PLL1, PLL2, PLL3⁽¹⁾

N11

0

N10

0

N9

0

N8

0

N7

0

N6

0

N5

0

N4

0

N3

0

N2

0

N1

N0

0

Div by

Default^{(2) (3)}

0

1

Not allowed

0

1

2

3

0

1

•

1

0

1

0

1

4093

4094

4095

(1) By selecting the PLL divider factors, M ≤ N and 80 MHz ≤ f_VCO≤ 300 MHz.

(2) Unless customer-specific setting

(3) Default setting of divider N for PLL1 = 8, for PLL2 = 250, and for PLL3 = 3136.

Byte 3 Bits [7:5]: PLL (VCO) Bypass Multiplexer

PLLxMUX

PLL (VCO) MUX Output

PLLx

Default⁽¹⁾

0

1

Yes

VCO bypass

(1) Unless customer-specific setting

Byte 6 Bits [7:5]: VCO Frequency Selection Mode for Each PLL⁽¹⁾

PLLxFVCO

VCO Frequency Range

Default⁽²⁾

0

1

80 MHz–200 MHz

180 MHz–300 MHz

Yes

(1) This bit selects the normal-speed mode or the high-speed mode for the dedicated VCO in PLL1, PLL2, or PLL3. At power up, the

high-speed mode is selected, f_VCOis 180 MHz–300 MHz. In case of a higher f_VCO, this bit must be set to 1.

(2) Unless customer-specific setting

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Bytes 9 to 12: Output Switch Matrix (5 × 6 Switch A) PLL Selection for P-Divider P0–P5

SWAPx2

SWAPx1

SWAPx0

Any Output Px

PLL bypass (input clock)

PLL1

Default⁽¹⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P2, P3, P4, P5

P0

PLL2 non-SSC

PLL2 with SSC⁽²⁾

PLL3

P1

Reserved

(1) Unless customer-specific setting

(2) PLL2 has an SSC output and a non-SSC output. If SSC bypass is selected (see byte 25, bits [6:4]), the SSC circuitry of PLL2 is

powered down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used.

Byte 10, Bits [1:0]: Configuration Settings of Input S0/A0/CLK_SEL

S01

S00

Function

Default⁽¹⁾

If S0 is low, the PLLs and the clock-input stage go into power-down mode, outputs are in the

high-impedance state, all actual register settings are maintained, SMBus stays active. If S0 is high,

then the device is powered on and outputs are active.

Yes

0

(2)

If S0 is low, the PLL and all dividers (M-Div and P-Div) are bypassed and PLL is in power down,

all outputs are active (inv. or non-inv.), actual register settings are maintained, SMBus stays

active; this mode is useful for production test. If S0 is high, then the device is powered on and

outputs are active.

0

1

CLK_SEL (input clock selection—overwrites the CLK_SEL setting in byte 10, bit [4])⁽³⁾

—CLK_SEL when set low selects CLK_IN_IN0.

—CLK_SEL when set high selects CLK_IN_IN1.

1

0

1

In this mode, the control input S0 is interpreted as address bit A0 of the slave receiver address

byte⁽⁴⁾

.

(1) Unless customer-specific setting

(2) Power-down mode overwrites the high-impedance state or low state of the S1 setting in byte 10, bits [3:2].

(3) If the clock input (CLK_IN0/CLK_IN1) is selected as crystal input or differential clock input (byte 11, bits [7:6]), then this setting is not

relevant.

(4) To use this pin as slave receiver address bit A0, an initialization pattern must be sent to the CDCE706. When S00/S01 is set to 1, the

S0 input pin is interpreted in the next read or write cycle as address bit A0 of the slave receiver address byte. Note that right after

byte 10 (S00/S01) has been written, A0 (via the S0-pin) is immediately active (also when byte 10 is sent within a block-write sequence).

After the initialization, each CDCE706 has its own S0-dependent slave receiver address and can be addressed according to its new

valid address.

Byte 10, Bits [3:2]: Configuration Settings of Input S1/A1

S11

S10

Function

Default⁽¹⁾

If S1 is set low, all outputs are switched to a low-state (non-inv.) or high-state (inv.). If S1 is high, then all

the outputs are active.

Yes

0

If S1 is set low, all outputs are switched to a high-impedance state. If S1 is high, then all the outputs are

active.

0

1

0

1

Reserved

In this mode, control input S1 is interpreted as address bit A1 of the slave receiver address byte.⁽²⁾

(1) Unless customer-specific setting

(2) To use this pin as slave-receiver address bit A1, an initialization pattern must be sent to the CDCE706. When S10/S11 is set to be 1,

the S1 input pin is interpreted in the next read or write cycle as address bit A1 of the slave receiver address byte. Note that right after

byte 10 (S10/S11) has been written, A1 (via the S1-pin) is immediately active (also when byte 10 is sent within a block-write sequence).

After the initialization, each CDCE706 has its own S1-dependent slave receiver address and can be addressed according to its new

valid address.

Byte 10, Bit [4]: Input Clock Selection⁽¹⁾

CLKSEL

Input Clock

CLK_IN0

Default⁽²⁾

0

1

Yes

CLK_IN1

(1) This bit is not relevant if crystal input or differential clock input is selected, byte 11, bits [7:6].

(2) Unless customer-specific setting

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Byte 11, Bits [7:6]: Input Signal Source⁽¹⁾

IS1

IS0

Function

Default⁽²⁾

0

CLK_IN0 is the crystal oscillator input, and CLK_IN1 serves as the crystal oscillator output.

Yes

CLK_IN0 and CLK_IN1 are two LVCMOS inputs. CLK_IN0 or CLK_IN1 is selectable via the CLK_SEL

control pin.

0

1

0

1

CLK_IN0 and CLK_IN1 serve as differential signal inputs.

Reserved

(1) In case the crystal input or differential clock input is selected, the input clock selection, byte 10, bit [4], is not relevant.

(2) Unless customer-specific setting

Byte 12, Bit [6]: Power-Down Mode (Except SMBus)

PD

0

Power-Down Mode

Normal device operation

Power down⁽²⁾

Default⁽¹⁾

Yes

1

(1) Unless customer-specific setting

(2) In power down, all PLLs and the clock-input stage go into power-down mode, all outputs are in the high-impedance state, all actual

register settings are maintained, and the SMBus stays active. The power-down mode overwrites the high-impedance state or low state

of the S0 and S1 settings in byte 10.

Bytes 13 to 18, Bit [6:0]: Outputs Switch Matrix 6 × 7-Bit Divider P0–P5

DIVYx6

DIVYx5

DIVYx4

DIVYx3

DIVYx2

DIVYx1

DIVYx0

Div by

Default⁽¹⁾⁽²⁾

0

1

0

1

0

Not allowed

1

2

•

1

0

1

0

1

125

126

127

(1) Unless customer-specific setting

(2) Default settings of divider P0 = 10, P1 = 20, P2 = 8, P3 = 9, P4 = 32, and P5 = 4.

Bytes 19 to 24, Bits [5:4]: LVCMOS Output Rise/Fall Time Setting at Y0–Y5

SRCYx1

SRCYx0

Yx

Default⁽¹⁾

0

1

0

1

0

1

Nominal +3 ns (t_r0/t_f0)

Nominal +2 ns (t_r1/t_f1)

Nominal +1 ns (t_r2/t_f2)

Nominal (t_r3/t_f3)

Yes

(1) Unless customer-specific setting

Bytes 19 to 24, Bits [2:0]: Outputs Switch Matrix (6 × 6 Switch B) Divider (P0–P5) Selection for Outputs Y0–Y5

SWBYx2

SWBYx1

SWBYx0

Any Output Yx

Divider P0

Divider P1

Divider P2

Divider P3

Divider P4

Divider P5

Reserved

Default⁽¹⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Y0, Y1, Y2, Y3, Y4, Y5

Reserved

(1) Unless customer-specific setting

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Bytes 19 to 24, Bit [3]: Output Y0–Y5 Enable or Low-State

ENDISYx

Output Yx

Disable to low

Enable

Default⁽¹⁾

0

1

Yes

(1) Unless customer-specific setting

Bytes 19 to 24, Bit [6]: Output Y0–Y5 Noninverting/Inverting

INVYx

Output Yx Status

Noninverting

Inverting

Default⁽¹⁾

0

1

Yes

(1) Unless customer-specific setting

Byte 24, Bit [7] (Read-Only): EEPROM Programming In Process Status⁽¹⁾

EEPIP

Indicate EEPROM Write Process

Default

0

1

No programming

Programming in process

(1) This read-only bit indicates an EEPROM write process. It is set to high if programming starts and resets to low if programming is

completed. Any data written to the EEPIP bit is ignored. During programming, no data are allowed to be sent to the device via the

SMBus until the programming sequence is completed. Data, however, can be read out during the programming sequence (byte read or

block read).

Byte 25, Bits [3:0]: SSC Modulation Frequency Selection in the Range of 30 kHz to 60 kHz⁽¹⁾

f_vco(MHz)

Modulation

Factor

FSSC3 FSSC2 FSSC1

FSSC0

Default⁽²⁾

100

17.6

18.5

19.4

20.5

21.7

23.0

24.6

26.3

28.3

30.4

33.3

36.6

40.6

45.5

51.9

60.2

110

19.4

20.3

21.4

22.6

23.9

25.3

27.0

28.9

31.1

33.5

36.7

40.3

44.6

50.1

57.1

66.3

120

21.1

22.2

23.3

24.6

26.0

27.6

29.5

31.5

33.9

36.5

40.0

43.9

48.7

54.6

62.2

72.3

130

22.9

24.0

25.3

26.7

28.2

30.0

31.9

34.2

36.8

39.6

43.3

47.6

52.8

59.2

67.4

78.3

140

24.6

25.9

27.2

28.7

30.4

32.3

34.4

36.8

39.6

42.6

46.7

51.2

56.8

63.8

72.6

84.3

150

26.4

27.7

29.2

30.8

32.6

34.6

36.8

39.4

42.4

45.6

50.0

54.9

60.9

68.3

77.8

90.4

160

28.2

29.6

31.1

32.8

34.7

36.9

39.3

42.1

45.2

48.7

53.3

58.6

64.9

72.9

83.0

167

29.4

30.9

32.5

34.2

36.2

38.5

41.0

43.9

47.2

50.8

55.7

61.1

67.8

76.0

86.6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5680

5412

5144

4876

4608

4340

4072

3804

3536

3286

3000

2732

2464

2196

1928

1660

f_mod

[kHz]

Yes

96.4 100.6

(1) The PLL must be bypassed (turned off) when changing the SSC Modulation Frequency Factor on-the-fly. This can be done by the

following programming sequence: bypass PLL2 (byte 3, bit 6 = 1); write new Modulation Factor (byte 25); re-activate PLL2 (byte 3,

bit 6 = 0).

(2) Unless customer-specific setting

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Byte 25, Bits [6:4]: SSC Modulation Amount⁽¹⁾

SSC2

SSC1

SSC0

Function

Default⁽²⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SSC modulation amount 0% = SSC bypass for PLL⁽³⁾

SSC modulation amount ±0.1% (center spread)

SSC modulation amount ±0.25% (center spread)

SSC modulation amount ±0.4% (center spread)

SSC modulation amount 1% (down spread)

SSC modulation amount 1.5% (down spread)

SSC modulation amount 2% (down spread)

SSC modulation amount 3% (down spread)

Yes

(1) The PLL must be bypassed (turned off) when changing SSC Modulation Amount on-the-fly. This can be done by the following

programming sequence: bypass PLL2 (byte 3, bit 6 = 1); write new Modulation Amount (byte 25); re-activate PLL2 (byte 3, bit 6 = 0).

(2) Unless customer-specific setting

(3) If SSC bypass is selected, the SSC circuitry of PLL2 is powered down and the SSC output is reset to logic low. The non-SSC output of

PLL2 is not affected by this mode and can still be used.

Byte 25, Bit [7]: Permanently Lock EEPROM Data

(1)

EELOCK

Permanently Lock EEPROM

Default⁽²⁾

0

1

No

Yes

(1) If this bit is set, the actual data in the EEPROM is permanently locked. Note that the EEPROM lock becomes effective when this bit is

set in the EEPROM and not in the internal volatile register. No further programming is possible, even if this bit is set low. Data, however

can still be written via SMBUS to the internal register to change device function on the fly. But new data no longer can be stored into the

EEPROM.

(2) Unless customer-specific setting

Byte 26, Bits [6:0]: Byte Count⁽¹⁾

BC6

BC5

BC4

BC3

BC2

BC1

BC0

No. of Bytes

Default⁽²⁾

0

1

0

1

0

1

Not allowed

1

2

3

•

0

1

0

1

27

Yes

•

1

0

1

0

1

125

126

127

(1) Defines the number of bytes, which is sent from this device at the next block-read protocol.

(2) Unless customer-specific setting

Byte 26, Bit [7]: Initiate EEPROM Write Cycle⁽¹⁾

EEWRITE

Starts EEPROM Write Cycle

Default⁽²⁾

Yes

0

1

No

Yes

(1) The EEPROM WRITE cycle is initiated with the rising edge of the EEWRITE bit. The EEPROM WRITE bit must be sent last to ensure

that the content of all internal registers is stored in the EEPROM. Do not interrupt the EEPROM WRITE cycle; otherwise, random data

can be stored in the EEPROM. A static level-high does not trigger an EEPROM WRITE cycle. This bit stays high until the user resets it

to low (it is not automatically reset after the programming has been completed). Therefore, to initiate an EEPROM WRITE cycle, it is

recommended to send a zero-one sequence to the EEWRITE bit in byte 26.

During EEPROM programming, no data are allowed to be sent to the device via the SMBus until the programming sequence has been

completed. Data, however, can be read out during the programming sequence (byte read or block read). The programming status can

be monitored by reading out EEPIP, byte 24, bit 7. If EELOCK is set, no EEPROM programming is possible.

(2) Unless customer-specific setting

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FUNCTIONAL DESCRIPTION

Clock Inputs (CLK_IN0 and CLK_IN1)

The CDCE706 features two clock inputs which can be used as:

•

Crystal oscillator input (default setting)

Two independent single-ended LVCMOS inputs

Differential signal input

The dedicated clock input can be selected by the input signal source bits [7:6] of byte 11.

Crystal Oscillator Inputs

The input frequency range in crystal mode is 8 MHz to 54 MHz. The CDCE706 uses Pierce-type oscillator

circuitry with included feedback resistance for the inverting amplifier. The user, however, must add external

capacitors (C_X0, C_X1) to match the input load capacitor from the crystal (see Figure 14). The required values can

be calculated:

C_X0= C_X1= 2 × C_L– C_ICB

,

where C_Lis the crystal load capacitor as specified for the crystal unit and C_ICBis the input capacitance of the

device, including the board capacitance (stray capacitance of PCB).

For example, for a fundamental 27-MHz crystal with C_Lof 9 pF and C_ICBof 4 pF,

C_X0= C_X1= (2 × 9 pF) – 3 pF = 15 pF.

It is important to use a short PCB trace from the device to the crystal unit to keep the stray capacitance of the

oscillator loop to a minimum.

Input Source Select

(From EEPROM)

CLK_IN0

XO

or

C_X0

C_ICB

2LVCMOS

or

Crystal

Unit

Differential

Input

CLK_IN1

C_X1

C_ICB

S0377-01

Figure 14. Crystal Input Circuitry

In order to ensure stable oscillation, a certain drive power must be applied. The CDCE706 features an input

oscillator with adaptive gain control, which relieves the user of manually programming the gain. Additionally,

adaptive gain control eliminates the use of external resistors to compensate the ESR of the crystal. The drive

level is the amount of power dissipated by the oscillating crystal unit and is usually specified in terms of power

dissipated by the resonator (equivalent series resistance (ESR)). Figure 15 gives the resulting drive level vs

crystal frequency and ESR.

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100

C = 18 pF

L

ESR = 60

ESR = 50

ESR = 40

ESR = 30

ESR = 25

ESR = 15

90

80

70

60

50

40

30

20

10

0

V

(pk)

= 300 mV

21 W

5

10

15

20

25

30

35

40

45

50

55

f − Frequency − MHz

G005

Figure 15. Crystal Drive Power

For example, if a 27-MHz crystal with ESR of 50 Ω is used and 2 × C_Lis 18 pF, the drive power is 21 µW. Drive

level should be held to a minimum to avoid overdriving the crystal. The maximum power dissipation is specified

for each type of crystal in the oscillator specifications, i.e., 100 µW for the example above.

Single-Ended LVCMOS Clock Inputs

When selecting the LVCMOS clock mode, CLK_IN0 and CLK_IN1 act as regular clock input pins and can be

driven up to 200 MHz. Both clock input circuits are equal in design and can be used independently of each other

(see Figure 16). The internal clock select bit, byte 10, bit [4], selects one of the two input clocks. CLK_IN0 is the

default selection. There is also the option to program the external control pin S0/A0/CLK_SEL as the clock-select

pin, byte 10, bits [1:0].

The two clock inputs can be used for redundancy switching, i.e., to switch between a primary clock and

secondary clock. Note that a phase difference between the clock inputs may require PLL correction. Also, in case

of different frequencies between the primary and secondary clock, the PLL must re-lock to the new frequency.

Input Source Select

(From EEPROM)

CLK_IN0

XO

or

2LVCMOS

or

Differential

Input

CLK_IN1

CLK_SEL⁽¹⁾

S0378-01

(1) CLK_SEL is optional and can be configured by EEPROM setting.

Figure 16. LVCMOS Clock Input Circuitry

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Differential Clock Inputs

The CDCE706 supports differential signaling as well. In this mode, the CLK_IN0 and CLK_IN1 pins serve as

differential signal inputs and can be driven up to 200 MHz.

The minimum magnitude of the differential input voltage is 100 mV over a differential common-mode input

voltage range of 200 mV to V_CC– 0.6 V. If LVDS or LVPECL signal levels are applied, ac coupling and a biasing

structure are recommended to adjust the different physical layers (see Figure 17). The capacitor removes the dc

component of the signal (common-mode voltage), whereas the ac component (voltage swing) is passed on. A

resistor pullup and/or pulldown network represents the biasing structure used to set the common-mode voltage

on the receiver side of the ac-coupling capacitor. DC coupling is also possible.

Input Source Select

(From EEPROM)

CLK_IN0

XO

or

2LVCMOS

or

Differential

Input

CLK_IN1

S0379-01

Figure 17. Differential Clock Input Circuitry

PLL Configuration and Setting

The CDCE706 includes three PLLs which are equal in function and performance, except PLL2, which in addition

supports spread-spectrum clocking (SSC) generation. Figure 18 shows the block diagram of the PLL.

VCO Bypass

PLLx

9-Bit Divider M

Input Clock

1 ... 511

PFD

Filter

VCO

PLL Output

MUX

12-Bit Divider N

1 ... 4095

SSC

(PLL2 Only)

SSC Output

(PLL2 Only)

Programming

B0337-01

Figure 18. PLL Architecture

All three PLLs are designed for easiest configuration. The user must define only the input and output frequencies

or the divider (M, N, P) setting. All other parameters, such as charge-pump current, filter components, phase

margin, or loop bandwidth are controlled and set by the device itself. This assures optimized jitter attenuation and

loop stability.

The PLLs supports normal-speed mode (80 MHz ≤ f_VCO≤ 200 MHz) and high-speed mode (180 MHz ≤ f_VCO

≤

300 MHz), which can be selected by PLLxFVCO (bits [7:5] of byte 6). The speed option assures stable operation

and lowest jitter.

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Divider M and divider N operate internally as a fractional divider for f_VCOup to 250 MHz. This allows a fractional

divider ratio for zero-ppm output clock error.

In the case of f_VCO> 250 MHz, it is recommended that only integer factors of N/M are used.

For optimized jitter performance, keep divider M as small as possible. Also, the fractional divider concept

requires a PLL divider configuration, M ≤ N (or N/M ≥ 1).

Additionally, each PLL supports two bypass options:

•

PLL bypass

VCO bypass

In PLL bypass mode, the PLL is completely bypassed, so that the input clock is switched directly to output

switch A (SWAPxx of bytes 9 to 12). In the VCO bypass mode, only the VCO of the PLL is bypassed by setting

PLLxMUX to 1 (bits [7:5] of byte 3). But divider M still is useable and expands the output divider by an additional

9 bits. This gives a total divider range of M × P = 511 × 127 = 64,897. In VCO bypass mode, the PLL block is

powered down and minimizes current consumption.

Table 3. Example for Divide, Multiplication, and Bypass Operation

f_IN

[MHz]

f_OUT-desired

[MHz]

f_OUT-actual

[MHz]

Divider

Function

Fractional⁽²⁾

Integer factor⁽³⁾

Equation⁽¹⁾

f_VCO[MHz]

M

16

1

N

P

1

N/M

5.0625

10

f_OUT= f_IN× (N/M)/P

f_OUT= f_IN/(M × P)

30.72

27

155.52

270

155.52

270

81

10

—

155.52

270

1

VCO bypass

30.72

0.06

8

64

—

(1) P-divider of output-switch matrix is included in the calculation.

(2) Fractional operation for f_VCO≤ 250 MHz

(3) Integer operation for f_VCO> 250 MHz

Spread-Spectrum Clocking and EMI Reduction

In addition to the basic PLL function, PLL2 supports spread-spectrum clocking (SSC). Thus, PLL 2 features two

outputs, an SSC output and a non-SSC output. Both outputs can be used in parallel. The mean phase of the

center-spread, SSC-modulated signal is equal to the phase of the nonmodulated input frequency. SSC is

selected by output switch A (SWAPxx of bytes 9 to 12).

SSC also is bypassable (byte 25, bits [6:4]) by powering down the SSC output and setting it to the logic-low

state. The non-SSC output of PLL2 is not affected by this mode and can still be used.

SSC is an effective method to reduce electromagnetic interference (EMI) noise in high-speed applications. It

reduces the RF energy peak of the clock signal by modulating the frequency and spreads the energy of the

signal to a broader frequency range. Because the energy of the clock signal remains constant, a varying

frequency that broadens the overtones necessarily lowers their amplitudes. Figure 19 shows the effect of SSC on

a 54-MHz clock signal for DSP.

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Center Spread ±±0.4

9^thHarmonic, f_m= 6±

Down Spread 34

9^thHarmonic, f_m= 6±

7dB

1103dB

C±±1

Figure 19. Spread-Spectrum Clocking With Center Spread and Down Spread

The peak amplitude of the modulated clock is 11.3 dB lower than the nonmodulated carrier frequency for down

spread and radiates less electromagnetic energy.

In SSC mode, the user can select the SSC modulation amount and SSC modulation frequency. The modulation

amount is the frequency deviation relative to the carrier (min/max frequency), whereas the modulation frequency

determines the speed of the frequency variation. In SSC mode, the maximum VCO frequency is limited to

167 MHz.

SSC Modulation Amount

The CDCE706 supports center-spread modulation and down-spread modulation. In center spread, the clock is

symmetrically shifted around the carrier frequency and can be ±0.1%, ±0.25%, or ±0.4%. For down spread, the

clock frequency is always lower than the carrier frequency and can be 1%, 1.5%, 2%, or 3%. The down spread is

preferred if a system cannot tolerate an operating frequency higher than the nominal frequency (overclocking

problem).

Example:

Minimum

Frequency

Center

Frequency

Maximum

Frequency

Modulation Type

A

B

C

±0.25% center spread

53.865 MHz

53.46 MHz

53.73 MHz

54 MHz

—

54.135 MHz

54 MHz

1% down spread

0.5% down spread⁽¹⁾

53.865 MHz

54 MHz

(1) A down spread of 0.5% of a 54-MHz carrier is equivalent to 59.865 MHz at a center spread of ±0.25%.

SSC Modulation Frequency

The modulation frequency (sweep rate) can be selected between 30 kHz and 60 kHz. It is also based on the

VCO frequency as shown in the SSC Modulation Amount as shown in the Byte 25, Bits [6:4] table. As shown in

Figure 20, the damping increases with higher modulation frequencies. It may be limited by the tracking skew of a

downstream PLL. The CDCE706 uses a triangle modulation profile which is one of the common profiles for SSC.

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12

3% Down Spread

11

10

9

2% Down Spread

8

±0.4 Center Spread

±0.25 Center Spread

7

6

5

4

3

30

35

40

45

50

55

60

f

− Modulation Frequency − kHz

Modulation

G006

Figure 20. EMI Reduction vs f_Modulationand f_Amount

Further EMI Reduction

The optimum damping is a combination of modulation amount, modulation frequency, and the harmonics which

are considered. Note that higher-order harmonic frequencies result in stronger EMI reduction because of higher

frequency deviation.

As seen in Figure 21 and Figure 22, a slower output slew rate and/or smaller output-signal amplitude helps to

reduce EMI emission even more. Both measures reduce the RF energy of clock harmonics. The CDCE706

allows slew rate control in four steps between 0.6 ns and 3.3 ns (bytes 19–24, bits [5:4]). The output amplitude is

set by the two independent output supply voltage pins, V_CCOUT1and V_CCOUT2, and can vary from 2.3 V to 3.6 V.

Even a lower output supply voltage down to 1.8 V works, but the maximum frequency must be considered.

Slew-Rate for V_CCOUT= 2.5 V

Slew-Rate for V_CCOUT= 3.3 V

–2.5 dB

5.6 dB

–3 dB

6.4 dB

7dB

11.3dB

Nom – 1

Nom

Nom + 2

C002

Figure 21. EMI Reduction vs Slew-Rate and V_CCOUT

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5

4

3

2

1

0

−1

2.5

3

3.6

V

− Supply Voltage − V

CCOUT

G007

Figure 22. EMI Reduction vs V_CCOUT

Multifunction Control Inputs S0 and S1

The CDCE706 features two user-definable input pins which can be used as external control pins or address pins.

When programmed as control pins, they can function as the clock-select pin, enable/disable pin, or device

power-down pin. If both pins are used as address bits, up to four devices can be connected to the same SMBus.

The function is set in byte 10, bits [3:0]. Table 4 shows the possible settings for the different output conditions,

clock select, and device addresses.

Table 4. Configuration Setting of Control Inputs

Configuration Bits

External Control Pins

Device Function

Byte 10,

Bit [3:2]

Byte 10,

Bit [1:0]

S1

(Pin 2)

S0

(Pin 1)

Power

Down

S11

S10

S01

S00

Yx Outputs

Pin 2

Pin 1

0

X

0

1

X

0

X

0

1

0

X

1

0

Active

Low/high⁽¹⁾

No

Output ctrl

High impedance

Outputs only

Output ctrl

PLL, inputs, and

outputs

Output ctrl and pd

0

X

0

1

0

S10 = 0: low/high⁽¹⁾

PLL only

Output ctrl

PLL and div. bypass

S10 = 1: high impedance

0

X

0

1

0

1

0

Active

S10 = 0: Low/High⁽¹⁾

PLL only

No

Output ctrl

PLL and div. bypass

CLK_SEL

0/1⁽²⁾

S10 = 1: high impedance

0

1

X

1

0

1

0/1⁽²⁾

X

Active

No

Output ctrl

A1⁽³⁾

CLK_SEL

A0⁽³⁾

X

(1) A noninverting output is set to low, and an inverting output is set to high.

(2) If S0 is 0, CLK_IN0 is selected; if S0 is 1, CLK_IN1 is selected.

(3) S0 and S1 are interpreted as address bits A0 and A1 of the slave receiver address byte.

As shown in Table 4, there is a specific order of the different output conditions: power-down mode overwrites

high-impedance state, high-impedance state overwrites low-state, and low-state overwrites active-state.

Output Switching Matrix

The flexible architecture of the output switch matrix allows the user to switch any of the internal clock signal

sources via a free-selectable post-divider to any of the six outputs.

As shown in Figure 23, the CDCE706 is based on two banks of switches and six post-dividers. Switch A

comprises six five-input multiplexers which select one of the four PLL clock outputs or directly select the input

clock and feed it to one of the 7-bit post-dividers (P-divider). Switch B is made up of six six-input multiplexers

which take any P-divider and feed it to one of the six outputs, Yx.

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Switch B was added to the output switch matrix to ensure that output frequencies derived from one P-divider are

100% phase-aligned. Also, the P-divider is built in a way that every divide factor is automatically duty-cycle

corrected. Changing the divider value on the fly may cause a glitch on the output.

Internal Clock Sources

Output Switch Matrix

Outputs

5 x 6 - Switch A

6 x 6 - Switch B

7-Bit Divider

P0

(1...127)

Y0

Input CLK

(PLL Bypass)

P1

(1...127)

Y1

Y2

Y3

Y4

Y5

PLL1

P2

(1...127)

P3

(1...127)

PLL2

Non-SSC

P4

(1...127)

PLL2

w/ SSC

P5

(1...127)

PLL3

Programming

PLL/Input_Clk

Selection

P-Divider

Setting

P-Divider

Selection

Output Selection:

Active/Low/3-State

Inverting/Non-Inverting

Slew Rate/V_CCOUT

B0335-02

Figure 23. CDCE706 Output Switch Matrix

In addition, the outputs can be switched active, low, high-impedance state, and/or 180-degree phase-shifted.

Also, the output slew rate and the output voltage are user-selectable.

LVCMOS Output Configuration

The output stage of the CDCE706 supports all common output settings, such as enable, disable, low-state, and

signal inversion (180-degree phase shift). It further features slew-rate control (0.6 ns to 3.3 ns) and variable

output supply voltage (2.3 V to 3.6 V).

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V_CCOUT1/V_CCOUT2

P-Div(0) Output

P-Div(1) Output

P-Div(2) Output

M

U

X

Sel

Buffer

Yx

P-Div(3) Output

P-Div(4) Output

P-Div(5) Output

P-Divider Select

Inversion Select

Slew-Rate Control

Low Select

Enable/Disable

S1

(Optional; All

Outputs Low

or 3-State)

B0338-01

Figure 24. Block Diagram of Output Architecture

Clock

Div by 3

Inverting

Slew Rate

Low Select

Enable/Disable

T0410-01

Figure 25. Example for Output Waveforms

All output settings are programmable via SMBus:

•

Enable, disable, low-state via external control pins S0 and S1 → byte 10, bits[3:0]

Enable or disable-to-low → bytes 19 to 24, bit[3]

Inverting/noninverting → bytes 19 to 24, bit[6]

Slew-rate control → bytes 19 to 24, bits[5:4]

Output swing → external pins V_CCOUT1(pin 14) and V_CCOUT2(pin 18)

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Performance Data: Output Skew, Jitter, Cross-Coupling, Noise Rejection (Spur Suppression),

and Phase Noise

Output Skew

Skew is an important parameter for clock distribution circuits. It is defined as the time difference between outputs

that are driven by the same input clock. Table 5 shows the output skew (t_sk(o)) of the CDCE706 for high-to-low

and low-to-high transitions over the entire range of supply voltages, operating temperature and output voltage

swing.

Table 5. Output Skew

PARAMETER

CONDITION

V_CCOUT= 2.5 V

V_CCOUT= 3.3 V

TYP

130

MAX

250

UNIT

ps

t_sk(o)

Output skew

200

ps

Jitter Performance

Jitter is a major parameter for PLL-based clock driver circuits. This becomes important as speed increases and

timing budget decreases. The PLL and internal circuits of CDCE706 are designed for lowest jitter. The

peak-to-peak period jitter is only 60 ps (typical). Table 6 gives the peak-to-peak and rms deviation of

cycle-to-cycle jitter, period jitter and phase jitter as taken during characterization.

Table 6. Jitter Performance of CDCE706

TYP⁽¹⁾

MAX⁽¹⁾

PARAMETER

CONDITION

UNIT

rms

(One Sigma)

rms

(One Sigma)

Peak-Peak

f_out= 50 MHz

f_out= 133 MHz

f_out= 245.76 MHz

f_out= 50 MHz

55

50

–

75

85

–

t_jit(cc)

Cycle-to-cycle jitter

ps

45

–

60

–

60

4

76

7

t_jit(per)

Period jitter

Phase jitter

f_out= 133 MHz

f_out= 245.76 MHz

f_out= 50 MHz

55

5

84

11

8

ps

55

5

72

730

930

720

90

130

90

840

1310

930

115

175

125

t_jit(phase)

f_out= 133 MHz

f_out= 245.76 MHz

(1) All typical and maximum values are at V_CC= 3.3 V, temperature = 25°C, V_CCOUT= 3.3 V; one output is switching, data taken over

several 10,000 cycles.

Figure 26, Figure 27, and Figure 28 show the relationship between cycle-to-cycle jitter, period jitter, and phase

jitter over 10,000 samples. The jitter varies with a smaller or wider sample window. The cycle-to-cycle jitter and

period jitter show the measured value, whereas the phase jitter is the accumulated period jitter.

Cycle-to-Cycle jitter (t_jit(cc)) is the variation in cycle time of a clock signal between adjacent cycles, over a random

sample of adjacent cycle pairs. Cycle-to-cycle jitter is never greater than the period jitter. It is also known as

adjacent-cycle jitter.

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40

30

20

10

0

−10

−20

−30

−40

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

G008

Figure 26. Snapshot of Cycle-to-Cycle Jitter

Period jitter (t_jit(per)) is the deviation in cycle time of a clock signal with respect to the ideal period (1/f_O) over a

random sample of cycles. In reference to a PLL, period jitter is the worst-case period deviation from the ideal that

would ever occur on the PLL outputs. This is also referred to as short-term jitter.

25

20

15

10

5

0

−5

−10

−15

−20

−25

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

G009

Figure 27. Snapshot of Period Jitter

Phase jitter (t_jit(phase)) is the long-term variation of the clock signal. It is the cumulative deviation in t(Θ) for a

controlled edge with respect to a t(Θ) mean in a random sample of cycles. Phase jitter, time-interval error (TIE),

and wander are used in literature to describe long-term variation in frequency. As of ITU-T: G.810, wander is

defined as phase variation at rates less than 10 Hz, whereas jitter is defined as phase variation greater than

10 Hz. The measurement interval must be long enough to gain a meaningful result. Wander can be caused by

temperature drift, aging, supply-voltage drift, etc.

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300

250

200

150

100

50

0

−50

−100

−150

−200

−250

−300

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

G010

Figure 28. Snapshot of Phase Jitter

Jitter depends on the VCO frequency (f_VCO) of the PLL. A higher f_VCOresults in better jitter performance

compared to a lower f_VCO. The VCO frequency can be defined via the M- and N-dividers of the PLL.

As the CDCE706 supports a wide frequency range, the device offers VCO frequency-selection bits, bits [7:5] of

byte 6. These bits define the jitter-optimized frequency range of each PLL. The user can select between the

normal-speed mode (80 MHz to 200 MHz) and the high-speed mode (180 MHz to 300 MHz). Figure 29 shows

the jitter performance over f_VCOfor the two frequency ranges.

300

T = 25°C

A

280

260

240

220

200

180

160

140

120

100

80

V

CC

= 3.3 V

M div = 4

N div = 15

P div = 3

f

− Frequency Range

VCO

f

− Frequency Range

for High-Speed Mode

VCO

for Normal-Speed Mode

High-Speed Mode > 180 MHz

60

40

Normal-Speed Mode < 200 MHz

20

0

20

40

60

80 100 120 140 160 180 200 220 240 260 280 300 320 340 360

− VCO Frequency − MHz Set Point

f

VCO

G011

Figure 29. Period Jitter vs f_VCOfor Normal-Speed Mode and High-Speed Mode

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The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance.

Cross-Coupling, Spur Suppression, and Noise Rejection

Cross-coupling in ICs occurs through interactions between several parts of the chip such as between output

stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive, and resistive (ohmic),

induced by output switching, leakage current, ground bouncing, power supply transients, etc.

The CDCE706 is designed using RFSiGe process technology. This process gives excellent performance in

linearity, low power consumption, best-in-class noise performance, and very good isolation characteristics

between the on-chip components.

The good isolation is a major benefit of the RFSiGe process because it minimizes the coupling effect. Even if all

three PLLs are active and all outputs are on, the noise suppression is well above 50 dB. Figure 30 and Figure 31

show an example of noise coupling, spur-suppression, and power-supply noise rejection of the CDCE706. The

measurement conditions are shown in Figure 30 and Figure 31.

· Measured Y1: 48 MHz

· Y0 is 27 MHz (XTAL Buffered, Loaded by 50 W)

· Y2 is 56.448 MHz (Loaded by 50 W)

· Y3 is 33.33 MHz (Loaded by 50 W)

· Y4, Y5 in the High-Impedance State

Carrier

48 MHz

2^ndHarmonic

Spur at

27 MHz

C003

Figure 30. Noise Coupling and Spur Suppression

· Measured Y0: 48 MHz

· Y1, Y2, Y3 Y4 and Y5 in the High-Impedance State

· Inserted 30 mV, 1 MHz at V_CC= 3.3 V

Carrier

48 MHz

Carrier

48 MHz

Spurs at

47 MHz and 49 MHz

Spur 47 MHz and

Fundamental at 1 MHz

C004

Figure 31. Power-Supply Noise Rejection

Phase Noise Characteristic

In high-speed communication systems, the phase-noise characteristic of the PLL frequency synthesizer is of high

interest. Phase noise describes the stability of the clock signal in the frequency domain, similar to the jitter

specification in the time domain.

34

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Phase noise is a result of random and discrete noise causing a broad slope and spurious peaks. The discrete

spurious components could be caused by known clock frequencies in the signal source, power line interference,

and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the

result of thermal noise, shot noise, and/or flicker noise in active and passive devices.

An important factor for the PLL synthesizer is the loop bandwidth (–3-dB cutoff frequency)—large loop bandwidth

(LBW) results in fast transient response but less reference spur attenuation. The LBW of the CDCE706 is about

100 kHz to 250 kHz, depending on the selected PLL parameter.

For the CDCE706, two phase-noise characteristics are of interest, the phase noise of the crystal-input stage and

the phase noise of the internal PLL (VCO). Figure 32 shows the respective phase noise characteristic.

−50

Phase Noise Comparison

−60

−70

f

= 135 MHz

out

f

= 270 MHz

−80

VCO

f

= 135 MHz

VCO

−90

−100

−110

−120

−130

−140

−150

27-MHz Crystal

Buffered Output

10

100

1k

10k

− Offset Frequency − Hz

100k

1M

10M

f

offset

G012

Figure 32. Phase Noise Characteristic

PLL-Lock Time

Some applications use frequency switching, e.g., changing frequency in a TV application (switching between

channels) or changing the PCI-X frequency in computers. The time spent by the PLL in achieving the new

frequency is of main interest. The lock time is the time it takes to jump from one specified frequency to another

specified frequency within a given frequency tolerance (see Figure 33). It should be low, because a long lock

time impacts the data rate of the system.

The PLL-lock time depends on the device configuration and can be changed by the VCO frequency, i.e., by

changing the M/N divider values. Table 7 gives the typical lock times of the CDCE706 and Figure 33 shows a

snapshot of a frequency switch.

Table 7. CDCE706 PLL Lock-Times

Description

Lock Time

100

Unit

µs

Frequency change via reprogramming of N/M counter

Frequency change via CLK_SEL pin (switching between CLK_IN0 and CLK_IN1)

Power-up lock time with system clock

100

µs

50

µs

Power-up lock time with 27-MHz crystal at CLK_IN0 and CLK_IN1

300⁽¹⁾

µs

(1) Is the result of crystal lock time (200 µs) and PLL lock time (100 µs).

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f_VCO(MHz)

Frequency

Start Condition:

Response

Acknowledge of

Curve of Y0

N-Divider Byte

297

81

t (ms)

0

60

· Y0 (PLL1), Y1–Y4 in High-Impedance State

· Measured Channel: Y0

· Start Condition: f(M = 10, N = 30) = 81 MHz

· Byte-2 Write: N = 30 (81 MHz) > N = 110 (297 MHz)

· 60 ms to PLL Pull-In

20 ms/div

C005

Figure 33. Snapshot of the PLL Lock-Time

Power-Supply Sequencing

The CDCE706 includes three power-supply pins, V_CC, V_CCOUT1, and V_CCOUT2. There are no power-supply

sequencing requirements, as the three power nodes are separated from each other. So, power can be supplied

in any order to the three nodes.

Also, the part has power-up circuitry which switches the device on if V_CCexceeds 2.1 V (typ) and switches the

device off at V_CC< 1.7 V (typ). In power-down mode, all outputs and clock inputs are switched off.

Device Behavior During Supply-Voltage Drops

The CDCE706 has a power-up circuit, which activates the device functionality at V_{PUC_ON}(typical 2.1 V). At the

same time, the EEPROM information is loaded into the register. This mechanism ensures that there is a

predefined default after power up and no need to reprogram the CDCE706 in the application.

In the event of a supply-voltage drop, the power-up circuit ensures that there is always a defined setup within the

register. Figure 34 shows possible voltage drops with different amplitudes.

36

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V

Typ 3.3 V

V_CC

A

Typ 2.1 V

V_{PUC_ON}

B

Typ 1.7 V

V_{PUC_OFF}

C

D

GND

t

T0411-01

Figure 34. Different Voltage Drops on V_CCDuring Operation

The CDCE706 power-up circuit has built-in hysteresis. If the voltage stays above V_{PUC_OFF}, which is typically at

1.7 V, the register content stays unchanged. If the voltage drops below V_{PUC_OFF}, the internal register is reloaded

by the EEPROM after V_{PUC_ON}is crossed again. V_{PUC_ON}is typically 2.1 V. Table 8 shows the content of the

EEPROM and the register after the voltage-drop scenarios shown in Figure 34.

Table 8. EEPROM and Register Content After V_CCDrop

Power Drop

EEPROM Content

Unchanged

Register Content

Unchanged

A

B

C

D

Unchanged

Reloaded from EEPROM

Unchanged

EVM and Programming Software

The CDCE706 EVM is a development kit consisting of a performance evaluation module, the TI Pro Clock

software, and the User's Guide. Contact a Texas Instruments sales or marketing representative for more

information.

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PACKAGE OPTION ADDENDUM

www.ti.com

7-Feb-2008

PACKAGING INFORMATION

Orderable Device

CDCE706PW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

20

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CDCE706PWG4

CDCE706PWR

CDCE706PWRG4

TSSOP

PW

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CDCE706_10
厂家：	TEXAS INSTRUMENTS
描述：	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER 可编程3 -PLL时钟合成器/乘法器/除法器时钟
文件：	总40页 (文件大小：1007K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDCE706_10 [TI]

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