CDCE706_技术文档

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

FEATURES

•

Separate Power Supplies for Outputs (2.3 V to

3.6 V) Supports Mixed Power Supply

Environments

•

High Performance 2:6 PLL based Clock

Synthesizer / Multiplier / Divider

•

3.3-V Device Power Supply

User Programmable PLL Frequencies using

EEPROM Technology

Industrial Temperature Range –40°C to 85°C

EEPROM Programming Without the Need to

Apply High Programming Voltage

Development and Programming Kit for Ease

PLL Design and Programming (TI

Pro-Clock™)

Easy In-Circuit Programming via SMBus Data

Interface

•

Packaged in 20-Pin TSSOP

Wide PLL Divider Ratio Allows 0-ppm Output

Clock Error

TERMINAL ASSIGNMENT

Clock Inputs Accept a Crystal or a

Single-Ended LVCMOS or a Differential Input

Signal

PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

S0/A0/CLK_SEL

S1/A1

Y5

Y4

V

CCOUT2

GND

Y3

Y2

V

CCOUT1

GND

Y1

•

Accepts Crystal Frequencies from 8 MHz up

to 54 MHz

V

CC

Accepts LVCMOS or Differential Input

Frequencies up to 200 MHz

GND

CLK_IN0

CLK_IN1

TSSOP 20

Pitch 0,65 mm

6.6 x 6.6

Two Programmable Control Inputs [S0/S1,

A0/A1] for User Defined Control Signals

V

CC

GND

SDATA

SCLOCK

Six LVCMOS Outputs with Output

Frequencies up to 300 MHz

Y0

LVCMOS Outputs can be Programmed for

Complementary Signals (Pseudo Differential

Outputs)

•

Free Selectable Output Frequency via

Programmable Output Switching Matrix [6x6]

Including 7-Bit Post-Divider for Each Output

•

PLL Loop Filter Components Integrated

Low Period Jitter (Typ 60 ps)

Features Spread Spectrum Clocking (SSC) for

Lowering System EMI

•

Programmable Output Slew-Rate Control

(SRC) for Lowering System EMI

DESCRIPTION

The CDCE706 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite

its small physical outlines, the CDCE706 is the most flexible. It has the capability to produce an almost

independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate

input waveform can be selected via the SMBus data interface controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Pro-Clock is a trademark of Texas Instruments.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

CDCE706

www.ti.com

SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL

can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO

(voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of

the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for

each output. The individual selectable inverting logic allows two LVCMOS outputs to work as pseudo differential

signal (0 degrees and 180 degree phase shift).

The deep M/N divider ratio allows the generation of zero ppm clocks from e.g., a 27-MHz reference input

frequency.

The CDCE706 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and

PLL3 are designed for frequencies up to 300 MHz and optimized for zero-ppm applications with wide divider

factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC) which effectively lower the energy

for the selected frequency range. The electro-magnetic interference (EMI) will be significantly reduced. Also, the

slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically

adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for ease-customized application. It is pre-programmed

with a factory default configuration (see Figure 8) and can be re-programmed to a different application

configuration before it goes onto the PCB or re-programmed by in-system programming. A different register

setting is programmed via the serial SMBus Interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic

control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE706 has three power supply pins, V_CC, V_CCOUT1and V_CCOUT2. V_CCis the power supply for the device. It

operates from a single 3.3-V supply voltage. V_CCOUT1and V_CCOUT2are the power supply pins for the outputs.

V_CCOUT1supplies the outputs Y0 and Y1 and V_CCOUT2supplies the outputs Y2, Y3, Y4, and Y5. Both outputs

supplies can be 2.3 V to 3.6 V.

The CDCE706 is characterized for operation from –40°C to 85°C.

2

CDCE706

www.ti.com

SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

FUNCTIONAL BLOCK DIAGRAM

V

CC

GND

V

CCOUT1

PLL Bypass

Output Switch Matrix

VCO1 Bypass

PLL1

MUX

prg. 9 Bit

Divider M

PFD

Filter

VCO

LV

CMOS

Y0

Y1

prg. 12 Bit

Divider N

LV

CMOS

CLK_IN0

CLK_IN1

VCO2 Bypass

XO

or

2 LVCMOS

or

Differential

Input

PLL2

w/ SSC

prg. 9 Bit

Divider M

LV

CMOS

Y2

Y3

PFD

Filter

VCO

MUX

prg. 12 Bit

Divider N

LV

CMOS

SSC

SO/AO/CLK_SEL

VCO3 Bypass

LV

CMOS

EEPROM

LOGIC

S1/A1

SDATA

PLL3

MUX

Y4

Y5

prg. 9 Bit

Divider M

PFD

Filter

VCO

SCLOCK

LV

CMOS

Factory Prg.

prg. 12 Bit

Divider N

GND

V

CCOUT2

OUTPUT SWITCH MATRIX

5x6 − Switch A

7-Bit Divider

P0

6x6 − Switch B

Y0

Y1

Y2

Y3

Y4

Y5

Input CLK

(PLL Bypass)

P1

P2

P3

P4

PLL 1

PLL 2

non SSC

PLL 2

w/ SSC

P5

PLL 3

Programming

3

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

TSSOP20

NO.

NAME

11, 12, 15,

16, 19, 20

Y0 to Y5

CLK_IN0

CLK_IN1

O

I

LVCMOS outputs

Dependent on SMBus settings, CLK_IN0 is the crystal oscillator input and can also be used as

LVCMOS input or as positive differential signal inputs.

5

6

Dependent on SMBus settings, CLK_IN1 is serving as the crystal oscillator output or can be

the second LVCMOS input or the negative differential signal input.

I/O

V_CC

3, 7

14

Power

Ground

3.3-V power supply for the device

V_CCOUT1

V_CCOUT2

GND

Power 2.5-V to 3.3-V power supply for outputs Y0, Y1

Power 2.5-V to 3.3-V power supply for outputs Y2, Y3, Y4, Y5

Ground

18

4, 8, 13, 17

User programmable control input S0 (PLL bypass or power-down mode) or AO (address bit 0),

or CLK_SEL (selects one of two LVCMOS clock inputs), dependent on the SMBus settings;

LVCMOS inputs; internal pullup 150 kΩ.

S0, A0,

CLK_SEL

1

I

User programmable control input S1 (output enable/disable or all output low), A1 (address bit

1), dependent on the SMBus settings; LVCMOS inputs; internal pullup 150 kΩ

S1, A1

2

I

SDATA

9

I/O

I

Serial control data input/output for SMBus controller; LVCMOS input

Serial control clock input for SMBus controller; LVCMOS input

SCLOCK

10

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

–0.5 to 4.6

–0.5 to V_CC+ 0.5

– 0.5 to V_CC+ 0.5

±20

UNIT

V

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

Output voltage range⁽²⁾

Input current (V_I< 0, V _I> V_CC

Continuous output current

Storage temperature range

V

V_O

I_I

V

)

mA

°C

I_O

±50

T_stg

T_J

–65 to 150

125

Maximum junction temperature

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

PACKAGE THERMAL RESISTANCE

for TSSOP20 (PW) Package⁽¹⁾

PARAMETER

Thermal resistance junction-to-ambient

Thermal resistance junction-to-case

AIRFLOW (lfm)

°C/W

66.3

59.3

56.3

51.9

19.7

0

150

250

500

θ_JA

θ_JC

(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_CC

Device supply voltage

3

3.3

3.6

V

4

CDCE706

www.ti.com

SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

2.3

NOM

MAX

3.6

UNIT

V

V_CCOUT1

V_CCOUT2

V_IL

Output Y0,Y1 supply voltage

Output Y2, Y3, Y4, Y5 supply voltage

Low level input voltage LVCMOS

High level input voltage LVCMOS

Input voltage threshold LVCMOS

Input voltage range LVCMOS

Differential input voltage

2.3

3.6

V

0.3 V_CC

V

V_IH

0.7 V_CC

V

V_Ithresh

V_I

0.5 V_CC

V

0

0.4

0.2

3.6

V

|V_ID

V_IC

I_OH

I_OL

C_L

|

V

Common-mode for differential input voltage

High-level output current

V_cc- 1

–6

V

mA

pF

°C

Low-level output current

6

Output load LVCMOS

25

T_A

Operating free-air temperature

–40

85

RECOMMENDED CRYSTAL SPECIFICATIONS

MIN

NOM

MAX

UNIT

MHz

Ω

f_Xtal

ESR

C_IN

Crystal input frequency range (fundamental mode)

Effective series resistance⁽¹⁾⁽²⁾

8

27

54

60

15

Input capacitance CLK_IN0 and CLK_IN1

4

pF

(1) For crystal frequencies above 50 MHz the effective series resistor should not exceed 50 Ω to assure stable start-up condition.

(2) Maximum Power Handling (Drive Level) see Figure 10.

EEPROM SPECIFICATION

MIN

TYP

TBD

MAX

UNIT

EEcyc

EEret

Programming cycles of EEPROM

Data retention

100

Cycles

Years

TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating-free air temperature

MIN NOM MAX UNIT

CLK_IN REQUIREMENTS

PLL mode

1

0

200

4

f_{CLK_IN}

LVCMOS CLK_IN clock input frequency

MHz

ns

PLL bypass mode

t_r/ t_f

Rise and fall time CLK_IN signal (20% to 80%)

Duty cycle CLK_IN at V_CC/ 2

duty_REF

40%

60%

SMBus TIMING REQUIREMENTS (see Figure 6)

f_SCLK

SCLK frequency

100

50

kHz

µs

ns

µs

t_h(START)

t_w(SCLL)

t_w(SCLH)

t_su(START)

t_h(SDATA)

t_su(SDATA)

t_r

START hold time

4

4.7

4

SCLK low-pulse duration

SCLK high-pulse duration

START setup time

0.6

0.3

0.25

SDATA hold time

SDATA setup time

SCLK / SDATA input rise time

SCLK / SDATA input fall time

STOP setup time

1000

300

t_f

t_su(STOP)

4

5

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

TIMING REQUIREMENTS (continued)

over recommended ranges of supply voltage, load, and operating-free air temperature

MIN NOM MAX UNIT

t_BUS

t_POR

Bus free time

4.7

µs

Time in which the device must be operational after power-on reset

500

ms

DEVICE CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

OVERALL PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

I_CC

Supply current

All PLLs on, all outputs on,

f_out= 80 MHz, f_{CLK_IN}= 27 MHz,

f_vco= 160 MHz

90

115

mA

I_CCPD

V_PUC

Power down current. Every circuit powered

down except SMBus

f_IN= 0 MHz, V_CC= 3.6 V

300

2.3

µA

Supply voltage V_ccthreshold for power up

control circuit

V

Normal speed-mode⁽²⁾

High-speed mode⁽²⁾

V_CC= 2.5 V

80

167

300

250

300

VCO frequency of internal PLL (any of three

PLLs)

f_VCO

MHz

150

f_OUT

LVCMOS output frequency range

V_CC= 3.3 V

LVCMOS PARAMETER

V_IK

I_I

LVCMOS input voltage

V_CC= 3 V; I_I= –18 mA

V_I= 0 V or V_CC, V_CC= 3.6 V

V_I= V_CC, V_CC= 3.6 V

V_I= 0 V, V_CC= 3.6 V

–1.2

V

LVCMOS input current

TBD

3

µA

pF

I_IH

I_IL

C_I

LVCMOS input current For S1/S0

Input capacitance at CLK_IN0 and CLK_IN1 V_I= 0 V or V_CC

(1) All typical values are at respective nominal V_CC

.

(2) Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in Byte 6, Bit [7:5]. The min fvco can be

lower but impacts jitter-performance.

6

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

LVCMOS PARAMETER FOR V_ccout= 3.3-V Mode

V_ccout= 3 V, I_OH= –0.1 mA

V_ccout= 3 V, I_OH= –4 mA

V_ccout= 3 V, I_OH= –6 mA

V_ccout= 3 V, I_OL= 0.1 mA

V_ccout= 3 V, I_OL= 4 mA

V_ccout= 3 V, I_OL= 6 mA

All PLL bypass

2.9

2.4

2.1

V_OH

LVCMOS high-level output voltage

V

0.1

0.5

V_OL

LVCMOS low-level output voltage

Propagation delay

V

0.85

9

11

t_PLH

,

ns

t_PHL

VCO bypass

t_r0/t_f0

t_r1/t_f1

t_r2/t_f2

t_r3/t_f3

Rise and fall time for output slew rate 0

Rise and fall time for output slew rate 1

Rise and fall time for output slew rate 2

Rise and fall time for output slew rate 3

V_ccout= 3.3 V (20%–80%)

1 PLL, 1 Output

3.3

2.5

1.6

0.6

50

ns

TBD

(3)(4)

t_jit(cc)

Cycle-to-cycle jitter

ps

3 PLLs, 3 Outputs

120

60

1 PLL, 1 Output

t_jit(per)

t_sk(o)

odc

Peak-to-peak period jitter⁽⁴⁾

3 PLLs, 3 Outputs

130

Output skew (see ⁽⁵⁾and Table 5)

1.6-ns rise/fall time (default) at

f_vco= 150 MHz, Pdiv = 3

200

ps

f_vco= 250 MHz, Pdiv = 1

f_vco= 250 MHz, Pdiv = 25

Output duty cycle⁽⁶⁾

45%

55%

LVCMOS PARAMETER FOR V_ccout= 2.5-V Mode

V_ccout= 2.3 V, I_OH= 0.1 mA

V_ccout= 2.3 V, I_OH= –3 mA

V_ccout= 2.3 V, I_OH= –4 mA

V_ccout= 2.3 V, I_OL= 0.1 mA

V_ccout= 2.3 V, I_OL= 3 mA

V_ccout= 2.3 V, I_OL= 4 mA

All PLL bypass

2.2

1.7

1.5

V_OH

LVCMOS high-level output voltage

V

0.1

0.5

V_OL

LVCMOS low-level output voltage

Propagation delay

V

0.85

9

t_PLH

,

ns

t_PHL

VCO Bypass

11

Rise and fall time for output

slew rate 0

t_r0/t_f0

t_r1/t_f1

t_r2/t_f2

t_r3/t_f3

V_ccout= 2.5 V (20%–80%)

3.9

2.9

2.0

0.8

ns

Rise and fall time for output

slew rate 1

Rise and fall time for output

slew rate 2

Rise and fall time for output

slew rate 3

(3)(4)

Cycle-to-cycle jitter

1 PLL, 1 Output

3 PLLs, 3 Outputs

1 PLL, 1 Output

3 PLLs, 3 Outputs

60

130

60

TBD

t_jit(cc)

ps

Peak-to-peak period jitter⁽⁴⁾

t_jit(per)

t_sk(o)

ps

140

Output skew (see ⁽⁵⁾and Table 5)

2-ns rise/fall time (default) at

fvco = 150 MHz, Pdiv = 3

250

(3) 50000 cycles

(4) Jitter depends on configuration.

(5) The t_sk(o)specification is only valid for equal loading of all outputs.

(6) odc depends on output rise and fall time (t_r/t_f); above limits are for normal t_r/t_f, except for frequencies ranging from 167 MHz to 300 MHz,

the fastest slew rate is used (0.6 ns at V_ccout= 3.3 V or 0.8 ns at V_ccout= 2.5 V).

7

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

Output duty cycle⁽⁶⁾

SMBus PARAMETER

TEST CONDITIONS

fvco = 250 MHz, Pdiv = 1

fvco = 250 MHz, Pdiv = 25

MIN

TYP⁽¹⁾

MAX

UNIT

odc

45%

55%

V_IK

SCLK and SDATA input clamp voltage

SCLK and SDATA input current

SCLK input high voltage

V_CC= 3 V, I_I= –18 mA

V_I= V_CC, V_CC= 3.6 V

V_I= 0 V, V_CC= 3.6 V

–1.2

5

V

µA

V

I_IH

I_IL

–15

2.1

–5

V_IH

V_IL

SCLK input low voltage

0.8

0.4

10

V

V_OL

C_ISCLK

C_ISDATA

SDATA low-level output voltage

Input capacitance at SCLK

I_OL= 4 mA, V_CC= 3 V

V_I= 0 V or V_CC

V

4

pF

Input capacitance at SDATA

V_I= 0 V or V_CC

10

PARAMETER MEASUREMENT INFORMATION

TYPICAL CHARACTERISTICS

TBD

8

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

APPLICATION INFORMATION

SMBus Data Interface

To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It follows

the SMBus specification Version 2.0, which is based upon the principals of operation of I2C. More details of the

SMBus specification can be found at http://www.smbus.org.

Through the SMBus, various device functions, such as individual clock output buffers, can be individually

enabled or disabled. The registers associated with the SMBus data interface initialize to their default setting upon

power-up, and therefore using this interface is optional. The clock device register changes are normally made

upon system initialization, if any are required.

Data Protocol

The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the

controller.

For Block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte

(most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and

Byte Read operations, the system controller can access individually addressed bytes.

Once a byte has been sent, it will be written into the internal register and effective immediately. This applies to

each transferred byte, independent of whether this is a Byte Write or a Block Write sequence.

If the EEPROM write cycle is initiated, the data of the internal SMBus register is written into the EEPROM.

During EEPROM write, no data is allowed to be sent to the device via the SMBus until the programming

sequence is completed. Data, however, can be readout during the programming sequence (byte read or block

read). The programming status can be monitored by EEPIP, byte 24 bit 7.

The offset of the indexed byte is encoded in the command code, as described in Table 1.

The Block Write and Block Read protocol is outlined in Figure 4 and Figure 5, while Figure 2 and Figure 3

outlines the corresponding Byte Write and Byte Read protocol.

Slave Receiver Address (7 bits)

A6

1

A5

1

A4

0

A3

1

A2

0

A1*

0

A0*

1

R/W

0

* Address bits A0 and A1 are programmable by the Configuration Inputs S0 and S1 (Byte 10 Bit [1:0] and Bit [3:2]. This allows addressing

up to four devices connected to the same SMBus.

Table 1. Command Code Definition

Bit

Description

7

0 = Block Read or Block Write operation

1 = Byte Read or Byte Write operation

(6:0)

Byte Offset for Byte Read and Byte Write operation.

For Block Read and Block Write operation, these bits have to be 000 0000.

9

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

1

7

1

8

1

S

Slave Address

Wr A

Data Byte

A

P

S

Start Condition

Reapeated Start Condition

Read (Bit Value = 1)

Sr

Rd

Write (Bit Value = 0)

Wr

A

Acknowledg (ACK = 0 and NACK =1)

Stop Condition

P

PE Packet Error

Master to Slave Transmission

Slave to Master Transmission

Figure 1. Generic Programming Sequence

Byte Write Programming Sequence

1

7

1

8

1

8

1

S

Slave Address

Wr

A

CommandCode

A

Data Byte

A

P

Figure 2. Byte Write Protocol

Byte Read Programming Sequence

1

7

1

8

1

7

1

S

Slave Address

Wr

A

CommandCode

A

S

Slave Address

Rd

A

8

1

Data Byte

A

P

Figure 3. Byte Read Protocol

Block Write Programming Sequence⁽¹⁾

1

7

1

8

1

8

1

S

Slave Address

Wr

A

CommandCode

A

Byte Count N

A

8

1

8

1

8

1

Data Byte 0

A

Data Byte 1

A

- - - - -

Data Byte N–1

A

P

⁽¹⁾Data bit is reserved for revision code and vendor identification. However, this byte is used for internal test. Do not write into it other than

0000 0000.

Figure 4. Block Write Protocol

10

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

Block Read Programming Sequence

1

7

1

8

1

7

1

S

Slave Address

Wr

A

CommandCode

A

Sr

Slave Address

Rd

A

8

1

8

1

8

1

Byte Count N

A

Data Byte 0

A

- - - - -

Data Byte N–1

A

P

Figure 5. Block Read Protocol

Bit 7 (MSB)

Bit 6

Bit 0 (LSB)

P

S

A

P

t

W(SCLH)

W(SCLL)

t

f(SM)

t

r(SM)

V

IH(SM)

IL(SM)

SCLK

V

t

h(START)

t

su(SDATA)

t

su(START)

t

h(SDATA)

su(STOP)

t

f(SM)

(BUS)

t

r(SM)

V

IH(SM)

IL(SM)

SDATA

Figure 6. Timing Diagram Serial Control Interface

SMBus Hardware Interface

The following diagram shows how the CDCE706 clock synthesizer is connected to the SMBus. Note that the

current through the pullup resistors (R_p) must meet the SMBus specifications (min 100 µA, max 350 µA).

R

P

R

P

SMB Host

SDATA

CDCE706

9

SCLK

10

C

BUS

C

BUS

Figure 7. SMBus Hardware Interface

11

CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

Table 2. Register Configuration Command Bitmap

Adr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Byte 0

Byte 1

Byte 2

Byte 3

Revision Code

Vendor Identification

PLL1 Reference Divider M 9-Bit [7:0]

PLL1 Feedback Divider N 12-Bit [7:0]

PLL1 Mux

PLL2 Mux

PLL3 Mux

PLL1 Feedback Divider N 12-Bit [11:8]

PLL1 Ref

Dev M [8]

Byte 4

Byte 5

Byte 6

PLL2 Reference Divider M 9-Bit [7:0]

PLL2 Feedback Divider N 12-Bit [7:0]

PLL1 fvco

Selection

PLL2 fvco

Selection

PLL3 fvco

Selection

PLL2 Feedback Divider N 12-Bit [11:8]

PLL2 Ref

Dev M [8]

Byte 7

Byte 8

Byte 9

PLL3 Reference Divider 9-Bit M [7:0]

PLL3 Feedback Divider N [12-Bit 7:0]

PLL Selection for P0 (Switch A)

PLL Selection for P1 (Switch A)

Input Signal Source

PLL3 Feedback Divider N 12-Bit [11:8]

PLL3 Ref

Dev M [8]

Byte 10

Inp. Clock

Selection

Configuration Inputs S1

Configuration Inputs S0

Byte 11

Byte 12

Byte 13

Byte 14

Byte 15

Byte 16

Byte 17

Byte 18

Byte 19

PLL Selection for P3 (Switch A)

PLL Selection for P5 (Switch A)

PLL Selection for P2 (Switch A)

PLL Selection for P4 (Switch A)

Reserved

Power Down

Reserved

7-Bit Divider P0 [6:0]

7-Bit Divider P1 [6:0]

7-Bit Divider P2 [6:0]

7-Bit Divider P3 [6:0]

7-Bit Divider P4 [6:0]

7-Bit Divider P5 [6:0]

Y0 Inv. or

Non-Inv

Y0 Slew-Rate Control

Y1 Slew-Rate Control

Y2 Slew-Rate Control

Y3 Slew-Rate Control

Y4 Slew-Rate Control

Y5 Slew-Rate Control

Y0 Enable or

Low

Y0 Divider Selection (Switch B)

Y1 Divider Selection (Switch B)

Y2 Divider Selection (Switch B)

Y3 Divider Selection (Switch B)

Y4 Divider Selection (Switch B)

Y5 Divider Selection (Switch B)

Byte 20

Byte 21

Byte 22

Byte 23

Byte 24

Byte 25

Byte 26

Reserved

Y1 Inv. or

Non-Inv

Y1 Enable or

Low

Y2 Inv. or

Non-Inv

Y2 Enable or

Low

Y3 Inv. or

Non-Inv

Y3 Enable or

Low

Y4 Inv. or

Non-Inv

Y4 Enable or

Low

EEPIP [read

only]

Y5 Inv or

Non-Inv

Y5 Enable or

Low

EELOCK

Spread Spectrum (SSC) Modulation

Selection

Frequency Selection for SSC

EEWRITE

7-Bit Byte Count

Default Device Setting

The internal EEPROM of CDCE706 is pre-programmed with a factory default configuration as shown below. This

puts the device in an operating mode without the need to program it first. The default setting appears after power

is switched on or after a power-down/up sequence until it is re-programmed by the user to a different application

configuration. A new register setting is programmed via the serial SMBUS Interface.

A different default setting can be programmed upon customer request. Contact a Texas Instruments sales or

marketing representative for more information.

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

f

= 245.76 MHz

Output Switch Matrix

VCO1

PLL1

Divider M

225

Y0

PFD

Filter

VCO

LV

CMOS

P0−Div

2

122.88 MHz

(3G RF Card))

MUX

Y1

Divider N

2048

LV

CMOS

30.72 MHz

(3G Baseband)

P1−Div

8

CLK_IN0

CLK_IN1

f

= 120 MHz

VCO2

XO

or

2 LVCMOS

PLL2

w/SSC

Y2

Y3

LV

CMOS

60 MHz (SSC off

(DSP)

P2−Div

2

27 MHz

Crystal

Divider M

9

or

Differential

Input

PFD

Filter

VCO

MUX

Divider N

40

60 MHZ (SSC on)

(DSP)

LV

CMOS

P3−Div

2

SSC

SO/AO/CLK_SEL

S1/A1

f

= 225.792 MHz

VCO2

Y4

Y5

LV

CMOS

P4−Div

10

22.5792 MHz

(Audio)

EEPROM

LOGIC

PLL3

Divider M

375

SMBus

SDATA

PFD

Filter

VCO

SCLOCK

27 MHz

(Video)

LV

CMOS

MUX

P5−Div

1

Divider N

3136

PLL Bypass

NOTE: All outputs are enabled and in non-inverting mode. S0, S1, and SSC comply according the default setting described in

Byte 10 and Byte 25 respectively.

Figure 8. Default Device Setting

The output frequency can be calculated:

27 MHz 3136

fin

M P

N

fout +

, i.e. fout +

+ 22.5792 MHz

(375 10)

(1)

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Functional Description of the Logic

All Bytes are read-/write-able, unless otherwise expressly mentioned.

Byte 0 (read only): Vendor Identification Bits [3:0]; Revision Code Bit [7:4]

Revision Code

Vendor Identification

0

1

Byte 1 to 9: Reference Divider M of PLL1, PLL2, PLL3⁽¹⁾

M8

0

M7

0

M6

0

M5

0

M4

0

M3

0

M2

0

M1

0

M0

0

Div by

Default⁽²⁾⁽³⁾

Not allowed

0

1

2

3

0

1

0

1

•

1

0

1

0

1

509

510

511

(1) By selecting the PLL divider factors, M ≤ N and 80 MHz ≤ fvco ≤ 300 MHz.

(2) Unless customer specific setting.

(3) Default setting of divider M for PLL1 = 225, for PLL2 = 9 and for PLL3 = 375.

Byte 1 to 9: Feedback Divider N of PLL1, PLL2, PLL3⁽¹⁾

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

Div by

Default⁽²⁾⁽³⁾

0

Not

allowed

0

1

0

1

2

3

•

1

0

1

0

1

4093

4094

4095

(1) By selecting the PLL divider factors, M ≤ N and 80 MHz ≤ fvco ≤ 300 MHz.

(2) Unless customer specific setting.

(3) Default setting of divider N for PLL1 = 1024, for PLL2 = 40 and for PLL3 = 1568.

Byte 3 Bit [7:5]: PLL (VCO) Bypass Multiplexer

PLLxMUX

PLL (VCO) MUX Output

PLLx

Default⁽¹⁾

0

1

Yes

VCO bypass

(1) Unless customer specific setting.

Byte 6 Bit [7:5]: VCO Frequency Selection Mode for each PLL⁽¹⁾

PLLxFVCO

VCO Frequency Range

Default⁽²⁾

0

1

80-200 MHz

Yes

180-300 MHz

(1) This bit selects the normal-speed mode or the high-speed mode for the dedicated VCO in PLL1, PLL2 or PLL3. At power-up the

normal-speed mode is selected, fvco is 80-200 MHz. In case of higher fvco, this bit has to be set to [1].

(2) Unless customer specific setting.

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Byte 9 to 12: Outputs Switch Matrix (5x6 Switch A) PLL Selection for P-Divider P0-P5

SWAPx2

SWAPx1

SWAPx0

Any Output Px

Default⁽¹⁾

P5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PLL bypass (input clock)

PLL1

P0, P1

P2

PLL2 non-SSC

PLL2 w/ SSC⁽²⁾

PLL3

P3

P4

Reserved

(1) Unless customer specific setting.

(2) PLL2 has a SSC output and non-SSC output. If SSC bypass is selected (see Byte 25, Bit [6:4]), the SSC circuitry of PLL2 is

powered-down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used.

Byte 10, Bit [1:0]: Configuration Settings of Input S0/A0/CLK_SEL

S01

S00

Function

Default⁽¹⁾

If S0 is low, the PLLs and the clock-input stage are going into power-down mode, outputs are in

3-state, all actual register settings will be maintained, SMBus stays active

Yes

0

(2)

If S0 is low, the PLL and all dividers (M-Div and P-Div) are bypassed and PLL is in power-down,

all outputs are active (inv. or non-inv.), actual register settings will be maintained, SMBus stays

active; this mode is useful for production test;

0

1

CLK_SEL (input clock selection — overwrites the CLK_SEL setting in Byte 10, Bit [4])⁽³⁾

— CLK_SEL is set low selects CLK_IN_IN0

— CLK_SEL is set high selects CLK_IN_IN1

1

0

1

In this mode, the control input S0 is interpreted as address bit A0 of the slave receiver address

byte⁽⁴⁾

(1) Unless customer specific setting.

(2) Power-down mode overwrites 3-state or low-state of S1 setting in Byte 10, Bit [3:2].

(3) If the clock input (CLK_IN0/CLK_IN1) is selected as crystal input or differential clock input (Byte 11, Bit [7:6]) then this setting is not

relevant.

(4) To use this pin as Slave Receiver Address Bit A0, an Initialization pattern needs to be sent to CDCE706. When S00/S01 is set to be 1,

the S0 input pin will be interpreted in the next read or write cycle as the Address Bit A0 of the Slave Receiver Address Byte. Note that

right after the Byte 10 (S00/S01) has been written, A0 (via S0-pin) will immediately be active (also when Byte 10 is sent within a block

write sequence). After the Initialization each CDCE706 has its own S0 dependent Slave Receiver Address and can be addressed

accordingly to their new valid address.

Byte 10, Bit [3:2]: Configuration Settings of Input S1/A1

S11

0

S10

0

Function

If S1 is set low, all outputs are switched to a low-state (non-inv.) or high-state (inv.);

If S1 is set low, all outputs are switched to a 3-state

Reserved

Default⁽¹⁾

Yes

0

1

0

In this mode, the control input S1 is interpreted as Address Bit A1 of the Slave Receiver Address

Byte⁽²⁾

1

(1) Unless customer specific setting.

(2) To use this pin as Slave Receiver Address Bit A1, an Initialization pattern needs to be sent to CDCE706. When S10/S11 is set to be 1,

the S1 input pin will be interpreted in the next read or write cycle as the Address Bit A1 of the Slave Receiver Address Byte. Note that

right after the Byte 10 (S10/S11) has been written, A1 (via S1-pin) will immediately be active (also when Byte 10 is sent within a block

write sequence). After the Initialization each CDCE706 has its own S1 dependent Slave Receiver Address and can be addressed

accordingly to their new valid address.

Byte 10, Bit [4]: Input Clock Selection⁽¹⁾

CLKSEL

Input Clock

CLK_IN0

Default⁽²⁾

0

1

Yes

CLK_IN1

(1) This bit is not relevant, if crystal input or differential clock input is selected, Byte 11, Bit [7:6].

(2) Unless customer specific setting.

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

Byte 11, Bit [7:6]: Input Signal Source⁽¹⁾

IS1

IS0

Function

Default⁽²⁾

0

CLK_IN0 is Crystal Oscillator Input and CLK_IN1 is serving as Crystal Oscillator Output.

Yes

CLK_IN0 and CLK_IN1 are two LVCMOS Inputs. CLK_IN0 or CLK_IN1 are selectable via

CLK_SEL control pin.

0

1

0

1

CLK_IN0 and CLK_IN1 serve as differential signal inputs.

Reserved

(1) In case the crystal input or differential clock input is selected, the input clock selection, Byte 10, Bit [4], is not relevant.

(2) Unless customer specific setting.

Byte 12, Bit [6]: Power-Down Mode (except SMBus)

PD

0

Power-Down Mode

Normal Device Operation

Power Down⁽²⁾

Default⁽¹⁾

Yes

1

(1) Unless customer specific setting.

(2) In power down, all PLLs and the Clock-Input-Stage are going into power-down mode, all outputs are in 3-State, all actual register

settings will be maintained and SMBus stays active. Power-Down Mode overwrites 3-State or Low-State of S0 and S1 setting in Byte 10.

Byte 13 to 18, Bit [6:0]: Outputs Switch Matrix - 6x7-Bit Divider P0-P5

DIVYx6

DIVYx5

DIVYx4

DIVYx3

DIVYx2

DIVYx1

DIVYx0

Div by

Default⁽¹⁾⁽²⁾

0

1

0

1

0

Not allowed

1

2

•

1

0

1

0

1

125

126

127

(1) Unless customer specific setting.

(2) Default setting of divider P0 = 1, P1 = 4, P2 = 2, P3 = 2, P4 = 5, and P5 = 1

Byte 19 to 24, Bit [5:4]: LVCMOS Output Rise/Fall Time Setting at Y0-Y5

SRCYx1

SRCYx0

Yx

Default⁽¹⁾

0

1

0

1

0

1

Nominal +2 ns (t_r0/t_f0)

Nominal +1 ns (t_r1/t_f1)

Nominal (t_r2/t_f2)

Yes

Nominal –1 ns (t_r3/t_f3)

(1) Unless customer specific setting.

Byte 19 to 24, Bit [2:0]: Outputs Switch Matrix (6 x 6 Switch B) Divider (P0-P5) Selection for Outputs Y0-Y5

SWBYx2

SWBYx1

SWBYx0

Any Output Yx

Divider P0

Divider P1

Divider P2

Divider P3

Divider P4

Divider P5

Reserved

Default⁽¹⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Y0

Y1

Y2

Y3

Y4

Y5

Reserved

(1) Unless customer specific setting.

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CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

Byte 19 to 24, Bit [3]: Output Y0-Y5 Enable or Low-State

ENDISYx

Output Yx

Disable to low

Enable

Default⁽¹⁾

0

1

Yes

(1) Unless customer specific setting.

Byte 19 to 24, Bit [6]: Output Y0-Y5 Non-Inverting/Inverting

INVYx

Output Yx Status

Non-inverting

Inverting

Default⁽¹⁾

0

1

Yes

(1) Unless customer specific setting.

Byte 24, Bit [7] (read only): EEPROM Programming In Process Status⁽¹⁾

EEPIP

Indicate EEPROM Write Process

No programming

Programming in process

Default

0

1

(1) This read only Bit indicates an EEPROM write process. It is set to high if programming starts and resets to low if programming is

completed. Any data written to the EEPIP-Bit will be ignored. During programming, no data are allowed to be sent to the device via the

SMBus until the programming sequence is completed. Data, however, can be readout during the programming sequence (Byte Read or

Block Read).

Byte 25, Bit [3:0]: SSC Modulation Frequency Selection in the Range of 30 kHz 60 kHz⁽¹⁾

FSSC3 FSSC2 FSSC1

FSSC0

Modulation

Factor

f_vco[MHz

130

Default⁽²⁾

100

17.6

18.5

19.4

20.5

21.7

23.0

24.6

26.3

28.3

30.4

33.3

36.6

40.6

45.5

51.9

60.2

110

19.4

20.3

21.4

22.6

23.9

25.3

27.0

28.9

31.1

33.5

36.7

40.3

44.6

50.1

57.1

66.3

120

21.1

22.2

23.3

24.6

26.0

27.6

29.5

31.5

33.9

36.5

40.0

43.9

48.7

54.6

62.2

72.3

140

24.6

25.9

27.2

28.7

30.4

32.3

34.4

36.8

39.6

42.6

46.7

51.2

56.8

63.8

72.6

84.3

150

26.4

27.7

29.2

30.8

32.6

34.6

36.8

39.4

42.4

45.6

50.0

54.9

60.9

68.3

77.8

90.4

160

28.2

29.6

31.1

32.8

34.7

36.9

39.3

42.1

45.2

48.7

53.3

58.6

64.9

72.9

83.0

167

29.4

30.9

32.5

34.2

36.2

38.5

41.0

43.9

47.2

50.8

55.7

61.1

67.8

76.0

86.6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5680

5412

5144

4876

4608

4340

4072

3804

3536

3286

3000

2732

2464

2196

1928

1660

f_mod

[kHz]

22.9

24.0

25.3

26.7

28.2

30.0

31.9

34.2

36.8

39.6

43.3

47.6

52.8

59.2

67.4

78.3

Yes

96.4 100.6

(1) The PLL has to be bypassed (turned off) when changing SSC Modulation Frequency Factor on-the-fly. This can be done by following

programming sequence: bypass PLL2 (Byte 3, Bit 6 = 1); write new Modulation Factor (Byte 25); re-activate PLL2 (Byte 3, Bit 6 = 0).

(2) Unless customer specific setting.

(1)

Byte 25, Bit [6:4]: SSC Modulation Amount

SSC2

SSC1

SSC0

Function

Default⁽²⁾

0

1

0

1

0

1

0

1

0

SSC Modulation Amount 0% = SSC bypass for PLL⁽³⁾

SSC Modulation Amount ±0.1% (center spread)

SSC Modulation Amount ±0.25% (center spread)

SSC Modulation Amount ±0.4% (center spread)

SSC Modulation Amount 1% (down spread)

Yes

(1) The PLL has to be bypassed (turned off) when changing SSC Modulation Amount on-the-fly. This can be done by following

programming sequence: bypass PLL2 (Byte 3, Bit 6 = 1); write new Modulation Amount (Byte 25); re-activate PLL2 (Byte 3, Bit 6 = 0).

(2) Unless customer specific setting.

(3) If SSC bypass is selected, SSC circuitry of PLL2 is powered-down and the SSC output is reset to logic low. The non-SSC output of

PLL2 is not affected by this mode and can still be used.

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(1)

Byte 25, Bit [6:4]: SSC Modulation Amount

SSC2

SSC1

SSC0

Function

Default⁽²⁾

1

0

1

0

1

SSC Modulation Amount 1.5% (down spread)

SSC Modulation Amount 2% (down spread)

SSC Modulation Amount 3% (down spread)

Byte 25, Bit [7]: Permanently Lock EEPROM-Data

(1)

EELOCK

Permanently Lock EEPROM

Default⁽²⁾

Yes

0

1

No

Yes

(1) If this bit is set, the actual data in the EEPROM will be permanently locked. There is no further programming possible, even this bit is set

low. Data, however can still be written via SMBUS to the internal register to change device function on the fly. But new data no longer

can be stored into the EEPROM.

(2) Unless customer specific setting.

Byte 26, Bit [6:0]: Byte Count⁽¹⁾

BC6

BC5

BC4

BC3

BC2

BC1

BC0

No. of Bytes

Default⁽²⁾

0

1

0

1

0

1

Not allowed

1

2

3

•

0

1

0

1

27

Yes

•

1

0

1

0

1

125

126

127

(1) Defines the number of Bytes, which will be sent from this device at the next Block Read protocol.

(2) Unless customer specific setting.

Byte 26, Bit [7]: Initiate EEPROM Write Cycle⁽¹⁾

EEWRITE

Starts EEPROM Write Cycle

Default⁽²⁾

Yes

0

1

No

Yes

(1) The EEPROM WRITE cycle is initiated with the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE

cycle. This bit stays high until the user reset it to low (it will not automatically be reset after the programming has been completed).

Therefore, to initiate an EEPROM WRITE cycle, it is recommended to send a zero-one sequence to the EEWRITE bit in Byte 26.

During EEPROM programming, no data are allowed to be sent to the device via the SMBus until the programming sequence has been

completed. Data, however, can be readout during the programming sequence (Byte Read or Block Read). The programming status can

be monitored by readout EEPIP, Byte 24–Bit 7. If EELOCK is set, no EEPROM programming will be possible.

(2) Unless customer specific setting.

FUNCTIONAL DESCRIPTION

Clock Inputs (CLK_IN0 and CLK_IN1)

The CDCE706 features two clock inputs which can be used as:

•

Crystal oscillator input (default setting)

Two independent single-ended LVCMOS inputs

Differential signal input

The dedicated clock input can be selected by the input signal source Bit [7:6] of Byte 11.

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Crystal Oscillator Inputs

The input frequency range in crystal mode is 8 MHz to 54 MHz. The CDCE706 uses a Pierce-type oscillator

circuitry with included feedback resistance for the inverting amplifier. The user, however, has to add external

calculated:

C_X0= C_X1= 2 × C_L– C_ICB

,

where C_Lis the crystal load capacitor as specified for the crystal unit and C_ICBis the input capacitance of the

device including the board capacitance (stray capacitance of PCB).

For example, for a fundamental 27-MHz crystal with C_Lof 9 pF and C_ICBof 4 pF,

C_X0= C_X1= (2 × 9 pF) – 4 pF = 14 pF.

It is important to use a short PCB trace from the device to the crystal unit to keep the stray capacitance of the

oscillator loop to a minimum.

Input source select

(from EEPROM)

CLK_IN0

C_ICB

XO

or

C_X0

crystal

unit

2LVCMOS

or

Differential

Input

CLK_IN1

C_ICB

C_X1

Figure 9. Crystal Input Circuitry

In order to ensure a stable oscillating, a certain drive power must be applied. The CDCE706 features an input

oscillator with adaptive gain control which relieves the user to manually program the gain. The drive level is the

amount of power dissipated by the oscillating crystal unit and is usually specified in terms of power dissipated by

the resonator (equivalent series resistance (ESR)). Figure 10 gives the resulting drive level vs crystal frequency

and ESR.

100

C = 18 pF

ERS = 60 W

90

80

70

60

50

40

30

20

10

0

U

pk

= 300 mV

ERS = 50 W

ERS = 40 W

ERS = 30 W

ERS = 25 W

ERS = 15 W

~21 mW

5

10

15

20

25

30

35

40

45

50

55

Frequency − MHz

Figure 10. Crystal Drive Power

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For example, if a 27-MHz crystal with ESR of 50 Ω is used and 2 × C_Lis 18 pF, the drive power is 21 µW. Drive

level should be held to a minimum to avoid over driving the crystal. The maximum power dissipation is specified

for each type of crystal in the oscillator specifications, i.e., 100 µW for the example above.

Single-Ended LVCMOS Clock Inputs

When selecting the LVCMOS clock mode, CLK_IN0 and CLK_IN1 act as regular clock inputs pins and can be

driven up to 200 MHz. Both clock inputs circuitry are equal in design and can be used independently to each

other (see Figure 11). The internal clock select bit, Byte 10, Bit [4], selects one of the two input clocks. CLK_IN0

is the default selection. There is also the option to program the external control pin S0/A0/CLK_SEL as clock

select pin, Byte 10, Bit [1:0].

The two clock inputs can be used for redundancy switching, i.e. to switch between a primary clock and

secondary clock. Note a phase difference between the clock inputs may require PLL correction. Also in case of

different frequencies between the primary and secondary clock, the PLL has to re-lock to the new frequency.

CLK_IN0

XO

or

2LVCMOS

or

Differential

CLK_IN1

input

(A)

CLK_SEL

A. CLK_SEL is optional and can be configured by EEPROM setting.

Figure 11. LVCMOS Clock Input Circuitry

Differential Clock Inputs

The CDCE706 supports differential signaling as well. In this mode, CLK_IN0 and CLK_IN1 pin serve as

differential signal inputs and can be driven up to 200 MHz.

The minimum magnitude of the differential input voltage is 400mV over a differential common-mode input voltage

range of 300 mV to V_CC– 1. If LVDS or LVPECL signal levels are applied, ac-coupling and a biasing structure is

recommended to adjust the different physical layers (see Figure 12). The capacitor removes the dc component of

the signal (common-mode voltage), while the ac component (voltage swing) is passed on. A resistor pull-up

and/or pull-down network represents the biasing structure used to set the common-mode voltage on the receiver

side of the ac-coupling capacitor.

Input source select

(from EEPROM)

CLK_IN0

XO

or

2LVCMOS

or

Differential

CLK_IN1

input

Figure 12. Differential Clock Input Circuitry

PLL Configuration and Setting

The CDCE706 includes three PLLs which are equal in function and performance. Except PLL2 which in addition

supports spread spectrum clocking (SSC) generation. Figure 13 shows the block diagram of the PLL.

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CDCE706

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VCO Bypass

PLLx

9−Bit Divider M

1 .. 511

Input Clock

PFD

Filter

VCO

MUX

PLL output

12−Bit Divider N

1 .. 4095

SSC output

(PLL2 Only)

SSC

(PLL2 only)

Programming

Figure 13. PLL Architecture

All three PLLs are designed for easiest configuration. The user just has to define the input and output

frequencies or the divider (M, N, P) setting respectively. All other parameters, such as charge-pump current, filter

components, phase margin, or loop bandwidth are controlled and set by the device itself. This assures optimized

jitter attenuation and loop stability.

The PLL support normal-speed mode (80 MHz ≤ f_VCO≤ 167 MHz) and high-speed mode (150 MHz ≤ f_VCO≤ 300

MHz) which can be selected by PLLxFVCO (Bit [7:5] of Byte 6). The respective speed option assures stable

operation and lowest jitter.

The divider M and divider N operates internally as fractional divider for f_VCOup to 250 MHz. This allows fractional

divider ratio for zero ppm output clock error.

In case of f_VCO> 250 MHz, it is recommended that integer factors of N/M are used only.

For optimized jitter performance, keep divider M as small as possible. Also, the fractional divider concept

requires a PPL divider configuration, M ≤ N (or N/M ≥ 1).

Additionally, each PLL supports two bypass options:

•

PLL Bypass and

VCO Bypass

In PLL bypass mode, the PLL completely is bypassed, so that the input clock is switched directly to the

Output-Switch-A (SWAPxx of Byte 9 to12). In the VCO bypass mode, only the VCO of the respective PLL is

bypassed by setting PLLxMUX to 1 (Bit [7:5] of Byte 3). But the divider M still is useable and expands the output

divider by additional 9-bits. This gives a total divider range of M x P = 511 × 127 = 64897. In VCO bypass mode

the respective PLL block is powered down and minimizes current consumption.

Table 3. Example for Divide, Multiplication, and Bypass Operation

Function

Fractional⁽²⁾

Equation⁽¹⁾

f_IN

[MHz]

f_OUT-desired

[MHz]

f_OUT-actual

[MHz]

Divider

f_VCO[MHz]

M

16

1

N

P

1

N/M

5.0625

10

f_OUT= f_INx (N/M)/P

f_OUT= f_IN/(M x P)

30.72

27

155.52

270

155.52

270

81

10

—

155.52

270

Integer Factor⁽³⁾

1

VCO bypass

30.72

0.06

8

64

—

(1) P-divider of Output-Switch-Matrix is included in the calculation.

(2) Fractional operation for f_VCO≤ 250 MHz.

(3) Integer operation for f_VCO> 250 MHz.

Spread Spectrum Clocking and EMI Reduction

In addition to the basic PLL function, PLL2 supports spread spectrum clocking (SSC) as well. Thus, PLL 2

features two outputs, a SSC output and a non-SSC output. Both outputs can be used in parallel. The mean

phase of the Center Spread SSC modulated signal is equal to the phase of the non-modulated input frequency.

SSC is selected by Output-Switch-A (SWAPxx of Byte 9 to 12).

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SSC also is bypass-able (Byte 25, Bit [6:4]), which powers-down the SSC output and set it to logic low state. The

non-SSC output of PLL2 is not affected by this mode and can still be used.

SSC is an effective method to reduce electro-magnetic interference (EMI) noise in high-speed applications. It

reduces the RF energy peak of the clock signal by modulating the frequency and spread the energy of the signal

to a broader frequency range. Because the energy of the clock signal remains constant, a varying frequency that

broadens the overtones necessarily lowers their amplitudes. Figure 14 shows the effect of SSC on a 54-MHz

clock signal for DSP

+

Down Spread 3%

9^thHarmonic, fm = 60 kHz

Center Spread 0.4%

9^thHarmonic, fm = 60 kHz

7ddBB

111.3.3dBdB

Figure 14. Spread Spectrum Clocking With Center Spread and Down Spread

The peak amplitude of the modulated clock is 11.3 dB lower than the non-modulated carrier frequency for down

spread and radiated less electro-magnetic energy.

In SSC mode, the user can select the SSC modulation amount and SSC modulation frequency. The modulation

amount is the frequency deviation based to the carrier (min/max frequency), whereas the modulation frequency

determines the speed of the frequency variation. In SSC mode, the maximum VCO frequency is limited to 167

MHz.

SSC Modulation Amount

The CDCE706 supports center spread modulation and down spread modulation. In center spread, the clock is

symmetrically shifted around the carrier frequency and can be ±0.1%, ±0.25%, and ±0.4%. At down spread, the

clock frequency is always lower than the carrier frequency and can be 1%, 1.5%, 2%, and 3%. The down spread

is preferred if a system can not tolerate an operating frequency higher than the nominal frequency (over-clocking

problem).

Example:

Modulation Type

Minimum

Frequency

Center

Frequency

Maximum

Frequency

A

B

C

±0.25% center spread

53.865 MHz

53.46 MHz

53.73 MHz

54 MHz

—

54.135 MHz

54 MHz

1% down spread

0.5% down spread⁽¹⁾

53.865 MHz

54 MHz

(1) A down spread of 0.5% of a 54-MHz carrier is equivalent to 59.865 MHz at a center spread of ±0.25%.

SSC Modulation Frequency

The modulation frequency (sweep rate) can be selected between 30 kHz and 60 kHz. It also based on the VCO

frequency as shown in the SSC Modulation Frequency Selection as shown on page 17. As shown in Figure 15,

the damping increases with higher modulation frequencies. It may be limited by the tracking skew of a

downstream PLL. The CDCE706 uses a triangle modulation profile which is one of the common profiles for SSC.

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

12

11

10

9

3% Down Spread

2% Down Spread

8

+ 0.4 Center Spread

+ 0.25 Center Spread

7

6

5

4

3

30

40

50

60

fmodulation − kHz

Figure 15. EMI Reduction vs f_Modulationand f_Amount

Further EMI Reduction

The optimum damping is a combination of modulation amount, modulation frequency and the harmonics which

are considered. Note that higher order harmonic frequencies results in stronger EMI reduction because of

respective higher frequency deviation.

As seen in Figure 16 and Figure 17, a slower output slew rate and/or smaller output signal amplitude helps to

reduce EMI emission even more. Both measures reduce the RF energy of clock harmonics. The CDCE706

allows slew rate control in four steps between 0.6 ns and 3.3 ns (Byte 19-24, Bit [5:4]). The output amplitude is

set by the two independent output supply voltage pins, V_CCOUT1and V_CCOUT2, and can vary from 2.3 V to 3.6 V.

Even a lower output supply voltage down to 1.8 V works, but the maximum frequency has to be considered.

Slew−Rate for Vccout = 2.5 V

Slew−Rate for Vccout = 3.3 V

−2.5dB

5.6dB

−3dB

6.4dB

7dB

11.3dB

nom−1

nom

nom−1

nom

nom+2

Figure 16. EMI Reduction vs Slew-Rate and V_ccout

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

5

4

3

2

1

0

−1

2.5 V

3 V

3.6 V

V

CCOUT

Figure 17. EMI Reduction vs V_ccout

Multi-Function Control Inputs S0 and S1

The CDCE706 features two user definable inputs pins which can be used as external control pins or address

pins. When programmed as control pins, they can function as clock select pin, enable/disable pin or device

power-down pin. If both pins used as address-bits, up to four devices can be connected to the same SMBus. The

respective function is set in Byte 10; Bit [3:0]. Table 4 shows the possible setting for the different output

conditions, clock select and device addresses.

Table 4. Configuration Setting of Control Inputs

Configuration Bits

External Control Pins

Device Function

Byte 10,

Bit [3:2]

Byte 10,

Bit [1:0]

S11

S10

S01

S00

S1

(Pin 2)

S0

(Pin 1)

Yx Outputs

Power

Down

Pin 2

Pin 1

0

X

0

X

0

1

0

X

0

1

0

Active

Low/High⁽¹⁾

3-State

No

Output ctrl

1

Outputs only

PLL, inputs and outputs

PLL only

Output ctrl

X

3-State

Output ctrl and pd

PLL and Div bypass

1

S10=0: low/high⁽¹⁾

S10=1: 3-State

0

X

0

1

0

1

0

Active

PLL only

No

Output ctrl

PLL and Div bypass

CLK_SEL

0/1⁽²⁾

S10=0: Low/High⁽¹⁾

S10=1: 3-State

0

1

X

1

0

1

0/1⁽²⁾

X

Active

No

Output ctrl

A1⁽³⁾

CLK_SEL

A0⁽³⁾

X

(1) A non-inverting output will be set to low and an inverting output will be set to high.

(2) If S0 is 0, CLK_IN0 is selected; if S0 is 1, CLK_IN1 is selected.

(3) S0 and S1 are interpreted as Address Bit A0 and A1 of the Slave Receiver Address Byte.

As shown in Table 4, there is a specific order of the different output condition: Power-down mode overwrites

3-state, 3-state overwrites low-state, and low-state overwrites active-state.

Output Switching Matrix

The flexible architecture of the output switch matrix allows the user to switch any of the internal clock signal

sources via a free-selectable post-divider to any of the six outputs.

As shown in Figure 18, the CDCE706 is based on two banks of switches and six post-dividers. Switch A

comprises six 5-Input-Muxes which selects one of the four PLL clock outputs or directly selects the input clock

and feed it to one of the 7-bit post-divider (P-Divider). Switch B is made up of six 6-Input-Muxes which takes any

post-divider and feeds it to one of the six outputs, Yx.

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Switch B was added to the output switch matrix to ensure that outputs frequencies derive from one P-divider are

100% phase aligned. Also, the P-divider is built in a way that every divide factor is automatically duty-cycle

corrected. Changing the divider value on the fly may cause a glitch on the output.

Internal Clock Sources

Output Switch Matrix

7-Bit Divider

Outputs

5x6 − Switch A

6x6 − Switch B

P0

Y0

Y1

Y2

Y3

Y4

Y5

(1..127)

Input CLK

(PLL Bypass)

P1

(1..127)

PLL 1

P2

(1..127)

PLL 2

non SSC

P3

(1..127)

P4

(1..127)

PLL 2

w/ SSC

P5

(1..127)

PLL 3

Programming

Output Selection:

Active/Low/3-State/

PLL/Input_Clk

Selection

P-Divider

Setting

P-Divider

Selection

Inverting/Non-Inverting

Slew Rate/V

CCOUT

Figure 18. CDCE706 Output Switch Matrix

In addition, the outputs can be switched active, low or 3-state and/or 180 degree phase shifted. Also the outputs

slew-rate and the output-voltage is user selectable.

LVCMOS Output Configuration

The output stage of the CDCE706 supports all common output setting, such as enable, disable, low-state and

signal inversion (180 degree phase shift). It further features slew-rate control (0.6 ns to 3.3 ns) and variable

output supply voltage (2.3 V to 3.6 V).

Clock

V

/V

CCOUT1 CCOUT2

div by 3

Inverting

P−div(0) output

P−div(1) output

P−div(2) output

P−div(3) output

P−div(4) output

P−div(5) output

M

U

X

Buffer

Sel

Yx

S1

Slew Rate

P−Divider Select

Inversion Select

Slew-Rate Control

Low Select

Enable/Disable

(Optional all

outputs low

or 3−State)

Enable/Disable

Figure 19. Block Diagram of Output Architecture

Figure 20. Example for Output Waveforms

All output settings are programmable via SMBus:

•

enable, disable, low-state via external control pins S0 and S1 → Byte 10, Bit[3:0]

enable or disable-to-low → Byte 19 to 24, Bit[3]

inverting/non-inverting → Byte 19 to 24, Bit[6]

slew-rate control → Byte 19 to 24, Bit[5:4]

output swing → external pins V_CCOUT1(Pin 14) and V_CCOUT2(Pin 18)

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Performance Data: Output Skew, Jitter, Cross Coupling, Noise Rejection (Spur-Suppression),

and Phase Noise

Output Skew

Skew is an important parameter for clock distribution circuits. It is defined as the time difference between outputs

that are driven by the same input clock. Table 5 shows the output skew (t_sk(o)) of the CDCE706 for high-to-low

and low-to-high transitions over the entire range of supply voltages, operating temperature and output voltage

swing.

Table 5. Output Skew

PARAMETER

V_ccout

2.5 V

3.3 V

TYP

130

MAX

250

UNIT

ps

t_sk(o)

200

ps

Jitter Performance

Jitter is a major parameter for PLL-based clock driver circuits. This becomes important as speed increases and

timing budget decreases. The PLL and internal circuits of CDCE706 are designed for lowest jitter. The

peak-to-peak period jitter is only 60 ps (typical). Table 6 gives the peak-to-peak and rms deviation of

cycle-to-cycle jitter, period jitter and phase jitter as taken during characterization.

Table 6. Jitter Performance of CDCE706

PARAMETER

f_out

TYP⁽¹⁾

MAX⁽¹⁾

UNIT

Peak-Peak

rms

Peak-Peak

rms

(one sigma)

t_jit(cc)

50 MHz

133 MHz

245.76 MHz

50 MHz

55

50

–

75

85

–

ps

45

–

60

–

t_jit(per)

60

4

76

7

ps

133 MHz

245.76 MHz

50 MHz

55

5

84

11

8

50

4

72

t_jit(phase)

730

930

720

90

130

90

840

1310

930

115

175

125

133 MHz

245.76 MHz

(1) All typical and maximum values are at V_CC= 3.3 V, temperature = 25°C, V_ccout= 3.3 V; one output is switching, data taken over several

10000 cycles.

Figure 21, Figure 22, and Figure 23 show the relationship between cycle-to-cycle jitter, period jitter, and phase

jitter over 10000 samples. The jitter varies with a smaller or wider sample window. The cycle-to-cycle jitter and

period jitter show the measured value whereas the phase jitter is the accumulated period jitter.

Cycle-to-Cycle jitter (t_jit(cc)) is the variation in cycle time of a clock signal between adjacent cycles, over a random

sample of adjacent cycle pairs. Cycle-to-cycle jitter will never be greater than the period jitter. It is also known as

adjacent cycle jitter.

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40

30

20

10

0

−10

−20

−30

−40

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

Figure 21. Snapshot of Cycle-to-Cycle Jitter

Period jitter (t_jit(per)) is the deviation in cycle time of a clock signal with respect to the ideal period (1/fo) over a

random sample of cycles. In reference to a PLL, period jitter is the worst-case period deviation from the ideal that

would ever occur on the PLLs outputs. This is also referred to as short-term jitter.

25

20

15

10

5

0

−5

−10

−15

−20

−25

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

Figure 22. Snapshot of Period Jitter

Phase jitter (t_jit(phase)) is the long-term variation of the clock signal. It is the cumulative deviation in t(Θ) for a

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CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

controlled edge with respect to a t(Θ) mean in a random sample of cycles. Phase jitter, Time Interval Error (TIE),

or Wander are used in literature to describe long-term variation in frequency. As of ITU-T: G.810, wander is

defined as phase variation at rates less than 10 Hz while jitter is defined as phase variation greater than 10 Hz.

The measurement interval must be long enough to gain a meaningful result. Wander can be caused by

temperature drift, aging, supply voltage drift, etc.

300

250

200

150

100

50

0

−50

−100

−150

−200

−250

−300

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

Figure 23. Snapshot of Phase Jitter

Cross Coupling, Spur Suppression and Noise Rejection

Cross-Coupling in ICs occurs through interactions between several parts of the chip such as between output

stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive and resistive (ohmic)

induced by output switching, leakage current, ground bouncing, power supply transients, etc.

The CDCE706 is designed in BiCMOS process technology incorporating silicon-germanium (SiGe) technology.

This process gives excellent performance in linearity, low power consumption, best-in-class noise performance

and very good isolation characteristic between the on-chip components.

The good isolation was a major criteria to use BiCMOS process as it minimizes the coupling effect. Even if all

three PLLs are active and all outputs are on, the noise suppression is clearly above 50 dB. Figure 24 and

Figure 25 show an example of noise coupling, spur-suppression, and power supply noise rejection of CDCE706.

Die respective measurement conditions are shown in Figure 24 and Figure 25.

28

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

•

Measured Y1: 48 MHz

Y0 is 27 MHz (XTAL buffered ,loaded by 50O)

Y2 is 56.448 MHz (loaded by 50O)

Y3 is 33.33 MHz (loaded by 50O)

Y4, Y5 tri−stated

carrier

48MHz

2^ndharmonic

spur at

27MHz&54MHz

Figure 24. Noise Coupling and Spur Suppression

w Measured Y0: 48 MHz

w Y1, Y2, Y3, Y4 & Y5 tri−stated

w Inserted 30mV 1MHz @ Vcc = 3.3V

carrier

48MHz

carrier

48MHz

spurs at

47MHz&49MHz

spur 47MHz and

fundamental at 1MHz

Figure 25. Power Supply Noise Rejection

Phase Noise Characteristic

In high-speed communication systems, the phase noise characteristic of the PLL frequency synthesizer is of high

interest. Phase noise describes the stability of the clock signal in the frequency domain, similar to the jitter

specification in the time domain.

Phase noise is a result of random and discrete noise causing a broad slope and spurious peaks. The discrete

spurious components could be caused by known clock frequencies in the signal source, power line interference,

and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the

result of thermal noise, shot noise and/or flicker noise in active and passive devices.

Important factor for PLL synthesizer is the loop bandwidth (–3 dB cut-off frequency) — large LBW results in fast

transient response but have less reference spur attenuation. The LBW of the CDCE706 is about 100 kHz to 150

kHz, dependent on selected PLL parameter.

For the CDCE706, two phase noise characteristics are of interest: The phase noise of the crystal-input stage and

the phase noise of the internal PLL (VCO). The following Figure shows the respective phase noise characteristic.

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CDCE706

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SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005

foffset in Hz

10

100

1000

10000

100000

1000000

10000000

−50

−60

−70

Phase Noise Comparison

f_out135 MHz

f_VCO135 MHz vs. 270 MHz

CDCE706 f_out135 MHz

f_VC0135 MHz

−80

−90

CDCE706 f_out135 MHz

f_VC0270 MHz

−100

−110

−120

−130

−140

−150

CDCE706crystal 27 MHz

Figure 26. Phase Noise Characteristic

EVM and Programming SW

The CDCE706 comes with a development kit consisting of a performance evaluation module, the TI Pro Clock

software, and the User's Guide. Contact Texas Instruments sales or marketing representative for more

information.

30

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	CDCE706
厂家：	TEXAS INSTRUMENTS
描述：	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER 可编程3 -PLL时钟合成器/乘法器/除法器时钟
文件：	总32页 (文件大小：1632K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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