CDCLVD1213RGTT [TI]
1:4 Low Additive Jitter LVDS Buffer With Divider; 1 ： 4低附加抖动LVDS缓冲器，带有分频器
| 型号： | CDCLVD1213RGTT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1:4 Low Additive Jitter LVDS Buffer With Divider |
| 文件： | 总17页 (文件大小：717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCLVD1213
www.ti.com
SCAS897 –JULY 2010
1:4 Low Additive Jitter LVDS Buffer With Divider
Check for Samples: CDCLVD1213
1
FEATURES
DESCRIPTION
•
1:4 Differential Buffer
•
Low Additive Jitter: <300 fs RMS in 10-kHz to
20-MHz
The CDCLVD1213 clock buffer distributes an input
clock to 4 pairs of differential LVDS clock outputs with
low additive jitter for clock distribution. The input can
either be LVDS, LVPECL, or CML.
•
•
•
Low Output Skew of 20 ps (Max)
Selectable Divider Ratio 1, /2, /4
The CDCLVD1213 contains a high performance
divider for one output (QD) which can divide the input
clock signal by a factor of 1, 2, or 4.
Universal Input Accepts LVDS, LVPECL, and
CML
•
4 LVDS Outputs, ANSI EAI/TIA-644A Standard
Compatible
The CDCLVD1213 is specifically designed for driving
50 Ω transmission lines. The part supports a fail safe
function. The device incorporates an input hysteresis
which prevents random oscillation of the outputs in
the absence of an input signal.
•
•
•
•
•
Clock Frequency up to 800 MHz
2.375 V–2.625 V Device Power Supply
Industrial Temperature Range: –40°C to 85°C
Packaged in 3 mm × 3 mm 16-Pin QFN (RGT)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
The device operates in 2.5 V supply environment and
is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD1213 is packaged in
small 16-pin, 3-mm × 3-mm QFN package.
APPLICATIONS
•
•
•
•
•
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment
Wireless Communications
General Purpose Clocking
ASIC
PHY1
PHY2
156.25 MHz
CDCLVD1213
LVDS Buffer
with Divider
DIV
FPGA
Figure 1. Application Example
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CDCLVD1213
SCAS897 –JULY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
QP0
QN0
INP
INN
QP1
QN1
QP2
QN2
70 W
70 W
VT
VCC
QDP
QDN
/1 /2 /4
200 kW
DIV
200 kW
GND
Figure 2. CDCLVD1213 Block Diagram
RGT PACKAGE
(TOP VIEW)
12
11
10
9
13
14
15
16
8
7
6
5
QP1
QN1
QP2
QN2
VT
3mm x 3mm
16 pin QFN (RGT)
INP
INN
VCC
Thermal Pad
1
2
3
4
2
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SCAS897 –JULY 2010
PIN DESCRIPTIONS
CDCLVD1213 Pin Descriptions
PIN
TYPE
DESCRIPTION
NAME
NO.
5, 10
1, 9
VCC
Power
Ground
Input
2.5 V supply for the device
Device ground
GND
INP, INN
VT
7, 6
Differential input pair
8
Input
Input for threshold voltage
Differential divided LVDS output pair
Differential LVDS output pair no. 0
Differential LVDS output pair no. 1
Differential LVDS output pair no. 2
QDP, QDN
QP0, QN0
QP1, QN1
QP2, QN2
2,3
Output
Output
Output
Output
11,12
13,14
15,16
Input with an internal
200kΩ pull-up and
pull-down
DIV
4
Divider selection – selects divider ratio for QD output; (See Table 1)
See thermal management recommendations
Thermal Pad
Table 1. Divider Selection Table
DIV
0
DIVIDER RATIO
/1
/2
/4
open
1
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).(1)
VALUE
–0.3 to 2.8
UNIT
Supply voltage range, VCC
V
V
V
Input voltage range, VI
–0.2 to VCC +0.2
–0.2 to VCC+0.2
See Note(2)
>3000
Output voltage range, VO
Driver short circuit current , IOSD
Electrostatic discharge (Human Body Model 1.5 kΩ, 100 pF)
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The output can handle the permanent short.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
MIN
2.375
–40
TYP
MAX
2.625
85
UNIT
V
Device supply voltage, VCC
Ambient temperature, TA
2.5
°C
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UNITS
THERMAL INFORMATION
CDCLVD1213
THERMAL METRIC(1)
RGT(16 PINS)
qJA
Junction-to-ambient thermal resistance
51.3
85.4
20.1
1.3
qJC(top)
qJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
yJB
19.4
6
qJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIVIDER CONTROL INPUT (DIV) CHARACTERISTICS
VdI3
3-State
Open
0.5×VCC
V
V
VdIH
VdIL
Input high voltage
Input low voltage
Input high current
Input low current
Input pull-up/ pull-down resistor
0.7×VCC
0.2×VCC
30
V
IdIH
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
mA
mA
kΩ
IdIL
–30
Rpull(DIV)
200
DIFFERENTIAL INPUTS (INP, INN) CHARACTERISTICS
fIN
Input frequency
Clock input
800
1.6
MHz
VPP
Differential input voltage
peak-to-peak
VIN, DIFF
VICM = 1.25 V
0.3
1
VICM
RIN
Input common-mode voltage range
Input termination
VCC – 0.3
V
Ω
INP, INN to VT, DC
70
IIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
20% to 80%
10
mA
mA
V/ns
pF
IIL
Input low current
–10
ΔV/ΔT
CIN
Input edge rate
0.75
Input capacitance
2.5
4
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SCAS897 –JULY 2010
ELECTRICAL CHARACTERISTICS (continued)
At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVDS OUTPUT CHARACTERISTICS
|VOD
|
Differential output voltage magnitude
250
–15
450
15
mV
mV
Change in differential output voltage
magnitude
ΔVOD
VIN, DIFF, PP = 0.3V,
RL = 100 Ω
Steady-state common mode output
voltage
VOC(SS)
ΔVOC(SS)
1.1
1.375
15
V
Steady-state common mode output
voltage
VIN, DIFF, PP = 0.6V,
RL = 100 Ω
–15
mV
IOS
Short-circuit output current
Output ac common mode
VOD = 0 V
±24
70
mA
VOS
VIN, DIFF, PP = 0.6V, RL = 100 Ω
25
mVPP
Percentage of output amplitude
VOD
Vring
Output overshoot and undershoot
10%
tPD
Propagation delay
Part-to-part skew
VIN, DIFF, PP = 0.3 V
1.5
2.5
600
20
ns
ps
ps
tSK, PP
tSK, O
(1)
Output skew
Pulse skew (with 50% duty cycle
input)
Crossing-point-to-crossing-point
distortion
tSK,P
tRJIT
–50
50
50
ps
Random additive jitter (with 50% duty Edge speed 0.75V/ns
cycle input)
0.3 ps, RMS
10 kHz – 20 MHz
tR/tF
Output rise/fall time
Static supply current
20% to 80%,100 Ω, 5 pF
Outputs unterminated, f = 0 Hz
300
28
ps
ICCSTAT
17
40
mA
All outputs, RL = 100 Ω,
f = 100 MHz
ICC100
ICC800
Supply current
Supply current
58
85
mA
mA
All outputs, RL = 100 Ω,
f = 800 MHz
60
(1) Undivided outputs only.
Typical Additive Phase Noise Characteristics for 100 MHz Clock
PARAMETER
MIN
TYP
-132.9
-138.8
-147.4
-153.6
-155.2
-156.2
-156.6
171
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs, RMS
phn100
phn1k
Phase noise at 100 Hz offset
Phase noise at 1 kHz offset
phn10k
phn100k
phn1M
phn10M
phn20M
tRJIT
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
Phase noise at 20 MHz offset
Random additive jitter from 10 kHz to 20 MHz
Typical Additive Phase Noise Characteristics for 737.27 MHz Clock
PARAMETER
MIN
TYP
-80.2
-114.3
-138
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs, RMS
phn100
phn1k
Phase noise at 100 Hz offset
Phase noise at 1 kHz offset
phn10k
phn100k
phn1M
phn10M
phn20M
tRJIT
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
Phase noise at 20 MHz offset
Random additive jitter from 10 kHz to 20 MHz
-143.9
-145.2
-146.5
-146.6
65
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TYPICAL CHARACTERISTICS
INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES
vs
FREQUENCY FROM THE CARRIER (TA = 25°C and VCC = 2.5V)
Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs
Figure 3. 100 MHz Input and Output Phase Noise Plot
Differential Output Voltage
vs
Frequency
350
340
330
320
310
300
290
280
270
260
250
T
= 25oC
A
2.625V
2.5V
2.375V
0
100 200 300 400 500 600 700 800
Frequency − MHz
Figure 4.
6
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SCAS897 –JULY 2010
TEST CONFIGURATIONS
Oscilloscope
100 W
LVDS
Figure 5. LVDS Output DC Configuration During Device Test
Phase Noise
Analyzer
LVDS
50 W
Figure 6. LVDS Output AC Configuration During Device Test
VOH
VOL
OUTNx
OUTPx
V
OD
80%
VOUT,DIFF,PP (= 2 x V
)
20%
0 V
OD
tR
tF
Figure 7. Output Voltage and Rise/Fall Time
INN
INP
tPLH0
tPHL0
QN0
QP0
tPLH1
tPHL1
QN1
QP1
tPLH2
tPHL2
QN2
QP2
(1) Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn
or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2).
(2) Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2).
Figure 8. Output and Part-to-Part Skew
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V
ring
QNx
V
OD
0V Differential
QPx
Figure 9. Output Overshoot and Undershoot
VOS
GND
Figure 10. Output AC Common Mode
APPLICATION INFORMATION
THERMAL MANAGEMENT
For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to the package. Figure 11 shows a recommended land and
via pattern.
Figure 11. Recommended PCB Layout
8
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SCAS897 –JULY 2010
POWER-SUPPLY FILTERING
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed close to the power-supply pins and laid out with short loops to minimize inductance. It is
recommended to add as many high-frequency (for example, 0.1 µF) bypass capacitors as there are supply pins
in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and
the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip
supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for
proper operation.
Ferrite Bead
1 µF
10 µF
0.1 µF
Figure 12. Power-Supply Decoupling
LVDS OUTPUT TERMINATION
The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is
recommended to place termination resister close to the receiver. If the receiver is internally biased, ac-coupling
should be used. If the LVDS receiver has internal 100 Ω termination, external termination is not required.
Unused outputs can be left open without connecting any traces to the output pins.
100 W
LVDS
CDCLVD1213
Z = 50 W
Figure 13. Output DC Termination
100 nF
100 W
LVDS
CDCLVD1213
Z = 50 W
100 nF
Figure 14. Output AC Termination (With Receiver Internally Biased)
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INPUT TERMINATION
The CDCLVD1213 input has internal 140 Ω terminations, and an external 350 Ω resistor is required for a 50 Ω
transmission line. It can be interfaced with LVDS, LVPECL, or CML drivers. LVDS input can be connected
directly, dc or ac coupled. With ac coupling, external bias (VCC/2) must be provided to VT pin.
Figure 16 illustrates how to connect CML input to CDCLVD1213 input buffer. The input does not have internal
biasing, so external biasing (VCC/2 to VT) is required for ac coupling. If the CML output swing is >1.6 VPP, then
signal swing needs to be reduced to meet VIN, DIF, PP ≤ 1.6 VPP
.
350 W
CDCLVD1213
LVDS
Z = 50 W
Figure 15. LVDS Clock Driver Connected to CDCLVD1213 Input
100 nF
350 W
CDCLVD1213
CML
Z = 50 W
100 nF
V
T = 1.25V
Figure 16. CML Clock Driver Connected to CDCLVD1213 Input
Figure 17 shows how to connect LVPECL input to the CDCLVD1213 input buffer. The input does not have
internal biasing, so external biasing (VCC/2 to VT) is required for ac coupling. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 Vpp.
75 W
100 nF
350 W
CDCLVD1213
LVPECL
Z = 50 W
100 nF
75 W
150 W
150 W
V
T = 1.25V
Figure 17. LVPECL Clock Driver Connected to CDCLVD1213 Input
10
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDCLVD1213RGTR
CDCLVD1213RGTT
ACTIVE
ACTIVE
QFN
QFN
RGT
RGT
16
16
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCLVD1213RGTR
CDCLVD1213RGTT
QFN
QFN
RGT
RGT
16
16
3000
250
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCLVD1213RGTR
CDCLVD1213RGTT
QFN
QFN
RGT
RGT
16
16
3000
250
338.1
338.1
338.1
338.1
20.6
20.6
Pack Materials-Page 2
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