CDCLVD2106 [TI]
Dual 1:6 Low Additive Jitter LVDS Buffer; 双1 ： 6的低附加抖动LVDS缓冲器
| 型号： | CDCLVD2106 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 1:6 Low Additive Jitter LVDS Buffer |
| 文件： | 总21页 (文件大小：706K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCLVD2106
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SCAS902B –SEPTEMBER 2010–REVISED JANUARY 2011
Dual 1:6 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD2106
The CDCLVD2106 is specifically designed for driving
1
FEATURES
50-Ω transmission lines. In case of driving the inputs
in single ended mode, the appropriate bias voltage
(VAC_REF) should be applied to the unused negative
input pin.
•
Dual 1:6 Differential Buffer
•
Low Additive Jitter: <300 fs rms
in 10 kHz – 20 MHz
•
•
Low Within Bank Output Skew of 45 ps (Max)
Using the control pin (EN), outputs can be either
disabled or enabled. If the EN pin is left open two
buffers with all outputs are enabled, if switched to a
logical "0" both buffers with all outputs are disabled
(static logical "0"), if switched to a logical "1", one
buffer with six outputs is disabled and another buffer
with six outputs is enabled. The part supports a fail
safe function. It incorporates an input hysteresis,
which prevents random oscillation of the outputs in
absence of an input signal.
Universal Inputs Accept LVDS, LVPECL,
LVCMOS
•
•
One Input Dedicated for Six Outputs
Total of 12 LVDS Outputs, ANSI EIA/TIA-644A
Standard Compatible
•
•
•
Clock Frequency up to 800 MHz
2.375–2.625 V Device Power Supply
LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
The device operates in 2.5V supply environment and
is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD2106 is packaged in
small 40-pin, 6-mm × 6-mm QFN package.
•
•
•
Industrial Temperature Range –40°C to 85°C
Packaged in 6 mm x 6 mm 40-pin QFN (RHA)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
spacer
APPLICATIONS
•
•
•
•
•
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment
Wireless Communications
General Purpose Clocking
200 MHz
DAC6
Clock
Generator
EN
CDCLVD2106
DESCRIPTION
The CDCLVD2106 clock buffer distributes two clock
inputs (IN0, IN1) to a total of 12 pairs of differential
LVDS clock outputs (OUT0, OUT11). Each buffer
block consists of one input and 6 LVDS outputs. The
inputs can either be LVDS, LVPECL, or LVCMOS.
100 MHz
ADC6
Figure 1. Application Example
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCLVD2106
SCAS902B –SEPTEMBER 2010–REVISED JANUARY 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
V
V
AC_REF0
Reference
Generator
AC_REF1
INP0
INN0
OUTP [0..5]
OUTN [0..5]
LVDS
INP1
INN1
OUTP [6..11]
OUTN [6..11]
LVDS
V
CC
200 kW
EN
200 kW
GND
GND
Figure 2. CDCLVD2106 Block Diagram
30
29
28
27
26
25
24
23
22
21
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
VCC
OUTP8
OUTN8
OUTP9
OUTN9
OUTP10
OUTN10
OUTP11
OUTN11
VCC
VCC
OUTN3
OUTP3
OUTN2
OUTP2
OUTN1
OUTP1
OUTN0
OUTP0
VCC
6mm x 6mm
40 pin QFN (RHA)
Thermal Pad (GND)
1
2
3
4
5
6
7
8
9
10
2
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SCAS902B –SEPTEMBER 2010–REVISED JANUARY 2011
PIN FUNCTIONS
PIN
NAME
NO.
TYPE
DESCRIPTION
5, 6, 11,
20, 31, 40
VCC
Power
2.5V supplies for the device
Device ground
GND
21, 30
9, 8
Ground
Input
INP0, INN0
INP1, INN1
Differential input pair or single ended input
Differential redundant input pair or single ended input
Differential LVDS output pair no. 0
Differential LVDS output pair no. 1
Differential LVDS output pair no. 2
Differential LVDS output pair no. 3
Differential LVDS output pair no. 4
Differential LVDS output pair no. 5
Differential LVDS output pair no. 6
Differential LVDS output pair no. 7
Differential LVDS output pair no. 8
Differential LVDS output pair no. 9
Differential LVDS output pair no. 10
Differential LVDS output pair no. 11
2, 3
Input
OUTP0, OUTN0
OUTP1, OUTN1
OUTP2, OUTN2
OUTP3, OUTN3
OUTP4, OUTN4
OUTP5, OUTN5
OUTP6, OUTN6
OUTP7, OUTN7
OUTP8,OUTN8
OUTP9,OUTN9
OUTP10,OUTN10
OUTP11,OUTN11
12, 13
14, 15
16, 17
18, 19
22, 23
24, 25
26, 27
28, 29
32, 33
34, 35
36, 37
38, 39
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
INP0/INN0 is the input
INP1/INN1 is the input
Bias voltage output for capacitive coupled inputs. If used, it is recommended to use a
0.1µF to GND on this pin.
VAC_REF0
7
Output
Output
Bias voltage output for capacitive coupled inputs. If used, it is recommended to use a
0.1µF to GND on this pin.
VAC_REF1
NC
4
10
No connect
Input with
internal
200kΩ pull-up
and pull-down
EN
1
Control pin – enables or disables the outputs (See Table 1).
Device ground. Thermal pad must be soldered to ground. See thermal management
recommendations.
Thermal Pad
Ground
Table 1. Output Control Table
EN
0
CLOCK OUTPUTS
All outputs disabled (static "0")
Open
1
All outputs enabled
OUT0 to OUT5 enabled and OUT6 to OUT11 disabled (static "0")
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 2.8
UNIT
Supply voltage range, VCC
V
V
V
Input voltage range, VI
–0.2 to (VCC + 0.2)
–0.2 to (VCC + 0.2)
See note(2)
Output voltage range, VO
Driver short circuit current, IOSD
Electrostatic discharge (HBM, 1.5 kΩ, 100 pF)
>3000
V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) The outputs can handle permanent short.
RECOMMENDED OPERATING CONDITIONS
MIN
2.375
–40
TYP
2.5 2.625
85
MAX UNIT
Device supply voltage, VCC
Ambient temperature, TA
V
°C
THERMAL INFORMATION
CDCLVD2106
THERMAL METRIC(1)
UNITS
RHA (40 PINS)
qJA
Junction-to-ambient thermal resistance
31.0
28.7
9.3
qJC(top)
qJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.4
yJB
9.3
qJC(bottom)
3.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
At VCC = 2.375V to 2.625V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EN CONTROL INPUT CHARACTERISTICS
VdI3
3 State
Open
0.5×VCC
V
V
VdIH
VdIL
Input high voltage
Input low voltage
Input high current
Input low current
Input pull-up/ pull-down resistor
0.7×VCC
0.2×VCC
V
IdIH
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
30
mA
mA
kΩ
IdIL
–30
Rpull(EN)
200
2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS
fIN
Input frequency
200
1.5
MHz
V
External threshold voltage applied to
complementary input
Vth
Input threshold voltage
1.1
VIH
VIL
Input high voltage
Input low voltage
Input high current
Input low current
Input edge rate
Vth + 0.1
0
VCC
Vth – 0.1
10
V
V
IIH
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
20%–80%
mA
mA
V/ns
pF
IIL
–10
ΔV/ΔT
CIN
1.5
Input capacitance
2.5
4
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 2.375V to 2.625V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIFFERENTIAL INPUT CHARACTERISTICS
fIN
Input frequency
Clock input
800
1.6
MHz
VPP
V
VIN, DIFF
VICM
IIH
Differential input voltage peak-to-peak VICM = 1.25 V
0.3
1.0
Input common mode voltage range
Input high current
VIN, DIFF, PP > 0.4 V
VCC – 0.3
10
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625, VIL = 0 V
20%–80%
mA
IIL
Input low current
–10
mA
ΔV/ΔT
CIN
Input edge rate
0.75
V/ns
pF
Input capacitance
2.5
LVDS OUTPUT CHARACTERISTICS
|VOD
|
Differential output voltage magnitude
250
–15
450
15
mV
mV
Change in differential output voltage
magnitude
ΔVOD
VIN, DIFF, PP = 0.3V, RL = 100 Ω
Steady-state common mode output
voltage
V
VOC(SS)
ΔVOC(SS)
1.1
1.375
Steady-state common mode output
voltage
mV
VIN, DIFF, PP = 0.6V, RL = 100 Ω
–15
15
Vring
Output overshoot and undershoot
Output ac common mode
Short-circuit output current
Propagation delay
Percentage of output amplitude VOD
VIN, DIFF, PP = 0.6V, RL = 100 Ω
VOD = 0 V
10%
VOS
40
70 mVP-P
IOS
±24
mA
ns
ps
ps
ps
ps
tPD
VIN, DIFF, PP = 0.3 V
1.5
2.5
600
45
tSK, PP
tSK.O_WB
tSK.O_BB
Part-to-part skew
Within bank output skew
Bank-to-bank output skew
Both inputs are phase aligned
75
Crossing-point-to-crossing-point
distortion
tSK,P
tRJIT
Pulse skew(with 50% duty cycle input)
–50
50
50
Random additive jitter (with 50% duty Edge speed = 0.75 V/ns,
cycle input)
ps,
RMS
0.3
10 kHz – 20 MHz
tR/tF
Output rise/fall time
Static supply current
Supply current
20% to 80%, 100 Ω, 5 pF
Outputs unterminated, f = 0 Hz
300
45
ps
ICCSTAT
ICC100
27
97
mA
mA
All outputs enabled; RL = 100 Ω, f =
133
100 MHz
ICC800
Supply current
All outputs enabled; RL = 100 Ω, f =
800 MHz
137
177
mA
V
VAC_REF CHARACTERISTICS
VAC_REF
Reference output voltage
VCC = 2.5 V, Iload = 100 µA
1.1
1.25
1.35
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Typical Additive Phase Noise Characteristics for 100 MHz Clock
PARAMETER
MIN
TYP
-132.9
-138.8
-147.4
-153.6
-155.2
-156.2
-156.6
171
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs, RMS
phn100
phn1k
Phase noise at 100 Hz offset
Phase noise at 1 kHz offset
phn10k
phn100k
phn1M
phn10M
phn20M
tRJIT
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
Phase noise at 20 MHz offset
Random additive jitter from 10 kHz to 20 MHz
Typical Additive Phase Noise Characteristics for 737.27 MHz Clock
PARAMETER
MIN
TYP
-80.2
-114.3
-138
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs, RMS
phn100
phn1k
Phase noise at 100 Hz offset
Phase noise at 1 kHz offset
phn10k
phn100k
phn1M
phn10M
phn20M
tRJIT
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
Phase noise at 20 MHz offset
Random additive jitter from 10 kHz to 20 MHz
-143.9
-145.2
-146.5
-146.6
65
6
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TYPICAL CHARACTERISTICS
INPUT- AND OUTPUT-CLOCK PHASE NOISES
vs
FREQUENCY FROM the CARRIER
(TA = 25°C and VCC = 2.5V)
Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs
Figure 3. 100 MHz Input and Output Phase Noise Plots
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
350
340
330
320
310
300
290
280
270
260
250
T
A
= 25oC
2.625V
2.5V
2.375V
0
100 200 300 400 500 600 700 800
Frequency − MHz
Figure 4. Differential Output Voltage vs Frequency
TEST CONFIGURATIONS
Oscilloscope
100 W
LVDS
Figure 5. LVDS Output DC Configuration During Device Test
Phase Noise
Analyzer
LVDS
50 W
Figure 6. LVDS Output AC Configuration During Device Test
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TYPICAL CHARACTERISTICS (continued)
V
IH
V
th
IN
V
IL
IN
V
th
Figure 7. DC Coupled LVCMOS Input During Device Test
V
OUTNx
OUTPx
OH
VOD
V
OL
80%
V
(= 2 x VOD)
20%
0 V
OUT,DIFF,PP
t
r
t
f
Figure 8. Output Voltage and Rise/Fall Time
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TYPICAL CHARACTERISTICS (continued)
INNx
INPx
t
t
t
PLH0
PHL0
PHL1
OUTN0
OUTP0
t
PLH1
OUTN1
OUTP1
t
t
PLH2
PHL2
OUTN2
OUTP2
t
t
PHL11
PLH11
OUTN11
OUTP11
A. Output skew is calculated as the greater of the following: As of the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..11)
B. Part to part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..11)
C. Both inputs (IN0 and IN1) are phase aligned
Figure 9. Output Skew and Part-to-Part Skew
spacer
spacer
V
ring
OUTNx
VOD
0 V Differential
OUTPx
Figure 10. Output Overshoot and Undershoot
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TYPICAL CHARACTERISTICS (continued)
V
OS
GND
Figure 11. Output AC Common Mode
APPLICATION INFORMATION
THERMAL MANAGEMENT
For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to of the package. Check the mechanical data at the end of
the data sheet for land and via pattern examples.
POWER SUPPLY FILTERING
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is very critical to the application.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It is
recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply pins
in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and
the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
very low dc resistance because it is imperative to provide adequate isolation between the board supply and the
chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required
for proper operation.
Chip
Supply
Board
Supply
Ferrite Bead
1µF
10µF
0.1µF (x6)
Figure 12. Power Supply Filtering
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LVDS OUTPUT TERMINATION
The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is
recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage
different than the output common mode voltage of the CDCLVD2106, ac-coupling should be used. If the LVDS
receiver has internal 100 Ω termination, external termination must be omitted.
Unused outputs can be left open without connecting any trace to the output pins.
Z = 50 W
100 W
LVDS
CDCLVD2106
Z = 50 W
Figure 13. LVDS Output DC Termination
100 nF
Z = 50 W
100 W
LVDS
CDCLVD2106
Z = 50 W
100 nF
Figure 14. LVDS Output AC Termination with Receiver Internally Biased
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INPUT TERMINATION
The CDCLVD2106 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.
LVDS Driver can be connected to CDCLVD2106 inputs with dc or ac coupling as shown Figure 15 and Figure 16
respectively.
Figure 17 shows how to connect LVPECL inputs to the CDCLVD2106. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 VPP
.
Figure 18 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2106 directly. The series
resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs
to be limited to VIH ≤ VCC
.
Z = 50 W
100 W
CDCLVD2106
LVDS
Z = 50 W
Figure 15. LVDS Clock Driver Connected to CDCLVD2106 Input (DC coupled)
spacer
100 nF
Z = 50 W
CDCLVD2106
LVDS
Z = 50 W
100 nF
50 W
50 W
VAC_REF
Figure 16. LVDS Clock Driver Connected to CDCLVD2106 Input (AC coupled)
spacer
75 W
100 nF
Z = 50 W
CDCLVD2106
LVPECL
75 W
Z = 50 W
100 nF
50 W
50 W
150 W
150 W
VAC_REF
Figure 17. LVPECL Clock Driver Connected to CDCLVD2106 Input
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R
s
LVCMOS
(2.5V)
Z = 50 W
CDCLVD2106
VIH +VIL
2
Vth
=
Figure 18. 2.5V LVCMOS Clock Driver Connected to CDCLVD2106 Input
If one of the input buffers is used, then the other buffer should be disabled using the control pin EN; and, unused
input pins should be grounded by 1-kΩ resistors.
Spacer
REVISION HISTORY
Changes from Original (September 2010) to Revision A
Page
•
•
Changed tSK.O_BB Bank-to-bank output slew From: 170 ps (Max) To: 75 ps (Max) .............................................................. 5
Deleted the Recommended PCB Layout illustration .......................................................................................................... 11
Changes from Revision A (November 2010) to Revision B
Page
•
Changed the device status From: Product Preview To: Production ..................................................................................... 1
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PACKAGE OPTION ADDENDUM
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5-Feb-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDCLVD2106RHAR
CDCLVD2106RHAT
ACTIVE
ACTIVE
VQFN
VQFN
RHA
RHA
40
40
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCLVD2106RHAR
CDCLVD2106RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
330.0
330.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCLVD2106RHAR
CDCLVD2106RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
336.6
336.6
336.6
336.6
28.6
28.6
Pack Materials-Page 2
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