CDCLVD2102RGTR [TI]
Dual 1:2 Low Additive Jitter LVDS Buffer; 双1 ： 2低附加抖动LVDS缓冲器
| 型号： | CDCLVD2102RGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 1:2 Low Additive Jitter LVDS Buffer |
| 文件： | 总20页 (文件大小：753K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCLVD2102
www.ti.com
SCAS904A –MAY 2010–REVISED JUNE 2010
Dual 1:2 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD2102
1
FEATURES
DESCRIPTION
•
Dual 1:2 Differential Buffer
•
Low Additive Jitter <300 fs RMS in 10-kHz to
20-MHz
The CDCLVD2102 clock buffer distributes two clock
inputs (IN0, IN1) to a total of 4 pairs of differential
LVDS clock outputs (OUT0, OUT3). Each buffer block
consists of one input and 2 LVDS outputs. The inputs
can either be LVDS, LVPECL, or LVCMOS.
•
•
Low Within Bank Output Skew of 15 ps (Max)
Universal Inputs Accept LVDS, LVPECL,
LVCMOS
The CDCLVD2102 is specifically designed for driving
50-Ω transmission lines. If driving the inputs in single
•
•
One Input Dedicated for Two Outputs
Total of 4 LVDS Outputs, ANSI EIA/TIA-644A
Standard Compatible
ended mode, the appropriate bias voltage (VAC_REF
)
should be applied to the unused negative input pin.
•
•
•
Clock Frequency up to 800 MHz
2.375–2.625V Device Power Supply
Using the control pin (EN), outputs can be either
disabled or enabled. If the EN pin is left open two
buffers with all outputs are enabled, if switched to a
logical "0" both buffers with all outputs are disabled
(static logical "0"), if switched to a logical "1", one
buffer with two outputs is disabled and another buffer
with two outputs is enabled. The part supports a fail
safe function. It incorporates an input hysteresis,
which prevents random oscillation of the outputs in
absence of an input signal.
LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
•
•
•
Industrial Temperature Range –40°C to 85°C
Packaged in 3mm × 3mm 16-Pin QFN (RGT)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
The device operates in 2.5V supply environment and
is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD2102 is packaged in
small 16-pin, 3-mm × 3-mm QFN package.
•
•
•
•
•
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment
Wireless Communications
General Purpose Clocking
200 MHz
DAC2
Clock
EN
Generation
CDCLVD2102
100 MHz
ADC2
Figure 1. Application Example
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CDCLVD2102
SCAS904A –MAY 2010–REVISED JUNE 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
V
CC
V
Reference
Generator
AC_REF
INP0
INN0
OUTP [0..1]
OUTN [0..1]
LVDS
INP1
INN1
OUTP [2..3]
OUTN [2..3]
LVDS
V
CC
200 kW
EN
200 kW
GND
Figure 2. CDCLVD2102 Block Diagram
TOP VIEW
12
11
10
9
13
14
15
16
8
7
6
5
OUTP2
OUTN2
OUTP3
OUTN3
VAC_REF
INN0
INP0
3mm x 3mm
16 pin QFN (RGT)
Thermal Pad
VCC
1
2
3
4
2
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SCAS904A –MAY 2010–REVISED JUNE 2010
PIN FUNCTIONS
PIN
TYPE
DESCRIPTION
NAME
NO.
5
VCC
Power
Ground
Input
2.5V supplies for the device
Device ground
GND
1
INP0, INN0
INP1, INN1
6, 7
3, 4
Differential input pair or single ended input
Input
Differential redundant input pair or single ended input
Bias voltage output for capacitive coupled inputs. If used, it is recommended to
use a 0.1µF to GND on this pin
VAC_REF
8
Output
OUTP0, OUTN0
OUTP1, OUTN1
OUTP2, OUTN2
OUTP3, OUTN3
9, 10
11, 12
13, 14
15, 16
Output
Output
Output
Output
Differential LVDS output pair no. 0
INP0/INN0 is the input
Differential LVDS output pair no. 1
Differential LVDS output pair no. 2
INP1/INN1 is the input
Differential LVDS output pair no. 3
Input with internal
200kΩ pull-up and
pull-down
EN
2
Control pin – enables or disables the outputs, (See Table 1)
See thermal management recommendations
Thermal Pad
Table 1. Output Control Table
EN
CLOCK OUTPUTS
All outputs disabled (static "0")
0
OPEN
1
All outputs enabled
OUT0, OUT1 enabled and OUT2, OUT3 disabled (static "0")
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE / UNIT
–0.3 to 2.8 V
Supply voltage range, VCC
Input voltage, VI
–0.2 to (VCC + 0.2) V
–0.2 to (VCC + 0.2) V
Output voltage range, VO
(2)
Driver short circuit current, IOSD
Electrostatic discharge (HBM, 1.5 kΩ, 100 pF)
See Note
>3000 V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) The outputs can handle permanent short.
RECOMMENDED OPERATING CONDITIONS
MIN
2.375
–40
TYP
MAX
2.625
85
UNITS
V
Device supply voltage, VCC
Ambient temperature, TA
2.5
oC
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UNITS
THERMAL INFORMATION
CDCLVD2102
THERMAL METRIC(1)
RGT
16 PINS
51.3
85.4
20.1
1.3
qJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
qJC(top)
qJB
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
yJB
19.4
6
qJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS:
At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN PIN INPUT CHARACTERISTICS
VdI3
VdIH
VdIL
IdIH
3-State
Open
0.5×VCC
V
V
Input high voltage
Input low voltage
Input high current
Input low current
Input pull-up/ pull-down resistor
0.7×VCC
0.2×VCC
30
V
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
mA
mA
kΩ
IdIL
–30
Rpull(EN)
200
2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS
fIN
Input frequency
200
1.5
MHz
V
External threshold voltage applied
to complementary input
Vth
Input threshold voltage
1.1
VIH
VIL
Input high voltage
Input low voltage
Input high current
Input low current
Input edge rate
Vth + 0.1
0
VCC
Vth – 0.1
10
V
V
IIH
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
20% – 80%
mA
mA
V/ns
pF
IIL
–10
ΔV/ΔT
CIN
1.5
Input capacitance
2.5
DIFFERENTIAL INPUT CHARACTERISTICS
fIN
Input frequency
Clock input
800
1.6
MHz
VP-P
Differential input voltage
peak-to-peak
VIN, DIFF
VICM = 1.25 V
0.3
1
VICM
IIH
Input common-mode voltage range
Input high current
VIN, DIFF, PP > 0.4V
VCC – 0.3
10
V
mA
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
20% to 80%
IIL
Input low current
–10
mA
ΔV/ΔT
CIN
Input edge rate
0.75
V/ns
pF
Input capacitance
2.5
4
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SCAS904A –MAY 2010–REVISED JUNE 2010
ELECTRICAL CHARACTERISTICS: (continued)
At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVDS OUTPUT CHARACTERISTICS
|VOD
|
Differential output voltage magnitude
250
–15
450
15
mV
mV
Change in differential output voltage
magnitude
ΔVOD
VIN, DIFF, PP = 0.3 V,RL = 100 Ω
Steady-state common mode output
voltage
VOC(SS)
ΔVOC(SS)
Vring
1.1
1.375
15
V
Steady-state common mode output
voltage
VIN, DIFF, PP = 0.6 V,RL = 100 Ω
–15
mV
Percentage of output amplitude
VOD
Output overshoot and undershoot
10%
VOS
Output ac common mode
Short-circuit output current
Propagation delay
VIN, DIFF, PP = 0.6 V, RL = 100 Ω
VOD = 0 V
25
70
±24
2.5
600
15
mVPP
mA
ns
IOS
tPD
VIN, DIFF, PP = 0.3 V
1.5
tSK, PP
tSK, O_WB
tSK,O_BB
Part-to-part skew
ps
Within bank output skew
Bank-to-bank output skew
ps
Both inputs are phase aligned
100
ps
Pulse skew(with 50% duty cycle
input)
Crossing-point-to-crossing-point
distortion
tSK,P
tRJIT
–50
50
50
ps
Random additive jitter (with 50% duty Edge speed = 0.75V/ns,
cycle input)
0.3 ps, RMS
10 kHz – 20 MHz
tR/tF
Output rise/fall time
Static supply current
20% to 80%,100 Ω, 5 pF
Outputs unterminated, f = 0 Hz
300
45
ps
ICCSTAT
27
49
mA
All outputs enabled, RL = 100 Ω,
f = 100 MHz
ICC100
ICC800
Supply current
Supply current
77
mA
mA
All outputs enabled, RL = 100 Ω,
f = 800 MHz
76
106
VAC_REF CHARACTERISTICS
VAC_REF
Reference output voltage
VCC = 2.5 V, Iload = 100 µA
1.1
1.25
1.35
V
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Typical Additive Phase Noise Characteristics for 100 MHz Clock
PARAMETER
MIN
TYP
-132.9
-138.8
-147.4
-153.6
-155.2
-156.2
-156.6
171
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs, RMS
phn100
phn1k
Phase noise at 100 Hz offset
Phase noise at 1 kHz offset
phn10k
phn100k
phn1M
phn10M
phn20M
tRJIT
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
Phase noise at 20 MHz offset
Random additive jitter from 10 kHz to 20 MHz
Typical Additive Phase Noise Characteristics for 737.27 MHz Clock
PARAMETER
MIN
TYP
-80.2
-114.3
-138
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs, RMS
phn100
phn1k
Phase noise at 100 Hz offset
Phase noise at 1 kHz offset
phn10k
phn100k
phn1M
phn10M
phn20M
tRJIT
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
Phase noise at 20 MHz offset
Random additive jitter from 10 kHz to 20 MHz
-143.9
-145.2
-146.5
-146.6
65
6
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SCAS904A –MAY 2010–REVISED JUNE 2010
TYPICAL CHARACTERISTICS
INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES
vs
FREQUENCY FROM THE CARRIER (TA = 25°C and VCC = 2.5V)
Input clock jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs
Figure 3. 100 MHz Input and Output Phase Noise Plot
Differential Output Voltage
vs
Frequency
350
340
330
320
310
300
290
280
270
260
250
T
= 25oC
A
2.625V
2.5V
2.375V
0
100 200 300 400 500 600 700 800
Frequency − MHz
Figure 4.
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TEST CONFIGURATIONS
Oscilloscope
100 W
LVDS
Figure 5. LVDS Output DC Configuration During Device Test
Phase Noise
Analyzer
LVDS
50 W
Figure 6. LVDS Output AC Configuration During Device Test
Figure 7. DC Coupled LVCMOS Input During Device Test
V
OUTNx
OUTPx
OH
V
OD
V
OL
80%
V
(= 2 x V
)
OD
20%
0 V
OUT,DIFF,PP
t
r
t
f
Figure 8. Output Voltage and Rise/Fall Time
8
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SCAS904A –MAY 2010–REVISED JUNE 2010
INNx
INPx
tPLH0
tPHL0
OUTN0
OUTP0
tPLH1
tPHL1
OUTN1
OUTP1
tPLH2
tPHL2
OUTN2
OUTP2
tPLH3
tPHL3
OUTN3
OUTP3
A. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn
or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, 3).
B. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, 3).
C. Both inputs (IN0 and IN1) are phase aligned.
Figure 9. Output Skew and Part-to-Part Skew
V
ring
OUTNx
VOD
0V Differential
OUTPx
Figure 10. Output Overshoot and Undershoot
VOS
GND
Figure 11. Output AC Common Mode
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APPLICATION INFORMATION
THERMAL MANAGEMENT
For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The Thermal Pad must be
soldered down to ensure adequate heat conduction to of the package. Figure 12 shows a recommended land
and via pattern.
Figure 12. Recommended PCB Layout
POWER-SUPPLY FILTERING
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It
is recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply
pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply
and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
very low dc resistance because it is imperative to provide adequate isolation between the board supply and the
chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required
for proper operation.
Chip
Supply
Board
Supply
Ferrite Bead
1 µF
10 µF
0.1 µF
Figure 13. Power-Supply Decoupling
10
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SCAS904A –MAY 2010–REVISED JUNE 2010
LVDS OUTPUT TERMINATION
The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is
recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage
different than the output common mode voltage of the CDCLVD2102, ac-coupling should be used. If the LVDS
receiver has internal 100 ohm termination, external termination must be omitted.
Unused outputs can be left open without connecting any trace to the output pins.
100 W
LVDS
CDCLVD2102
Z = 50 W
Figure 14. Output DC Termination
100 nF
100 W
LVDS
CDCLVD2102
Z = 50 W
100 nF
Figure 15. Output AC Termination With Receiver Internally Biased
INPUT TERMINATION
The CDCLVD2102 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.
LVDS Driver can be connected to CDCLVD2102 inputs with dc or ac coupling as shown Figure 16 and
Figure 17, respectively.
100 W
LVDS
CDCLVD2102
Z = 50 W
Figure 16. LVDS Clock Driver Connected to CDCLVD2102 Input (DC Coupled)
100 nF
LVDS
CDCLVD2102
Z = 50 W
100 nF
50 W
50 W
V
AC_REF
Figure 17. LVDS Clock Driver Connected to CDCLVD2102 Input (AC Coupled)
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Figure 18 shows how to connect LVPECL inputs to the CDCLVD2102. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 VPP
.
75 W
100 nF
CDCLVD2102
LVPECL
Z = 50 W
100 nF
50 W
75 W
150 W
150 W
50 W
V
AC_REF
Figure 18. LVPECL Clock Driver Connected to CDCLVD2102 Input
Figure 19 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2102 directly. The series
resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs
to be limited to VIH ≤ VCC
.
R
S
LVCMOS
(2.5V)
CDCLVD2102
V
V
IL
+
2
IH
V
=
th
Figure 19. 2.5V LVCMOS Clock Driver Connected to CDCLVD2102 Input
If one of the buffers is used, then the other unused buffer should be disabled through the EN pin, and the unused
input pins should be grounded by 1kΩ resistors.
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SCAS904A –MAY 2010–REVISED JUNE 2010
REVISION HISTORY
Changes from Original (May 2010) to Revision A
Page
•
Changed Features bullet From: ESD Protection Exceeds 2kV HBM, 500V CDM To: ESD Protection Exceeds 3 kV
HBM, 1 kV CDM ................................................................................................................................................................... 1
•
•
•
•
•
•
•
•
•
•
•
Electrostatic discharge was <2000 ....................................................................................................................................... 3
ΔVOD values, MIN was-50, MAX was 50 .............................................................................................................................. 5
VOC(SS) MIN value was 1.125 ................................................................................................................................................ 5
ΔVOC(SS) values, MIN was-50, MAX was 50 .......................................................................................................................... 5
Vring MAX value was 20% ..................................................................................................................................................... 5
VOS values, TYP was 30, MAX was 100 ............................................................................................................................... 5
tPD MAX value was 2 ............................................................................................................................................................. 5
tSK, PP - deleted the TYP value of 300 ................................................................................................................................... 5
tR/tF MIN value was 200 ........................................................................................................................................................ 5
ICCSTAT MAX value was 42 .................................................................................................................................................... 5
Added new paragraph following Figure 19 ......................................................................................................................... 12
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PACKAGE OPTION ADDENDUM
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26-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDCLVD2102RGTR
CDCLVD2102RGTT
ACTIVE
ACTIVE
QFN
QFN
RGT
RGT
16
16
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCLVD2102RGTR
CDCLVD2102RGTT
QFN
QFN
RGT
RGT
16
16
3000
250
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCLVD2102RGTR
CDCLVD2102RGTT
QFN
QFN
RGT
RGT
16
16
3000
250
338.1
338.1
338.1
338.1
20.6
20.6
Pack Materials-Page 2
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