CDCLVD2108RGZR [TI]
Dual 1:8 Low Additive Jitter LVDS Buffer; 双1 ： 8低附加抖动LVDS缓冲器
| 型号： | CDCLVD2108RGZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 1:8 Low Additive Jitter LVDS Buffer |
| 文件： | 总20页 (文件大小：778K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCLVD2108
www.ti.com
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
Dual 1:8 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD2108
1
FEATURES
DESCRIPTION
•
Dual 1:8 Differential Buffer
•
Low Additive Jitter <300 fs RMS in
10 kHz to 20 MHz
The CDCLVD2108 clock buffer distributes two clock
inputs (IN0, IN1) to a total of 16 pairs of differential
LVDS clock outputs (OUT0, OUT15). Each buffer
block consists of one input and 8 LVDS outputs. The
inputs can either be LVDS, LVPECL, or LVCMOS.
•
•
Low Within Bank Output Skew of 50 ps (Max)
Universal Inputs Accept LVDS, LVPECL,
LVCMOS
The CDCLVD2108 is specifically designed for driving
50-Ω transmission lines. In case of driving the inputs
in single ended mode, the appropriate bias voltage
(VAC_REF) should be applied to the unused negative
input pin.
•
•
One Input Dedicated for Eight Outputs
Total of 16 LVDS Outputs, ANSI EIA/TIA-644A
Standard Compatible
•
•
•
Clock Frequency up to 800 MHz
2.375–2.625V Device Power Supply
Using the control pin (EN) outputs can be either
disabled or enabled. If the EN pin is left open all
outputs are active, if switched to a logical '0' all
outputs are disabled (static logical 0), if switched to a
logical '1', OUT (8..15) are switched off and OUT
(0..7) are active. The part supports a fail safe
function. It incorporates an input hysteresis, which
prevents random oscillation of the outputs in absence
of an input signal.
LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
•
•
•
Industrial Temperature Range –40°C to 85°C
Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
The device operates in 2.5V supply environment and
is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD2108 is packaged in
small 48-pin, 7-mm x 7-mm QFN package.
•
•
•
•
•
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment
Wireless Communications
General Purpose Clocking
200 MHz
PHY 8
Clock
Generator
EN
CDCLVD2108
100 MHz
PHY16
Figure 1. Application Example
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CDCLVD2108
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
V
V
AC_REF0
Reference
Generator
AC_REF1
INP0
INN0
OUTP [0..7]
OUTN [0..7]
LVDS
INP1
INN1
OUTP [8..15]
OUTN [8..15]
LVDS
V
CC
200 kW
EN
200 kW
GND
GND
Figure 2. CDCLVD2108 Block Diagram
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VCC
OUTP11
OUTN11
OUTP12
OUTN12
OUTP13
OUTN13
OUTP14
OUTN14
OUTP15
OUTN15
VCC
VCC
OUTN4
OUTP4
OUTN3
OUTP3
OUTN2
OUTP2
OUTN1
OUTP1
OUTN0
OUTP0
VCC
7mm x 7mm
48 pin QFN (RGZ)
Thermal Pad (GND)
1
2
3
4
5
6
7
8
9
10
11
12
2
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVD2108
CDCLVD2108
www.ti.com
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
PIN FUNCTIONS
PIN
TYPE
DESCRIPTION
NAME
NO.
6, 7, 13,
24, 37, 48
2.5V supplies for the device
Device ground
VCC
Power
GND
1,12
Ground
Input
INP0, INN0
INP1, INN1
10, 9
Differential input pair or single ended input for buffer 0
Differential input pair or single ended input for buffer 1
Differential LVDS output pair no. 0
3,4
Input
OUTP0, OUTN0
OUTP1, OUTN1
OUTP2, OUTN2
OUTP3, OUTN3
OUTP4, OUTN4
OUTP5, OUTN5
OUTP6, OUTN6
OUTP7, OUTN7
OUTP8,OUTN8
OUTP9,OUTN9
OUTP10,OUTN10
OUTP11,OUTN11
OUTP12,OUTN12
OUTP13,OUTN13
OUTP14,OUTN14
OUTP15,OUTN15
14, 15
16,17
18,19
20, 21
22,23
25, 26
27, 28
29, 30
31, 32
33, 34
35, 36
38, 39
40, 41
42, 43
44, 45
46, 47
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Differential LVDS output pair no. 1
Differential LVDS output pair no. 2
Differential LVDS output pair no. 3
INP0/INN0 is the input
Differential LVDS output pair no. 4
Differential LVDS output pair no. 5
Differential LVDS output pair no. 6
Differential LVDS output pair no. 7
Differential LVDS output pair no. 8
Differential LVDS output pair no. 9
Differential LVDS output pair no. 10
Differential LVDS output pair no. 11
Differential LVDS output pair no. 12
Differential LVDS output pair no. 13
Differential LVDS output pair no. 14
Differential LVDS output pair no. 15
INP1/INN1 is the input
Bias voltage output for capacitive coupled inputs. If used, it is recommended to use
a 0.1µF to GND on this pin.
VAC_REF0
8
Output
Output
Bias voltage output for capacitive coupled inputs. If used, it is recommended to use
a 0.1µF to GND on this pin.
VAC_REF1
N.C.
5
11
No connect
Input with an
internal 200kΩ
pull-up and
pull-down
EN
2
Control pin – enables or disables the outputs (See Table 1)
Device ground. Thermal Pad must be soldered to ground. See thermal
management recommendations.
Thermal Pad
Ground
Table 1. Output Control Table
EN
CLOCK OUTPUTS
0
OPEN
1
All outputs disabled (static "0")
All outputs enabled
OUT0 to OUT7 enabled and OUT8 to OUT15 disabled (static "0")
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): CDCLVD2108
CDCLVD2108
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE / UNIT
VCC
VI
Supply voltage range
–0.3 to 2.8 V
Input voltage range
–0.2 to (VCC + 0.2) V
–0.2 to (VCC + 0.2) V
VO
Output voltage range
(2)
IOSD
ESD
Driver short circuit current
Electrostatic discharge (HBM, 1.5 kΩ, 100 pF)
See Note
>3000 V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) The outputs can handle permanent short.
RECOMMENDED OPERATING CONDITIONS
MIN
2.375
–40
TYP
MAX
2.625
85
UNITS
V
VCC
TA
Device supply voltage
Ambient temperature
2.5
°C
THERMAL INFORMATION
CDCLVD2108
THERMAL METRIC(1)
UNITS
RGZ (48 PINS)
qJA
Junction-to-ambient thermal resistance
30.6
28.5
10.5
0.4
qJC(top)
qJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
yJB
10.2
3.1
qJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN CONTROL INPUT CHARACTERISTICS
VdI3
3-State
Open
0.5×VCC
V
V
VdIH
VdIL
Input high voltage
Input low voltage
Input high current
Input low current
Input pull-up/ pull-down resistor
0.7×VCC
0.2×VCC
30
V
IdIH
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
mA
mA
kΩ
IdIL
–30
Rpull(EN)
200
2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS
fIN
Input frequency
200
1.5
MHz
V
External threshold voltage applied
to complementary input
Vth
Input threshold voltage
1.1
VIH
VIL
Input high voltage
Input low voltage
Input high current
Input low current
Input edge rate
Vth + 0.1
0
VCC
Vth – 0.1
10
V
V
IIH
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
20% – 80%
mA
mA
V/ns
pF
IIL
–10
ΔV/ΔT
CIN
1.5
Input capacitance
2.5
4
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVD2108
CDCLVD2108
www.ti.com
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIFFERENTIAL INPUT CHARACTERISTICS
fIN
Input frequency
Clock input
800
1.6
MHz
VPP
Differential input voltage
peak-to-peak
VIN, DIFF
VICM = 1.25 V
0.3
1.0
VICM
IIH
Input common-mode voltage range
Input high current
VIN, DIFF, PP > 0.4V
VCC – 0.3
10
V
mA
VCC = 2.625 V, VIH = 2.625 V
VCC = 2.625 V, VIL = 0 V
20% to 80%
IIL
Input low current
–10
mA
ΔV/ΔT
CIN
Input edge rate
0.75
V/ns
pF
Input capacitance
2.5
LVDS OUTPUT CHARACTERISTICS
|VOD
|
Differential output voltage magnitude
250
–15
450
15
mV
mV
Change in differential output voltage
magnitude
ΔVOD
VIN, DIFF, PP = 0.3 V,RL = 100 Ω
Steady-state common mode output
voltage
VOC(SS)
ΔVOC(SS)
1.1
1.375
15
V
Steady-state common mode output
voltage
VIN, DIFF, PP = 0.6 V,RL = 100 Ω
–15
mV
Vring
Output overshoot and undershoot
Output ac common mode
Short-circuit output current
Propagation delay
Percentage of output amplitude VOD
VIN, DIFF, PP = 0.6 V, RL = 100 Ω
VOD = 0 V
10%
70
VOS
40
mVPP
mA
ns
IOS
±24
2.5
600
50
tPD
VIN, DIFF, PP = 0.3 V
1.5
tSK, PP
tSK, O_WB
tSK,O_BB
Part-to-part skew
ps
Within bank output skew
Bank-to-bank output skew
ps
both inputs are phase aligned
80
ps
Pulse skew(with 50% duty cycle
input)
Crossing-point-to-crossing-point
distortion
tSK,P
tRJIT
–50
50
50
ps
Random additive jitter (with 50% duty Edge speed 0.75V/ns
cycle input)
0.3 ps, RMS
10 kHz – 20 MHz
tR/tF
Output rise/fall time
Static supply current
20% to 80%,100 Ω, 5 pF
Outputs unterminated, f = 0 Hz
300
45
ps
ICCSTAT
27
mA
All outputs enabled, RL = 100 Ω,
f = 100 MHz
ICC100
ICC800
Supply current
Supply current
119
158
211
mA
mA
All outputs enabled, RL = 100 Ω,
f = 800 MHz
168
VAC_REF CHARACTERISTICS
VAC_REF
Reference output voltage
VCC = 2.5 V, Iload = 100 µA
1.1
1.25
1.35
V
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): CDCLVD2108
CDCLVD2108
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
Typical Additive Phase Noise Characteristics for 100 MHz Clock
PARAMETER
MIN
TYP
-132.9
-138.8
-147.4
-153.6
-155.2
-156.2
-156.6
171
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs, RMS
phn100
phn1k
Phase noise at 100 Hz offset
Phase noise at 1 kHz offset
phn10k
phn100k
phn1M
phn10M
phn20M
tRJIT
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
Phase noise at 20 MHz offset
Random additive jitter from 10 kHz to 20 MHz
Typical Additive Phase Noise Characteristics for 737.27 MHz Clock
PARAMETER
MIN
TYP
-80.2
-114.3
-138
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs, RMS
phn100
phn1k
Phase noise at 100 Hz offset
Phase noise at 1 kHz offset
phn10k
phn100k
phn1M
phn10M
phn20M
tRJIT
Phase noise at 10 kHz offset
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 10 MHz offset
Phase noise at 20 MHz offset
Random additive jitter from 10 kHz to 20 MHz
-143.9
-145.2
-146.5
-146.6
65
6
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVD2108
CDCLVD2108
www.ti.com
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES
vs
FREQUENCY FROM THE CARRIER (TA = 25°C and VCC = 2.5V)
Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs
Figure 3. 100 MHz Input and Output Phase Noise Plot
spacer
350
340
330
320
310
300
290
280
270
260
250
T
= 25oC
A
2.625V
2.5V
2.375V
0
100 200 300 400 500 600 700 800
Frequency − MHz
Figure 4. Differential Output Voltage vs Frequency
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): CDCLVD2108
CDCLVD2108
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
TEST CONFIGURATIONS
Oscilloscope
100 W
LVDS
Figure 5. LVDS Output DC Configuration During Device Test
Phase Noise
Analyzer
LVDS
50 W
Figure 6. LVDS Output AC Configuration During Device Test
Figure 7. DC Coupled LVCMOS Input During Device Test
V
OUTNx
OUTPx
OH
V
OD
V
OL
80%
V
(= 2 x V
)
OD
20%
0 V
OUT,DIFF,PP
t
r
t
f
Figure 8. Output Voltage and Rise/Fall Time
8
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVD2108
CDCLVD2108
www.ti.com
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
INNx
INPx
t
t
PLH0
PHL0
OUTN0
OUTP0
t
t
PLH1
PHL1
OUTN1
OUTP1
t
t
PLH2
PHL2
OUTN2
OUTP2
t
t
PHL15
PLH15
OUTN15
OUTP15
A. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn
or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..15).
B. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..15).
C. Both inputs (IN0 and IN1) are phase aligned.
Figure 9. Output Skew and Part-to-Part Skew
V
ring
OUTNx
V
OD
0V Differential
OUTPx
Figure 10. Output Overshoot and Undershoot
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): CDCLVD2108
CDCLVD2108
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
VOS
GND
Figure 11. Output AC Common Mode
APPLICATION INFORMATION
THERMAL MANAGEMENT
For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to of the package. Check the mechanical data at the end of
the data sheet for land and via pattern examples.
POWER-SUPPLY FILTERING
High-performance clock buffers are sensitive to noises on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is very critical to the application.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It
is recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply
pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply
and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
very low dc resistance because it is imperative to provide adequate isolation between the board supply and the
chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required
for proper operation.
Chip
Supply
Board
Supply
Ferrite Bead
1 µF
10 µF
0.1 mF (x6)
Figure 12. Power-Supply Filtering
10
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVD2108
CDCLVD2108
www.ti.com
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
LVDS OUTPUT TERMINATION
The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is
recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage
different than the output common mode voltage of the CDCLVD2108, ac-coupling should be used. If the LVDS
receiver has internal 100 Ω termination, external termination must be omitted.
Unused outputs can be left open without connecting any trace to the output pins.
100 W
LVDS
CDCLVD2108
Z = 50 W
Figure 13. LVDS Output DC Termination
100 nF
100 W
LVDS
CDCLVD2108
Z = 50 W
100 nF
Figure 14. LVDS Output AC Termination With Receiver Internally Biased
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): CDCLVD2108
CDCLVD2108
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
www.ti.com
INPUT TERMINATION
The CDCLVD2108 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.
LVDS Driver can be connected to CDCLVD2108 inputs with dc or ac coupling as shown Figure 15 and
Figure 16, respectively.
100 W
LVDS
CDCLVD2108
Z = 50 W
Figure 15. LVDS Clock Driver Connected to CDCLVD2108 Input (DC Coupled)
100 nF
LVDS
CDCLVD2108
Z = 50 W
100 nF
50 W
50 W
V
AC_REF
Figure 16. LVDS Clock Driver Connected to CDCLVD2108 Input (AC Coupled)
Figure 17 shows how to connect LVPECL inputs to the CDCLVD2108. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 VPP
.
75 W
100 nF
CDCLVD2108
LVPECL
Z = 50 W
100 nF
50 W
75 W
150 W
150 W
50 W
V
AC_REF
Figure 17. LVPECL Clock Driver Connected to CDCLVD2108 Input
Figure 18 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2108 directly. The series
resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs
to be limited to VIH ≤ VCC
.
12
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVD2108
CDCLVD2108
www.ti.com
SCAS905C –OCTOBER 2010–REVISED DECEMBER 2010
R
S
LVCMOS
(2.5V)
CDCLVD2108
V
V
IL
+
2
IH
V
=
th
Figure 18. 2.5V LVCMOS Clock Driver Connected to CDCLVD2108 Input
If one of the input buffers is used, the other buffer should be disabled through the EN pin, and unused input pins
should be grounded by 1 kΩ resistors.
REVISION HISTORY
Changes from Original (October 2010) to Revision A
Page
•
•
•
•
Feature - Low Within Bank Output Skew of 45 ps (Max) To: Low Within Bank Output Skew of 50 ps (Max) ..................... 1
Changed tSK, O_WB Within bank output skew From: 45 ps (Max) To: 50 ps (Max) ................................................................ 5
Changed tSK, O_WB Bank-to-bank output skew From: 100 ps (Max) To: 80 ps (Max) ............................................................ 5
Deleted the Recommended PCB Layout illustration .......................................................................................................... 10
Changes from Revision A (November 2010) to Revision B
Page
•
•
Changed the ICC100, Supply current Typ value From: 97 To: 119 mA .................................................................................. 5
Changed the ICC800, Supply current Typ value From: 138 To: 168 mA ................................................................................ 5
Changes from Revision B (December 2010) to Revision C
Page
•
Changed the device status From: Product Preview To: Production ..................................................................................... 1
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): CDCLVD2108
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDCLVD2108RGZR
CDCLVD2108RGZT
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCLVD2108RGZR
CDCLVD2108RGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
330.0
330.0
16.4
16.4
7.3
7.3
7.3
7.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCLVD2108RGZR
CDCLVD2108RGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
336.6
336.6
336.6
336.6
28.6
28.6
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明