CDCV857BIGG [TI]
857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48;
| 型号： | CDCV857BIGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
D
Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
D
Enters Low-Power Mode When No CLK
Input Signal Is Applied or PWRDWN Is Low
D
Operates From Dual 2.5-V Supplies
D
D
D
D
D
D
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 200 MHz
Low Jitter (cycle-cycle): ±50 ps
Low Static Phase Offset: ±50 ps
Low Jitter (Period): ±35 ps
D
Available in a 48-Pin TSSOP Package or
56-Ball MicroStar Junior BGA Package
D
D
Consumes < 100-µA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
Distributes One Differential Clock Input to
10 Differential Outputs
D
Meets/Exceeds the Latest DDR JEDEC
Spec JESD82–1
description
The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback
clocks (FBIN, FBIN), and the analog power input (AV ). When PWRDWN is high, theoutputs switch in phase
DD
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this
detection circuit turns the PLL on and enables the outputs.
When AV is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also able
DD
to track spread spectrum clocking for reduced EMI.
Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857B is characterized for both commercial and
industrial temperature ranges.
AVAILABLE OPTIONS
T
TSSOP (DGG)
CDCV857BDGG
CDCV857BIGG
MicroStar Junior BGA (GQL)
A
0°C to 85°C
CDCV857BGQL
—
–40°C to 85°C
FUNCTION TABLE
(Select Functions)
INPUTS
PWRDWN
OUTPUTS
PLL
AV
CLK
L
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
DD
GND
H
H
L
H
L
L
H
Z
Z
L
H
L
L
H
Z
Z
L
H
L
Bypassed/Off
GND
H
Bypassed/Off
X
L
H
L
Z
Z
H
L
Z
Z
H
L
Off
Off
On
On
Off
X
L
H
2.5 V (nom)
2.5 V (nom)
2.5 V (nom)
H
H
X
L
H
L
H
H
Z
H
Z
<20 MHz <20 MHz
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments Incorporated.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
MicroStar Junior (GQL) Package
(TOP VIEW)
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
GND
Y0
GND
Y5
1
48
47
46
45
44
43
A
2
Y0
Y5
3
V
V
4
DDQ
Y1
DDQ
B
C
Y6
Y6
Y6
Y6
Y1
Y1
5
Y1
GND
GND
Y2
6
7
42 GND
41 GND
40 Y7
NC
NC
NC
GND
GND
GND
GND
8
9
D
E
F
NC
NC
NC
Y7
Y7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Y2
Y7
Y2
Y2
V
V
DDQ
DDQ
V
PWRDWN
FBIN
DDQ
CLK
PWRDN
V
V
DDQ
DDQ
V
DDQ
CLK
FBIN
NC
NC
NC
FBIN
FBIN
CLK
CLK
V
V
DDQ
DDQ
AV
FBOUT
FBOUT
GND
Y8
DD
G
H
J
NC
NC
AGND
GND
Y3
V
DDQ
V
DDQ
AV
DD
FBOUT
FBOUT
GND
AGND
GND
Y3
Y8
V
V
DDQ
Y4
DDQ
Y8
Y8
Y9
Y3
Y3
Y4
Y9
GND
GND
K
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
functional block diagram
3
Y0
2
Y0
5
Y1
37
PWRDWN
6
Power Down
and Test
Logic
Y1
16
AV
DD
10
Y2
9
Y2
20
Y3
19
Y3
22
Y4
23
Y4
46
Y5
47
Y5
13
14
CLK
CLK
44
Y6
43
Y6
PLL
FBIN 36
39
Y7
35
FBIN
40
Y7
29
Y8
30
Y8
27
Y9
26
Y9
32
FBOUT
33
FBOUT
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
Terminal Functions
TERMINAL
DGG
DESCRIPTION
NAME
AGND
AV
GQL
H1
17
Ground for 2.5-V analog supply
2.5-V Analog supply
16
G2
DD
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
13, 14
35, 36
32, 33
F1, F2
F5, F6
H6, G5
I
I
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
O
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
A3, A4,
C1, C2,
C5, C6,
H2, H5,
K3, K4
PWRDWN
37
E6
I
Output enable for Y and Y
2.5-V Supply
V
DDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
B3, B4,
E1, E2,
E5, G1,
G6, J3, J4
Y[0:9]
Y[0:9]
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
A1, B2,
D1, J2,
K1, A6,
B5, D6,
J5, K6
O
O
Buffered output copies of input clock, CLK
Buffered output copies of input clock, CLK
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
A2, B1,
D2, J1,
K2, A5,
B6, D5,
J6, K5
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
AV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
,
DDQ
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
DDQ
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
IK
I
I
DDQ
Output clamp current, I
(V < 0 or V > V )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
OK
O
O
DDQ
DDQ
Continuous output current, I (V = 0 to V
Continuous current to GND or V
Package thermal impedance, θ (see Note 3): GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.6°C/W
Storage temperature range T
)
O
O
DDQ
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
recommended operating conditions (see Note 4)
MIN
2.3
TYP
MAX UNIT
V
2.7
2.7
V
V
DDQ
AV
Supply voltage
V
DDQ
– 0.12
DD
CLK, CLK, FBIN, FBIN
PWRDWN
V
DDQ
/2 – 0.18
0.7
Low-level input voltage, V
V
IL
–0.3
CLK, CLK, FBIN, FBIN
PWRDWN
V
DDQ
/2 + 0.18
1.7
High-level input voltage, V
IH
V
V
V
DDQ
V
DDQ
V
DDQ
V
DDQ
+ 0.3
+ 0.3
+ 0.6
+ 0.6
DC input signal voltage (see Note 5)
–0.3
0.36
0.7
dc
ac
CLK, FBIN
CLK, FBIN
Differential input signal voltage, V (see Note 6)
ID
V
Input differential pair cross voltage, V (see Note 7)
IX
V
DDQ
/2 – 0.2
V
DDQ
/2 + 0.2
–12
12
V
High-level output current, I
mA
mA
V/ns
OH
Low-level output current, I
Input slew rate, SR
OL
1
0
4
Commercial
Industrial
85
Operating free-air temperature, T
°C
A
–40
85
NOTES: 4. The unused inputs must be held high or low to prevent them from floating.
5. The dc input signal voltage specifies the allowable dc execution of the differential input.
6. The differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input
level and VCP is the complementary input level.
7. The differential cross-point voltage is expected to track variations of V
be crossing.
and is the voltage at which the differential signals must
CC
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
= 2.3 V, I = –18 mA
MIN
TYP
MAX UNIT
V
V
All inputs
V
V
V
V
V
–1.2
V
IK
DDQ
DDQ
DDQ
DDQ
DDQ
I
= min to max, I
= –1 mA
V
– 0.1
OH
= –12 mA
DDQ
High-level output voltage
Low-level output voltage
V
OH
= 2.3 V, I
1.7
OH
= min to max, I
= 1 mA
0.1
0.6
OL
= 12 mA
V
OL
V
V
= 2.3 V, I
OL
}
Differential outputs are terminated
with 120 Ω /CL = 14 pF (See
Figure 3)
V
V
Output voltage swing
1.1
V
– 0.4
OD
DDQ
w
Output differential cross-voltage
V
/2–0.15
V
/2
V
/2+0.15
OX
DDQ
DDQ
DDQ
I
I
Input current
V
V
= 2.7 V, V = 0 V to 2.7 V
±10
±10
µA
µA
I
DDQ
I
High-impedance state output current
Power-down current on
= 2.7 V, V = V
or GND
DDQ
OZ
DDQ
O
CLK and CLK = 0 MHz; PWRDWN
= Low; Σ of I
I
20
100
µA
DDPD
V
DDQ
+ AV
DD
and AI
DD
DD
= 170 MHz
f
f
7
9
10
12
O
AI
DD
Supply current on AV
Input capacitance
mA
pF
DD
= 200 MHz
= 2.5 V, V = V
O
C
V
DDQ
or GND
2
2.5
3.5
I
I
DDQ
†
‡
All typical values are at a respective nominal V
The differential output signal voltage specifies the differential voltage VTR – VCP , where VTR is the true output level and VCP is the
.
DDQ
complementary output level.
The differential cross-point voltage is expected to track variations of V
The frequency range is 100 MHz to 200 MHz.
§
and is the voltage at which the differential signals must be crossing.
DDQ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
110
f
f
= 170 MHz
= 200 MHz
100
105
O
Without load
120
O
Differential outputs
terminated with
120 Ω/CL = 0 pF
f
O
f
O
f
O
f
O
= 170 MHz
= 200 MHz
= 170 MHz
= 200 MHz
200
210
260
280
240
I
Dynamic current on V
mA
DD
DDQ
250
Differential outputs
terminated with
120 Ω/CL = 14 pF
300
320
Part-to-part input capacitance
variation
∆C
V
= 2.5 V, V = V
or GND
or GND
1
pF
DDQ
I
DDQ
DDQ
Input capacitance difference between
CLK and CLKB, FBIN, and FBINB
C
C
V
= 2.5 V, V = V
0.25
3.5
pF
pF
I(∆)
DDQ
DDQ
I
Output capacitance
V
= 2.5 V, V = V or GND
DDQ
2.5
3
O
O
†
All typical values are at a respective nominal V
.
DDQ
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
Operating clock frequency
Application clock frequency
Input clock duty cycle
f
60
200
MHz
CLK
40%
60%
10
{
Stabilization time (PLL mode)
µs
}
Stabilization time (Bypass mode)
30
ns
†
The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
afixed-frequency, fixed-phase reference signal must be present at CLK and V must be applied. Until phase lock is obtained, thespecifications
DD
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply
for input modulation under SSC application.
A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
‡
switching characteristics
PARAMETER
TEST CONDITIONS
Test mode/CLK to any output
Test mode/CLK to any output
66 MHz
MIN
TYP
3.5
MAX
UNIT
ns
w
w
t
t
Low to high level propagation delay time
High-to low level propagation delay time
PLH
PHL
3.5
ns
–60
–35
–75
–50
–100
–75
1
60
35
ps
t
Jitter (period), See Figure 7
jit(per)
jit(cc)
100/133/167/200 MHz
66 MHz
ps
75
t
Jitter (cycle-to-cycle), See Figure 4
ps
100/133/167/200 MHz
66 MHz
50
100
75
t
t
Half-period jitter, See Figure 8
ps
jit(hper)
100/133/167/200 MHz
Load: 120 Ω/14 pF
66 MHz
Output clock slew rate, See Figure 9
2
V/ns
slr(o)
–100
–50
100
50
t
Static phase offset, See Figure 5
ps
(Ø)
100/133/167/200 MHz
Load: 120 Ω/14 pF
Load: 120 Ω/14 pF
tsk
Output skew, See Figure 6
70
100
900
ps
ps
(o)
t , t
Output rise and fall times (20% – 80%)
600
r f
§
¶
Refers to the transition of the noninverting output.
This parameter is assured by design but can not be 100% production tested.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
V
DD
V
Yx
R = 60 Ω
R = 60 Ω
V
DD
/2
V
Yx
CDCV857B
GND
Figure 1. IBIS Model Output Load
V
DD
/2
SCOPE
CDCV857B
–V /2
DD
C = 14 pF
R = 10 Ω
Z = 50 Ω
Z = 60 Ω
R = 50 Ω
(TT)
V
Z = 50 Ω
Z = 60 Ω
R = 10 Ω
R = 50 Ω
C = 14 pF
V
(TT)
–V /2
DD
V
(TT)
= GND
–V /2
DD
Figure 2. Output Load Test Circuit
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
V
DD
PROBE
CDCV857B
C = 14 pF
GND
Z = 60 Ω
Z = 60 Ω
C = 1 pF
R = 1 MΩ
R = 120 Ω
V
(TT)
C = 1 pF
C = 14 pF
R = 1 MΩ
V
(TT)
GND
V
(TT)
= GND
GND
Figure 3. Output Load Test Circuit for Crossing Point
Yx, FBOUT
Yx, FBOUT
t
t
c(n+1)
c(n)
t
= t
– t
jit(cc) c(n) c(n+1)
Figure 4. Cycle-to-Cycle Jitter
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
CLK
CLK
FBIN
FBIN
t
t
(
) n
(
) n+1
n = N
1
∑
t
(
) n
t
=
)
(
N
(N > 1000 Samples)
Figure 5. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
t
sk(o)
Figure 6. Output Skew
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
t
c(n)
Yx, FBOUT
Yx, FBOUT
1
f
o
1
t
= t –
jit(per) cn
f
= Average input frequency measured at CLK/CLK
O
f
o
Figure 7. Period Jitter
Yx, FBOUT
Yx, FBOUT
t
t
(hper_n+1)
(hper_n)
1
f
o
n = any half cycle
1
t
= t
jit(hper) (hper_n) –
f
= Average input frequency measured at CLK/CLK
O
2xf
o
Figure 8. Half-Period Jitter
V , V
OH IH
80%
80%
20%
20%
20%
Clock Inputs
and Outputs
V , V
OL IL
t
t
f
r
V
* V
V
* V
80%
t
20%
80%
+
t
+
t
slr(IńO)
slf(IńO)
t
r(IńO)
f(IńO)
Figure 9. Input and Output Slew Rates
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–ā8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689 – FEBRUARY 2003
MECHANICAL DATA
GQL (R-PBGA-N56)
PLASTIC BALL GRID ARRAY
4,60
4,40
3,25
0,65
0,325
K
J
3X Via Hole
Without
Ball
H
G
F
7,10
6,90
5,85
E
D
C
B
A
Missing Via
Hole Indicates
Pin A1
Quadrant
1
2
3
4
5
6
A1 Corner
Bottom View
1,00 MAX
0,08
Seating Plane
0,45
0,35
56×
0,25
0,15
M
0,05
4200583/D 06/2002
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA configuration
D. Falls within JEDEC MO-225 variation BA.
E. This package is tin-lead (SnPb). Refer to the 56 ZQL package (drawing 4204437) for lead-free.
MicroStar Junior is a trademark of Texas Instruments.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLG003D – MAY 2000 – REVISED FEBRUARY 2003
GQL (R-PBGA-N56)
PLASTIC BALL GRID ARRAY
4,60
4,40
3,25
0,65
0,325
K
J
3X Via Hole
Without
Ball
H
G
F
7,10
6,90
5,85
E
D
C
B
A
Missing Via
Hole Indicates
Pin A1
Quadrant
1
2
3
4
5
6
A1 Corner
Bottom View
1,00 MAX
0,08
Seating Plane
0,45
0,35
56×
0,25
0,15
M
0,05
4200583-2/E 02/2003
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA configuration
D. Falls within JEDEC MO-225 variation BA.
E. This package is tin-lead (SnPb). Refer to the 56 ZQL package (drawing 4204437) for lead-free.
MicroStar Junior is a trademark of Texas Instruments.
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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