CDCVF2505PWRG4 [TI]
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER; 3.3 V时钟锁相环时钟驱动器
| 型号： | CDCVF2505PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER |
| 文件： | 总14页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS640E − JULY 2000 − REVISED MARCH 2005
D OR PW PACKAGE
(TOP VIEW)
D
Phase-Lock Loop Clock Driver for
Synchronous DRAM and General-Purpose
Applications
CLKIN
1Y1
CLKOUT
1Y3
1
2
3
4
8
7
6
5
D
D
D
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
1Y0
V
3.3 V
DD
Low Jitter (Cycle-cycle): <|150 ps| Over the
Range 66 MHz−200 MHz
GND
1Y2
D
Distributes One Clock Input to One Bank of
Five Outputs (CLKOUT Is Used to Tune the
Input-Output Delay)
D
Three-States Outputs When There Is no
Input Clock
D
D
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC
Packages
D
D
Consumes Less Than 100 µA (Typically) in
Power Down Mode
Internal Feedback Loop Is Used to
Synchronize the Outputs to the Input Clock
D
25-Ω On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates
the Need for External Components
D
description
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the output clocks (1Y[0−3] and CLKOUT) to the input clock
signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that
make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50
percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input
signal is applied to CLKIN.
Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop
filter for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2000 − 2005, Texas Instruments Incorporated
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1
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SCAS640E − JULY 2000 − REVISED MARCH 2005
FUNCTION TABLE
INPUT
CLKIN
OUTPUTS
1Y (0:3) CLKOUT
L
H
L
H
Z
L
H
Z
†
<10 MHz
†
Typically, below 2 MHz the device goes in power-down mode in
which the PLL is turned off and the outputs enter into Hi-Z mode. If
a >10-MHz signal is applied at CLKIN the PLL turns on, reacquires
lock, and stabilizes after approximately 100 µs. The outputs will then
be enabled.
functional block diagram
8
3
CLKOUT
1Y0
PLL
1
25 Ω
CLKIN
25 Ω
2
5
Power Down
1Y1
1Y2
25 Ω
25 Ω
25 Ω
7
1Y3
3-State
Edge Detect
Typical <10 MHz
2
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SCAS640E − JULY 2000 − REVISED MARCH 2005
Terminal Functions
TERMINAL
NAME
1Y[0−3]
I/O
DESCRIPTION
NO.
2, 3, 5, 7
O
Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25-Ω
series damping resistor.
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver.
CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once
the circuit is powered up and a valid signal is applied, a stabilization time (100 µs) is required for the
PLL to phase lock the feedback signal to CLKIN.
CLKOUT
GND
8
O
Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is
made inside the chip and an external feedback loop should NOT be connected. CLKOUT can be
loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs.
4
6
Power Ground
V
Power 3.3-V Supply
DD3.3V
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.3 V
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
DD
DD
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
I
DD
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O DD
Continuous total output current, I (V = 0 to V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
O
DD
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.5°C/W
JA
PWR package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230.5°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.3 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
DD
3
3.3
3.6
High-level input voltage, V
IH
0.7 V
V
DD
Low-level input voltage, V
IL
0.3 V
V
DD
Input voltage, V
0
V
DD
V
I
High-level output current, I
−12
12
mA
mA
°C
OH
Low-level output current, I
OL
Operating free-air temperature, T
−40
85
A
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SCAS640E − JULY 2000 − REVISED MARCH 2005
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN NOM
MAX
200
UNIT
f
Clock frequency
24
MHz
clk
24 MHz − 85 MHz (see Note 4)
86 MHz − 200 MHz
30%
85%
60%
100
Input clock duty cycle
40%
50%
Stabilization time (see Note 5)
µs
NOTES: 4. Ensured by design but not 100% production tested.
5. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does
not apply for input modulation under SSC application.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
I = −18 mA
V
MIN TYP
MAX
UNIT
DD
V
IK
3 V
MIN to MAX
3 V
−1.2
V
I
I
I
I
I
I
I
= −100 µA
= −12 mA
= −6 mA
= 100 µA
= 12 mA
= 6 mA
V
DD
−0.2
2.1
OH
OH
OH
OL
OL
OL
V
OH
High-level output voltage
Low-level output voltage
V
V
3 V
2.4
MIN to MAX
3 V
0.2
0.8
V
OL
3 V
0.55
V
V
V
V
= 1 V
3 V
−27
O
O
O
O
I
High-level output current
Low-level output current
mA
mA
OH
= 1.65 V
= 2 V
3.3 V
3 V
−36
40
27
I
I
OL
= 1.65 V
3.3 V
Input current
V = 0 V or V
I
5
µA
I
DD
C
Input capacitance
V = 0 V or V
3.3 V
3.3 V
4.2
2.8
5.2
pF
i
I
DD
Yn
C
Output capacitance
V = 0 V or V
pF
o
I
DD
CLKOUT
†
All typical values are at respective nominal V
DD
and 25°C.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 25 pF, V = 3.3 V 0.3 V (see Note 5)
L
DD
†
PARAMETER
TEST CONDITIONS
CLKIN to Yn, f= 66 MHz to 200 MHz
Yn to Yn
MIN
MAX
150
150
150
400
55%
2
UNIT
ps
TYP
t
t
Propagation delay (normalized (see Figure 3)
Output skew (see Note 6)
−150
pd
ps
sk(o)
f = 66 MHz to 200 MHz
f = 24 MHz to 50 MHz
70
t
Jitter (cycle to cycle) (see Figure 5)
ps
c(jit_cc)
200
odc
Output duty cycle (see Figure 4)
f = 24 MHz to 200 MHz at 50% V
DD
45%
0.5
t
t
Rise time
Fall time
V
V
= 0.4 V to 2 V
= 2 V to 0.4 V
ns
ns
r
O
0.5
2
f
O
†
All typical values are at respective nominal V
and 25°C.
specification is only valid for equal loading of all outputs.
DD
NOTE 6: The t
sk(o)
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SCAS640E − JULY 2000 − REVISED MARCH 2005
ESD information
ESD MODELS
LIMIT
2.0 kV
300 V
1 kV
Human Body Model (HBM)
Machine Model (MM)
Charge Device Model (CDM)
thermal information
THERMAL AIR FLOW (CFM)
UNIT
CDCVF2505 8-PIN SOIC
0
150
87
250
83
500
77
R
R
R
R
High K
Low K
High K
Low K
97
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJC
θJC
165
126
113
97
39
42
THERMAL AIR FLOW (CFM)
CDCVF2505 8-PIN TSSOP
UNIT
0
150
142
185
250
138
170
500
132
150
R
R
R
R
High K
Low K
High K
Low K
149
230
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJC
θJC
65
69
TYPICAL CHARACTERISTICS
t
, PROPAGATION DELAY TIME
pd
t
PROPAGATION DELAY TIME
vs
pd,
vs
DELTA LOAD (TYPICAL VALUES @ 3.3 V, 25°C)
FREQUENCY (TYPICAL VALUES @ 3.3 V, 25°C)
CLOCK FREQUENCY, f = 100 MHz
500
1400
Y
n
= 25 pF
Y = 3 pF
n
Load: CLKOUT = 12 pF || 500 Ω,
= 25 pF || 500 Ω
Y
n
1050
700
CLKOUT = Y
25 pF || 500 Ω
3 pF || 500 Ω
=
n
400
300
350
CLKOUT
3 pF to 25 pF
0
−13
−4
200
−350
CLKOUT
3 pF to 25 pF
−700
100
0
−1050
−1400
−30
−20
−10
0
10
20
30
25
50
75
100
125
150
175
200
Delta Load − pF
f − Frequency − MHz
Figure 2
Figure 1
NOTE: Delta Load = CLKOUT Load − Yn Load
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SCAS640E − JULY 2000 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
t
, TYPICAL PROPAGATION DELAY TIME
vs
DUTY CYCLE
vs
pd
FREQUENCY(TUNED FOR MINIMUM DELAY)
FREQUENCY
55
150
100
50
Load: CLKOUT = 12 pF || 500 Ω,
Yn = 25 pF || 500 Ω
Load: CLKOUT = 21 pF || 500 Ω,
Yn = 25 pF || 500 Ω
52.5
0
50
−50
−100
−150
47.5
45
0
50
100
150
200
25
50
75
100
125
150
175
200
f − Frequency − MHz
f − Frequency − MHz
Figure 3
Figure 4
CYCLE−CYCLE JITTER
I
, SUPPLY CURRENT
vs
FREQUENCY
CC
vs
FREQUENCY
500
400
300
200
100
120
Typical Values @ 3.3 V,
Worst Case @ V
CC
= 3.6 V, T = 85°C,
A
T
= 25°C
Load: Y and CLKOUT = 25 pF || 500 Ω
A
100
80
60
40
20
0
0
25
50
75
100
125
150
175
200
0
20 40 60 80 100 120 140 160 180 200
f − Frequency − MHz
f − Frequency − MHz
Figure 5
Figure 6
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SCAS640E − JULY 2000 − REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500 Ω
Yn = 25 pF || 500 Ω
CLKOUT = 12 pF || 500 Ω
Figure 7. Test Load Circuit
3 V
0 V
CLKIN
50% V
DD
t
pd
V
V
OH
2 V
0.4 V
2 V
1Y0 − 1Y3
50% V
DD
0.4 V
OL
t
t
f
r
Figure 8. Voltage Threshold for Measurements, Propagation Delay (t
)
pd
Any Y
50 % V
DD
t
sk(o)
Any Y
50 % V
DD
Figure 9. Output Skew
t
t
c2
c1
t
= t − t
c(jit_CC) c1 c2
Figure 10. Cycle-to-Cycle Jitter
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDCVF2505D
CDCVF2505DG4
CDCVF2505DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Purchase Samples
Purchase Samples
Request Free Samples
Purchase Samples
Purchase Samples
SOIC
D
2500
2500
150
Green (RoHS
& no Sb/Br)
CDCVF2505DRG4
CDCVF2505PW
CDCVF2505PWR
CDCVF2505PWRG4
SOIC
D
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
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26-Jun-2010
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CDCVF2505 :
Automotive: CDCVF2505-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CDCVF2505DR
SOIC
D
8
8
2500
2000
330.0
330.0
12.4
12.4
6.4
7.0
5.2
3.6
2.1
1.6
8.0
8.0
12.0
12.0
Q1
Q1
CDCVF2505PWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCVF2505DR
SOIC
D
8
8
2500
2000
346.0
346.0
346.0
346.0
29.0
29.0
CDCVF2505PWR
TSSOP
PW
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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