CDCVF25084 [TI]
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER; 3.3 -V 1 ： 8零延迟（ PLL ） X4时钟乘法器
| 型号： | CDCVF25084 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER |
| 文件： | 总12页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
PW PACKAGE (TSSOP)
(TOP VIEW)
D
Phase-Locked Loop-Based Multiplier by
Four
D
Input Frequency Range: 2.5 MHz to 45 MHz
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKIN
1Y0
FBIN
1Y3
1Y2
D
Output Frequency Range: 10 MHz to
180 MHz
1Y1
D
D
D
D
LVCMOS/LVTTL I/O Compatible
V
V
DD
DD
GND
2Y0
2Y1
S2
GND
2Y3
2Y2
S1
Low Jitter (Cycle-Cycle): ±120 ps Over the
Range 75 MHz to 180 MHz
Distributes One Clock Input to Two Banks
of Four Outputs
Auto Frequency Detection to Disable
Device (Power-Down Mode)
D
Operates From Single 3.3-V Supply
D
Industrial Temperature Range –40°C to
85°C
D
D
D
D
25-Ω On-Chip Series Damping Resistors
No External RC Network Required
Spread Spectrum Clock Compatible (SSC)
Available in 16-Pin TSSOP Package
description
The CDCVF25084 is a high-performance, low-skew, low-jitter, phase-lock loop clock multiplier. It uses a PLL
to precisely align, in both frequency and phase, the output clocks to the input clock signal including a
multiplication factor of four. The CDCVF25084 operates from a nominal supply voltage of 3.3 V. The device also
includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point
loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN x four. All outputs operate at the
same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device
automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a
low state. Unlike many products containing PLLs, the CDCVF25084 does not require an external RC network.
The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25084 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization is required following power up and application of
a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25084 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
S2
0
S1
0
1Y0–1Y3
Hi-Z
2Y0–2Y3
Hi-Z
OUTPUT SOURCE
PLL SHUTDOWN
N/A
Yes
No
†
0
1
Active
Active
Active
Hi-Z
PLL
Input clock (PLL bypass)
1
0
Active
Active
Yes
No
†
PLL
1
1
†
A CLK input frequency < 2 MHz switches the outputs to low level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
PIN NO.
1Y[0:3]
2, 3, 14, 15
O
Bank 1Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series-damping resistor.
2Y[0:3]
CLKIN
6, 7, 10, 11
1
O
I
Bank 2Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series-damping resistor.
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF25084 clock driver. CLKIN is
used to provide the reference signal to the integrated PLL that generates the output signal. CLKIN must
have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and
a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to
CLKIN.
FBIN
16
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the
outputstocompletethefeedbackloopoftheinternalPLL.TheintegratedPLLsynchronizestheFBINand
output signal so there is nominally zero-delay from input clock to output clock.
GND
5, 12
9, 8
Ground Ground
S1, S2
I
Select pins to determine mode of operation. See the FUNCTION TABLE for mode selection options.
V
DD
4, 13
Power
Supply voltage. The supply voltage range is 3 V to 3.6 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
functional block diagram
2
1Y0
25 Ω
16
Div by 4
FBIN
PLL
M
U
X
1
3
CLKIN
1Y1
1Y2
1Y3
25 Ω
25 Ω
25 Ω
14
15
8
S2
S1
Input
Select
Decoding
9
6
2Y0
2Y1
2Y2
2Y3
25 Ω
25 Ω
25 Ω
25 Ω
7
10
11
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
DD
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous total output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O
O
DD
Package thermal impedance, θ (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147°C/W
JA
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
NOM MAX
UNIT
V
Supply voltage, V
DD
3
3.3
3.6
0.8
Low level input voltage, V
V
IL
High level input voltage, V
2
0
V
IH
Input voltage, V
3.6
–12
12
V
I
High-level output current, I
mA
mA
°C
OH
Low-level output current, I
OL
Operating free-air temperature, T
–40
85
A
timing requirements over recommended ranges of supply voltage, load and operating free-air
temperature
MIN
2.5
NOM MAX
45
UNIT
Input clock frequency, f
Input clock duty cycle
MHz
CLKIN
40%
10
60%
180
Clock frequency, f
clkout
C
= 15 pF
MHz
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
= 3 V, I = –18 mA
MIN TYP
MAX
–1.2
±5
UNIT
V
V
IK
V
DD
V = 0 V or V
I
I
I
I
I
Input current
µA
µA
mA
µA
pF
I
I
DD
= 0 MHz,
Power-down current
Dynamic current
f
f
V
= 3.3 V
= 15 pF
100
80
PD
DD
OZ
CLKIN
= 80 MHz,
DD
‡
C
60
out
L
Output 3-state
V = 0 V or V
,
V
DD
= 3.6 V
±5
o
DD
DD
DD
DD
C
C
C
Input capacitance at FBIN, CLKIN
Input capacitance at S1, S2
Output capacitance
V = 0 V or V
4
2.2
3
I
I
V = 0 V or V
pF
I
I
V = 0 V or V
pF
O
I
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= min to max,
= 3 V,
I
I
I
I
I
I
= –100 µA
= –12 mA
= –6 mA
V
DD
– 0.2
2.1
OH
OH
OH
V
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
V
V
OH
= 3 V,
2.4
= min to max,
= 3 V,
= 100 µA
= 12 mA
= 6 mA
0.2
0.8
OL
OL
OL
V
I
OL
= 3 V,
0.55
= 3 V,
V
V
V
V
V
V
= 1 V
–24
O
O
O
O
O
O
= 3.3 V,
= 3.6 V,
= 3 V,
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
–30
mA
mA
OH
-15
14
26
I
= 3.3 V,
= 3.6 V,
33
OL
†
‡
All typical values are at respective nominal V
.
DD
over frequency see Figure 9.
All outputs are switching; for I
DD
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
PLL lock time
TEST CONDITIONS
= 100 MHz
MIN TYP
MAX
UNIT
t
t
f
f
f
2
µs
(lock)
out
out
out
= 40 MHz to 75 MHz, Vth = V /2
DD
±200
±100
4.5
Phase offset (CLKIN to FBIN), (see
Note 5)
ps
(phoffset)
= 75 MHz to 180 MHz, Vth = V /2
DD
t
t
, t
Propagation delay
S2 = High, S1 = Low (PLL bypass mode)
See Figure 3
2.3
ns
ps
PLH PHL
Output skew (Yn to Yn) (see Note 4)
75
150
sk(o)
PLL bypass mode
900
Part-to-part skew
(low-to-high transition)
PLL mode, f
PLL mode, f
= 40 MHz to 75 MHz
= 75 MHz to 180 MHz
350
t
ps
out
out
sk(pp)
300
f
f
f
f
f
= 40 MHz to 75 MHz
±220
±120
260
ps
ps
ps
ps
out
out
out
out
out
t
t
Jitter (cycle-to-cycle)
Period jitter
jit(cc)
= 75 MHz to 180 MHz
= 40 MHz to 75 MHz
jit(per)
= 75 MHz to 180 MHz
140
= 75 MHz to 180 MHz, peak-to-peak
±110
ps
ps
(see Note 6)
t
Phase jitter
jit(θ)
f
f
= 75 MHz to 180 MHz, RMS (see Note 6)
= 10 MHz to 180 MHz
26
55%
0.3
3
out
odc
Output duty cycle
Pulse skew
45%
1
out
t
S2 = High, S1 = low (PLL bypass mode)
See Figure 4
ns
sk(p)
t , t
Rise / fall time rate
V/ns
r f
†
All typical values are at respective nominal V
.
DD
specification is only valid for equal loading of all outputs.
NOTES: 4. The t
sk(o)
5. Similarwaveform at CLKIN and FBIN are required. Output 1Y3 is used as a feedback to FBIN loaded with 11 pF and all otheroutputs
have 15 pF. For phase displacement between CLKIN and Y-outputs, see Figure 5.
6. Input phase jitter < ±50 ps; output sample size is 20000 cycles.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
V
DD
1000 Ω
1000 Ω
From Output Under Test
= 15 pF at f = 10 MHz to 180 MHz
C
L
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: Z = 50 Ω, t < 1.2 ns, t < 1.2 ns
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Test Load Circuit
V
V
OH
50% V
DD
CLKIN
OL
t
(phoffset)
V
OH
50% V
DD
FBIN
V
OL
Figure 2. Voltage Thresholds for Measurements, Phase Offset (PLL Mode)
50% V
DD
Any Y
Any Y
50% V
50% V
DD
DD
t
t
1
sk(0)
t
2
NOTE: odc = t /(t + t ) x 100%
1
1
2
Figure 3. Output Skew and Output Duty Cycle (PLL Mode)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
V
OH
50% V
DD
CLKIN
V
OL
t
t
PHL
PLH
V
OH
80%
80%
50% V
50% V
DD
20%
DD
20%
Any Y
V
OL
t
t
f
r
NOTE: t |
=|t
t
sk(p) PLH– PHL
Figure 4. Propagation Delay and Pulse Skew (Non-PLL Mode)
PHASE DISPLACEMENT
PHASE OFFSET
vs
vs
CLOAD
FREQUENCY
500
250
C
C
= 15 pF,
400
300
200
100
V
C
= 3.3 V,
= 15 pF
L(Yn)
L(FBIN)
CC
Yn
= 11 pF
200
150
0
–100
–200
–300
–400
–500
100
50
–600
–700
–800
–900
–1000
–1100
–1200
–1300
0
–50
–10 –5
0
5
10 15 20 25 30 50 35 40 45
10
110
130 150 170
30
50
70
90
Cload Difference Between FBIN and Yn Pins – pF
f – Output Frequency – MHz
(C + 4 pF) – C
FBIN
Yn
Figure 5
Figure 6
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
CYCLE-TO-CYCLE / PERIOD JITTER
vs
FREQUENCY
TRANSFER CHARACTERISTIC FROM CLKIN TO Yn
20
1300
1200
1100
1000
900
V
= 3.3 V
DD
All Outputs
Switching
18
16
14
12
10
800
700
600
Cycle-to-Cycle Jitter
Period Jitter
500
8
6
4
400
300
200
2
0
100
0
10 30 50 70 90 110 130 150 170 190
0.1
1
10
f – Output Frequency – MHz
f – Frequency – MHz
Figure 8
Figure 7
SUPPLY CURRENT
vs
FREQUENCY
180
160
140
120
100
80
V
= 3.6 V
= 85°C
DD
A
T
V
T
A
= 3 V
DD
= –40°C
V
T
A
= 3 V
= –40°C
DD
V
T
A
= 3 V
= –40°C
DD
60
40
20
0
10 30 50 70 90 110 130 150 170 190
f – Output frequency – MHz
Figure 9
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
M
0,10
0,65
0,19
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2003, Texas Instruments Incorporated
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