CDCVF25081PWG4 [TI]
3.3-V PHASED-LOCK LOOP CLOCK DRIVER; 3.3 -V锁相环时钟驱动器
| 型号： | CDCVF25081PWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V PHASED-LOCK LOOP CLOCK DRIVER |
| 文件： | 总16页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
D PACKAGE (SOIC)
PW PACKAGE (TSSOP)
(TOP VIEW)
D
Phase-Locked Loop-Based Zero-Delay
Buffer
D
Operating Frequency: 8 MHz to 200 MHz
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKIN
1Y0
FBIN
1Y3
1Y2
D
Low Jitter (Cycle-Cycle): ±100 ps Over the
Range 66 MHz to 200 MHz
1Y1
D
D
D
Distributes One Clock Input to Two Banks
of Four Outputs
V
V
DD
DD
GND
2Y0
2Y1
S2
GND
2Y3
2Y2
S1
Auto Frequency Detection to Disable
Device (Power Down Mode)
Consumes Less Than 20 µA in Power Down
Mode
D
Operates From Single 3.3-V Supply
D
Industrial Temperature Range –40°C to
85°C
D
D
D
D
25-Ω On-Chip Series Damping Resistors
No External RC Network Required
Spread Spectrum Clock Compatible (SSC)
Available in 16-Pin TSSOP or 16-Pin SOIC
Packages
description
The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to
precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081
operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors
in the output drivers that make it ideal for driving point-to-point loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN. All outputs operate at the same
frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device
automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a
low state. Unlike many products containing PLLs, the CDCVF25081 does not require an external RC network.
The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization is required following power up and application of
a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25081 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
S2
0
S1
0
1Y0–1Y3
Hi-Z
2Y0–2Y3
Hi-Z
OUTPUT SOURCE
PLL SHUTDOWN
N/A.
Yes
No
†
0
1
Active
Active
Active
Hi-Z
PLL
Input clock (PLL bypass)
1
0
Active
Active
Yes
No
†
PLL
1
1
†
CLK input frequency < 2 MHz switches the outputs to low level
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001 – 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
PIN NO.
1Y[0:3]
2Y[0:3]
CLKIN
2, 3, 14, 15
O
Bank 1Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series-damping resistor.
6, 7, 10, 11
1
O
I
Bank 2Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series-damping resistor.
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF25081 clock driver. CLKIN is
used to provide the reference signal to the integrated PLL that generates the output signal. CLKIN must
have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and
a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to
CLKIN.
FBIN
16
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the
outputstocompletethefeedbackloopoftheinternalPLL.TheintegratedPLLsynchronizestheFBINand
output signal so there is nominally zero-delay from input clock to output clock.
GND
5, 12
9, 8
Ground Ground
S1, S2
I
Select pins to determine mode of operation. See the FUNCTION TABLE for mode selection options.
V
DD
4, 13
Power
Supply voltage. The supply voltage range is 3 V to 3.6 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
functional block diagram
2
1Y0
25 Ω
16
FBIN
PLL
M
U
X
1
3
CLKIN
1Y1
25 Ω
14
1Y2
25 Ω
15
1Y3
25 Ω
8
S2
Input
Select
Decoding
9
S1
6
2Y0
25 Ω
7
2Y1
25 Ω
10
2Y2
25 Ω
11
2Y3
25 Ω
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
DD
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous total output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
O
DD
Package thermal impedance, θ (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147°C/W
JA
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
NOM MAX
UNIT
V
Supply voltage, V
DD
3
3.3
3.6
0.8
Low level input voltage, V
V
IL
High level input voltage, V
2
0
V
IH
Input voltage, V
3.6
–12
12
V
I
High-level output current, I
mA
mA
°C
OH
Low-level output current, I
OL
Operating free-air temperature, T
-40
85
A
timing requirements over recommended ranges of supply voltage, load and operating free-air
temperature
MIN
NOM MAX
UNIT
C
C
= 25 pF
= 15 pF
8
100
200
L
L
Clock frequency, f
clk
MHz
66
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
= 3 V, I = -18 mA
MIN TYP
MAX
–1.2
±5
UNIT
V
V
IK
V
DD
V = 0 V or V
I
I
I
I
Input current
µA
µA
µA
pF
pF
pF
I
I
DD
= 0 MHz,
‡
Power down current
Output 3-state
f
V
V
= 3.3 V
= 3.6 V
20
PD
OZ
CLKIN
= 0 V or V
DD
V
o
±5
DD,
DD
DD
DD
DD
C
C
C
Input capacitance at FBIN, CLKIN
Input capacitance at S1, S2
Output capacitance
V = 0 V or V
4
I
I
V = 0 V or V
2.2
3
I
I
V = 0 V or V
O
I
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= min to max,
= 3 V,
I
I
I
= -100 µA
= -12 mA
= -6 mA
= 100 µA
= 12 mA
= 6 mA
V
DD
– 0.2
2.1
OH
OH
OH
V
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
V
V
OH
= 3 V,
2.4
= min to max,
= 3 V,
I
0.2
0.8
OL
I
I
V
I
OL
OL
OL
= 3 V,
0.55
= 3 V,
V
V
V
V
V
V
= 1 V
–24
O
O
O
O
O
O
= 3.3 V,
= 3.6 V,
= 3 V,
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
–30
mA
mA
OH
-15
14
26
I
= 3.3 V,
= 3.6 V,
33
OL
†
‡
All typical values are at respective nominal V
.
DD
For I
over frequency see Figure 7.
DD
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
PLL lock time
TEST CONDITIONS
MIN TYP
10
MAX
UNIT
t
f = 100 MHz
f = 8 MHz to 66 MHz,
Vth = V /2 (see Note 5)
DD
µs
(lock)
–200
200
t
Phase offset (CLKIN to FBIN)
ps
ns
(phoffset)
f = 66 MHz to 200 MHz,
Vth = V /2 (see Note 5)
DD
–150
150
6
t
t
t
Low-to-high level output propagation delay
High-to-low level output propagation delay
Output skew (Yn to Yn) (see Note 4)
2.5
PLH
PHL
sk(o)
S2 = High,
f = 1 MHz,
S1 = Low (PLL bypass)
= 25 pF
C
L
150
600
ps
ps
S2 = high,
S2 = high,
S1 = high (PLL mode)
S1 = low (PLL bypass)
t
Part-to-part skew
sk(pp)
jit(cc)
700
f = 66 MHz to 200 MHz, C = 15 pF
L
±100
t
Jitter (cycle-to-cycle)
ps
f = 66 MHz to 100 MHz, C = 25 pF
L
±150
57%
0.7
f = 8 MHz to 66 MHz (see Figure 6)
odc
Output duty cycle
Pulse skew
f = 8 MHz to 200 MHz
43%
S2 = High,
f = 1 MHz,
S1 = low (PLL bypass)
= 25 pF
t
t
t
ns
sk(p)
C
L
C
C
C
C
= 15 pF,
= 25 pF,
= 15 pF,
= 25 pF,
See Figure 4
See Figure 4
See Figure 4
See Figure 4
0.8
0.5
0.8
0.5
3.3
2
L
L
L
L
Rise time rate
Fall time rate
V/ns
V/ns
r
f
3.3
2
†
All typical values are at respective nominal V
.
DD
specification is only valid for equal loading of all outputs.
NOTES: 4. The t
sk(o)
5. Similar waveform at CLKIN and FBIN are required. For phase displacement between CLKIN and Y-outputs see Figure 5.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
V
DD
1000 Ω
1000 Ω
From Output Under Test
C
C
= 25 pF at f = 8 MHz to 100 MHz
= 15 pF at f = 66 MHz to 200 MHz
L
L
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: Z = 50 Ω, t < 1.2 ns, t < 1.2 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Test Load Circuit
V
DD
50% V
DD
CLKIN
0 V
t
(phoffset)
V
OH
50% V
DD
FBIN
V
OL
Figure 2. Voltage Thresholds for Measurements, Phase Offset (PLL Mode)
50% V
DD
Any Y
Any Y
50% V
50% V
DD
DD
t
t
1
sk(0)
t
t
2
sk(0)
NOTE: odc = t /(t + t ) x 100%
1
1
2
Figure 3. Output Skew and Output Duty Cycle (PLL Mode)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
V
DD
50% V
0 V
DD
CLKIN
t
t
PHL
PLH
V
OH
80%
80%
50% V
50% V
DD
20%
DD
20%
Any Y
V
OL
t
t
f
r
NOTE: t
=|t |
t
sk(p) PLH– PHL
Figure 4. Propagation Delay and Pulse Skew (Non-PLL Mode)
PHASE DISPLACEMENT
CYCLE-TO-CYCLE JITTER
vs
CLOAD
vs
FREQUENCY
100
50
500
450
400
350
300
250
200
150
100
50
V
= 3.3 V
DD
All Outputs Switching
C (Yn) = 25 pF || 500 Ω
V
= 3 V
L
DD
0
V
DD
= 3.6 V
–50
–100
–150
V
= 3.3 V
DD
0
–10 –8 –6 –4 –2
0
2
4
6
8
10
10
20
30
40
50
60
70
80
90 100
Cload Difference Between FBIN and Yn Pins – pF
f – Frequency – MHz
(C + 4 pF) – C
FB
Yn
Figure 5
Figure 6
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
SUPPLY CURRENT
vs
FREQUENCY
180
160
140
120
100
80
V
= 3 V to 3.6 V
DD
C (Yn) = 15 pF || 500 Ω
V
= 3.6 V
DD
T = 85°C
A
L
T
A
= –40°C to 85°C
V
= 3.6 V
DD
T
A
= –40°C
V = 3 V
DD
= –40°C
T
A
60
V
T
A
= 3 V
DD
= 85°C
40
20
0
0
20 40 60 80 100 120 140 160 180 200
f – Frequency – MHz
Figure 7
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
PACKAGING INFORMATION
Orderable Device
CDCVF25081D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDCVF25081DG4
CDCVF25081DR
SOIC
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDCVF25081DRG4
CDCVF25081PW
CDCVF25081PWG4
CDCVF25081PWR
CDCVF25081PWRG4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCVF25081DR
SOIC
D
16
16
2500
2000
330.0
330.0
16.4
12.4
6.5
6.9
10.3
5.6
2.1
1.6
8.0
8.0
16.0
12.0
Q1
Q1
CDCVF25081PWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCVF25081DR
SOIC
D
16
16
2500
2000
367.0
367.0
367.0
367.0
38.0
35.0
CDCVF25081PWR
TSSOP
PW
Pack Materials-Page 2
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