CDCVF25084PWR [TI]
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER; 3.3 -V 1 : 8零延迟( PLL ) X4时钟乘法器![CDCVF25084PWR](http://pdffile.icpdf.com/pdf2/p00215/img/icpdf/CDCVF2_1215231_icpdf.jpg)
型号: | CDCVF25084PWR |
厂家: | ![]() |
描述: | 3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER |
文件: | 总15页 (文件大小:539K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
PW PACKAGE (TSSOP)
(TOP VIEW)
D
Phase-Locked Loop-Based Multiplier by
Four
D
Input Frequency Range: 2.5 MHz to 45 MHz
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKIN
1Y0
FBIN
1Y3
1Y2
D
Output Frequency Range: 10 MHz to
180 MHz
1Y1
D
D
D
D
LVCMOS/LVTTL I/O Compatible
V
V
DD
DD
GND
2Y0
2Y1
S2
GND
2Y3
2Y2
S1
Low Jitter (Cycle-Cycle): ±120 ps Over the
Range 75 MHz to 180 MHz
Distributes One Clock Input to Two Banks
of Four Outputs
Auto Frequency Detection to Disable
Device (Power-Down Mode)
D
Operates From Single 3.3-V Supply
D
Industrial Temperature Range –40°C to
85°C
D
D
D
D
25-Ω On-Chip Series Damping Resistors
No External RC Network Required
Spread Spectrum Clock Compatible (SSC)
Available in 16-Pin TSSOP Package
description
The CDCVF25084 is a high-performance, low-skew, low-jitter, phase-lock loop clock multiplier. It uses a PLL
to precisely align, in both frequency and phase, the output clocks to the input clock signal including a
multiplication factor of four. The CDCVF25084 operates from a nominal supply voltage of 3.3 V. The device also
includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point
loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN x four. All outputs operate at the
same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device
automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a
low state. Unlike many products containing PLLs, the CDCVF25084 does not require an external RC network.
The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25084 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization is required following power up and application of
a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25084 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
S2
0
S1
0
1Y0–1Y3
Hi-Z
2Y0–2Y3
Hi-Z
OUTPUT SOURCE
PLL SHUTDOWN
N/A
Yes
No
†
0
1
Active
Active
Active
Hi-Z
PLL
Input clock (PLL bypass)
1
0
Active
Active
Yes
No
†
PLL
1
1
†
A CLK input frequency < 2 MHz switches the outputs to low level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
PIN NO.
1Y[0:3]
2, 3, 14, 15
O
Bank 1Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series-damping resistor.
2Y[0:3]
CLKIN
6, 7, 10, 11
1
O
I
Bank 2Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series-damping resistor.
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF25084 clock driver. CLKIN is
used to provide the reference signal to the integrated PLL that generates the output signal. CLKIN must
have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and
a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to
CLKIN.
FBIN
16
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the
outputstocompletethefeedbackloopoftheinternalPLL.TheintegratedPLLsynchronizestheFBINand
output signal so there is nominally zero-delay from input clock to output clock.
GND
5, 12
9, 8
Ground Ground
S1, S2
I
Select pins to determine mode of operation. See the FUNCTION TABLE for mode selection options.
V
DD
4, 13
Power
Supply voltage. The supply voltage range is 3 V to 3.6 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
functional block diagram
2
1Y0
25 Ω
16
Div by 4
FBIN
PLL
M
U
X
1
3
CLKIN
1Y1
1Y2
1Y3
25 Ω
25 Ω
25 Ω
14
15
8
S2
S1
Input
Select
Decoding
9
6
2Y0
2Y1
2Y2
2Y3
25 Ω
25 Ω
25 Ω
25 Ω
7
10
11
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
DD
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous total output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O
O
DD
Package thermal impedance, θ (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147°C/W
JA
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
NOM MAX
UNIT
V
Supply voltage, V
DD
3
3.3
3.6
0.8
Low level input voltage, V
V
IL
High level input voltage, V
2
0
V
IH
Input voltage, V
3.6
–12
12
V
I
High-level output current, I
mA
mA
°C
OH
Low-level output current, I
OL
Operating free-air temperature, T
–40
85
A
timing requirements over recommended ranges of supply voltage, load and operating free-air
temperature
MIN
2.5
NOM MAX
45
UNIT
Input clock frequency, f
Input clock duty cycle
MHz
CLKIN
40%
10
60%
180
Clock frequency, f
clkout
C
= 15 pF
MHz
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
= 3 V, I = –18 mA
MIN TYP
MAX
–1.2
±5
UNIT
V
V
IK
V
DD
V = 0 V or V
I
I
I
I
I
Input current
µA
µA
mA
µA
pF
I
I
DD
= 0 MHz,
Power-down current
Dynamic current
f
f
V
= 3.3 V
= 15 pF
100
80
PD
DD
OZ
CLKIN
= 80 MHz,
DD
‡
C
60
out
= 0 V or V
L
Output 3-state
V
o
,
V
DD
= 3.6 V
±5
DD
DD
DD
DD
C
C
C
Input capacitance at FBIN, CLKIN
Input capacitance at S1, S2
Output capacitance
V = 0 V or V
4
2.2
3
I
I
V = 0 V or V
pF
I
I
V = 0 V or V
pF
O
I
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= min to max,
= 3 V,
I
I
I
I
I
I
= –100 µA
= –12 mA
= –6 mA
V
DD
– 0.2
2.1
OH
OH
OH
V
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
V
V
OH
= 3 V,
2.4
= min to max,
= 3 V,
= 100 µA
= 12 mA
= 6 mA
0.2
0.8
OL
OL
OL
V
I
OL
= 3 V,
0.55
= 3 V,
V
V
V
V
V
V
= 1 V
–24
O
O
O
O
O
O
= 3.3 V,
= 3.6 V,
= 3 V,
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
–30
mA
mA
OH
-15
14
26
I
= 3.3 V,
= 3.6 V,
33
OL
†
‡
All typical values are at respective nominal V
.
DD
over frequency see Figure 9.
All outputs are switching; for I
DD
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
PLL lock time
TEST CONDITIONS
= 100 MHz
MIN TYP
MAX
UNIT
t
t
f
f
f
2
µs
(lock)
out
out
out
= 40 MHz to 75 MHz, Vth = V /2
DD
±200
±100
4.5
Phase offset (CLKIN to FBIN), (see
Note 5)
ps
(phoffset)
= 75 MHz to 180 MHz, Vth = V /2
DD
t
t
, t
Propagation delay
S2 = High, S1 = Low (PLL bypass mode)
See Figure 3
2.3
ns
ps
PLH PHL
Output skew (Yn to Yn) (see Note 4)
75
150
sk(o)
PLL bypass mode
900
Part-to-part skew
(low-to-high transition)
PLL mode, f
PLL mode, f
= 40 MHz to 75 MHz
= 75 MHz to 180 MHz
350
t
ps
out
out
sk(pp)
300
f
f
f
f
f
= 40 MHz to 75 MHz
±220
±120
260
ps
ps
ps
ps
out
out
out
out
out
t
t
Jitter (cycle-to-cycle)
Period jitter
jit(cc)
= 75 MHz to 180 MHz
= 40 MHz to 75 MHz
jit(per)
= 75 MHz to 180 MHz
140
= 75 MHz to 180 MHz, peak-to-peak
±110
ps
ps
(see Note 6)
t
Phase jitter
jit(θ)
f
f
= 75 MHz to 180 MHz, RMS (see Note 6)
= 10 MHz to 180 MHz
26
55%
0.3
3
out
odc
Output duty cycle
Pulse skew
45%
1
out
t
S2 = High, S1 = low (PLL bypass mode)
See Figure 4
ns
sk(p)
t , t
Rise / fall time rate
V/ns
r
f
†
All typical values are at respective nominal V
.
DD
specification is only valid for equal loading of all outputs.
NOTES: 4. The t
sk(o)
5. Similarwaveform at CLKIN and FBIN are required. Output 1Y3 is used as a feedback to FBIN loaded with 11 pF and all otheroutputs
have 15 pF. For phase displacement between CLKIN and Y-outputs, see Figure 5.
6. Input phase jitter < ±50 ps; output sample size is 20000 cycles.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
V
DD
1000 Ω
1000 Ω
From Output Under Test
= 15 pF at f = 10 MHz to 180 MHz
C
L
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: Z = 50 Ω, t < 1.2 ns, t < 1.2 ns
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Test Load Circuit
V
V
OH
50% V
DD
CLKIN
OL
t
(phoffset)
V
OH
50% V
DD
FBIN
V
OL
Figure 2. Voltage Thresholds for Measurements, Phase Offset (PLL Mode)
50% V
DD
Any Y
Any Y
50% V
50% V
DD
DD
t
t
1
sk(0)
t
2
NOTE: odc = t /(t + t ) x 100%
1
1
2
Figure 3. Output Skew and Output Duty Cycle (PLL Mode)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
V
OH
50% V
DD
CLKIN
V
OL
t
t
PHL
PLH
V
OH
80%
80%
50% V
50% V
DD
20%
DD
20%
Any Y
V
OL
t
t
f
r
NOTE: t |
=|t
t
sk(p) PLH– PHL
Figure 4. Propagation Delay and Pulse Skew (Non-PLL Mode)
PHASE DISPLACEMENT
PHASE OFFSET
vs
vs
CLOAD
FREQUENCY
500
250
C
C
= 15 pF,
400
300
200
100
V
C
= 3.3 V,
= 15 pF
L(Yn)
L(FBIN)
CC
Yn
= 11 pF
200
150
0
–100
–200
–300
–400
–500
100
50
–600
–700
–800
–900
–1000
–1100
–1200
–1300
0
–50
–10 –5
0
5
10 15 20 25 30 50 35 40 45
10
110
130 150 170
30
50
70
90
Cload Difference Between FBIN and Yn Pins – pF
f – Output Frequency – MHz
(C + 4 pF) – C
FBIN
Yn
Figure 5
Figure 6
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF25084
3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A – APRIL 2003 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
CYCLE-TO-CYCLE / PERIOD JITTER
vs
FREQUENCY
TRANSFER CHARACTERISTIC FROM CLKIN TO Yn
20
1300
1200
1100
1000
900
V
= 3.3 V
DD
All Outputs
Switching
18
16
14
12
10
800
700
600
Cycle-to-Cycle Jitter
Period Jitter
500
8
6
4
400
300
200
2
0
100
0
10 30 50 70 90 110 130 150 170 190
0.1
1
10
f – Output Frequency – MHz
f – Frequency – MHz
Figure 8
Figure 7
SUPPLY CURRENT
vs
FREQUENCY
180
160
140
120
100
80
V
= 3.6 V
= 85°C
DD
A
T
V
T
A
= 3 V
DD
= –40°C
V
T
A
= 3 V
= –40°C
DD
V
T
A
= 3 V
= –40°C
DD
60
40
20
0
10 30 50 70 90 110 130 150 170 190
f – Output frequency – MHz
Figure 9
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2006
PACKAGING INFORMATION
Orderable Device
CDCVF25084PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
16
16
16
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDCVF25084PWG4
CDCVF25084PWR
CDCVF25084PWRG4
TSSOP
TSSOP
TSSOP
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCVF25084PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
CDCVF25084PWR
2000
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明