CDCVF310_15 [TI]
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER;
| 型号： | CDCVF310_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER |
| 文件： | 总12页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
•
High-Performance 1:10 Clock Driver for
General-Purpose Applications
PW PACKAGE
(TOP VIEW)
•
•
•
•
•
•
Pin-to-Pin Skew < 100 ps at VDD 3.3 V
VDD Range = 2.3 V to 3.6 V
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
CLK
2
V
DD
V
DD
Input Clock Up To 200 MHz (See Figure 7)
Operating Temperature Range –40°C to 85°C
Output Enable Glitch Suppression
3
1Y0
1Y1
1Y2
GND
GND
1Y3
V
DD
4
2Y0
2Y1
GND
GND
2Y2
2Y3
5
Distributes One Clock Input to Two Banks of
Five Outputs
6
7
8
•
•
Packaged in 24-Pin TSSOP
9
1Y4
Pin-to-Pin Compatible to the CDCVF2310,
Except the R = 22-Ω Series Damping
Resistors at Yn
10
11
12
V
DD
V
V
DD
1G
2Y4
DD
2G
DESCRIPTION
The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless
of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a
low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on
the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a
2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable
sequence to distribute full period clock signals.
The CDCVF310 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
FUNCTIONAL BLOCK DIAGRAM
3
4
1Y0
1Y1
1Y2
1Y3
1Y4
5
8
9
11
Logic Control
Logic Control
1G
13
2G
21
20
17
16
12
2Y0
2Y1
2Y2
2Y3
2Y4
24
CLK
2
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
FUNCTION TABLE
INPUT
OUTPUT
1G
L
2G
L
CLK
1Y[0:4]
2Y[0:4]
L
↓
↓
↓
↓
L
H
L
L
CLK(1)
L
H
H
L
CLK(1)
CLK(1)
H
CLK(1)
(1) After detecting one negative edge on the CLK input, the output
follows the input CLK if the control pin is held high.
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
1G
11
I
Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the
1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
2G
13
I
Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the
2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
1Y[0:4]
2Y[0:4]
CLK
3, 4, 5, 8, 9
21, 20, 17, 16, 12
24
O
O
I
Buffered output clocks
Buffered output clocks
Input reference frequency
Ground
GND
1, 6, 7, 18, 19
2, 10, 14, 15, 22, 23
VDD
DC power supply, 2.3 V – 3.6 V
3
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
DETAILED DESCRIPTION
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.
CLK
G
n
n
Y
t
t
h(en)
su(en)
a) Enable Mode
CLK
G
n
n
Y
t
t
h(dis)
su(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
4
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage range, VDD
Input voltage range, VI(2)(3)
–0.5 V to 4.6 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
±50 mA
(2)(3)
Output voltage range, VO
Input clamp current, IIK (VI < 0 or VI> VDD
)
Output clamp current, IOK (VO < 0 or VO > VDD
)
±50 mA
Continuous total output current, IO (VO = 0 to VDD
Package thermal impedance, θJA(4): PW package
Storage temperature range Tstg
)
±50 mA
88°C/W, high K
120°C/W, low K
–65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51.
(1)
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
2.3
2.5
3.3
Supply voltage, VDD
V
3.6
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
0.8
V
Low-level input voltage, VIL
0.7
2
1.7
0
High-level input voltage, VIH
Input voltage, VI
V
VDD
-12
-6
V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
High-level output current, IOH
mA
12
6
Low-level output current, IOL
mA
Operating free-air temperature, TA
-40
85
°C
(1) Unused inputs must be held high or low to prevent them from floating.
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 2.3 V to 3.6 V, See Figure 7
MIN
TYP
MAX
200
UNIT
fclk
Clock frequency
0
MHz
5
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
Input voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIK
II
VDD = 3 V,
II = –18 mA
–1.2
±5
V
Input current
VI = 0 V or VDD
µA
µA
pF
pF
pF
(2)
IDD
CI
Static device current
Input capacitance
Output capacitance
Power dissipation(3)
CLK = 0 V or VDD = 3.6 V, IO = 0 mA
80
VDD = 2.3 V to 3.6 V,
VDD = 2.3 V to 3.6 V,
VDD = 2.3 V to 3.6 V,
VI = 0 V or VDD
2.5
2.6
CO
VI = 0 V or VDD
VI= 0 V or VDD
CPD
32
(1) All typical values are with respect to nominal VDD
.
(2) For dynamic IDD over Frequency see Figure 6.
(3) This is the formula for the power dissipation calculation.
P_tot + P_stat ) P_Dyn ) P_Load[W]
P_stat + V I [W]
DD
DD
P_Dyn + C_PD V V ƒ [W]
DD
DD
P_Load + C_Load V V ƒ n [W]
DD
DD
n + Number of switching output pins
VDD = 3.3 V ±0.3 V
PARAMETER
TEST CONDITIONS
MIN
VDD - 0.2
2.1
TYP(1) MAX UNIT
VDD = min to max,
IOH = –100 µA
IOH = –12 mA
IOH = –6 mA
IOL = 100 µA
IOL = 12 mA
IOL = 6 mA
VOH
VOL
IOH
IOL
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
V
VDD = 3 V
2.4
VDD = min to max,
VDD = 3 V
0.2
0.4
0.3
V
VDD = 3 V,
VO = 1 V
-37
37
VDD = 3.3 V,
VDD = 3.6 V,
VDD = 3 V,
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
-57
57
mA
mA
-38
38
VDD = 3.3 V,
VDD = 3.6 V,
(1) All typical values are with respect to nominal VDD
.
VDD = 2.5 V ±0.2 V
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VDD = min to max,
VDD = 2.3 V
IOH = –100 µA
IOH = –6 mA
IOL = 100 µA
IOL = 6 mA
VO = 1 V
VDD - 0.2
1.8
VOH
High-level output voltage
Low-level output voltage
V
VDD = min to max,
VDD = 2.3 V
0.2
V
VOL
0.4
VDD = 2.3 V,
VDD = 2.5 V,
VDD = 2.7 V,
VDD = 2.3 V,
VDD = 2.5 V,
VDD = 2.7 V,
-20
20
IOH
High-level output current
Low-level output current
VO = 1.25 V
VO = 2.375 V
VO = 1.2 V
VO = 1.25 V
VO = 0.3 V
-36
mA
-25
IOL
36
mA
25
(1) All typical values are with respect to nominal VDD
.
6
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
VDD = 3.3 V ±0.3 V (see Figure 2)
tPLH
1
1
2.8
ns
CLK to Yn
tPHL
f = 0 MHz to 200 MHz
2.8
tsk(o)
tsk(p)
tsk(pp)
tr
Output skew (Ym to Yn) (2) (see Figure 4)
100
150
250
350
2.7
ps
ps
Pulse skew (see Figure 5)
Part-to-part skew
ps
Rise time
VO = 0.4 V to 2 V
VO = 2 V to 0.4 V
1.3
1.3
0.1
0.1
0.4
0.4
V/ns
V/ns
ns
tf
Fall time
2.7
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time, G_high before CLK ↓
Disable setup time, G_low before CLK ↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
ns
ns
ns
VDD = 2.5 V ±0.2 V (see Figure 2)
tPLH
1.3
1.3
4
4
CLK to Yn
tPHL
f = 0 MHz to 200 MHz
ns
tsk(o)
tsk(p)
tsk(pp)
tr
Output skew (Ym to Yn) (2) (see Figure 4 )
150
230
280
400
1.6
1.6
ps
ps
Pulse skew (see Figure 5)
Part-to-part skew
ps
Rise time
VO = 0.4 V to 1.7 V
VO = 1.7 V to 0.4 V
0.5
0.5
0.1
0.1
0.4
0.4
V/ns
V/ns
ns
tf
Fall time
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time, G_high before CLK ↓
Disable setup time, G_low before CLK ↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
ns
ns
ns
(1) All typical values are with respect to nominal VDD
.
(2) The tsk(o) specification is only valid for equal loading of all outputs.
7
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C
L
= 25 pF on Y
500 Ω
n
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: Clock Frequency ≤ 200 MHz, ZO = 50
Ω,
tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
V
DD
CLK
50% V
0 V
DD
t
t
PHL
PLH
V
OH
1.7 V or 2 V
Y
n
50% V
DD
0.4 V
0.4 V
V
OL
t
r
t
f
Figure 3. Voltage Waveforms Propagation Delay Times
V
DD
CLK
0 V
V
OH
50% V
Any Y
DD
V
V
OL
OH
50% V
DD
Any Y
V
OL
t
t
sk(o)
sk(o)
Figure 4. Output Skew
V
DD
50% V
DD
CLK
0 V
t
t
PHL
PLH
V
OH
V
OL
Y
n
50% V
DD
NOTE: t
= | t
− t
PHL
|
sk(p)
PLH
Figure 5. Pulse Skew
8
CDCVF310
www.ti.com
SCAS771A–AUGUST 2004–REVISED AUGUST 2004
DYNAMIC SUPPLY CURRENT
vs
CLOCK FREQUENCY
50
45
40
35
30
25
20
15
10
5
V
= 2.3 V to 3.6 V
DD
C (Y ) = No Load
C
C
C = 3 x 2.5 pF
I
All Outputs Switching
L
n
= 32 pF
= 10 x 2.6 pF
V
DD
= 3.3 V, No C_Load, T = 255C
PD
A
O
T
A
= -405C to 855C
V
DD
= 3.6 V, No C_Load, T = -405C
A
V
= 2.7 V, No C_Load, T = -405C
DD
A
V
DD
= 2.5 V, No C_Load, T = 255C
A
0
0
20
40
60
80
100
120
140
160
180
200
f
- Clock Frequency - MHz
CLK
Figure 6.
C_LOAD(max) PER OUTPUT PIN Yn
vs
CLOCK FREQUENCY
40
35
30
25
20
15
10
5
V
= 2.7 V, T = -405C
DD
A
for High-K Material
V
= 3.6 V, T = -405C
DD
A
for High-K Material
V
= 2.3 V to 3.6 V
DD
C (Y ) max = According to Graph
L
n
C
C
= 32 pF
= 10 x 2.6 pF
PD
O
C = 3 x 2.5 pF
I
All Outputs Switching
T
A
= -405C to 855C
0
0
20
40
60
80
100
120
140
160
180
200
f
- Clock Frequency - MHz
CLK
Figure 7.
9
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
CDCVF310PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
24
24
24
60
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
CDCVF310PWR
CDCVF310PWRG4
TSSOP
TSSOP
PW
PW
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
CDCVF857IDGG
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, MO-153, TSSOP-48
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