CSD87333Q3DT [TI]
CSD87333Q3D Synchronous Buck NexFET⢠Power Block;
| 型号： | CSD87333Q3DT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CSD87333Q3D Synchronous Buck NexFET⢠Power Block 开关 光电二极管 |
| 文件： | 总24页 (文件大小：1016K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD87333Q3D
SLPS350 –FEBRUARY 2014
CSD87333Q3D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
The CSD87333Q3D NexFET™ power block is an
optimized design for synchronous buck and boost
applications offering high current, high efficiency, and
high frequency capability in a small 3.3-mm × 3.3-mm
outline. Optimized for 5 V gate drive applications, this
product offers a flexible solution in high duty cycle
applications when paired with an external controller or
driver.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Half-Bridge Power Block
Optimized for High Duty Cycle
Up to 24 Vin
94.7% System Efficiency at 8 A
1.5 W PLoss at 8 A
Up to 15 A operation
High Frequency Operation (Up to 1.5 MHz)
High Density – SON 3.3-mm × 3.3-mm Footprint
Optimized for 5 V Gate Drive
Low Switching Losses
TEXT ADDED FOR SPACING
Top View
VIN
VIN
TG
VSW
VSW
VSW
1
2
3
4
8
7
6
5
Ultra-Low Inductance Package
RoHS Compliant
PGND
(Pin 9)
Halogen Free
TGR
BG
Pb-Free Terminal Plating
P0116-01
2 Applications
TEXT ADDED FOR SPACING
Ordering Information
•
Synchronous Buck Converters
Device
Qty
2500 13-Inch Reel
250 7-Inch Reel
Media
Package
Ship
–
–
High Frequency Applications
High Duty Cycle Applications
CSD87333Q3D
SON 3.3-
mm × 3.3-mm
Plastic Package
Tape and
Reel
CSD87333Q3DT
•
•
Synchronous Boost Converters
POL DC-DC Converters
SPACER
SPACER
Typical Circuit
Typical Power Block Efficiency and Power Loss
100
90
80
70
60
50
5
VIN
BOOT
VDD
VDD
GND
VIN
4
3
TG
DRVH
LL
VSW
TGR
VOUT
ENABLE
PWM
ENABLE
PWM
VGS = 5V
2
BG
DRVL
VIN = 12V
VOUT = 3.3V
LOUT = 1.0µH
fSW = 500kHz
TA = 25ºC
PGND
CSD87333Q3D
Driver IC
1
0
0
3
6
9
12
15
Output Current (A)
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87333Q3D
SLPS350 –FEBRUARY 2014
www.ti.com
Table of Contents
6.2 Safe Operating Curves (SOA) ............................... 10
6.3 Normalized Curves ................................................ 10
6.4 Calculating Power Loss and SOA .......................... 11
Recommended PCB Design Overview ............. 12
7.1 Electrical Performance ........................................... 12
7.1 Thermal Performance ............................................ 13
Device and Documentation Support ................. 14
8.1 Trademarks ............................................................ 14
8.2 Electrostatic Discharge Caution ............................. 14
8.3 Glossary ................................................................. 14
1
2
3
4
5
Features ................................................................. 1
Applications .......................................................... 1
Description ............................................................ 1
Revision History ................................................... 2
Specifications ........................................................ 3
5.1 Absolute Maximum Ratings ..................................... 3
5.2 Handling Ratings ...................................................... 3
5.3 Recommended Operating Conditions ...................... 3
5.4 Power Block Performance ....................................... 3
5.5 Thermal Information ................................................. 4
5.6 Electrical Characteristics .......................................... 4
5.7 Typical Power Block Device Characteristics ............ 6
5.8 Typical Power Block MOSFET Characteristics ........ 8
Applications ........................................................ 10
6.1 Power Loss Curves ................................................ 10
7
8
9
Mechanical, Packaging, and Orderable
Information .......................................................... 15
9.1 Q3D Package Dimensions ..................................... 16
9.2 Land Pattern Recommendation ............................. 18
9.3 Stencil Recommendation ....................................... 18
9.4 Q3D Tape and Reel Information ............................ 19
6
4 Revision History
DATE
REVISION
NOTES
February 2014
*
Initial release.
2
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5 Specifications
5.1 Absolute Maximum Ratings(1)
TA = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
VIN to PGND
–0.8
30
30
32
10
10
40
6
VSW to PGND
V
Voltage Range
VSW to PGND (10ns)
TG to TGR
V
–0.3
–0.3
V
BG to PGND
V
Pulsed Current Rating, IDM
Power Dissipation, PD
A
W
Sync FET, ID = 19, L = 0.1mH
Control FET, ID = 19, L = 0.1mH
18
18
150
Avalanche Energy EAS
mJ
°C
Operating Junction Temperature Range, TJ
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
5.2 Handling Ratings
PARAMETER
DEFINITION
MIN
MAX
UNIT
Tstg
Storage Temperature Range
–55
150
°C
5.3 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX
8
UNIT
VGS
VIN
fSW
Gate Drive Voltage
Input Supply Voltage
Switching Frequency
Operating Current
3.3
V
V
24
CBST = 0.1 µF (min)
1500
15
kHz
A
TJ
Operating Temperature
125
°C
5.4 Power Block Performance(1)
TA = 25° (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
1.5
10
MAX UNIT
VIN = 12 V, VGS = 5 V, VOUT = 3.3 V,
IOUT = 8 A, fSW = 500 kHz,
LOUT = 1 µH, TJ = 25ºC
PLOSS
IQVIN
Power Loss(1)
W
VIN Quiescent Current
TG to TGR = 0 V BG to PGND = 0 V
µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5V driver IC.
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5.5 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX UNIT
Junction to ambient thermal resistance (Min Cu)(1)
Junction to ambient thermal resistance (Max Cu)(1)(2)
Junction to case thermal resistance (Top of package)(1)
Junction to case thermal resistance (PGND Pin)(1)
150
RθJA
80
°C/W
36
RθJC
(1)
3.7
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu.
5.6 Electrical Characteristics
TA = 25°C (unless otherwise stated)
Q1 Control FET
Q2 Sync FET
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Static Characteristics
BVDSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, IDS = 250 µA
VGS = 0 V, VDS = 20 V
30
30
V
Drain-to-Source Leakage
Current
1
100
1
100
µA
Gate-to-Source Leakage
Current
VDS = 0 V, VGS = +10 / –8
V
IGSS
nA
V
Gate-to-Source Threshold
Voltage
VGS(th)
VDS = VGS, IDS = 250 µA
0.75
0.95
1.20
0.75
0.95
1.20
VGS = 3.5 V, IDS = 4 A
VGS = 4.5 V, IDS = 4 A
VGS = 8 V, IDS = 4 A
VDS = 15 V, IDS = 4 A
14.7
13.4
11.9
43
17.7
16.1
14.3
14.7
13.4
11.9
43
17.7
16.1
14.3
Drain-to-Source On
Resistance
RDS(on)
mΩ
gfs
Transconductance
S
Dynamic Characteristics
CISS
Input Capacitance
Output Capacitance
509
222
662
289
509
222
662
289
pF
pF
COSS
VGS = 0V, VDS = 15V,
f = 1MHz
Reverse Transfer
Capacitance
CRSS
8.2
10.7
8.2
10.7
pF
RG
Qg
Series Gate Resistance
3.4
3.5
0.3
6.8
4.6
3.4
3.5
0.3
6.8
4.6
Ω
Gate Charge Total (4.5 V)
Gate Charge – Gate to Drain
nC
nC
Qgd
VDS = 15 V,
IDS = 4 A
Gate Charge – Gate to
Source
Qgs
1.6
1.6
nC
Qg(th)
QOSS
td(on)
tr
Gate Charge at Vth
Output Charge
Turn On Delay Time
Rise Time
0.6
5.3
2.1
3.9
9.4
2.2
0.6
5.3
2.1
3.9
9.4
2.2
nC
nC
ns
ns
ns
ns
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 4 A, RG = 2 Ω
td(off)
tf
Turn Off Delay Time
Fall Time
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
IDS = 4 A, VGS = 0 V
0.80
10
1.0
0.80
10
1.0
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDS = 15 V, IF = 4 A,
di/dt = 300 A/µs
11
11
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HD
LD
HD
LD
Max RθJA = 80°C/W
when mounted on
1 inch2 (6.45 cm2) of 2-
oz. (0.071-mm thick)
Cu.
Max RθJA = 150°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
LG HS
LG HS
LS
LS
HG
HG
M0205-01
M0206-01
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5.7 Typical Power Block Device Characteristics
The Typical Power Block System Characteristic curves (Figure 1 through Figure 9) are based on measurements made on a
PCB design with dimensions of 4.0-inch (W) × 3.5-inch (L) × 0.062-inch (H) and 6 copper layers of 1 oz. copper thickness.
See Applications for detailed explanation. TA = 125°C, unless stated otherwise.
6
5
4
3
2
1
0
1.1
1
VIN = 12V
VGS = 5V
VOUT = 3.3V
fSW = 500kHz
LOUT = 1.0µH
VIN = 12V
VGS = 5V
VOUT = 3.3V
fSW = 500kHz
LOUT = 1.0µH
0.9
0.8
0.7
0.6
0.5
0
3
6
9
12
15
−50
−25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (ºC)
G001
G001
Figure 1. Power Loss vs Output Current
Figure 2. Power Loss vs Temperature
18
15
12
9
18
15
12
9
6
6
VIN = 12V
400LFM
200LFM
100LFM
Nat Conv
400LFM
200LFM
100LFM
Nat Conv
VGS = 5V
VOUT = 3.3V
fSW = 500kHz
LOUT =1.0µH
3
3
0
0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
Ambient Temperature (ºC)
Ambient Temperature (ºC)
G001
G001
Figure 3. Safe Operating Area – PCB Horizontal Mount
Figure 4. Safe Operating Area – PCB Vertical Mount
20
18
16
14
12
10
8
6
4
2
0
0
20
40
60
80
100
120
140
Board Temperature (ºC)
G001
Figure 5. Typical Safe Operating Area
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Typical Power Block Device Characteristics (continued)
The Typical Power Block System Characteristic curves (Figure 1 through Figure 9) are based on measurements made on a
PCB design with dimensions of 4.0-inch (W) × 3.5-inch (L) × 0.062-inch (H) and 6 copper layers of 1 oz. copper thickness.
See Applications for detailed explanation. TA = 125°C, unless stated otherwise.
1.15
1.12
1.09
1.06
1.03
1
3.0
2.4
1.8
1.2
0.6
0.0
−0.6
1.2
1.15
1.1
4.0
VIN = 12V
VGS = 5V
VOUT = 3.3V
LOUT = 1.0µH
IOUT = 15A
VGS = 5V
VOUT = 3.3V
LOUT =1.0µH
fSW = 500kHz
IOUT = 15A
3.0
2.0
1.05
1
1.0
0.0
0.95
0.9
−1.0
−2.0
−3.0
0.97
0.85
0
200
400
600
800 1000 1200 1400 1600
0
4
8
12
16
20
24
28
Switching Frequency (kHz)
Input Voltage (V)
G001
G001
Figure 6. Normalized Power Loss vs Switching Frequency
Figure 7. Normalized Power Loss vs Input Voltage
1.08
1.44
1.08
0.72
0.36
0
1.2
1.16
1.12
1.08
1.04
1
3.99
VIN = 12V
VGS = 5V
VOUT = 3.3V
fSW = 500kHz
IOUT = 15A
1.06
1.04
1.02
1
3.19
2.39
1.6
0.8
VIN = 12V
VGS = 5V
fSW = 500kHz
LOUT = 1.0µH
IOUT = 15A
0.98
0.96
0.94
−0.36
−0.72
−1.08
0
0.96
0.92
−0.8
−1.6
0
1
2
3
4
5
6
7
8
0
400
800
1200
1600
2000
2400
Output Voltage (V)
Output Inductance (nH)
G001
G001
Figure 8. Normalized Power Loss vs Output Voltage
Figure 9. Normalized Power Loss vs Output Inductance
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5.8 Typical Power Block MOSFET Characteristics
TA = 25°C, unless stated otherwise.
50
45
40
35
30
25
20
15
50
10
VDS = 5V
1
0.1
0.01
0.001
VGS = 8.0V
VGS =6V
VGS = 4.5V
TC = 125°C
TC = 25°C
TC = −55°C
10
5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VDS - Drain-to-Source Voltage (V)
1
0
0
0
0.5
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 10. MOSFET Saturation Characteristics
Figure 11. MOSFET Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
1000
100
10
ID = 4A
VDS = 15V
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
1
2
3
4
5
6
7
8
3
6
9
12
15
18
21
24
27
30
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 12. MOSFET Gate Charge
Figure 13. MOSFET Capacitance
1.25
1.15
1.05
0.95
0.85
0.75
0.65
0.55
0.45
36
32
28
24
20
16
12
8
ID = 250µA
TC = 25°C
TC = 125ºC
4
ID = 4A
1
0
−75
−25
25
75
125
175
2
3
4
5
6
7
8
9
10
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 14. MOSFET VGS(th)
Figure 15. MOSFET RDS(on) vs VGS
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
1.6
1.4
1.2
1
100
10
ID = 4A
VGS = 8V
1
0.1
0.01
0.001
0.0001
0.8
0.6
VGS = 3.5V
VGS = 8V
TC = 25°C
TC = 125°C
−75
−25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature - ºC
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 16. MOSFET Normalized RDS(on)
Figure 17. MOSFET Body Diode
100
10
TC = 25°C
TC = 125°C
1
0.01
0.1
1
10
t
- Time in Avalanche (ms)
(AV)
G001
Figure 18. MOSFET Unclamped Inductive Switching
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6 Applications
The CSD87333Q3D NexFET power block is an optimized design for synchronous buck applications using 5 V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
6.1 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87333Q3D as a function of load current. This curve
is measured by configuring and running the CSD87333Q3D as it would be in the final application (see
Figure 19). The measured power loss is the CSD87333Q3D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.2 Safe Operating Curves (SOA)
The SOA curves in the CSD87333Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 inches
(W) × 3.5 inches (L) × 0.062 inches (T) and 6 copper layers of 1 oz. copper thickness.
6.3 Normalized Curves
The normalized curves in the CSD87333Q3D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries adjust for a given set of system conditions. The primary Y-axis is the normalized change in power
loss, and the secondary Y-axis is the change is system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Input Current (IIN)
VIN
A
BOOT
DRVH
LL
VDD
A
VDD
V
VIN
Input Voltage (VIN)
Gate Drive
Voltage (VDD)
V
TG
ENABLE
PWM
Output Current (IOUT
)
VSW
TGR
A
VOUT
PWM
BG
DRVL
PGND
GND
Averaged Switch
V Node Voltage
Averaging
Circuit
CSD87333Q3D
Driver IC
(VSW_AVG
)
Figure 19. Typical Application
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6.4 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure outlines the steps the user should take to predict product performance for any set of system
conditions.
6.4.1 Design Example
Operating Conditions:
•
•
•
•
•
Output Current = 10 A
Input Voltage = 20 V
Output Voltage = 1 V
Switching Frequency = 1000 kHz
Inductor = 0.6 µH
6.4.2 Calculating Power Loss
•
•
•
•
•
•
Power Loss at 10 A = 2.6 W (Figure 1)
Normalized Power Loss for input voltage ≈ 1.10 (Figure 7)
Normalized Power Loss for output voltage ≈ 0.96 (Figure 8)
Normalized Power Loss for switching frequency ≈ 1.04 (Figure 6)
Normalized Power Loss for output inductor ≈ 1.03 (Figure 9)
Final calculated Power Loss = 2.6 W x 1.10 × 0.96 × 1.04 × 1.03 ≈ 2.9 W
6.4.3 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 2.0ºC (Figure 7)
SOA adjustment for output voltage ≈ - 0.2ºC (Figure 8)
SOA adjustment for switching frequency ≈ 0.8ºC (Figure 6)
SOA adjustment for output inductor ≈ 0.8ºC (Figure 9)
Final calculated SOA adjustment = 2.0 + (-0.2) + 0.8 + 0.8 ≈ 3.4ºC
In the Design Example, the estimated power loss of the CSD87333Q3D would increase to 2.9 W. In addition, the
maximum allowable board or ambient temperature, or both, would have to decrease by 3.4ºC. Figure 20
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board or ambient temperature.
3. Adjust the SOA board or ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 3.4ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board or ambient temperature.
SPACE
Figure 20. Power Block SOA
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7 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and
Thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief
description on how to address each parameter is provided.
7.1 Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
•
The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 21).
The example in Figure 21 uses 6 × 10-µF ceramic capacitors (TDK part number C3216X5R1C106KT or
equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of
vias interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and
C8 should follow in order.
•
•
The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to
the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, and so forth). The
bootstrap capacitor for the Driver IC will also connect to this pin.
The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level.(1) In the event the switch node waveform exhibits ringing that
reaches undesirable levels, the use of a Boost Resistor or RC snubber can be an effective way to easily
reduce the peak ring level. The recommended Boost Resistor value will range between 1.0 to 4.7 Ω
depending on the output characteristics of Driver IC used in conjunction with the Power Block. The RC
snubber values can range from 0.5 to 2.2 Ω for the R and 330 to 2200 pF for the C. Please refer to TI
Application Note SLUP100 for more details on how to properly tune the RC snubber values. The RC snubber
(1)
should be placed as close as possible to the Vsw node and PGND (see Figure 21).
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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7.1 Thermal Performance
The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in Figure 21 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
•
Tent the opposite side of the via with solder-mask.
The number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 21. Recommended PCB Layout (Top Down)
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8 Device and Documentation Support
8.1 Trademarks
NexFET is a trademark of Texas Instruments.
8.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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CSD87333Q3D
SLPS350 –FEBRUARY 2014
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9.1 Q3D Package Dimensions
MILLIMETERS
INCHES
DIM
MIN
MAX
1.05
MIN
.033
MAX
.041
A
b
0.850
0.280
0.400
0.011
0.016
b1
c
0.310 Nom.
0.012 Nom.
0.150
0.150
0.940
0.160
0.150
0.250
0.175
3.200
2.650
3.200
3.200
1.750
0.250
0.250
1.040
0.260
0.250
0.350
0.275
3.400
2.750
3.400
3.400
1.850
0.006
0.006
0.037
0.006
0.006
0.010
0.007
0.126
0.104
0.126
0.126
0.069
0.010
0.010
0.041
0.010
0.010
0.014
0.011
0.134
0.108
0.134
0.134
0.073
c1
d
d1
d2
d3
d4
D1
D2
E
E1
E2
e
0.650 TYP
0.300 TYP
0.026 TYP
0.012 TYP
L
0.400
0.00
0.500
–
0.016
–
0.020
–
θ
K
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Pinout Configuration
Position
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Designation
VIN
VIN
TG
TGR
BG
VSW
VSW
VSW
PGND
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9.2 Land Pattern Recommendation
1.900 (0.075)
0.200
(0.008)
0.210
(0.008)
0.350 (0.014)
0.440
(0.017)
0.650
(0.026)
2.800
(0.110)
2.390
(0.094)
1.090
(0.043)
0.210
(0.008)
0.300 (0.012)
0.650 (0.026)
0.650 (0.026)
3.600 (0.142)
M0193-01
NOTE: Dimensions are in mm (inches).
9.3 Stencil Recommendation
0.160 (0.005)
0.550 (0.022)
0.200 (0.008)
0.300 (0.012)
0.300
(0.012)
0.340
(0.013)
2.290
(0.090)
0.333
(0.013)
0.990
(0.039)
0.100
(0.004)
0.350 (0.014)
0.300 (0.012)
0.850 (0.033)
3.500 (0.138)
M0207-01
NOTE: Dimensions are in mm (inches).
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
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SLPS350 –FEBRUARY 2014
9.4 Q3D Tape and Reel Information
4.00 0.ꢀ0 ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
Ø ꢀ.ꢃ0
+0.ꢀ0
–0.00
3.60
M0ꢀ44-0ꢀ
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ± 0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ± 0.05 mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2014
PACKAGING INFORMATION
Orderable Device
CSD87333Q3D
CSD87333Q3DT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 150
0 to 0
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSON
VSON
DPB
8
8
2500 Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-1-260C-UNLIM
87333D
87333D
ACTIVE
DPB
250
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD87333Q3D
CSD87333Q3DT
VSON
VSON
DPB
DPB
8
8
2500
250
330.0
180.0
12.4
12.4
3.6
3.6
3.6
3.6
1.2
1.2
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD87333Q3D
CSD87333Q3DT
VSON
VSON
DPB
DPB
8
8
2500
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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