CSD95372BQ5MCT [TI]
CSD95372BQ5MC Synchronous Buck NexFET Smart Power Stage;
| 型号： | CSD95372BQ5MCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CSD95372BQ5MC Synchronous Buck NexFET Smart Power Stage 开关 光电二极管 |
| 文件： | 总13页 (文件大小：799K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD95372BQ5MC
SLPS417A –APRIL 2014–REVISED JULY 2015
CSD95372BQ5MC Synchronous Buck NexFET™ Smart Power Stage
1 Features
2 Applications
1
•
60-A Continuous Operating Current Capability
93.4% System Efficiency at 30 A
•
Multiphase Synchronous Buck Converters
•
•
•
•
•
–
–
High-Frequency Applications
Low Power Loss of 2.8 W at 30 A
High-Current, Low Duty-Cycle Applications
High-Frequency Operation (up to 1.25 MHz)
Diode Emulation Mode With FCCM
•
•
•
POL DC-DC Converters
Memory and Graphic Cards
Temperature-Compensated Bidirectional Current
Sense
Desktop and Server VR11.x / VR12.x V-Core and
Memory Synchronous Converters
•
•
Analog Temperature Output (600 mV at 0°C)
Fault Monitoring
3 Description
The CSD95372BQ5MC NexFET™ smart power
stage is a highly optimized design for use in a high-
power, high-density synchronous buck converter.
This product integrates the driver IC and Power
MOSFETs to complete the power stage switching
function. This combination produces high-current,
high-efficiency, and high-speed switching capability in
a small 5 mm × 6 mm outline package. It also
integrates the accurate current sensing and
temperature sensing functionality to simplify system
design and improve accuracy. In addition, the PCB
footprint is optimized to help reduce design time and
simplify the completion of the overall system design.
–
High-Side Short, Overcurrent, and
Overtemperature Protection
•
•
•
•
•
•
•
•
•
•
3.3-V and 5-V PWM Signal Compatible
Tri-State PWM Input
Integrated Bootstrap Diode
Optimized Deadtime for Shoot-Through Protection
High-Density SON 5 × 6 mm Footprint
Ultra-Low Inductance Package
System-Optimized PCB Footprint
DualCool™ Packaging
RoHS Compliant – Lead-Free Terminal Plating
Halogen-Free
Device Information(1)
DEVICE
CSD95372BQ5MC 13-Inch Reel 2500
CSD95372BQ5MCT 7-Inch Reel 250
MEDIA
QTY
PACKAGE
SHIP
Tape
and
Reel
SON 5 × 6 mm
DualCool Package
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Diagram
Typical Power Stage Efficiency and Power Loss
100
90
80
70
60
50
40
30
14
12
10
8
VIN
CSD95372B
VOUT
VCC
VDD = 5V
VIN = 12V
VOUT = 1.2V
LOUT = .225µH
fSW = 500kHz
TA = 25ºC
6
VCC
4
PWM1
+Is1
2
-Is2
VOUT
VOUT
SS
0
0
10
20
30
40
50
60
TSEN
Output Current (A)
G001
+Is2
-Is2
RT
PWM2
PGND
Multiphase
Controller
CSD95372B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD95372BQ5MC
SLPS417A –APRIL 2014–REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
7
8
Application Schematic .......................................... 5
Device and Documentation Support.................... 6
8.1 Community Resources.............................................. 6
8.2 Trademarks............................................................... 6
8.3 Electrostatic Discharge Caution................................ 6
8.4 Glossary.................................................................... 6
9
Mechanical, Packaging, and Orderable
Information ............................................................. 7
9.1 Mechanical Drawing.................................................. 7
9.2 Recommended PCB Land Pattern............................ 8
9.3 Recommended Stencil Opening ............................... 8
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2014) to Revision A
Page
•
•
Updated Application Schematic to show IOUT (not IMON) for each CSD95372B ..................................................................... 5
Corrected MAX A dimensions in Mechanical Drawing table to 1.050 mm (0.041 inch)......................................................... 7
2
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SLPS417A –APRIL 2014–REVISED JULY 2015
5 Pin Configuration and Functions
Top View
IOUT
REFIN
ENABLE
PGND
1
2
3
4
5
12 PWM
11 TAO/FAULT
10 FCCM
9
8
BOOT
13
VDD
BOOT_R
PGND
VSW
6
7
VIN
Pin Functions
PIN
NUMBER
DESCRIPTION
NAME
BOOT
Bootstrap capacitor connection. Connect a minimum of 0.1 µF 16 V X7R ceramic capacitor from BOOT to BOOT_R
pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.
9
8
BOOT_R
Return path for HS gate driver, connected to VSW internally.
Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is turned
off and both MOSFET gates are actively pulled low. An internal 100 kΩ pulldown resistor will pull the ENABLE pin
LOW if left floating.
ENABLE
FCCM
3
This pin enables the Diode Emulation function. When this pin is held LOW, Diode Emulation Mode is enabled for
sync FET. When FCCM is HIGH, the device is operated in Forced Continuous Conduction Mode. An internal 5 µA
current source will pull the FCCM pin to 3.3 V if left floating.
10
IOUT
PGND
PGND
1
4
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
Power ground, connected directly to pin 13.
13
Power ground
Pulse width modulated 3-state input from external controller. Logic LOW sets control FET gate low and sync FET
gate high. Logic HIGH sets control FET gate high and sync FET gate low. Open or High Z sets both MOSFET
gates low if greater than the tri-state shutdown hold-off time (t3HT).
PWM
12
2
REFIN
External reference voltage input for current sensing amplifier
Temperature Analog Output. Reports a voltage proportional to the die temperature. An ORing diode is integrated in
the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only
the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown occurs. TAO should be
bypassed to PGND with a 1 nF 16 V X7R ceramic capacitor.
TAO/
FAULT
11
VDD
VIN
5
7
6
Supply voltage to gate driver and internal circuitry
Input voltage pin. Connect input capacitors close to this pin.
VSW
Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.
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6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–7
MAX
UNIT
V
VIN to PGND
25
VIN to VSW
25
V
VIN to VSW (10 ns)
VSW to PGND
27
V
–0.3
–7
20
V
VSW to PGND (10 ns)
VDD to PGND
23
V
–0.3
–0.3
–0.3
7
VDD + 0.3 V
VDD + 0.3 V
12
V
ENABLE, PWM, FCCM. TAO, IOUT, REFIN to PGND
V
BOOT to BOOT_R(2)
Power dissipation
Operating junction
Storage temperature
V
PD
TJ
W
°C
°C
–55
–55
150
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Should not exceed 7 V
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM)
V(ESD) Electrostatic discharge
V
Charged device model (CDM)
6.3 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
MIN
MAX
UNIT
VDD
VIN
Gate drive voltage
Input supply voltage(1)
4.5
5.5
16
V
V
VOUT
Output voltage
5.5
V
IOUT
Continuous output current
VIN = 12 V, VDD = 5V, VOUT = 3.3 V,
ƒSW = 500 kHz, LOUT = 0.47 µH(2)
60
A
IOUT-PK Peak output current(3)
90
A
ƒSW
Switching frequency
On time duty cycle
CBST = 0.1 µF (min)
ƒSW = 1 MHz
1250
85%
kHz
Minimum PWM on time
Operating temperature
40
ns
°C
–40
125
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
(2) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(3) System conditions as defined in Note 1. Peak Output Current is applied for tp = 50 µs
6.4 Thermal Information
TA = 25°C (unless otherwise noted)
THERMAL METRIC
MIN
TYP
MAX UNIT
°C/W
1.5 °C/W
θJC(top) is determined with the device mounted on a 1 inch² (6.45 cm²), 2-oz (0.071 mm thick) Cu pad on a 1.5 inches x 1.5 inches,
0.06-inch (1.52 mm) thick FR4 board.
(1)
RθJC(top) Junction-to-case (top of package) thermal resistance
5
RθJB
Junction-to-board thermal resistance(2)
(1)
(2)
R
R
θJB value based on hottest board temperature within 1 mm of the package.
4
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SLPS417A –APRIL 2014–REVISED JULY 2015
7 Application Schematic
12V
BOOT
BOOT_R
VIN
TPS53661
TAO/FAULT
PWM1
PWM
VCORE_OUT
VSP
VSW
SKIP#-RAMP
FCCM
VDD
CSD95372B
PGND
5V
VSN
Load
ENABLE
PGND IOUT REFIN
OCP-I
COMP
CSP1
TSEN
12V
VREF
BOOT
BOOT_R
VIN
F-IMAX
TAO/FAULT
PWM
PWM2
VSW
FCCM
VDD
CSD95372B
PGND
5V
B-TMAX
ENABLE
PGND IOUT REFIN
CSP2
O-USR
12V
BOOT
BOOT_R
VIN
TAO/FAULT
ADDR
PWM
PWM3
VSW
FCCM
VDD
CSD95372B
PGND
5V
ENABLE
PGND IOUT REFIN
SLEW-MODE
CSP3
12V
ISUM
IMON
IMON
BOOT
BOOT_R
VIN
TAO/FAULT
PWM
PWM4
VSW
FCCM
VDD
CSD95372B
PGND
5V
ENABLE
PGND IOUT REFIN
SCLK
ALERT#
SDIO
To/From
CPU
CSP4
VR_RDY
12V
VR_HOT#
PMB_CLK
PMB_ALERT#
PMB_DIO
ENABLE
BOOT
BOOT_R
VIN
I2C or
PMBus
(Optional)
TAO/FAULT
PWM
PWM5
VSW
FCCM
VDD
CSD95372B
PGND
5V
ENABLE
ENABLE
PGND IOUT REFIN
VR_FAULT#
VR_FAULT#
CSP5
12V
12V
5V
V12
V5
BOOT
BOOT_R
VIN
TAO/FAULT
PWM
PWM6
VSW
FCCM
VDD
CSD95372B
PGND
5V
ENABLE
3.3V
IOUT REFIN
V3R3
PGND
CSP6
GND
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8 Device and Documentation Support
8.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.2 Trademarks
DualCool, NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
6
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SLPS417A –APRIL 2014–REVISED JULY 2015
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Mechanical Drawing
Exposed tie clip may vary
A
c2
E2
d2
E1
c1
L1
d1
K
b3
b2
b1
E
D2
b
e
a1
L
0.300 x 45°
d
MILLIMETERS
NOM
INCHES
DIM
MIN
0.950
0.000
0.200
MAX
MIN
NOM
MAX
A
a1
b
1.000
1.050
0.050
0.320
0.037
0.000
0.008
0.039
0.000
0.041
0.002
0.013
0.000
0.250
0.010
b1
b2
b3
c1
c2
D2
d
2.750 TYP
0.250
0.108 TYP
0.010
0.200
0.320
0.008
0.013
0.250 TYP
0.200
0.010 TYP
0.008
0.150
0.200
5.300
0.200
0.350
1.900
5.900
4.900
3.200
0.250
0.300
5.500
0.300
0.450
2.100
6.100
5.100
3.400
0.006
0.008
0.209
0.008
0.014
0.075
0.232
0.193
0.126
0.010
0.012
0.217
0.012
0.018
0.083
0.240
0.201
0.134
0.250
0.010
5.400
0.213
0.250
0.010
d1
d2
E
0.400
0.016
2.000
0.079
6.000
0.236
E1
E2
e
5.000
0.197
3.300
0.130
0.500 TYP
0.350 TYP
0.500
0.020 TYP
0.014 TYP
0.020
K
L
0.400
0.210
0.00
0.600
0.410
—
0.016
0.008
0.00
0.024
0.016
—
L1
θ
0.310
0.012
—
—
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9.2 Recommended PCB Land Pattern
0.331(0.013)
0.370 (0.015)
1.000 (0.039)
0.410 (0.016)
0.550 (0.022)
0.300 (0.012)
2.800
(0.110)
6.300
(0.248)
5.300
(0.209)
5.639
(0.222)
0.500
(0.020)
0.300
(0.012)
R0.127 (R0.005)
3.400
(0.134)
5.900
(0.232)
1. Dimensions are in mm (inches).
9.3 Recommended Stencil Opening
0.350(0.014)
2.750
(0.108)
0.250
(0.010)
1. Dimensions are in mm (inches).
2. Stencil thickness is 100 µm.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Aug-2015
PACKAGING INFORMATION
Orderable Device
CSD95372BQ5MC
CSD95372BQ5MCT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 0
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSON-CLIP
VSON-CLIP
DMC
12
12
2500 Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
95372BMC
95372BMC
ACTIVE
DMC
250
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
0 to 0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Aug-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD95372BQ5MC
VSON-
CLIP
DMC
12
2500
330.0
15.4
5.3
6.3
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Oct-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON-CLIP DMC 12
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 41.3
CSD95372BQ5MC
2500
Pack Materials-Page 2
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