CSD97370AQ5M_技术文档

CSD97370AQ5M

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SLPS352 –SEPTEMBER 2011

Synchronous Buck NexFET™ Power Stage

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1

FEATURES

APPLICATIONS

•

90% System Efficiency at 25A

•

Synchronous Buck Converters

Multiphase Synchronous Buck Converters

Input Voltages up to 22V

High Frequency Operation (Up To 2MHz)

Incorporates Power Block Technology

High Density – SON 5-mm × 6-mm Footprint

Low Power Loss 2.8W at 25A

Ultra Low Inductance Package

System Optimized PCB Footprint

Universal 5V PWM Signal Compatibility

3-State PWM Input

POL DC-DC Converters

Memory and Graphic Cards

Desktop and Server VR11.x and VR12.x V-Core

Synchronous Buck Converters

ORDERING INFORMATION

Device

Package

Media

Qty

Ship

SON 5-mm × 6-mm

Plastic Package

13-Inch

Reel

Tape and

Reel

CSD97370AQ5M

2500

Integrated Bootstrap Diode

spacer

Pre-Bias Start-Up Protection

Shoot Through Protection

RoHS Compliant – Lead Free Terminal Plating

Halogen Free

DESCRIPTION

The CSD97370AQ5M NexFET Power Stage is an optimized design for use in a high power, high density

Synchronous Buck converter. This product integrates an enhanced gate driver IC and Power Block Technology

to complete the power stage switching function. This combination produces a high current, high efficiency, high

speed switching device and delivers an excellent thermal solution in a small 5-mm × 6-mm outline package due

to its large ground based thermal pad. In addition, the PCB footprint has been optimized to help reduce design

time and simplify the completion of the overall system design.

spacer

100

90

80

70

60

50

40

6

5

4

3

2

1

0

V_GS= 5V

V_IN= 12V

V_OUT= 1.2V

L_OUT= 0.3µH

f_SW= 500kHz

T_A= 25ºC

0

5

10

15

20

25

Output Current (A)

Figure 1. Application Diagram

Figure 2. Efficiency and Power Loss

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CSD97370AQ5M

SLPS352 –SEPTEMBER 2011

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

T_A= 25°C (unless otherwise noted)

VALUE

UNIT

MIN

MAX

(2)

V_INto P_GND

30

V

V_SWto P_GND, V_INto V_SW

V_SWto P_GND(10ns)

V_DDto P_GND

-0.8

-7

30

32

6

V

–0.3

V

(3)

ENABLE to P_GND

V_DD+ 0.3

2

V

(3)

PWM to P_GND

BOOT to BOOT_R⁽³⁾

V

Human Body Model (HBM)

Charged Device Model (CDM)

kV

V

ESD Rating

500

Power Dissipation, P_D

12

W

°C

Operating Temperature Range, T_J

Storage Temperature Range, T_STG

-40

150

–55

150

(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating

Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

(2) V_INto V_SWMax = 32V for 10ns

(3) Should not exceed 6V

RECOMMENDED OPERATING CONDITIONS

T_A= 25° (unless otherwise noted)

Parameter

Gate Drive Voltage, V_DD

Conditions

MIN

4.5

MAX

5.5

UNIT

V

Input Supply Voltage, V_IN

Output Voltage, V_OUT

3.3

22

V

5.5

V

Continuous Output Current, I_OUT

V_IN= 12V, V_DD= 5V, V_OUT= 1.2V,

40

A

f_SW= 500kHz, L_OUT= 0.3µH⁽¹⁾

(2)

Peak Output Current, I_OUT-PK

60

A

Switching Frequency, f_SW

On Time Duty Cycle

C_BST= 0.1µF (min)

200

2000

85%

kHz

Minimum PWM On Time

Operating Temperature

40

ns

–40

125

°C

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins.

(2) System conditions as defined in Note 1. Peak Output Current is applied for t_p= 50µs.

THERMAL INFORMATION

T_A= 25°C (unless otherwise noted)

PARAMETER

Thermal Resistance, Junction-to-Case (Top of package)

Thermal Resistance, Junction-to-Board⁽¹⁾

MIN

TYP

MAX UNIT

R_θJC

R_θJB

20 °C/W

2

°C/W

(1)

R_θJBvalue based on hottest board temperature within 1mm of the package.

2

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ELECTRICAL CHARACTERISTICS

T_A= 25°C, V_DD= POR to 5.5V (unless otherwise noted)

PARAMETER

P_LOSS

CONDITIONS

MIN

TYP

MAX

UNIT

V_IN= 12V, V_DD= 5V, V_OUT= 1.2V, I_OUT= 25A,

f_SW= 500kHz, L_OUT= 0.3µH , T_J= 25°C

Power Loss⁽¹⁾

Power Loss⁽²⁾

–

2.8

8

3.3

10

W

V_IN= 12V, V_DD= 5V, V_OUT= 1.2V, I_OUT= 40A,

f_SW= 500kHz, L_OUT= 0.3µH , T_J= 125°C

V_IN

V_INQuiescent Current (I_Q)

V_DD

ENABLE = 0V, V_DD= 5V

ENABLE = 0V, PWM = 0V

–

100

µA

Standby Supply Current ( I_DD

)

–

1

5

µA

ENABLE = 5V, PWM = 50% Duty cycle,

f_SW= 500kHz

Operating Supply Current (I_DD

)

16

20

mA

POWER-ON RESET AND UNDER VOLTAGE LOCKOUT

Power on Reset (V_DDRising)

UVLO (V_DDFalling)

–

3.4

100

–

3.6

3.5

–

3.9

–

V

Hysteresis

250

1000

mV

ns

Startup Delay⁽³⁾

ENABLE = PWM = 5V

600

ENABLE

Logic Level Low Threshold (V_IL)

Logic Level High Threshold (V_IH

Threshold Hysteresis

Weak Pull-down Impedance

0.8

–

1

1.6

–

2.0

–

V

)

–

580

100

600

200

mV

kΩ

ns

Schmitt Trigger Input PWM = 5V (See Figure 5)

–

Rising Propagation Delay (t_PDH

)

–

Falling Propagation Delay (t_PDL

)

–

PWM

I_PWMH

PWM = 5V

PWM = 0V

–

450

–450

–

580

µA

V

I_PWML

–580

PWM Logic Level High (V_PWMH

)

–

4

–

PWM Logic Level Low (V_PWML

PWM 3-State open Voltage

)

0.8

–

V

2.4

V

PWM to VSW propagation delay

(t_PDLHand t_PDHL

V_DD= POR to 5.5V, C_PWM= 10pF (See Figure 6)

–

100

–

ns

)

3-State Shutdown Hold-off Time (t_3HT

)

–

100

650

75

–

ns

3-State Shutdown Propagation Delay (t_3SD

)

3-State Recovery Propagation Delay (t_3RD

)

BOOTSTRAP SWITCH

Forward Voltage (V_FBOOT

)

V

_DD– V_BOOT, I_F= 20mA

_BOOT– V_DD= 20V

–

180

360

1

mV

(2)

Reverse Leakage (I_RBOOT

)

V

0.15

µA

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins.

(2) Specified by design

(3) POR to V_SWrising

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PIN CONFIGURATION

SON 5mm ´ 6mm

22-Pin Package

(Top View)

1

2

22

ENABLE

NC

PWM

NC

21

20

19

V_DD

3

NC

4

NC

BOOT

5

18 BOOT_R

NC

PGND

23

V_SW

V_IN

6

17

V_SW

V_IN

7

16

V_IN

8

15

V_IN

9

14

V_IN

10

11

13

V_IN

12

P0125-01

PIN DESCRIPTION

DESCRIPTION

NO.

NAME

1

ENABLE

Enables device operation. If ENABLE=logic HIGH, turns on the device. If ENABLE=logic LOW, the device is turned off

and MOSFET gates are actively pulled low. An internal 100kΩ pull down resistor will pull the ENABLE pin LOW if left

floating.

2

3

NC

Not for electrical connection, connect to floating pad only.

Supply Voltage to Gate Drivers and internal circuitry.

V_DD

NC

4

Not for electrical connection, connect to floating pad only.

Voltage Switching Node – pin connection to the output inductor.

Input Voltage Pin. Connect input capacitors close to this pin.

5

NC

6

V_SW

V_IN

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

V_IN

BOOT_R

BOOT

NC

Bootstrap capacitor connection. Connect a minimum 0.1µF 16V X5R, ceramic cap from BOOT to BOOT_R pins. The

bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.

Not for electrical connection, connect to floating pad only.

NC

PWM

Pulse Width modulated 3-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate

high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if

greater than the 3-State Shutdown Hold-off Time (t_3HT

)

23

P_GND

Power Ground

4

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V_DD

Boot

V_IN

Control

FET

Boot_R

V_SW

PWM

EN

UVLO

and

Control Logic

Shoot

Through

Control

Sync

FET

P_GND

B0433-01

Figure 3. Functional Block Diagram

FUNCTIONAL DESCRIPTION

POWERING CSD97370AQ5M AND GATE DRIVERS

An external V_DDvoltage is required to supply the integrated gate driver IC and provide the necessary gate drive

power for the MOSFETS. The gate driver IC is capable of supplying in excess of 4 Amps peak current into the

MOSFET gates to achieve fast switching. A 1uF 10V X5R or higher ceramic capacitor is recommended to

bypass V_DDpin to PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included.

The bootstrap supply to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor

between BOOT and BOOT_R pins. An optional R_BOOTresistor which can be used to slow down the turn on

speed of the Control FET and reduce voltage spikes on the Vsw node. A typical 1Ω to 4.7Ω value is a

compromise between switching loss and V_SWspike amplitude.

UVLO (Under Voltage Lock Out)

The V_DDsupply is monitored for UVLO conditions and both Control FET and Sync FET gates are held low until

adequate supply is available. An internal comparator evaluates the V_DDvoltage level and if V_DDis greater than

the Power On Reset threshold (V_POR) the gate driver becomes active. If V_DDis less than the UVLO threshold, the

gate driver is disabled and the internal MOSFET gates are actively driven low. At the rising edge of the V_DD

voltage, both Control FET and Sync FET gates will be actively held low during V_DDtransitions between 1.0V to

V_POR. This region is referred to the Gate Drive Latch Zone (see Figure 4). In addition, at the falling edge of the

V_DDvoltage, both Control FET and Sync FET gates are actively held low during the UVLO to 1.0V transition.

The Power Stage CSD97370AQ5M device must be powered up and Enabled before the PWM signal is applied.

V_DD

V_POR

UVLO

Gate Drive

Latch Zone

1.0V

T0487-01

Figure 4. POR and UVLO

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ENABLE

The ENABLE pin is TTL compatible. The logic level thresholds are sustained under all V_DDoperating conditions

between V_PORto V_DD. In addition, if this pin is left floating, a weak internal pull down resistor of 100kΩ will pull the

ENABLE pin below the logic level low threshold. The operational functions of this pin should follow the timing

diagram outlined in Figure 5. A logic level low will actively hold both Control FET and Sync FET gates low and

V_DDpin should typically draw less than 5µA.

POWER UP SEQUENCING

If the ENABLE signal is used, it is necessary to ensure proper co-ordination with the ENABLE and soft-start

features of the external PWM controller in the system. If the CSD97370AQ5M was disabled through ENABLE

without sequencing with the PWM IC controller, the buck converter output will have no voltage or fall below

regulation set point voltage. As a result, the PWM controller IC delivers Max duty cycle on the PWM line. If the

Power Stage CSD97370AQ5M is re-enabled by driving the ENABLE pin high, there will be an extremely large

input inrush current when the output voltage builds back up again. The input inrush current might have

undesirable consequences such as inductor saturation, driving the input power supply into current limit or even

catastrophic failure of the CSD97370AQ5M device. Disabling the PWM controller is recommended when the

CSD97370AQ5M is disabled. The PWM controller should always be re-enabled by going through soft-start

routine to control and minimize the input inrush current and reduce current and voltage stress on all buck

converter components. It is recommended that the external PWM controller be disabled when CSD97370AQ5M

is disabled or nonoperational because of UVLO.

PWM

The input PWM pin incorporates a 3-State function. The Control FET and Sync FET gates are forced low if the

PWM pin is left floating for more than the 3-State Hold off time (t_3HT), typically 100ns. This requires the source

impedance of the driving PWM signal to be a minimum of 250kΩ when in 3-State mode. Operation in and out of

3-State mode should follow the timing diagram outlined in Figure 6. Both V_PWMLand V_PWMHthreshold levels are

set to accommodate both 3.3V and 5V logic controllers. During normal operation, the PWM signal should be

driven to logic levels Low and High with a maximum of 220Ω/320Ω sink/source impedance respectively.

GATE DRIVERS

The CSD97370AQ5M has an internal high-performance gate driver IC that ensures minimum MOSFET

dead-time while eliminating potential shoot-through currents. Propagation delays between the Control FET and

Sync FET gates are kept to a minimum to minimize body diode conduction and improve efficiency. The gate

driver IC incorporates an adaptive shoot through protection scheme which ensures that neither MOSFET is

turned on while the other one is still conducting at the same time, preventing cross conduction. See Table 1.

Table 1. Truth Table

CONTROL FET

ENABLE

PWM

SYNC FET GATE

V_SW

GATE

L

H

X

L

H

L

H

L

3-State

P_GND

<Min ON time

L

3-State

H

3-State

V_IN

L = Logic Low; H = Logic High; X = Don't care; minimum on time = 40ns

START UP IN PRE-BIASED OUTPUT VOLTAGE

The CSD97370AQ5M incorporates a simple pre-bias feature to protect against the discharging of a prebiased

output voltage and inducing large negative inductor currents. After the Power On Reset threshold is crossed and

the ENABLE pin is set to logic level high, both internal MOSFETs are actively held low until the PWM pin

receives a signal that crosses logic level high threshold and meets the minimum on time criteria (see the

Electrical Characteristics Table). This allows the PWM control IC to provide a soft start routine that creates a

monotonic startup of the output voltage. The pre-bias feature is enabled for a single event and subsequent PWM

signals creates normal switching of the internal MOSFETs (see Table 1). To reactivate the pre-bias feature, the

ENABLE pin needs to be pulled below logic level low or the V_DDsupply voltage needs to cross UVLO.

6

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90%

t_PDL

ENABLE

t_PDH

10%

90%

V_SW

10%

T0488-01

Figure 5. CSD97370AQ5M ENABLE Timing Diagram (V_DD= PWM = 5V)

spacer

PWM 3-State Window

V_PWMH

PWM

V_PWML

t_3RD

t_3HT+ t_3SD

V_OUT

V_SW

t_PDLH

t_PDHL

t_3HT+ t_3SD

t_3RD

T0489-01

Figure 6. CSD97370AQ5M PWM Timing Diagram

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TYPICAL CHARACTERISTICS

Test conditions: V_IN= 12V, V_DD= 5V, f_SW= 500kHz, V_OUT= 1.2V, L_OUT= 0.3μH, DCR = 0.54mΩ, T_J= 125°C

spacer

10

9

8

7

6

5

4

3

2

1

0

1.4

1.3

1.2

1.1

1

Max

Typ

0.9

0.8

0.7

0.6

0.5

0.4

0

5

10

15

20

25

30

35

40

−50

−25

0

25

50

75

100

125

150

Output Current (A)

T_C− Junction Temperature − ºC

Figure 7. Power Loss vs Output Current

Figure 8. Power Loss vs Temperature

50

45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

400LFM

200LFM

100LFM

Nat Conv

400LFM

200LFM

100LFM

Nat Conv

0

10

20

30

40

50

60

70

80

90

0

10

20

30

40

50

60

70

80

90

Ambient Temperature (°C)

G003

G004

Figure 9. Safe Operating Area – PCB Vertical Mount ⁽¹⁾

Figure 10. Safe Operating Area – PCB Horizontal Mount ⁽¹⁾

50

45

40

35

30

25

20

15

10

Typ SOA

5

Min SOA

0

20

40

60

80

100

120

140

Board Temperature (ºC)

Figure 11. Typical and Min Safe Operating Area ⁽¹⁾

1. The Typical CSD97370AQ5M System Characteristic curves are based on measurements made on a PCB design with

dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness. See the Application section

for detailed explanation.

8

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TYPICAL CHARACTERISTICS

Test conditions: V_IN= 12V, V_DD= 5V, f_SW= 500kHz, V_OUT= 1.2V, L_OUT= 0.3μH, DCR = 0.54mΩ, T_J= 125°C

spacer

1.6

17.1

14.2

11.4

8.5

1.6

1.5

1.4

1.3

1.2

1.1

1

17.0

14.2

11.3

8.5

1.5

1.4

1.3

1.2

1.1

1

5.7

2.8

0.0

0.9

0.8

0.7

0.6

−2.8

−5.7

−8.5

−11.4

0.9

0.8

0.7

0.6

−2.8

−5.7

−8.5

−11.3

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

3

5

7

9

11

13

15

17

19

21

23

Switching Frequency (kHz)

Input Voltage (V)

Figure 12. Normalized Power Loss vs Frequency

Figure 13. Normalized Power Loss vs Input Voltage

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

22.7

19.9

17

1.6

1.5

1.4

1.3

1.2

1.1

1

17

14.2

11.3

8.5

14.2

11.4

8.5

5.7

2.8

5.7

0

2.8

0.9

0.8

0.7

0.6

−2.8

−5.7

−8.5

−11.3

0

0.9

0.8

−2.8

−5.7

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Inductance (µH)

1

1.1

Output Voltage (V)

Figure 14. Normalized Power Loss vs Output Voltage

Figure 15. Normalized Power Loss vs Output Inductance

20

19

18

17

16

15

14

13

12

11

10

70

65

60

55

50

45

40

35

30

25

20

15

10

200 400 600 800 1000 1200 1400 1600 1800 2000

Switching Frequency (kHz)

-50

-25

0

25

50

75

100

125

150

Junction Temperature (°C)

G030

G031

Figure 16. Driver Current vs Frequency

Figure 17. Driver Current vs Temperature

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APPLICATION INFORMATION

The Power Stage CSD97370AQ5M is a highly optimized design for synchronous buck applications using

NexFET devices with a 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield

the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards

a more systems centric environment. The high-performance gate driver IC integrated in the package helps

minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level

performance curves such as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict

the product performance in the actual application.

Power Loss Curves

MOSFET centric parameters such as R_DS(ON)and Q_gdare primarily needed by engineers to estimate the loss

generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has

provided measured power loss performance curves. Figure 7 plots the power loss of the CSD97370AQ5M as a

function of load current. This curve is measured by configuring and running the CSD97370AQ5M as it would be

in the final application (see Figure 18). The measured power loss is the CSD97370AQ5M device power loss

which consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss

curve.

Power Loss = (V_INx I_IN) + (V_DDx I_DD) – (V_{SW_AVG}x I_OUT

)

(1)

The power loss curve in Figure 7 is measured at the maximum recommended junction temperature of

T_J= 125°C under isothermal test conditions.

Safe Operating Curves (SOA)

The SOA curves in the CSD97370AQ5M datasheet give engineers guidance on the temperature boundaries

within an operating system by incorporating the thermal resistance and system power loss. Figure 9, Figure 10,

and Figure 11 outline the temperature and airflow conditions required for a given load current. The area under

the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design

with dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.

Normalized Curves

The normalized curves in the CSD97370AQ5M data sheet give engineers guidance on the Power Loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in

power loss and the secondary Y-axis is the change is system temperature required in order to comply with the

SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is

subtracted from the SOA curve.

10

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Figure 18. Power Loss Test Circuit

Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).

Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the

following procedure will outline the steps engineers should take to predict product performance for any set of

system conditions.

Design Example

Operating Conditions: Output Current (l_OUT) = 25A, Input Voltage (V_IN) = 7V, Output Voltage (V_OUT) = 1V,

Switching Frequency (f_SW) = 800kHz, Output Inductor (L_OUT) = 0.2µH

Calculating Power Loss

•

Typical Power Loss at 25A = 3.5W (Figure 7)

Normalized Power Loss for switching frequency ≈ 1.08 (Figure 12)

Normalized Power Loss for input voltage ≈ 1.05 (Figure 13)

Normalized Power Loss for output voltage ≈ 0.7 (Figure 14)

Normalized Power Loss for output inductor ≈ 1.04 (Figure 15)

Final calculated Power Loss = 3.5W × 1.08 × 1.05 × 0.7 × 1.04 ≈ 2.89W

Calculating SOA Adjustments

•

SOA adjustment for switching frequency ≈ 2.6°C (Figure 12)

SOA adjustment for input voltage ≈ 1.4°C (Figure 13)

SOA adjustment for output voltage ≈ –1.0°C (Figure 14)

SOA adjustment for output inductor ≈ 1.3°C (Figure 15)

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•

Final calculated SOA adjustment = 2.6 + 1.4 + (–1.0) + 1.3 ≈ 4.3°C

50

45

40

35

30

1

25

20

2

15

10

5

3

0

20

40

60

80

100

120

140

Board Temperature (°C)

Figure 19. Power Stage CSD97370AQ5M SOA

In the design example above, the estimated power loss of the CSD97370AQ5M would increase to 2.89W. In

addition, the maximum allowable board and/or ambient temperature would have to decrease by 4.3°C. Figure 19

graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.

2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.

3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient

temperature of 4.3°C. In the event the adjustment value is a negative number, subtracting the negative number

would yield an increase in allowable board/ambient temperature.

RECOMMENDED PCB DESIGN OVERVIEW

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below

is a brief description on how to address each parameter.

Electrical Performance

The CSD97370AQ5M has the ability to switch at voltages rates greater than 10kV/µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.

•

The placement of the input capacitors relative to V_INand P_GNDpins of CSD97370AQ5M device should have

the highest priority during the component placement routine. It is critical to minimize these node lengths. As

such, ceramic input capacitors need to be placed as close as possible to the V_INand P_GNDpins (see

Figure 20). The example in Figure 20 uses 6 x 10µF 1206 25V ceramic capacitors (TDK Part #

C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an

appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power

Stage C5, C8 and C7, C19 should follow in order.

•

The bootstrap cap C_BOOT0.1µF 0603 16V ceramic capacitor should be closely connected between BOOT and

BOOT_R pins

The switching node of the output inductor should be placed relatively close to the Power Stage

CSD97370AQ5M V_SWpins. Minimizing the V_SWnode length between these two components will reduce the

PCB conduction losses and actually reduce the switching noise level.⁽¹⁾

(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

12

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Thermal Performance

The CSD97370AQ5M has the ability to use the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

Use the smallest drill size allowed in your design. The example in Figure 20 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

•

Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

Figure 20. Recommended PCB Layout (Top Down View)

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MECHANICAL DATA

q

h

c2

c

A

L

K

E1

c1

E2

q

b

23

E

D2

D1

e

q

0.3 x 45

A1

L

Top View

Side View

Bottom View

Note: Exposed tie clips may vary

c

E1

M0201-01

MILLIMETERS

Nom

INCHES

DIM

Min

Max

1.50

Min

Nom

0.059

0.000

0.010

0.008

0.010

0.236

0.216

0.236

0.197

0.128

0.020 TYP

0.049

0.015 TYP

0.020

—

Max

A

A1

b

1.400

0.000

0.200

0.150

0.200

5.900

5.379

5.900

4.900

3.140

1.45

0.057

0.000

0.008

0.006

0.008

0.232

0.212

0.232

0.193

0.124

0.061

0.002

0.013

0.010

0.012

0.240

0.220

0.240

0.201

0.132

0.000

0.050

0.320

0.250

0.300

6.100

5.579

6.100

5.100

3.340

0.250

c

0.200

c1

c2

D1

D2

E

0.200

0.250

6.000

5.479

6.000

E1

E2

e

5.000

3.240

0.500 TYP

1.250

h

1.150

1.350

0.045

0.053

K

0.380 TYP

0.500

L

0.400

0.00

0.600

0.016

0.00

0.024

θ

—

14

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SLPS352 –SEPTEMBER 2011

Land Pattern Recommendation

0.331 (0.013)

0.410 (0.016)

0.370 (0.015)

1.000 (0.039)

0.300

(0.012)

6.300

(0.248)

5.300

(0.209)

5.639

(0.222)

0.500

(0.020)

3.400

(0.134)

5.900

(0.232)

M0202-01

NOTE: Dimensions are in mm (inches).

spacer

Stencil Recommendation

0.250 (0.010)

0.311

(0.012)

0.850 (0.033)

0.250 (0.010)

0.300 (0.012)

0.500 (0.020)

5.250

(0.207)

1.145 (0.045)

0.300

(0.012)

0.250 (0.010)

0.600 (0.024)

0.750 (0.030)

0.300

(0.012)

1.400 (0.055)

5.700 (0.224)

M0204-01

NOTE: Dimensions are in mm (inches).

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PACKAGE MATERIALS INFORMATION

www.ti.com

17-Oct-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CSD97370AQ5M

SON

DQP

22

2500

330.0

12.4

5.3

6.3

1.8

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Oct-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SON DQP 22

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 29.0

CSD97370AQ5M

2500

Pack Materials-Page 2

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型号：	CSD97370AQ5M
厂家：	TEXAS INSTRUMENTS
描述：	Synchronous Buck NexFET? Power Stage 同步降压NexFET™功率级
文件：	总22页 (文件大小：1177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CSD97370AQ5M [TI]

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