CSD97374Q4M_15 [TI]
Synchronous Buck NexFET Power Stage;
| 型号： | CSD97374Q4M_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Synchronous Buck NexFET Power Stage |
| 文件： | 总18页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD97374Q4M
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SLPS382C –JANUARY 2013–REVISED JULY 2013
Synchronous Buck NexFET™ Power Stage
1
FEATURES
APPLICATIONS
23
•
Over 92% System Efficiency at 15A
Max Rated Continuous Current 25A, Peak 60A
High Frequency Operation (up to 2 MHz)
High Density - SON 3.5x4.5-mm Footprint
Ultra Low Inductance Package
System Optimized PCB Footprint
Ultra Low Quiescent (ULQ) Current Mode
3.3V and 5V PWM Signal Compatible
Diode Emulation Mode with FCCM
Input Voltages up to 24V
•
•
•
Ultrabook/Notebook DC/DC Converters
Multiphase Vcore and DDR Solutions
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Point-of-Load Synchronous Buck in
Networking, Telecom, and Computing Systems
ORDERING INFORMATION
Device
Package
Media
Qty
Ship
SON 3.5 × 4.5-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
CSD97374Q4M
2500
Three-State PWM Input
Integrated Bootsrap Diode
Shoot Through Protection
RoHS Compliant – Lead Free Terminal Plating
Halogen Free
DESCRIPTION
The CSD97374Q4M NexFET™ Power Stage is a highly optimized design for use in a high power, high density
Synchronous Buck converter. This product integrates the driver IC and NexFET technology to complete the
power stage switching function. The driver IC has a built-in selectable diode emulation function that enables
DCM operation to improve light load efficiency. In addition, the driver IC supports ULQ mode that enables
Connected Standby for Windows™ 8 . With the PWM input in tri-state, quiescent current is reduced to 130 µA,
with immediate response. When SKIP# is held at tri-state, the current is reduced to 8 µA (typically 20 µs is
required to resume switching). This combination produces a high current, high efficiency, and high speed
switching device in a small 3.5 × 4.5-mm outline package. In addition, the PCB footprint has been optimized to
help reduce design time and simplify the completion of the overall system design.
100
90
80
70
60
50
40
12
10
8
VGS = 5V
VIN = 12V
VOUT = 1.8V
LOUT = .29µH
fSW = 500kHz
TA = 25ºC
6
4
2
0
0
5
10
15
20
25
Output Current (A)
G001
Figure 1. Application Diagram
Figure 2. Efficiency and Power Loss
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
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SLPS382C –JANUARY 2013–REVISED JULY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)
TA = 25°C (unless otherwise noted)
VALUE
UNIT
MIN
-0.3
-0.3
-7
MAX
30
VIN to PGND
V
V
VSW to PGND , VIN to VSW
VSW to PGND, VIN to VSW (<10ns)
VDD to PGND
30
33
V
–0.3
–0.3
–0.3
-2
6
V
PWM, SKIP# to PGND
BOOT to PGND
6
V
35
V
BOOT to PGND (<10ns)
BOOT to BOOT_R
38
V
–0.3
6
V
Human Body Model (HBM)
Charged Device Model (CDM)
2000
500
8
V
ESD Rating
V
Power Dissipation, PD
W
°C
°C
Operating Temperature Range, TJ
Storage Temperature Range, TSTG
-40
150
150
–55
(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
Parameter
Gate Drive Voltage, VDD
Conditions
MIN
MAX
5.5
24
UNIT
V
4.5
Input Supply Voltage, VIN
V
Continuous Output Current, IOUT
VIN = 12V, VDD = 5V, VOUT = 1.8V,
fSW = 500kHz, LOUT = 0.29µH(1)
25
A
(2)
Peak Output Current, IOUT-PK
60
A
Switching Frequency, fSW
On Time Duty Cycle
CBST = 0.1µF (min)
2000
85
kHz
%
Minimum PWM On Time
Operating Temperature
40
ns
°C
–40
125
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) System conditions as defined in Note 1. Peak Output Current is applied for tp = 10ms, duty cycle ≤ 1%
THERMAL INFORMATION
TA = 25°C (unless otherwise noted)
PARAMETER
Thermal Resistance, Junction-to-Case (Top of package)(1)
Thermal Resistance, Junction-to-Board(2)
MIN
TYP
MAX UNIT
22.8 °C/W
2.5 °C/W
RθJC
RθJB
(1)
(2)
R
θJC is determined with the device mounted on a 1-inch² (6.45 -cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inch x 1.5-inch, 0.06-inch
(1.52-mm) thick FR4 board.
RθJB value based on hottest board temperature within 1mm of the package.
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ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = POR to 5.5V (unless otherwise noted)
PARAMETER
PLOSS
CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 12V, VDD = 5V, VOUT = 1.8V, IOUT = 15A,
fSW = 500kHz, LOUT = 0.29µH , TJ = 25°C
Power Loss(1)
Power Loss(2)
Power Loss(2)
2.3
2.5
2.8
W
W
W
VIN = 19V, VDD = 5V, VOUT = 1.8V, IOUT = 15A,
fSW = 500kHz, LOUT = 0.29µH , TJ = 25°C
VIN = 19V, VDD = 5V, VOUT = 1.8V, IOUT = 15A,
fSW = 500kHz, LOUT = 0.29µH , TJ = 125°C
VIN
VIN Quiescent Current, IQ
PWM=Floating, VDD = 5V, VIN= 24V
1
µA
VDD
PWM = Float, SKIP# = VDD or 0V
SKIP# = Float
130
8
µA
µA
Standby Supply Current, IDD
Operating Supply Current, IDD
PWM = 50% Duty cycle, fSW = 500kHz
8.2
mA
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power-On Reset, VDD Rising
UVLO, VDD Falling
4.15
V
V
3.7
Hysteresis
0.2
mV
PWM and SKIP# I/O Specifications
Pull Up to VDD
1700
800
Input Impedance, RI
kΩ
Pull Down (to GND)
Logic Level High, VIH
Logic Level Low, VIL
Hysteresis, VIH
2.65
1.3
0.6
2
V
0.2
Tri-State Voltage, VTS
Tri-state Activation Time (falling) PWM,
tTHOLD(off1)
60
60
1
ns
µs
Tri-state Activation Time (rising) PWM,
tTHOLD(off2)
Tri-state Activation Time (falling) SKIP#,
tTSKF
Tri-state Activation Time (rising) SKIP#,
tTSKR
1
(2)
Tri-state Exit Time PWM, t3RD(PWM)
100
50
ns
µs
(2)
Tri-state Exit Time SKIP#, t3RD(SKIP#)
BOOTSTRAP SWITCH
Forward Voltage, VFBST
IF = 10mA
120
240
2
mV
µA
(2)
Reverse Leakage, IRLEAK
VBST – VDD = 25V
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design
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TYPICAL CHARACTERISTICS
TJ = 125°C, unless stated otherwise.
9
1.2
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
VIN = 12V
VGS = 5V
VOUT = 1.8V
fSW = 500kHz
LOUT = 0.29µH
8
1.1
1
7
LOUT = 0.29µH
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0.5
Typ
Max
1
3
5
7
9
11 13 15 17 19 21 23 25
Output Current (A)
−75 −50 −25
0
25
50
75
100 125 150
Junction Temperature (ºC)
G001
G001
Figure 3. Power Loss vs Output Current
Figure 4. Power Loss vs Temperature
30
25
20
15
10
5
30
25
20
15
10
5
Typ
Max
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
LOUT = 0.29µH
VIN = 12V
VGS = 5V
VOUT = 1.8V
fSW = 500kHz
400LFM
200LFM
100LFM
Nat Conv
LOUT = 0.29µH
0
0
0
10
20
30
40
50
60
70
80
90
0
20
40
60
80
100
120
140
Ambient Temperature (ºC)
Board Temperature (ºC)
G001
G001
Figure 5. Safe Operating Area – PCB Horizontal Mount (1)
Figure 6. Typical Safe Operating Area (1)
1.45
8.0
7.1
6.2
5.3
4.4
3.5
2.7
1.8
0.9
0.0
−0.9
1.25
1.2
4.4
3.5
2.7
1.8
0.9
0.0
−0.9
VIN = 12V
VDD = 5V
VOUT = 1.8V
LOUT = 0.29µH
IOUT = 25A
VDD = 5V
1.4
1.35
1.3
VOUT = 1.8V
LOUT = 0.29µH
fSW = 500kHz
IOUT = 25A
1.15
1.1
1.25
1.2
1.15
1.1
1.05
1
1.05
1
0.95
0.95
0
400
800
1200
1600
2000
2400
3
5
7
9
11
13
15
17
19
21
23
Input Voltage (V)
Switching Frequency (kHz)
G001
G001
Figure 7. Normalized Power Loss vs Frequency
Figure 8. Normalized Power Loss vs Input Voltage
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TYPICAL CHARACTERISTICS (continued)
TJ = 125°C, unless stated otherwise.
1.5
9
1.25
1.2
4.4
3.5
2.7
1.8
0.9
0
VIN = 12V
VDD = 5V
fSW = 500kHz
LOUT = 0.29µH
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
IOUT = 25A
1.4
7.2
5.4
3.6
1.8
0
1.3
1.15
1.1
IOUT = 25A
1.2
1.1
1
1.05
1
0.9
0.8
0.7
0.6
−1.8
−3.6
−5.4
−7.2
0.95
0.9
−0.9
−1.8
0
0.5
1
1.5
2
2.5
3
3.5
4
0
100 200 300 400 500 600 700 800 900 1000 1100
Output Inductance (nH)
Output Voltage (V)
G001
G001
Figure 9. Normalized Power Loss vs Output Voltage
Figure 10. Normalized Power Loss vs Output Inductance
45
11
10.5
10
VIN = 12V
VDD = 5V
VOUT = 1.8V
LOUT = 0.29µH
40
35
IOUT = 25A
30
25
20
15
10
5
9.5
VIN = 12V
VDD = 5V
VOUT = 1.8V
LOUT = 0.29µH
IOUT = 25A
9
0
8.5
0
400
800
1200
1600
2000
2400
−75 −50 −25
0
25
50
75
100 125 150
Switching Frequency (kHz)
Junction Temperature (°C)
G000
G000
Figure 11. Driver Current vs Frequency
Figure 12. Driver Current vs Temperature
1. The Typical CSD97374Q4M System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness. See the Application
Information section for detailed explanation.
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PIN CONFIGURATION
SKIP#
1
2
3
8
PWM
VDD
7
6
BOOT
PGND
BOOT_R
9
PGND
VSW
VIN
4
5
Figure 13. Top View
PIN DESCRIPTION
PIN
NAME
DESCRIPTION
NO.
1
SKIP#
This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the
Sync FET. When SKIP# is High, the CSD97374Q4M operates in Forced Continuous Conduction Mode. A tri-state
voltage on SKIP# puts the driver into a very low power state.
2
3
4
5
6
7
8
VDD
Supply Voltage to Gate Drivers and internal circuitry.
PGND
VSW
Power Ground, Needs to be connected to Pin 9 and PCB
Voltage Switching Node – pin connection to the output inductor.
Input Voltage Pin. Connect input capacitors close to this pin.
VIN
BOOT_R
BOOT
PWM
Bootstrap capacitor connection. Connect a minimum 0.1µF 16V X5R, ceramic cap from BOOT to BOOT_R pins. The
bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.
Pulse Width modulated 3-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate
high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if
greater than the 3-State Shutdown Hold-off Time (t3HT
)
9
PGND
Power Ground
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Figure 14. Functional Block Diagram
FUNCTIONAL DESCRIPTION
POWERING CSD97374Q4M AND GATE DRIVERS
An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive
power for the MOSFETS. A 1µF 10V X5R or higher ceramic capacitor is recommended to bypass VDD pin to
PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply
to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor between BOOT and
BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn on speed of the Control FET and
reduce voltage spikes on the VSW node. A typical 1Ω to 4.7Ω value is a compromise between switching loss and
VSW spike amplitude.
Undervoltage Lockout Protection (UVLO)
The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both the Control
FET and Sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H).,
Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower
UVLO threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the
Control FET and Sync FET gates actively low. Figure 15 shows this function.
CAUTION
Do not start the driver in the very low power mode (SKIP# = Tri-state).
V
UVLO_H
V
UVLO_L
V
VDD
Driver On
UDG-12218
Figure 15. UVLO Operation
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PWM Pin
The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when
PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin
incorporates a weak pull-up to maintain the voltage within the tri-state window during low-power modes.
Operation into and out of tri-state mode follows the timing diagram outlined in Figure 16.
When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The
window is defined the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The
device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3 V
(typical) and 5 V (typical) PWM drive signals.
When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP#
pin. Normal operation requires this time period in order for the auto-zero comparator to resume.
Figure 16. PWM Tri-State Timing Diagram
SKIP# Pin
The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is
low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current
is less than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM
mode. When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the
driver enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent
current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.
Table 1 shows the logic functions of UVLO, PWM, SKIP#, the Control FET Gate and the Sync FET Gate.
Table 1. Logic Functions of the Driver IC
UVLO
Active
PWM
—
SKIP#
—
Sync FET Gate
Control FET Gate
MODE
Disabled
DCM(1)
FCCM
Low
Low
Low
Low
High
Low
Low
Inactive
Inactive
Inactive
Inactive
Inactive
Low
Low
High(1)
High
Low
High
High
Tri-state
—
H or L
H or L
Tri-state
Low
Low
LQ
Low
ULQ
(1) Until zero crossing protection occurs.
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Zero Crossing (ZX) Operation
The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy
load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,
which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects
the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the
rectifying MOSFET.
Integrated Boost-Switch
To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the
conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL
signal.
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APPLICATION INFORMATION
The Power Stage CSD97374Q4M is a highly optimized design for synchronous buck applications using NexFET
devices with a 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest
power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more
systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the
parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such
as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance
in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss
generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has
provided measured power loss performance curves. Figure 3 plots the power loss of the CSD97374Q4M as a
function of load current. This curve is measured by configuring and running the CSD97374Q4M as it would be in
the final application (see Figure 17). The measured power loss is the CSD97374Q4M device power loss which
consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.
Power Loss = (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT
)
(1)
The power loss curve in Figure 3 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD97374Q4M datasheet give engineers guidance on the temperature boundaries within
an operating system by incorporating the thermal resistance and system power loss. Figure 5 and Figure 6
outline the temperature and airflow conditions required for a given load current. The area under the curve
dictates the safe operating area. All the curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.
Normalized Curves
The normalized curves in the CSD97374Q4M data sheet give engineers guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Figure 17. Power Loss Test Circuit
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Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).
Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the
following procedure will outline the steps engineers should take to predict product performance for any set of
system conditions.
Design Example
Operating Conditions: Output Current (lOUT) = 15A, Input Voltage (VIN ) = 7V, Output Voltage (VOUT) = 1.5V,
Switching Frequency (fSW) = 800kHz, Output Inductor (LOUT) = 0.2µH
Calculating Power Loss
•
•
•
•
•
•
Typical Power Loss at 15A = 2.8W (Figure 3)
Normalized Power Loss for switching frequency ≈ 1.02 (Figure 7)
Normalized Power Loss for input voltage ≈ 1.07 (Figure 8)
Normalized Power Loss for output voltage ≈ 0.94(Figure 9)
Normalized Power Loss for output inductor ≈ 1.08 (Figure 10)
Final calculated Power Loss = 2.8W × 1.02 × 1.07 × 0.94 × 1.08 ≈ 3.1W
Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for switching frequency ≈ 0.3°C (Figure 7)
SOA adjustment for input voltage ≈ 1.2°C (Figure 8)
SOA adjustment for output voltage ≈ –1.1°C (Figure 9)
SOA adjustment for output inductor ≈ 1.4°C (Figure 10)
Final calculated SOA adjustment = 0.3 + 1.2 + (–1.1) + 1.4 ≈ 1.8°C
Figure 18. Power Stage CSD97374Q4M SOA
In the design example above, the estimated power loss of the CSD97374Q4M would increase to 3.1W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 1.8°C. Figure 18
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 1.8°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
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RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below
is a brief description on how to address each parameter.
Electrical Performance
The CSD97374Q4M has the ability to switch at voltage rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.
•
The placement of the input capacitors relative to VIN and PGND pins of CSD97374Q4M device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 19).
The example in Figure 19 uses 1 x 1nF 0402 25V and 3 x 10µF 1206 25V ceramic capacitors (TDK Part #
C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an
appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power
Stage C5, C8 and C6, C19 should follow in order.
•
•
The bootstrap cap CBOOT 0.1µF 0603 16V ceramic capacitor should be closely connected between BOOT and
BOOT_R pins
The switching node of the output inductor should be placed relatively close to the Power Stage
CSD97374Q4M VSW pins. Minimizing the VSW node length between these two components will reduce the
(2)
PCB conduction losses and actually reduce the switching noise level.
Thermal Performance
The CSD97374Q4M has the ability to use the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in Figure 19 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
•
Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 19. Recommended PCB Layout (Top Down View)
(2) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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CSD97374Q4M
www.ti.com
SLPS382C –JANUARY 2013–REVISED JULY 2013
MECHANICAL DATA
°
Ө
c1
a1
D2
4
1
0.300
(x45°)
8
5
MILLIMETERS
Nom
INCHES
DIM
Min
Max
Min
Nom
0.035
0.000
0.008
0.087
0.008
0.008
0.156
0.177
0.138
0.083
0.016 TYP
0.012 TYP
0.016
0.009
—
Max
A
a1
b
0.800
0.000
0.150
2.000
0.150
0.150
3.850
4.400
3.400
2.000
0.900
1.000
0.080
0.250
2.400
0.250
0.250
4.050
4.600
3.600
2.200
0.031
0.000
0.006
0.079
0.006
0.006
0.152
0.173
0.134
0.079
0.039
0.003
0.010
0.095
0.010
0.010
0.160
0.181
0.142
0.087
0.000
0.200
b1
b2
c1
D2
E
2.200
0.200
0.200
3.950
4.500
E1
E2
e
3.500
2.100
0.400 TYP
0.300 TYP
0.400
K
L
0.300
0.180
0.00
0.500
0.280
—
0.012
0.007
0.00
0.020
0.011
—
L1
θ
0.230
—
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CSD97374Q4M
SLPS382C –JANUARY 2013–REVISED JULY 2013
www.ti.com
Recommended PCB Land Pattern
(0.006)
0.150
(0.016)
0.400
(0.010)
0.250
(x18)
(0.006)
0.150
(0.024)
0.600 (x 2)
(0.008)
0.200
(x2)
(0.087)
2.200
R0.100
R0.100
0.225 ( x 2)
(0.009)
(0.088)
2.250
(0.012)
0.300
(0.159)
4.050
Recommended Stencil Opening
(0.016)
0.400
(0.029)
0.738 (x 8)
(0.008)
0.200
(0.008)
0.200
(0.015)
0.390
(0.014)
0.350
0.300
R0.100
(0.012)
0.850 (x8)
(0.033)
(0.012)
0.300
R0.100
(0.004)
0.115
0.440 (0.017)
(0.008)
0.200
(0.009)
0.225
0.200
(0.008)
(0.087)
2.200
NOTE: Dimensions are in mm (inches).
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SLPS382C –JANUARY 2013–REVISED JULY 2013
REVISION HISTORY
Changes from Original (January 2013) to Revision A
Page
•
Changed the ROC table, From: VSW to PGND, VIN to VSW (<20ns) MIN = -5 To: VSW to PGND, VIN to VSW (<10ns) MIN
= -7 ........................................................................................................................................................................................ 2
•
•
•
•
Changed the ROC table, From: BOOT to PGND (<20ns) MIN = -3 To: BOOT to PGND (<10ns) MIN = -2 ............................ 2
Changed Logic Level High, VIH From: MAX = 2.6 To: MIN = 2.65 ....................................................................................... 3
Changed Logic Level Low, VIL From: MIN = 0.6 To: MAX = 0.6 .......................................................................................... 3
Changed Tri-State Voltage, VTS From: MIN = 1.2 To: MIN = 1.3 ......................................................................................... 3
Changes from Revision A (March 2013) to Revision B
Page
•
•
•
Changed the Mechanical Drawing image ........................................................................................................................... 13
Changed the Recommended PCB Land Pattern image ..................................................................................................... 14
Changed the Recommended Stencil Opening image ........................................................................................................ 14
Changes from Revision B (May 2013) to Revision C
Page
•
Added dimension row b2 to the MECHANICAL DATA table .............................................................................................. 13
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PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD97374Q4M
VSON
DPC
8
2500
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON DPC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
CSD97374Q4M
8
2500
Pack Materials-Page 2
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