DAC2904Y/2K [TI]
IC PARALLEL, WORD INPUT LOADING, 0.03 us SETTLING TIME, 14-BIT DAC, PQFP48, 7 X 7 MM, 1 MM HEIGHT, TQFP-48, Digital to Analog Converter;
| 型号： | DAC2904Y/2K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC PARALLEL, WORD INPUT LOADING, 0.03 us SETTLING TIME, 14-BIT DAC, PQFP48, 7 X 7 MM, 1 MM HEIGHT, TQFP-48, Digital to Analog Converter 输入元件 转换器 |
| 文件： | 总26页 (文件大小：884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC2904
www.ti.com.............................................................................................................................................. SBAS198C –AUGUST 2001–REVISED OCTOBER 2009
Dual, 14-Bit, 125MSPS
DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC2904
1
FEATURES
APPLICATIONS
•
COMMUNICATIONS:
2
•
125MSPS UPDATE RATE
SINGLE SUPPLY: +3.3V or +5V
HIGH SFDR: 78dB at fOUT = 10MHz
LOW GLITCH: 2pV-s
–
–
Base Stations, WLL, WLAN
Baseband I/Q Modulation
•
•
•
•
•
•
•
•
MEDICAL/TEST INSTRUMENTATION
ARBITRARY WAVEFORM GENERATORS
(ARB)
DIRECT DIGITAL SYNTHESIS (DDS)
space
space
LOW POWER: 310mW
INTERNAL REFERENCE
•
POWER-DOWN MODE: 23mW
The DAC2904 combines high dynamic performance
with a high update rate to create a cost-effective
solution for a wide variety of waveform-synthesis
applications:
DESCRIPTION
The DAC2904 is a monolithic, 14-bit, dual-channel,
high-speed Digital-to-Analog Converter (DAC), and is
optimized to provide high dynamic performance while
dissipating only 310mW.
•
Pin compatibility between family members
provides 10-bit (DAC2900), 12-bit (DAC2902),
and 14-bit (DAC2904) resolution.
Operating with high update rates of up to 125MSPS,
•
•
Pin compatible to the AD9767 dual DAC.
Gain matching is typically 0.5% of full-scale, and
offset matching is specified at 0.02% max.
the
DAC2904
offers
exceptional
dynamic
performance, and enables the generation of very-high
output frequencies suitable for “Direct IF”
applications. The DAC2904 has been optimized for
communications applications in which separate I and
Q data are processed while maintaining tight-gain
and offset matching.
•
The DAC2904 utilizes an advanced CMOS
process; the segmented architecture minimizes
output-glitch energy, and maximizes the dynamic
performance.
All digital inputs are +3.3V and +5V logic
compatible. The DAC2904 has an internal
reference circuit, and allows use in a multiplying
configuration.
•
Each DAC has a high-impedance differential-current
output, suitable for single-ended or differential
analog-output configurations.
The DAC2904 is available in a TQFP-48 package,
and is specified over the extended industrial
temperature range of –40°C to +85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2009, Texas Instruments Incorporated
DAC2904
SBAS198C –AUGUST 2001–REVISED OCTOBER 2009.............................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
(2)
PRODUCT
DAC2904Y/250
DAC2904Y/1K
DAC2904IPFB
Tape and Reel, 250
Tape and Reel, 1k
Tray, 250
DAC2904Y
TQFP-48
PFB
–40°C to +85°C
DAC2904Y
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Models with a slash (/) are available only in tape and reel media in the quantities indicated (for example, /1K indicates 1000 devices per
reel). Ordering 1000 pieces of DAC2904Y/1K will get a single 1000-piece tape and reel.
ABSOLUTE MAXIMUM RATINGS(1)
DAC2904
–0.3 to +6
UNIT
V
+VA to AGND
+VD to DGND
–0.3 to +6
V
AGND to DGND
+VA to +VD
–0.3 to +0.3
–6 to +6
V
V
CLK, PD to DGND
D0–D9 to DGND
IOUT, I OUT to AGND
BW, BYP to AGND
REFIN, FSA to AGND
INT/EXT to AGND
Junction Temperature
Case Temperature
Storage Temperature
–0.3 to VD +0.3
–0.3 to VD +0.3
–1 to VA + 0.3
–0.3 to VA + 0.3
–0.3 to VA + 0.3
–0.3 to VA + 0.3
+150
V
V
V
V
V
V
°C
°C
°C
+100
+125
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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DAC2904
www.ti.com.............................................................................................................................................. SBAS198C –AUGUST 2001–REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS
TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise
noted. Independent Gain Mode.
DAC2904
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
14
Bits
Output Update Rate (fCLOCK
STATIC ACCURACY(1)
)
125
MSPS
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TA = +25°C
TA = +25°C
±4.0
±5.0
LSB
LSB
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
To Nyquist
0dBFS Output
–6dBFS Output
–12dBFS Output
71
82
77
72
82
81
81
78
72
80
69
69
64
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fOUT = 1MHz, fCLOCK = 50MSPS
fOUT = 1MHz, fCLOCK = 26MSPS
fOUT = 2.18MHz, fCLOCK = 52MSPS
fOUT = 5.24MHz, fCLOCK = 52MSPS
fOUT = 10.4MHz, fCLOCK = 78MSPS
fOUT = 15.7MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
fOUT = 20.2MHz, fCLOCK = 100MSPS
fOUT = 20.1MHz, fCLOCK = 125MSPS
fOUT = 40.2MHz, fCLOCK = 125MSPS
Spurious-Free Dynamic Range within a
Window
fOUT = 1MHz, fCLOCK = 50MSPS
fOUT = 5.24MHz, fCLOCK = 52MSPS
fOUT = 5.26MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 125MSPS
Total Harmonic Distortion (THD)
fOUT = 1MHz, fCLOCK = 50MSPS
fOUT = 5.24MHz, fCLOCK = 52MSPS
fOUT = 5.26MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 125MSPS
Multitone Power Ratio
2MHz span
10MHz span
10MHz span
10MHz span
80
90
88
88
88
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
–79
–77
–76
–75
–70
Eight tone with 110kHz spacing
0dBFS output
fOUT = 2.0MHz to 2.99MHz, fCLOCK
65MSPS
=
80
dBc
Signal-to-Noise Ratio (SNR)
fOUT = 5.02MHz, fCLOCK = 50MHz
Signal-to-Noise and Distortion (SINAD)
fOUT = 5.02MHz, fCLOCK = 50MHz
Channel Isolation
0dBFS output
0dBFS output
68
67
dBc
dBc
fOUT = 1MHz, fCLOCK = 52MSPS
fOUT = 20MHz, fCLOCK = 125MSPS
85
77
dBc
dBc
(1) At output lOUT, while driving a virtual ground.
Copyright © 2001–2009, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise
noted. Independent Gain Mode.
DAC2904
PARAMETER
DYNAMIC PERFORMANCE, continued
Output Settling Time(2)
Output Rise Time(2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
To 0.1%
30
2
ns
ns
10% to 90%
10% to 90%
Output Fall Time(2)
2
ns
Glitch Impulse
2
pV-s
DC ACCURACY
Full-Scale Output Range(3)(FSR)
Output Compliance Range
Gain Error—Full-Scale
Gain Error
All Bits HIGH, IOUT
With internal reference
With internal reference
With internal reference
With internal reference
2
–1.0
–5
20
+1.25
+5
mA
V
±1
±1
%FSR
%FSR
%FSR
–2.5
–2.0
+2.5
+2.0
Gain Matching
0.5
ppmFSR/°
C
Gain Drift
With internal reference
With internal reference
With internal reference
±50
Offset Error
Offset Drift
–0.02
+0.02
%FSR
ppmFSR/°
C
±0.2
Power-Supply Rejection, +VA
Power-Supply Rejection, +VD
Output Noise
+5V, ±10%
+3.3V, ±10%
–0.2
+0.2 %FSR/V
–0.025
+0.025 %FSR/V
IOUT = 20mA, RLOAD = 50Ω
IOUT = 2mA
50
30
pA/√Hz
pA/√Hz
kΩ
Output Resistance
200
6
Output Capacitance
IOUT, I OUT to ground
pF
REFERENCE/CONTROL AMP
Reference Voltage
+1.18
+0.5
+1.25
±50
+1.31
+1.25
V
ppmFSR/°
C
Reference Voltage Drift
Reference Output Current
Reference Multiplying Bandwidth
Input Compliance Range
DIGITAL INPUTS
100
0.3
nA
MHz
V
Logic Coding
Straight Binary
Logic High Voltage, VIH
Logic Low Voltage, VIL
Logic High Voltage, VIH
Logic Low Voltage, VIL
+VD = 5V
+VD = 5V
3.5
5
0
V
V
1.2
0.8
+VD = 3.3V
+VD = 3.3V
+VD = 3.3V
+VD = 3.3V
2
3
V
0
V
(4)
Logic High Current, IIH
±10
±10
5
μA
μA
pF
Logic Low Current
Input Capacitance
(2) Measured single-ended into 50Ω load.
(3) Nominal full-scale output current is 32 ×IREF; see Applicationxx section for details.
(4) Typically 45μA for the PD pin, which has an internal pull-down resistor.
4
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DAC2904
www.ti.com.............................................................................................................................................. SBAS198C –AUGUST 2001–REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise
noted. Independent Gain Mode.
DAC2904
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltages
+VA
+3.0
+3.0
+5
+5.5
+5.5
V
V
+VD
+3.3
Supply Current
(5)
IVA
+VA = +5V, lOUT = 20mA
Power-Down mode
58
1.7
4.2
17
65
3
mA
mA
(5)
IVA
(5)
IVD
7
mA
(6)
IVD
19.5
350
390
mA
Power Dissipation(5)
Power Dissipation(6)
Power Dissipation(5)
Power Dissipation
Thermal Resistance, TQFP-48
θJA
+VA = +5V, +VD = 3.3V, lOUT = 20mA
+VA = +5V, +VD = 3.3V, lOUT = 20mA
+VA = +5V, +VD = 3.3V, lOUT = 2mA
Power-Down mode
310
348
130
23
mW
mW
mW
mW
38
60
13
°C/W
°C/W
θJC
TEMPERATURE RANGE
Specified
Ambient
Ambient
–40
–40
+85
+85
°C
°C
Operating
(5) Measured at fCLOCK = 25MSPS and fOUT = 1MHz.
(6) Measured at fCLOCK = 100MSPS and fOUT = 40MHz.
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DAC2904
SBAS198C –AUGUST 2001–REVISED OCTOBER 2009.............................................................................................................................................. www.ti.com
DEVICE INFORMATION
PFB PACKAGE
TQFP-48
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
36 D0-2
35 D1-2
34 D2_2
33 D3_2
D13_1 (MSB)
D12_1
D11_1
D10_1
D9_1
32
D4_2
D8_1
31 D5_2
30 D6_2
29 D7_2
28 D8_2
DAC2904
D7_1
D6_1
D5_1
D4_1 10
D3_1 11
D2_1 12
27
D9_2
26 D10_2
25 D11_2
13 14 15 16 17 18 19 20 21 22 23 24
TERMINAL FUNCTIONS
TERMINAL
NAME
D[13:0]_1
DGND
+VD
NO.
1–14
15, 21
16, 22
17
DESCRIPTION
Data port DAC1, data bit 13 (MSB) to bit 0 (LSB)
Digital ground
Digital supply, +3.0V to +5.5V
DAC1 input latches write signal
Clock input DAC1
WRT1
CLK1
18
CLK2
19
Clock input DAC2
WRT2
D[13:0]_2
PD
20
DAC2 input latches write signal
Data port DAC2, data bit 13 (MSB) to bit 0 (LSB).
23–36
37
Power-down function control input. H = DAC in power-down mode; L = DAC in normal operation (internal pull-down for default L).
Analog ground
AGND
38
IOUT
2
39
Current output DAC2. Full-scale with all bits of data port 2 high.
Complementary current output DAC2. Full-scale with all bits of data port 2 low.
Full-scale adjust, DAC2. Connect external RSET resistor.
I OUT
2
40
FSA2
GSET
REFIN
FSA1
41
42
Gain-setting mode (H = one resistor, L = two resistors)
43
Internal reference voltage output; external reference voltage input. Bypass with 0.1μF capacitor to AGND for internal reference operation.
Full-scale adjust, DAC1. Connect external RSET resistor.
44
I OUT
IOUT
1
45
Complementary current output DAC1. Full-scale with all bits of data port 1 low.
Current output DAC1. Full-scale with all bits of data port 1 high.
Analog supply, +3.0V to +5.5V
1
46
+VA
NC
47
48
No connection
6
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tS
tH
DATA IN
D[13:0](n)
D[13:0](n + 1)
tLPW
WRT1
WRT2
tCPW
CLK1
CLK2
tSET
IOUT1
IOUT
IOUT
50%
(n)
(n + 1)
IOUT2
tPD
TIMING REQUIREMENTS
PARAMETER
MIN
TYP
MAX
UNIT
ns
tS
Input setup time
Input hold time
2
1.5
3.5
0
tH
ns
tLPW, tCPW
tCW
Latch/Clock pulse width
4
ns
Delay rising CLK edge to rising WRT edge
Propagation delay
tPW – 2
ns
tPD
1
ns
tSET
Settling time (0.1%)
30
ns
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2904 accept a standard positive coding with data bit D13 being the most
significant bit (MSB). The converter outputs support a clock rate of up to 125MSPS. The best performance will
typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long
as the timing specifications are met. Also, the set-up and hold times may be chosen within their specified limits.
All digital inputs of the DAC2904 are CMOS compatible. The logic thresholds depend on the applied digital
supply voltages, such that they are set to approximately half the supply voltage; Vth = +VD/2 (±20% tolerance).
The DAC2904 is designed to operate with a digital supply (+VD) of +3.0V to +5.5V.
The two converter channels within the DAC2904 consist of two independent, 14-bit, parallel data ports. Each
DAC channel is controlled by its own set of write (WRT1, WRT2) and clock (CLK1, CLK2) inputs. Here, the WRT
lines control the channel input latches and the CLK lines control the DAC latches. The data is first loaded into the
input latch by a rising edge of the WRT line. This data is presented to the DAC latch on the following falling edge
of the WRT signal. On the next rising edge of the CLK line, the DAC is updated with the new data and the analog
output signal will change accordingly. The double latch architecture of the DAC2904 results in a defined
sequence for the WRT and CLK signals, expressed by parameter tCW . A correct timing is observed when the
rising edge of CLK occurs at the same time, or before, the rising edge of the WRT signal. This condition can
simply be met by connecting the WRT and CLK lines together. Note that all specifications were measured with
the WRT and CLK lines connected together.
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SBAS198C –AUGUST 2001–REVISED OCTOBER 2009.............................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double terminated load, and
SFDR up to Nyquist, unless otherwise noted.
TYPICAL DNL
TYPICAL INL
4
3
6
5
4
2
3
1
2
0
1
0
-1
-2
-3
-4
-1
-2
-3
-4
0
2k
4k
6k
8k
10k
12k
14k
16k
0
2k
4k
6k
8k
10k
12k
14k
16k
Code
Code
Figure 1.
Figure 2.
SFDR vs fOUT AT 26MSPS
SFDR vs fOUT AT 52MSPS
90
85
80
75
70
65
60
90
85
80
75
70
65
60
-6dBFS
0dBFS
0dBFS
-6dBFS
-12dBFS
-12dBFS
0
2
4
6
8
10
12
0
5
10
15
20
25
fOUT (MHz)
fOUT (MHz)
Figure 3.
Figure 4.
SFDR vs fOUT AT 100MSPS
SFDR vs fOUT AT 78MSPS
85
80
75
70
65
60
55
85
80
75
70
65
60
55
50
0dBFS
-6dBFS
-6dBFS
-12dBFS
-12dBFS
0dBFS
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
40
45
fOUT (MHz)
fOUT (MHz)
Figure 5.
Figure 6.
8
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double terminated load, and
SFDR up to Nyquist, unless otherwise noted.
SFDR vs fOUT AT 125MHz
SFDR vs IOUTFS AND fOUT AT 78MSPS
85
80
75
70
65
60
55
50
82
80
78
76
74
72
70
68
66
64
62
20mA
10mA
-6dBFS
-12dBFS
5mA
0dBFS
0dBFs
0
10
20
30
fOUT (MHz)
40
50
60
0
5
10
15
20
25
fOUT (MHz)
Figure 7.
Figure 8.
SFDR AT 125MSPS vs TEMPERATURE
GAIN AND OFFSET DRIFT
0.8
0.6
0.004
0.003
0.002
0.001
0
90
85
80
75
70
65
60
55
50
2MHz
Offset Error
0.4
10MHz
0.2
20MHz
40MHz
0
-0.2
-0.4
-0.6
-0.8
-0.001
-0.002
-0.003
-0.004
Gain Error
-40
-20
0
20
40
60
80 85
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
Figure 9.
Figure 10.
IVD vs RATIO AT +VD = +3.3V
IVA vs IOUTFS
60
55
50
45
40
35
30
25
20
15
10
25
20
15
10
5
125MSPS
100MSPS
78MSPS
52MSPS
26MSPS
0
0
5
10
15
20
25
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
Ratio (fOUT/fCLK
)
IOUTFS (mA)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double terminated load, and
SFDR up to Nyquist, unless otherwise noted.
SINGLE-TONE SFDR
SINGLE-TONE SFDR
10
0
10
0
fCLOCK = 100MSPS
fOUT = 20.2MHz
fCLOCK = 52MSPS
fOUT = 5.23MHz
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
Amplitude = 0dBFS
Amplitude = 0dBFS
0
5.2
10.4
15.6
20.8
26
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 13.
Figure 14.
DUAL-TONE SFDR
FOUR-TONE SFDR
10
0
10
0
fCLOCK = 78MSPS
fOUT1 = 9.44MHz
fOUT2 = 10.44MHz
Amplitude = 0dBFS
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
Amplitude = 0dBFS
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
7.8
15.6
23.4
31.2
39
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
Figure 15.
Figure 16.
WCDMA—ACPR
-30
-40
fCLOCK = 61.44MSPS
PCHANNEL = -13dBm
ACPR = -69.2dB
-50
-60
-70
-80
-90
-100
-110
-120
-130
Center: 15.36MHz; Span: 14MHz
Figure 17.
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APPLICATION INFORMATION
THEORY OF OPERATION
DAC TRANSFER FUNCTION
The architecture of the DAC2904 uses the current
steering technique to enable fast switching and a high
update rate. The core element within the monolithic
DAC is an array of segmented current sources that
are designed to deliver a full-scale output current of
up to 20mA, as shown in Figure 18. An internal
decoder addresses the differential current switches
each time the DAC is updated and a corresponding
output current is formed by steering all currents to
Each of the DACs in the DAC2904 has a set of
complementary current output, IOUT and I
. The
OUT
full-scale output current, IOUTFS, is the summation of
the two complementary output currents:
IOUTFS = IOUT + IOUT
(1)
The individual output currents depend on the DAC
code and can be expressed as:
Code
´
16,384
IOUT = IOUTFS
either output summing node, IOUT or I
. The
OUT
(2)
complementary outputs deliver a differential output
signal, which improves the dynamic performance
through reduction of even-order harmonics,
common-mode signals (noise), and double the
peak-to-peak output signal swing by a factor of two,
compared to single-ended operation.
Code
16,384
I
OUT = IOUTFS ´ (16,383 -
)
(3)
where Code is the decimal representation of the DAC
data input word. Additionally, IOUTFS is a function of
the reference current IREF, which is determined by the
reference voltage and the external setting resistor,
The segmented architecture results in a significant
reduction of the glitch energy, improves the dynamic
performance (SFDR), and DNL. The current outputs
maintain a very high output impedance of greater
than 200kΩ.
RSET
.
VREF
RSET
IOUTFS = 32 ´ IREF = 32 ´
(4)
The full-scale output current is determined by the
ratio of the internal reference voltage (1.25V) and an
external resistor, RSET. The resulting IREF is internally
multiplied by a factor of 32 to produce an effective
DAC output current that can range from 2mA to
In most cases the complementary outputs will drive
resistive loads or a terminated transformer. A signal
voltage will develop at each output according to:
VOUT = IOUT ´ RLOAD
(5)
VOUT = IOUT ´ RLOAD
(6)
20mA, depending on the value of RSET
.
The value of the load resistance is limited by the
output compliance specification of the DAC2904. To
maintain specified linearity performance, the voltage
The DAC2904 is split into a digital and an analog
portion, each of which is powered through its own
supply pin. The digital section includes edge-triggered
input latches and the decoder logic, while the analog
section comprises the current source array with its
associated switches, and the reference circuitry.
for IOUT and I
should not exceed the maximum
OUT
allowable compliance range.
The two single-ended output voltages can be
combined to find the total differential output swing:
(2 ´ Code - 16,383)
VOUTDIFF = VOUT - VOUT
=
´ IOUTFS ´ RLOAD
16,384
(7)
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+VD
+VD
+VA
lOUT
1
Data Input
Port 1
DAC1
Segmented Switches
Current Sources
Input
Latch 1
DAC
Latch 1
D[13:0]_1
IOUT
1
REFIN
WRT1
CLK1
CLK2
WRT2
FSA1
FSA2
GSET
PD
Reference
Control Amplifier
DAC2904
lOUT
2
Data Input
Port 2
DAC2
Segmented Switches
Current Sources
Input
Latch 2
DAC
Latch 2
D[13:0]_2
IOUT
2
DGND
DGND
AGND
Figure 18. Block Diagram of the DAC2904
given by the breakdown voltage of the CMOS
process, and exceeding it will compromise the
reliability of the DAC2904, or even cause permanent
damage. With the full-scale output set to 20mA, the
positive compliance equals 1.25V, operating with an
analog supply of +VA = 5V. Note that the compliance
range decreases to about 1V for a selected output
current of IOUTFS = 2mA. Care should be taken that
the configuration of DAC2904 does not exceed the
compliance range to avoid degradation of the
distortion performance and integral linearity.
ANALOG OUTPUTS
The DAC2904 provides two complementary current
outputs, IOUT and I . The simplified circuit of the
OUT
analog output stage representing the differential
topology is shown in Figure 19. The output
impedance of IOUT and I
combination of the differential switches, along with
the current sources and associated parasitic
capacitances.
results from the parallel
OUT
Best distortion performance is typically achieved with
the maximum full-scale output signal limited to
approximately 0.5VPP. This is the case for a 50Ω
doubly terminated load and a 20mA full-scale output
current. A variety of loads can be adapted to the
output of the DAC2904 by selecting a suitable
transformer while maintaining optimum voltage levels
+VA
DAC2904
at IOUT and I
. Furthermore, using the differential
OUT
output configuration in combination with a transformer
will be instrumental for achieving excellent distortion
performance. Common-mode errors, such as
even-order harmonics or noise, can be substantially
reduced. This is particularly the case with high output
frequencies.
IOUT
RL
IOUT
RL
For those applications requiring the optimum
distortion and noise performance, it is recommended
to select a full-scale output of 20mA. A lower
full-scale range down to 2mA may be considered for
applications that require a low power consumption,
but can tolerate a slightly reduced performance level.
Figure 19. Equivalent Analog Output
The signal voltage swing that may develop at the two
outputs, IOUT and I
, is limited by a negative and
OUT
positive compliance. The negative limit of –1V is
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OUTPUT CONFIGURATIONS
DIFFERENTIAL WITH TRANSFORMER
The current outputs of the DAC2904 allow for a
variety of configurations, some of which are illustrated
in Table 1. As mentioned previously, utilizing the
converter differential outputs will yield the best
dynamic performance. Such a differential output
circuit may consist of an RF transformer or a
differential amplifier configuration. The transformer
configuration is ideal for most applications with ac
coupling, while op amps will be suitable for a
dc-coupled configuration.
Using an RF transformer provides a convenient way
of converting the differential output signal into a
single-ended signal while achieving excellent
dynamic performance (see Figure 20). The
appropriate transformer should be carefully selected
based on the output frequency spectrum and
impedance requirements. The differential transformer
configuration has the benefit of significantly reducing
common-mode signals, thus improving the dynamic
performance over a wide range of frequencies.
Furthermore, by selecting a suitable impedance ratio
(winding ratio), the transformer can be used to
provide optimum impedance matching while
controlling the compliance voltage for the converter
outputs. The model shown, ADTT1-1 (by
Mini-Circuits), has a 1:1 ratio and may be used to
interface the DAC2904 to a 50Ω load. This results in
Table 1. Input Coding vs Analog Output Current
INPUT CODE (D13 - D0)
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0000
IOUT
20mA
10mA
0mA
I OUT
0mA
10mA
20mA
a 25Ω load for each of the outputs, IOUT and I
The output signals are ac-coupled and inherently
isolated because of its magnetic coupling.
.
OUT
The single-ended configuration may be considered
for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs
to ground will convert the output current into a
ground-referenced voltage signal. To improve on the
dc linearity by maintaining a virtual ground, an I-to-V
or op amp configuration may be considered.
As shown in Figure 20, the transformer center tap is
connected to ground. This forces the voltage swing
on IOUT and I
to be centered at 0V. In this case
OUT
the two resistors, RL, may be replaced with one,
RDIFF, or omitted altogether. This approach should
only be used if all components are close to each
other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can
be realized, but the output compliance range should
be observed. Alternatively, if the center tap is not
connected, the signal swing will be centered at (RL ×
IOUTFS/2). However, in this case, the two load
resistors, RL, must be used to enable the necessary
dc-current flow for both outputs.
space
space
space
space
space
ADTT1-1
(Mini-Circuits)
1:1
IOUT
RL
RS
RDIFF
50W
DAC2904
50W
100W
IOUT
RL
50W
Figure 20. Differential Output Configuration Using an RF Transformer
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DIFFERENTIAL CONFIGURATION USING AN
OP AMP
slew-limitations or into an overload condition; both
would cause excessive distortion. The difference
amplifier can easily be modified to add a level shift for
applications requiring the single-ended output voltage
to be unipolar; that is, swing between 0V and +2V.
If the application requires a dc-coupled output, a
difference amplifier may be considered, as shown in
Figure 21. Four external resistors are needed to
configure the voltage-feedback op amp OPA690 as a
difference amplifier performing the differential to
single-ended conversion. Under the configuration
shown, the DAC2904 generates a differential output
signal of 0.5VPP at the load resistors, RL. The resistor
values shown were selected to result in a symmetric
25Ω loading for each of the current outputs since the
input impedance of the difference amplifier is in
parallel to resistors RL, and should be considered.
DUAL TRANSIMPEDANCE OUTPUT
CONFIGURATION
The circuit example of Figure 22 shows the signal
output currents connected into the summing junctions
of the dual voltage-feedback op amp OPA2690 that is
set up as a transimpedance stage, or -to-V converter.
With this circuit, the DAC output will be kept at a
virtual ground, minimizing the effects of output
impedance variations, which results in the best dc
linearity (INL). As mentioned previously, care should
be taken not to drive the amplifier into slew-rate
limitations, and produce unwanted distortion.
R2
402W
R1
200W
IOUT
+5V
VOUT
DAC2904
IOUT
OPA690
50W
1/2
R3
COPT
-VOUT = IOUT · RF1
OPA2690
200W
-5V +5V
RL
28.7W
R4
402W
RL
26.1W
RF1
DAC2904
CF1
IOUT
CD1
Figure 21. Difference Amplifier Provides
Differential to Single-Ended Conversion and
DC-Coupling
RF2
CF2
IOUT
CD2
The OPA690 is configured for a gain of two.
Therefore, operating the DAC2904 with a 20mA
full-scale output will produce a voltage output of ±1V.
This requires the amplifier to operate off of a dual
power supply (±5V). The tolerance of the resistors
typically sets the limit for the achievable
common-mode rejection. An improvement can be
obtained by fine-tuning resistor R4.
1/2
· RF2
-VOUT = IOUT
OPA2690
50W
-5V
This configuration typically delivers a lower level of ac
Figure 22. Dual, Voltage-Feedback Amplifier
OPA2690 Forms Differential Transimpedance
Amplifier
performance
than
the
previously
discussed
transformer solution because the amplifier introduces
another source of distortion. Suitable amplifiers
should be selected based on the slew rate, harmonic
distortion, and output swing capabilities. High-speed
amplifiers like the OPA690 or OPA687 may be
considered. The ac performance of this circuit may be
improved by adding a small capacitor, CDIFF, between
The dc gain for this circuit is equal to feedback
resistor RF. At high frequencies, the DAC output
impedance (CD1, CD2) will produce a zero in the noise
gain for the OPA2690 that may cause peaking in the
closed-loop frequency response.
the outputs IOUT and I
(see Figure 21). This will
OUT
introduce a real pole to create a low-pass filter in
order to slew-limit the DAC fast output signal steps,
which otherwise could drive the amplifier into
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CF is added across RF to compensate for this noise
gain peaking. To achieve a flat transimpedance
frequency response, the pole in each feedback
network should be set to:
INTERFACING ANALOG QUADRATURE
MODULATORS
One of the main applications for the dual-channel
DAC is baseband I- and Q-channel transmission for
digital communications. In this application, the DAC is
followed by an analog quadrature modulator,
modulating an IF carrier with the baseband data, as
shown in Figure 25. Often, the input stages of these
quadrate modulators consist of npn-type transistors
that require a dc bias (base) voltage greater than
0.8V. The wide output compliance range (–10V to
+1.25V) allows for a direct dc-coupling between the
DAC2904 and the quadrature modulator.
1
GBP
=
2pRFCF 4pRFCD
(8)
with GBP = Gain Bandwidth Product of the OPA
which will give
approximately:
a
corner frequency f–3dB of
GBP
f
=
-3dB
2pRFCD
(9)
Figure 24 shows an example of a dc-coupled
interface with dc level-shifting, using a precision
resistor network. An ac-coupled interface (see
Figure 26) has the advantage that the common-mode
levels at the input of the modulator can be set
independently of those at the output of the DAC.
Furthermore, no voltage loss is obtained in this setup.
The full-scale output voltage is simply defined by the
product of IOUTFS × RF, and has a negative unipolar
excursion. To improve on the ac performance of this
circuit, adjustment of RF and/or IOUTFS should be
considered. Further extensions of this application
example may include adding a differential filter at the
OPA2690 output followed by a transformer, in order
to convert to a single-ended signal.
VDC
SINGLE-ENDED CONFIGURATION
R3
Using a single load resistor connected to one of the
DAC outputs, a simple current-to-voltage conversion
can be accomplished. The circuit in Figure 23 shows
a 50Ω resistor connected to IOUT, providing the
termination of the further connected 50Ω cable.
Therefore, with a nominal output current of 20mA, the
DAC produces a total signal swing of 0V to 0.5V into
the 25Ω load.
VOUT1
VOUT
1
R4
IOUT1
DAC2904
IOUT1
IOUT
1
IOUTFS = 20mA
IOUT
1
VOUT = 0V to +0.5V
IOUT
R5
DAC2904
IOUT
50W
50W
25W
Figure 24. DC-Coupled Interface to Quadrature
Modulator Applying Level Shifting
Figure 23. Driving a Doubly-Terminated 50Ω
Cable Directly
Different load resistor values may be selected as long
as the output compliance range is not exceeded.
Additionally, the output current, IOUTFS, and the load
resistor may be mutually adjusted to provide the
desired output signal swing and performance.
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VOUT ~ 0VP to 1.20VP
VIN ~ 0.6VP to 1.8VP
IIN
IREF
IIN
DAC2904
IOUT1
IREF
IOUT
1
Signal
Conditioning
RF
S
QIN
IOUT2
QREF
IOUT
2
Quadrature Modulator
Signal conditioning (level-shifting) may be required to ensure correct dc common-mode levels at the input of the quadrature modulator.
Figure 25. Generic Interface to a Quadrature Modulator
VDC
INTERNAL REFERENCE OPERATION
The DAC2904 has an on-chip reference circuit which
R1
IOUT
1
DAC2904
consists of a 1.25V bandgap reference and two
control amplifiers, one for each DAC. The full-scale
output current, IOUTFS, of the DAC2904 is determined
by the reference voltage, VREF, and the value of
resistor RSET. IOUTFS can be calculated by:
0.01mF
0.01mF
IOUT
1
VOUT1
VOUT
1
IOUT
1
IOUT
1
50W
50W
RLOAD
R2
VREF
IOUTFS = 32 ´ IREF = 32 ´
RSET
(10)
Figure 26. AC-Coupled Interface to Quadrature
Modulator Applying Level Shifting
As shown in Figure 27, the external resistor RSET
connects to the FSA pin (Full-Scale Adjust). The
reference control amplifier operates as a V-to-I
converter producing a reference current, IREF, which
is determined by the ratio of VREF and RSET (see
+5V
Equation 10). The full-scale output current, IOUTFS
,
results from multiplying IREF by a fixed factor of 32.
+VA
DAC2904
Using the internal reference, a 2kΩ resistor value
results in a full-scale output of approximately 20mA.
Resistors with a tolerance of 1% or better should be
considered. Selecting higher values, the output
current can be adjusted from 20mA down to 2mA.
Operating the DAC2904 at lower than 20mA output
currents may be desirable for reasons of reducing the
total power consumption, improving the distortion
performance, or observing the output compliance
voltage limitations for a given load condition.
VREF
IREF
=
RSET
FSA
Ref
Control
Amp
Current
Sources
REFIN
RSET
2kW
0.1mF
+1.25V Ref.
It is recommended to bypass the REFIN pin with a
ceramic chip capacitor of 0.1μF or more. The control
amplifier is internally compensated, and its
small-signal bandwidth is approximately 0.3MHz.
Figure 27. Internal Reference Configuration
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GAIN SETTING OPTIONS
+5V
The full-scale output current on the DAC2904 can be
set two ways: either for each of the two DAC
+VA
DAC2904
channels independently or for both channels
VREF
IREF
=
RSET
simultaneously. For the independent gain set mode,
the GSET pin (pin 42) must be low (that is, connected
to AGND). In this mode, two external resistors are
required—one RSET connected to the FSA1 pin (pin
44) and the other to the FSA2 pin (pin 41). In this
configuration, the user has the flexibility to set and
adjust the full-scale output current for each DAC
independently, allowing for the compensation of
possible gain mismatches elsewhere within the
transmit signal path.
FSA
Ref
Control
Amp
Current
Sources
REFIN
External
Reference
RSET
+1.25V Ref.
Figure 28. External Reference Configuration
Alternatively, bringing the GSET pin high (that is,
connected to +VA), the DAC2904 will switch into the
simultaneous gain set mode. Now the full-scale
output current of both DAC channels is determined by
only one external RSET resistor connected to the
FSA1 pin. The resistor at the FSA2 pin may be
removed; however, this is not required because this
pin is not functional in this mode and the resistor has
no effect on the gain equation. The formula for
deriving the correct RSET remains unchanged; for
example, RSET = 2kΩ will result in a 20mA output for
both DACs.
GROUNDING, DECOUPLING AND LAYOUT
INFORMATION
Proper grounding and bypassing, short lead lengths,
and the use of ground planes are particularly
important for high-frequency designs. Multilayer
printed circuit boards (PCBs) are recommended for
best performance because they offer distinct
advantages such as minimization of ground
impedance, separation of signal layers by ground
layers, etc.
The DAC2904 uses separate pins for its analog and
digital supply and ground connections. The
placement of the decoupling capacitor should be such
that the analog supply (+VA) is bypassed to the
analog ground (AGND), and the digital supply
bypassed to the digital ground (DGND). In most
cases 0.1μF ceramic chip capacitors at each supply
pin are adequate to provide a low impedance
decoupling path. Keep in mind that the effectiveness
of these capacitors largely depends on the proximity
to the individual supply and ground pins. Therefore,
they should be located as close as physically
possible to those device leads. Whenever possible,
the capacitors should be located immediately under
each pair of supply/ground pins on the reverse side of
the PCB. This layout approach will minimize the
parasitic inductance of component leads and PCB
runs.
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by simply
applying an external reference voltage into the REFIN
pin, which in this case functions as an input, as
shown in Figure 28. The use of an external reference
may be considered for applications that require higher
accuracy and drift performance, or to add the ability
of dynamic gain control.
While a 0.1μF capacitor is recommended to be used
with the internal reference, it is optional for the
external reference operation. The reference input,
REFIN, has a high input impedance (1MΩ) and can
easily be driven by various sources. Note that the
voltage range of the external reference should stay
within the compliance range of the reference input.
POWER-DOWN MODE
Further supply decoupling with surface-mount
tantalum capacitors (1μF to 4.7μF) may be added as
needed in proximity of the converter.
The DAC2904 features a power-down function which
can be used to reduce the total supply current to less
than 6mA over the specified supply range of 3.0V to
5.5V. Applying a logic high to the PD pin will initiate
the power-down mode, while a logic low enables
normal operation. When left unconnected, an internal
active pulldown circuit will enable the normal
operation of the converter.
Low noise is required for all supply and ground
connections to the DAC2904. It is recommended to
use a multilayer PCB utilizing separate power and
ground planes. Mixed signal designs require
particular attention to the routing of the different
supply currents and signal traces. Generally, analog
supply and ground planes should only extend into
analog signal areas, such as the DAC output signal
and the reference signal. Digital supply and ground
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planes must be confined to areas covering digital
circuitry, including the digital input lines connecting to
the converter, as well as the clock signal. The analog
and digital ground planes should be joined together at
one point underneath the DAC. This can be realized
with a short track of approximately 1/8 inch (3,0 mm).
connected together at the supply connector of the
PCB. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with
bypass capacitors may be used to create an LC filter.
This will generate a low-noise analog supply voltage,
which can then be connected to the +VA supply pin of
the DAC2904.
The power to the DAC2904 should be provided
through the use of wide PCB runs or planes. Wide
runs will present a lower trace impedance, further
optimizing the supply decoupling. The analog and
digital supplies for the converter should only be
While designing the layout, it is important to keep the
analog signal traces separated from any digital line,
in order to prevent noise coupling onto the analog
signal path.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November, 2003) to Revision C .......................................................................................... Page
•
•
Updated document format to current standards ................................................................................................................... 1
Added DAC2904IPFB orderable to Package/Ordering Information table ............................................................................. 2
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PACKAGE OPTION ADDENDUM
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21-May-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DAC2904IPFB
DAC2904Y/1K
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
TQFP
TQFP
PFB
PFB
PFB
PFB
PFB
48
48
48
48
48
250
1000
1000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
DAC2904Y/1KG4
DAC2904Y/250
DAC2904Y/250G4
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2010
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC2904Y/1K
DAC2904Y/250
TQFP
TQFP
PFB
PFB
48
48
1000
250
330.0
330.0
16.4
16.4
9.6
9.6
9.6
9.6
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC2904Y/1K
DAC2904Y/250
TQFP
TQFP
PFB
PFB
48
48
1000
250
367.0
367.0
367.0
367.0
38.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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