DAC43508 [TI]
具有 SPI 的八路 8 位缓冲电压输出 DAC;
| 型号： | DAC43508 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 SPI 的八路 8 位缓冲电压输出 DAC |
| 文件： | 总38页 (文件大小：4082K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC53508, DAC43508
ZHCSNR2 –DECEMBER 2021
DACx3508 采用微型3 × 3 WQFN 封装的八路10 位或8 位SPI 接口
缓冲电压输出DAC
1 特性
3 说明
• ±1LSB INL 和DNL
• 宽工作范围
10 位 DAC53508 和 8 位 DAC43508 (DACx3508) 是
低功耗、八通道、电压输出数模转换器 (DAC)。
DACx3508 根据设计在 1.8V 至 5.5V 的宽电源电压范
围内具有单调性。DACx3508 使用外部基准，可提供
1.8V 至5.5V 的满标度输出电压范围，同时每通道消耗
的静态电流为 0.1mA。DACx3508 还包括基于每通道
且用户可编程的断电寄存器。这些寄存器有助于 DAC
输出缓冲器以 10kΩ-AGND 断电状态启动，并保持该
状态，直到向这些输出缓冲器发出加电命令。
– 电源：1.8V 至5.5V
– 温度范围：–40°C 至+125°C
• 3 线SPI 接口
– 2.7V ≤VDD ≤5.5V 时，VIH = 2.4V
– 1.8V ≤VDD ≤2.7V 时，VIH = (VDD –0.3V)
• 通过LDAC 引脚实现同步输出更新
• 功耗极低：0.1mA/通道(1.8V)
• 低功耗启动模式：输出断电，并通过10kΩ 连接至
AGND。
DACx3508 具有低静态电流、宽电源电压范围、八通
道和每通道断电选项，因此非常适合高密度、低功耗的
电池供电系统。
• 微型封装
– 16 引脚WQFN (3mm × 3mm)
这些器件通过3 线（只写）SPI 接口进行通信。这些器
件还具有负载DAC (LDAC) 和清零CLR 输入。
2 应用
• 多功能打印机
• 电视显示面板
• OLED 电视
• 虚拟现实耳麦
• 点钞机
器件信息
封装(1)
封装尺寸（标称值）
器件型号
DAC53508
DAC43508
WQFN (16)
3.00mm × 3.00mm
• 自动取款机(ATM)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VDD
VREFIN
DACx3508
SCLK
DAC
Registers
SDI
SYNC
DAC
VOUTA
VOUTH
BUF
Channel A
Channel H
LDAC
CLR
Power-On Reset
Resistive Network
Power-Down Logic
AGND
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASF08
DAC53508, DAC43508
ZHCSNR2 –DECEMBER 2021
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................22
8.5 Programming............................................................ 22
8.6 Register Map.............................................................23
9 Application and Implementation..................................26
9.1 Application Information............................................. 26
9.2 Typical Applications.................................................. 26
10 Power Supply Recommendations..............................30
11 Layout...........................................................................30
11.1 Layout Guidelines................................................... 30
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................31
12.1 Documentation Support.......................................... 31
12.2 接收文档更新通知................................................... 31
12.3 支持资源..................................................................31
12.4 Trademarks.............................................................31
12.5 静电放电警告.......................................................... 31
12.6 术语表..................................................................... 31
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configurations and Functions.................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements: SPI.......................................... 7
7.7 Timing Requirements: Logic....................................... 7
7.8 Timing Diagrams ........................................................8
7.9 Typical Characteristics: Static Performance............... 9
7.10 Typical Characteristics: Dynamic Performance...... 15
7.11 Typical Characteristics: General............................. 17
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
Information.................................................................... 31
4 Revision History
DATE
REVISION
NOTES
December 2021
*
Initial Release
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5 Device Comparison Table
DEVICE
RESOLUTION
DAC53508
DAC43508
10-Bit
8-Bit
6 Pin Configurations and Functions
VOUTA
VOUTB
VOUTC
VOUTD
1
2
3
4
12
11
10
9
VOUTH
VOUTG
VOUTF
VOUTE
Thermal Pad
Not to scale
图6-1. RTE (16-Pin WQFN) Package, Top View
表6-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
VOUTA
VOUTB
VOUTC
VOUTD
SDIN
Output
Output
Output
Output
Input
Analog voltage output from DAC channel A.
Analog voltage output from DAC channel B.
Analog voltage output from DAC channel C.
Analog voltage output from DAC channel D.
SPI data input.
2
3
4
5
6
SCLK
Input
SPI clock input.
7
SYNC
Input
SPI chip select input (active low).
8
LDAC
Input
Load DAC (active low) input for synchronous output update, simultaneous output update, or both.
Analog voltage output from DAC channel E.
9
VOUTE
VOUTF
VOUTG
VOUTH
VDD
Output
Output
Output
Output
Power
Ground
Power
Input
10
11
12
13
14
15
16
—
Analog voltage output from DAC channel F.
Analog voltage output from DAC channel G.
Analog voltage output from DAC channel H.
Power supply input (1.8 V to 5.5 V).
AGND
Ground reference for all circuitry on the device.
External reference input. To use VDD as the reference, connect this pin to VDD.
Asynchronous output clear input (active low).
VREFIN
CLR
Thermal Pad
Ground
Connect thermal pad to AGND.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–10
–40
–65
MAX
UNIT
V
VDD
Power-supply voltage to AGND
External reference voltage to AGND
Digital input(s) to AGND
6
VDD + 0.3
VDD + 0.3
VDD + 0.3
10
VREFIN
V
V
VOUT
Voltage output to AGND
V
Current into any pin
mA
°C
°C
TJ
Junction temperature,TJ
Storage temperature, Tstg
150
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
NOM
MAX
5.5
UNIT
V
VDD to AGND
Positive supply voltage to ground
Reference input supply voltage to ground
Digital input high voltage, 1.8 V ≤VDD ≤2.7 V
Digital input high voltage, 2.7 V < VDD ≤5.5 V
Digital input low voltage
VREFIN to AGND
1.8
VDD
V
VDD –0.3
2.4
VIH
V
VIL
TA
0.5
V
Ambient temperature
125
°C
–40
7.4 Thermal Information
DACx3508
THERMAL METRIC(1)
RTE (WQFN)
UNIT
16 PIN
49
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
50
24.1
1.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
YJB
24.1
8.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
all minimum/maximum specifications at TA = –40°C to +125°C and all typical specification at TA = 25°C, 1.8 V ≤VDD ≤5.5
V, VREFIN = 2.5 V for VDD ≥2.7 V, VREFIN = 1.8 V for VDD ≤2.7 V, RL= 5 kΩto AGND, CL = 200 pF to AGND, and digital inputs
at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
DAC53508
DAC43508
10
8
Resolution
Bits
INL
Integral nonlinearity(1)
Differential nonlinearity(1)
Zero-code error
1
1
LSB
LSB
mV
–1
–1
DNL
Code 0d into DAC
Code 0d into DAC
6
12
Zero-code-error temperature
coefficient
±5
µV/°C
Offset error(1)
0.25
±0.0003
0.25
0.5
0.5
%FSR
%FSR/°C
%FSR
–0.5
–0.5
Offset-error temperature coefficient(1)
Gain error(1)
Gain-error temperature coefficient(1)
±0.0004
0.25
%FSR/°C
0.5
1
2.7 V ≤VDD ≤5.5 V
1.8 V ≤VDD ≤2.7 V
–0.5
–1
Full-scale error(4)
%FSR
0.5
Full-scale-error temperature
coefficient(4)
±0.0004
%FSR/°C
OUTPUT
VOUTX
Output voltage
0
5.5
1
V
RL = Infinite
CL
Capacitive load(2)
nF
2
DAC at midscale,
‒10 mA ≤IOUT ≤+10 mA, VDD = 5.5 V
Load regulation
0.1
mV/mA
VDD = 1.8 V
10
25
Short-circuit current(3)
VDD = 2.7 V
mA
V
VDD = 5.5 V
50
Output voltage headroom
Output voltage headroom(2)
To VDD, DAC output unloaded
0.05
To VDD, load current = 10 mA at VDD = 5.5
V, load current = 3 mA at VDD = 2.7 V,
load current = 1 mA at VDD = 1.8 V,
DAC code at full-scale
10
%FSR
DAC at midscale
DAC at code 4d
DAC at code 1016d
0.25
0.25
0.26
ZO
DC output impedance
Ω
DC
PSRR
Power supply rejection ratio (dc)
DAC at midscale, VDD = 5 V ±10%
0.25
mV/V
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7.5 Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and all typical specification at TA = 25°C, 1.8 V ≤VDD ≤5.5
V, VREFIN = 2.5 V for VDD ≥2.7 V, VREFIN = 1.8 V for VDD ≤2.7 V, RL= 5 kΩto AGND, CL = 200 pF to AGND, and digital inputs
at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale
settling to 10%FSR, VDD = 5.5 V
tsett
SR
Output voltage settling time
10
µs
Slew rate
VDD = 5.5 V
0.6
V/µs
mV
Power-on glitch magnitude
110
f = 0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V
Vn
Vn
Output noise
Output noise
40
µVpp
f = 0.1 Hz to 100 kHz, DAC at midscale,
VDD = 5.5 V
0.05
mVrms
f = 1 kHz, DAC at midscale, VDD = 5.5 V
f = 10 kHz, DAC at midscale, VDD = 5.5 V
0.2
0.2
Vn
Output noise density
µV/√Hz
200-mV, 50-Hz or 60-Hz sine wave
superimposed on power-supply voltage,
DAC at midscale
AC
PSRR
Power-supply rejection ratio (ac)
Channel-to-channel ac crosstalk
Channel-to-channel dc crosstalk
dB
–71
1.5
Full-scale swing on adjacent channel
nV-s
LSB
Full-scale swing on all channels,
measured channel at zero-scale or
full-scale
0.05
±1-LSB change around midscale
(including feedthrough)
Code change glitch impulse
10
25
nV-s
mV
Code change glitch impulse
magnitude
±1-LSB change around midscale
(including feedthrough)
VOLTAGE REFERENCE INPUT
Reference input impedance
Reference input capacitance
DIGITAL INPUTS
All channels powered on
12.5
50
kΩ
pF
SCLK = 1 MHz, DAC output static at
midscale
Digital feedthrough
20
10
nV-s
pF
Pin capacitance
Per pin
POWER
Normal mode, all DACs at full-scale,
SPI static
3
5
mA
µA
IDD
Current flowing into VDD
All DAC channels powered down
50
(1) End point fit between codes: code 4d to code 1016d for 10 bit, code 1d to code 251d for 8 bit.
(2) Characterized by design. Not production tested.
(3) Full-scale output shorted per channel to AGND or zero-scale output shorted to VDD
.
(4) Code 1023d into DAC, no headroom.
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7.6 Timing Requirements: SPI
All inputs signals are specified with tR = tF = 1 V/ns (10% to 90% of VDD) and timed from a voltage level of VDD/2,
1.8 V ≤VDD ≤5.5 V and –40°C ≤TA ≤+125°C
MIN
NOM
MAX
25
UNIT
Serial clock frequency, 1.7 V ≤VDD < 2.7 V
Serial clock frequency, 2.7 V ≤VDD ≤5.5 V
SCLK high time, 1.7 V ≤VDD < 2.7 V
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
MHz
50
20
10
20
10
16
8
ns
ns
ns
ns
ns
ns
ns
SCLK high time, 2.7 V ≤VDD ≤5.5 V
SCLK low time, 1.7 V ≤VDD < 2.7 V
SCLK low time, 2.7 V ≤VDD ≤5.5 V
SDI setup time, 1.7 V ≤VDD < 2.7 V
SDI setup time, 2.7 V ≤VDD ≤5.5 V
10
5
SDI hold time, 1.7 V ≤VDD < 2.7 V
tSDIH
SDI hold time, 2.7 V ≤VDD ≤5.5 V
36
18
10
5
SYNC to SCLK falling edge setup time, 1.7 V ≤VDD < 2.7 V
SYNC to SCLK falling edge setup time, 2.7 V ≤VDD ≤5.5 V
SCLK falling edge to SYNC rising edge, 1.7 V ≤VDD < 2.7 V
SCLK falling edge to SYNC rising edge, 2.7 V ≤VDD ≤5.5 V
SYNC high time, 1.7 V ≤VDD < 2.7 V
tCSS
tCSH
50
25
tCSHIGH
SYNC high time, 2.7 V ≤VDD ≤5.5 V
7.7 Timing Requirements: Logic
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, 1.8 V ≤VREFIN ≤VDD, –40°C ≤TA ≤+125°C,
Vpullup = VDD for 1.8 V ≤VDD ≤2.7 V, Vpullup = 2.7 V or VDD for 2.7 V ≤VDD ≤5.5 V
MIN
100
50
NOM
MAX
UNIT
SYNC rise edge to LDAC fall edge, 1.7 V ≤VDD < 2.7 V
SYNC rise edge to LDAC fall edge, 2.7 V ≤VDD ≤5.5 V
LDAC low time, 1.7 V ≤VDD < 2.7 V
tCS2LDAC
tLDACW
tCLRW
ns
60
ns
ns
30
LDAC low time, 2.7 V ≤VDD ≤5.5 V
60
CLR low time, 1.7 V ≤VDD < 2.7 V
30
CLR low time, 2.7 V ≤VDD ≤5.5 V
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7.8 Timing Diagrams
tCSS
tCSH
tCSHIGH
SYNC
SCLK
tSCLKLOW
tSCLKHIGH
tSDIH
tSDIS
SDIN
Bit 23
Bit 1
Bit 0
LDAC
tCS2LDAC
tLDACW
图7-1. Serial Interface Timing Diagram
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7.9 Typical Characteristics: Static Performance
at TA = 25°C, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
4
132
260
388
516
644
772
900 1016
4
132
260
388
516
644
772
900 1016
Code
Code
VDD = 1.8 V
VDD = 5.5 V
图7-2. Integral Nonlinearity vs Digital Input Code
图7-3. Integral Nonlinearity vs Digital Input Code
1
1
INL Max
INL Min
INL Max
INL Min
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
VDD = 1.8 V
VDD = 5.5 V
图7-4. Integral Nonlinearity vs Temperature
图7-5. Integral Nonlinearity vs Temperature
1
INL Max
INL Min
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
1.8
2.725
3.65
4.575
5.5
Voltage Reference (V)
VDD = 5.5 V
图7-6. Integral Nonlinearity vs Supply Voltage
图7-7. Integral Nonlinearity vs Voltage Reference
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7.9 Typical Characteristics: Static Performance (continued)
at TA = 25°C, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
4
132
260
388
516
644
772
900 1016
4
132
260
388
516
644
772
900 1016
Code
Code
VDD = 1.8 V
VDD = 5.5 V
图7-8. Differential Nonlinearity vs Digital Input Code
图7-9. Differential Nonlinearity vs Digital Input Code
VDD = 1.8 V
VDD = 5.5 V
图7-10. Differential Nonlinearity vs Temperature
图7-11. Differential Nonlinearity vs Temperature
1
1
DNL Max
DNL Max
DNL Min
DNL Min
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
1.8
2.725
3.65
4.575
5.5
1.8
2.725
3.65
4.575
5.5
VDD (V)
Voltage Reference (V)
图7-12. Differential Nonlinearity vs Supply Voltage
图7-13. Differential Nonlinearity vs Voltage Reference
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7.9 Typical Characteristics: Static Performance (continued)
at TA = 25°C, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
4
132
260
388
516
644
772
900 1016
4
132
260
388
516
644
772
900 1016
Code
Code
VDD = 1.8 V
VDD = 5.5 V
图7-14. Total Unadjusted Error vs Digital Input Code
图7-15. Total Unadjusted Error vs Digital Input Code
1
1
TUE Max
TUE Min
TUE Max
TUE Min
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
VDD = 1.8 V
VDD = 5.5 V
图7-16. Total Unadjusted Error vs Temperature
图7-17. Total Unadjusted Error vs Temperature
1
1
TUE Max
TUE Min
TUE Max
TUE Min
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
1.8
2.725
3.65
4.575
5.5
1.8
2.725
3.65
4.575
5.5
VDD (V)
Voltage Reference (V)
VDD = 5.5 V
图7-18. Total Unadjusted Error vs Supply Voltage
图7-19. Total Unadjusted Error vs Voltage Reference
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7.9 Typical Characteristics: Static Performance (continued)
at TA = 25°C, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
6
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
4
2
0
-2
-4
-6
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
VDD = 5.5 V
VDD = 1.8 V
图7-21. Zero-Code Error vs Temperature
图7-20. Zero-Code Error vs Temperature
12
10
8
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
6
4
2
0
1.8
2.725
3.65
4.575
5.5
Voltage Reference (V)
VDD = 5.5 V
图7-22. Zero-Code Error vs Supply Voltage
图7-23. Zero-Code Error vs Voltage Reference
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
VDD = 1.8 V
VDD = 5.5 V
图7-24. Offset Error vs Temperature
图7-25. Offset Error vs Temperature
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7.9 Typical Characteristics: Static Performance (continued)
at TA = 25°C, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
1
0.75
0.5
1
0.75
0.5
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
1.8
2.725
3.65
4.575
5.5
1.8
2.725
3.65
4.575
5.5
VDD (V)
Voltage Reference (V)
VDD = 5.5 V
图7-26. Offset Error vs Supply Voltage
图7-27. Offset Error vs Voltage Reference
1
0.8
0.6
0.4
0.2
0
0.5
0.4
0.3
0.2
0.1
0
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
-0.2
-0.4
-0.6
-0.8
-1
-0.1
-0.2
-0.3
-0.4
-0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
VDD = 1.8 V
VDD = 5.5 V
图7-28. Gain Error vs Temperature
图7-29. Gain Error vs Temperature
1
1
0.75
0.5
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
1.8
2.725
3.65
4.575
5.5
1.8
2.725
3.65
4.575
5.5
VDD (V)
Voltage Reference (V)
VDD = 5.5 V
图7-30. Gain Error vs Supply Voltage
图7-31. Gain Error vs Voltage Reference
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7.9 Typical Characteristics: Static Performance (continued)
at TA = 25°C, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
0.5
0.4
0.3
0.2
0.1
0
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
-0.2
-0.4
-0.6
-0.8
-1
-0.1
-0.2
-0.3
-0.4
-0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
VDD = 1.8 V
VDD = 5.5 V
图7-32. Full-Scale Error vs Temperature
图7-33. Full-Scale Error vs Temperature
1
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
1.8
2.725
3.65
4.575
5.5
1.8
2.725
3.65
4.575
5.5
VDD (V)
Voltage Reference (V)
VDD = 5.5 V
VDD = 5.5 V
图7-34. Full-Scale Error vs Supply Voltage
图7-35. Full-Scale Error vs Voltage Reference
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7.10 Typical Characteristics: Dynamic Performance
at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
VOUT (1 LSB/div)
LDAC (2.5 V/div)
VOUT (1 LSB/div)
LDAC (2.5 V/div)
Time (1 s/div)
Time (1 s/div)
DAC code transition from midscale –1 to midscale,
output load: 5 kΩ || 200 pF
DAC code transition from midscale to midscale –1 LSB,
output load: 5 kΩ || 200 pF
图7-36. Glitch Impulse, Rising Edge, 1-LSB Step
图7-37. Glitch Impulse, Falling Edge, 1 LSB Step
Small Signal VOUT (1 LSB/div)
Large Signal VOUT (2.5 V/div)
LDAC (2.5 V/div)
Small Signal VOUT (1 LSB/div)
Large Signal VOUT (2.5 V/div)
LDAC (2.5 V/div)
Time (5 s/div)
Time (5 s/div)
DAC code transition from 102d to 922d, typical
channel shown, output load: 5 kΩ || 200 pF
DAC code transition from 922d to 102d, typical
channel shown, output load: 5 kΩ || 200 pF
图7-38. Full-Scale Settling Time, Rising Edge
图7-39. Full-Scale Settling Time, Falling Edge
18
16
14
12
10
8
20
15
10
5
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
0
6
-5
4
2
-10
-15
-20
0
-2
-4
Time (1 ms/div)
Time (50 s/div)
Output load: 5 kΩ || 200 pF
图7-41. Power-off Glitch
Output load: 5 kΩ || 200 pF
图7-40. Power-on Glitch
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7.10 Typical Characteristics: Dynamic Performance (continued)
at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
10
VOUT (2 mV/div)
SCL (2.5 V/div)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
10
100
1000
Frequency (Hz)
10000
100000
1000000
Time (1 s/div)
DAC at midscale, reference tied to VDD
,
DAC at full-scale, output load: 5 kΩ || 200 pF,
output load: 5 kΩ || 200 pF, SCLK = 1 MHz
图7-42. Clock Feedthrough
VDD = 5.25 V + 0.2 VPP, VREFIN = 4.5 V
图7-43. AC Power-Supply Rejection Ratio vs Frequency
1000
Code 0x20
Code 0x800
Code 0xFDC
800
600
400
200
0
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
Time (1 s/div)
DAC at midscale, f = 0.1 Hz to 10 Hz
图7-44. Flicker Noise
图7-45. Noise Spectral Density
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7.11 Typical Characteristics: General
at TA = 25°C, and DAC outputs unloaded (unless otherwise noted)
3
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
128
256
384
512
640
768
896 1024
0
128
256
384
512
640
768
896 1024
Code
Code
VDD = 1.8 V, reference = 1.8 V
VDD = 5.5 V, reference = 5.5 V
图7-46. Power-Supply Current vs Digital Input Code
图7-47. Power-Supply Current vs Digital Input Code
5
3
VDD = 5.5 V
VDD = 3.65 V
VDD = 1.8 V
4.5
2.5
4
3.5
3
2
1.5
1
2.5
2
1.5
1
0.5
0.5
0
0
1.8
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
2.725
3.65
4.575
5.5
VDD (V)
DAC at midscale
DAC at midscale, reference tied to VDD
图7-49. Power-Supply Current vs Supply Voltage
图7-48. Power-Supply Current vs Temperature
6
5
4
3
2
1
0
Code 0x3FF
Code 0
-20 -16 -12
-8
-4
0
4
8
12
16
20
Load Current (mA)
VDD = 1.8 V, reference = 1.8 V
VDD = 5.5 V, reference = 5.5 V
图7-51. Output Source and Sink Capability
图7-50. Output Source and Sink Capability
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7.11 Typical Characteristics: General (continued)
at TA = 25°C, and DAC outputs unloaded (unless otherwise noted)
50
45
40
35
30
25
20
15
10
5
VDD = 5.5 V
VDD = 3.65 V
VDD = 1.8 V
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
VDD = 5.5 V
图7-52. Power-Down Current vs Temperature
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8 Detailed Description
8.1 Overview
The 10-bit DAC53508 and 8-bit DAC43508 (DACx3508) are a pin-compatible family of eight-channel, buffered
voltage-output digital-to-analog converters (DACs). With an external reference ranging from 1.8 V to 5.5 V, a full-
scale output voltage of 1.8 V to 5.5 V is achievable. These devices are specified monotonic across the power-
supply range.
Communication to the devices is established through a three-wire SPI-compatible interface. These devices do
not support readback operation. These devices include a load DAC (LDAC) pin for simultaneous DAC updates
and a clear (CLR) pin for setting the outputs to zero scale.
The DACx3508 devices are characterized for operation over the temperature range of –40°C to +125°C and are
available in tiny QFN packages.
8.2 Functional Block Diagram
VDD
VREFIN
DACx3508
SCLK
SDI
DAC
Registers
DAC
VOUTA
VOUTH
BUF
SYNC
LDAC
CLR
Channel A
Channel H
Power-On Reset
Resistive Network
Power-Down Logic
AGND
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8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
Each output channel in the DACx3508 family of devices consists of string architecture with an output buffer
amplifier. 图8-1 shows a block diagram of the DAC architecture.
VREFIN
VDD
Serial Interface
DAC Data Register
DAC
Buffer
DAC
Active
VOUTX
String
BUF
Register
Register
READ
WRITE
(Asynchronous Mode)
LDAC Trigger
(Synchronous Mode)
AGND
图8-1. DACx3508 DAC Architecture
8.3.1.1 DAC Transfer Function
The device writes the input data to the individual DAC Data registers in straight binary format. After a power-on
or a reset event, the device sets all DAC registers to zero-code. 方程式1 shows DAC transfer function.
DACn_DATA
V
=
× V
(1)
OUTX
REFIN
N
2
where:
• N = resolution in bits: 10 (DAC53508) or 8 (DAC43508)
• DACn_DATA is the decimal equivalent of the binary code that is loaded to the DAC register
• DACn_DATA ranges from 0 to 2N –1
• VREFIN is the DAC reference voltage
8.3.1.2 DAC Register Update and LDAC Functionality
The device stores the data written to the DAC Data registers in the DAC buffer registers. Transfer of data from
the DAC buffer registers to the DAC active registers can be set to happen immediately (asynchronous mode) or
initiated by an LDAC trigger (synchronous mode). After the DAC active registers are updated, the DAC outputs
change to the new values.
The update mode for each DAC channel is determined by the status of LDAC pin.
In asynchronous mode (LDAC = low before the DAC write command), a write to the DAC data register results in
an immediate update of the DAC active register and DAC output at the end of SPI frame.
In synchronous mode (LDAC = high before the DAC write command), writing to the DAC data register does not
automatically update the DAC output. Instead, the update occurs only after LDAC is pulled low. The
synchronous update mode enables simultaneous update of all DAC outputs.
8.3.1.3 CLR Functionality
The CLR pin is an asynchronous input pin to the DAC. When this pin is pulled low, the DAC buffers and the DAC
active registers are set to zero code.
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8.3.1.4 Output Amplifier
The output buffer amplifier generates rail-to-rail voltages on the output, giving a maximum output range of 0 V to
DD. 方程式 1 shows that the full-scale output range of the DAC output is determined by the voltage on the
V
VREFIN pin
8.3.2 Reference
The DACx3508 require an external reference to operate. However, the reference pin, VREFIN, and the supply
pin, VDD, can be tied together. The reference input pin voltage ranges from 1.8 V to VDD. The typical input
impedance of this pin when all the channels are powered on is 12.5 kΩ.
8.3.3 Power-On Reset (POR)
The DACx3508 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to
initialize to default values, and communication with the device is valid only after a 5-ms delay, when VDD reaches
DAC operating range. The default value for the DAC data registers is zero-code. The DAC output remains at the
power-up voltage until a valid command is written to a channel.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in 图 8-2, to make sure that the internal capacitors discharge and reset the device on
power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops to
less than 1.7 V but remains greater than 0.7 V (shown as the undefined region), the device may or may not reset
under all specified temperature and power-supply conditions. In this case, initiate a POR. When VDD remains
greater than 1.7 V, a POR does not occur.
VDD (V)
5.50
Specified supply
voltage range
No power-on reset
1.80
1.70
Undefined
0.70
Power-on reset
0.00
图8-2. Threshold Levels for VDD POR Circuit
8.3.4 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to the SW_RST bit in the
STATUS_TRIGGER register.
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8.4 Device Functional Modes
The DACx3508 has two modes of operation: normal and power-down.
8.4.1 Power-Down Mode
The DACx3508 DAC output amplifiers can be independently or globally powered down (10 kΩ to AGND) through
the DEVICE_CONFIG register. In this state, the device consumes 50 µA (VDD = 1.8 V). At power-up, all output
channels buffer amplifiers start in power down (10 kΩ-AGND) mode until a power up command is issued by
writing 0 to the per-channel power-down register bits.
8.5 Programming
8.5.1 Serial Peripheral Interface (SPI)
The DACx3508 supports a three-wire SPI interface with write-only functionality. An SPI write cycle for DACx3508
is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a continuous or gated clock. SDI data
are clocked on SCLK falling edges. The SPI frame for DACx3508 is 24 bits long; therefore, the SYNC pin must
stay low for at least 24 SCLK falling edges. The write cycle ends when the SYNC pin is deasserted high. If the
write cycle contains less than the minimum clock edges, the communication is ignored. If the write cycle contains
more than the minimum clock edges, only the first 24 bits are used by the device.
表 8-1 describes the format for the 24-bit SPI write access cycle. The first byte input to SDI is the instruction
cycle. The instruction cycle identifies the request as the 8-bit address to be written. The last 16 bits in the cycle
form the data cycle.
表8-1. SPI Write Access Cycle
BIT
FIELD
DESCRIPTION
23-16
15-0
A[7:0]
Register address: specifies the register to be accessed during the write operation.
DI[15:0]
Data cycle bits: The data cycle bits are the values written to the register with
address A[7:0].
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8.6 Register Map
表8-2. Register Map
DATA BITS
B6
COMMAND
BITS
REGISTER NAME
MSDB
B11
LSDB
B4
B23-B16
B15-B12
B10
B9
B8
B7
PDNH
B5
B3
B2
B1
B0
DEVICE_CONFIG
(节8.6.1)
01h
X
RESERVED
PDN-All
PDNG
PDNF
PDNE
PDND
PDNC
PDNB
PDNA
STATUS_TRIGGER
(节8.6.2)
02h
03h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
X
X
X
X
X
X
X
X
X
X
X
SW_RST
BRDCAST
(节8.6.3)
BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0]
DACA_DATA[9:0] / DACA_DATA[7:0]
DACB_DATA[9:0] / DACB_DATA[7:0]
DACC_DATA[9:0] / DACC_DATA[7:0]
DACD_DATA[9:0] / DACD_DATA[7:0]
DACE_DATA[9:0] / DACE_DATA[7:0]
DACF_DATA[9:0] / DACF_DATA[7:0]
DACG_DATA[9:0] / DACG_DATA[7:0]
DACH_DATA[9:0] / DACAH_DATA[7:0]
X
X
X
X
X
X
X
X
X
DACA_DATA
(节8.6.4)
DACB_DATA
(节8.6.4)
DACC_DATA
(节8.6.4)
DACD_DATA
(节8.6.4)
DACE_DATA
(节8.6.4)
DACF_DATA
(节8.6.4)
DACG_DATA
(节8.6.4)
DACH_DATA
(节8.6.4)
表8-3. Register Section/Block Access Type Codes
Access Type
Code
Description
W
W
-n
W
Write only
X
Don't care
Value after reset or the default value
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8.6.1 DEVICE_CONFIG Register (address = 01h) [reset = 00FFh]
图8-3. DEVICE_CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
RESERVED
W-0h
PDN-All PDNH
W-0b
PDNG
PDNF
PDNE
PDND
PDNC
PDNB
PDNA
W-0h
W-FFh
表8-4. DEVICE_CONFIG Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-12
11-9
8
X
W
0h
00
0
Don't care
RESERVED
PDN-All
W
Reserved
W
Global power down bit:
0: Normal operation
1: All DAC channels and internal biasing blocks are powered
down.
7-0
PDNx
W
FFh
Channel-specific power down bits:
0: DACx powered up
1: DACx powered down with 10 kΩ pulldown resistor to AGND
.
8.6.2 STATUS_TRIGGER Register (address = 02h) [reset = 0000h]
图8-4. STATUS_TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
SW_RST
W-0h
W-000h
表8-5. STATUS_TRIGGER Register Field Descriptions
BIT
FIELD
TYPE
RESET
000h
0h
DESCRIPTION
15-4
3-0
X
W
Don't care
SW_RST
W
Device resets to default value when this bit field is set to 1010.
Other values do not have any impact.
8.6.3 BRDCAST Register (address = 03h) [reset = 0000h]
图8-5. BRDCAST Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0]
W-000h
X
W-0h
W-00b
表8-6. BRDCAST Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-12
11-2
X
W
0h
Don't care
BRDCAST_DATA[9:0] /
BRDCAST_DATA[7:0]
W
000h
Writing to the BRDCAST register forces the DAC channel to
update the active register data to BRDCAST_DATA.
Data are MSB-aligned in straight-binary format and follow the
format below:
DAC53508: { DATA[9:0] }
DAC43508: { DATA[7:0], x, x }
x –Don’t care bits
1-0
X
W
00
Don't care
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8.6.4 DACn_DATA Register (address = 08h to 0Fh) [reset = 0000h]
图8-6. DACn_DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
DACn_DATA[9:0] / DACn_DATA[7:0]
W-000h
X
W-0h
W-00b
表8-7. DACn_DATA Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-12
11-2
X
W
0h
Don't care
DACn_DATA[9:0] / DACn_DATA[7:0] W
000h
Writing to the DACn_DATA register forces the respective DAC
channel to update the active register data to the DACn_DATA.
Data are MSB-aligned in straight-binary format and follow the
format below:
DAC53508: { DATA[9:0] }
DAC43508: { DATA[7:0], x, x }
x –Don’t care bits
1-0
X
W
00
Don't care
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The DACx3508 is a buffered output, eight-channel, low-power DAC available in a tiny 3-mm x 3-mm package.
The multichannel, low power, and small package makes this DAC an excellent choice for general-purpose
applications in wide range of end equipment. Some of the most-common applications for these devices are LED
biasing-in multifunction printers, power-supply supervision with programmable comparators, offset and gain
trimming in precision circuits, and power-supply margining.
9.2 Typical Applications
9.2.1 Programmable LED Biasing
End equipments such as multifunction printers, projectors and electronic point-of-sale (EPOS) require a steady
luminous intensity from the LED. 图 9-1 shows a simplified circuit diagram for biasing an LED using the
DAC53508.
VCC
ILED=ISET
LED
VDD
VDAC
DAC53508
+
–
Q1
VDAC
RSET
ISET
图9-1. Programmable LED Biasing
9.2.1.1 Design Requirements
• Programmable constant current through an LED tied to a power supply on one end
• DAC output range: 0 V to 5 V
• LED current range: 0 mA to 20 mA
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9.2.1.2 Detailed Design Procedure
The DAC is used to set the source current of a MOSFET using a unity-gain buffer, as shown in 图 9-1. Connect
the LED between the power supply and the drain of the MOSFET. This configuration allows the DAC to control or
set the amount of current through the LED. The buffer following the DAC controls the gate-source voltage of the
MOSFET inside the feedback loop, thus compensating this drop and corresponding drift due to temperature,
current, and ageing of the MOSFET. The current set by the DAC that flows through the LED is calculated with 方
程式2. To generate 0 mA to 20 mA from a 0 V to 5 V DAC output range, a 250-ΩRSET is required.
V
DAC
I
=
(2)
SET
R
SET
The following pseudocode is provided to help get started with the LED biasing application:
//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <DATA>
//Power-up the device and channels
WRITE DEVICE_CONFIG(0x01), 0x0000
//Program mid code (or the desired voltage) on all channels
WRITE DACA_DATA(0x08), 0x07FC //10-bit MSB aligned
WRITE DACB_DATA(0x09), 0x07FC //10-bit MSB aligned
WRITE DACC_DATA(0x0A), 0x07FC //10-bit MSB aligned
WRITE DACD_DATA(0x0B), 0x07FC //10-bit MSB aligned
WRITE DACE_DATA(0x0C), 0x07FC //10-bit MSB aligned
WRITE DACF_DATA(0x0D), 0x07FC //10-bit MSB aligned
WRITE DACG_DATA(0x0E), 0x07FC //10-bit MSB aligned
WRITE DACH_DATA(0x0F), 0x07FC //10-bit MSB aligned
9.2.1.3 Application Curve
图9-2. DC Transfer Characteristics of LED Biasing Circuit
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9.2.2 Programmable Window Comparator
End equipment that use a centralized power supply (such as network servers, optical modules, and others)
require the monitoring of power buses to protect the components. This monitoring or supervision is
accomplished using a window comparator. A window comparator monitors a signal input for upper- and lower-
threshold violations. A trigger signal is generated when the threshold violations occur. Multichannel monitoring is
required to supervise all power supplies available in a module. The DACx3508 provides an easy-to-use, low-
footprint method to address this requirement. 图 9-3 shows how the DAC53508 is used to create a
programmable window comparator.
VIO
VDD
VDD
RPULL-UP
VOUT
THLD-HI
RA
DAC53508
+
–
R1
R2
VIN
RB
+
–
THLD-LO
图9-3. Programmable Window Comparator
9.2.2.1 Design Requirements
• Voltage to be monitored: 5 V
• High threshold: 5 V + 10%
• Low threshold: 5 V –10%
• Trigger output: 3.3-V open-drain single output
9.2.2.2 Detailed Design Procedure
图 9-3 provides an example in which single DAC channel is used to compare both high and low thresholds. A
dual comparator is used per DAC channel, as shown. A voltage divider formed by resistors RA and RB are used
in order to bring the signal level within the DAC range. Another pair of resistors, R1 and R2, are used to settle the
low threshold as a factor of the high threshold. This configuration allows the use of a single DAC channel to
monitor both the high- and low-threshold levels. Use open-drain comparators to provide the following
advantages.
• Generate a logic output level appropriate for the monitoring processor
• Allow shorting of the two outputs to generate a single trigger
In the circuit depicted in 图 9-3, the output of the circuit remains high as long as the signal input remains within
the high- and low-threshold levels. Upon violation of any one threshold, the output goes low. 方程式 3 provides
the derivation of the low threshold voltage from the high threshold set by the DAC.
R
2
+ R
V
= V
×
DAC
(3)
THLD − LO
R
1
2
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To monitor a power supply of 5 V within ±10%, place the nominal value at the DAC midcode. The output range of
the DACx3508 is 0 V to 5 V, thus the midcode voltage output is 2.5 V. Therefore, RA and RB are chosen so that
the voltage to be compared is 2.5 V. For this example, RA equals RB; use 10-kΩresistors for both. One channel
of the DACx3508 must be programmed to VTHLD-HI (for example, 2.5 V + 5% = 2.625 V). This result corresponds
to a 10-bit DAC code of (210 / 5 V) × 2.625 V = 537.6 (0x21Ah). To generate VTHLD-LO (for example, 2.5 V – 5%
= 2.405 V) from 2.625 V, the values of R1 and R2 are calculated as 7.5 kΩ and 82 kΩ, respectively, using 方程
式3.
The following pseudocode is provided to help get started with the programmable window comparator application
at the desired DAC value.
//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <DATA>
//Power-up the device and channels
WRITE DEVICE_CONFIG(0x01), 0x0000
//Program 2.625V on channel A
WRITE DACA_DATA(0x08), 0x0868 //10-bit MSB aligned
9.2.2.3 Application Curve
图9-4. Programmable Comparator Output Waveform
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10 Power Supply Recommendations
The DACx3508 family of devices does not require specific supply sequencing. These devices require a single
power supply, VDD. A 0.1-µF decoupling capacitor is recommended for the VDD pin.
11 Layout
11.1 Layout Guidelines
The DACx3508 pinout separates the analog, digital, and power pins for an optimized layout. For signal integrity,
separate digital and analog traces and place decoupling capacitors close to the device pins.
11.2 Layout Example
图11-1 shows an example layout drawing with decoupling capacitors and pullup resistors.
VREFIN
VDD
Decoupling
Capacitor
VIO
GND
GND
VOUTA
1
2
3
4
12
11
10
9
VOUTH
VOUTG
VOUTF
VOUTE
VOUTB
VOUTC
VOUTD
DACx3508
VIO
VIO
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following: Texas Instruments, DAC53608EVM user's guide
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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8-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC43508RTER
DAC53508RTER
DAC53508RTET
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RTE
RTE
RTE
16
16
16
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
D43508
Samples
Samples
Samples
NIPDAU
NIPDAU
D53508
D53508
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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8-Apr-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
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PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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